An error correction method for asynchronous communication in a differentiated model and a storage medium
By configuring calibration target information and selecting a two-dimensional strategy of hard or soft calibration, the problem of high hardware requirements for hard calibration is solved, achieving efficient and low-difficulty error calibration, applicable to different chip conditions, and simplifying system scale.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGSHA FANGWEI TECH CO LTD
- Filing Date
- 2022-11-25
- Publication Date
- 2026-06-02
AI Technical Summary
In existing differentiated models, error calibration for asynchronous communication typically employs hard calibration. Hard calibration places high demands on hardware circuitry, lacks flexibility, and requires strict control over the reference signal during the calibration process.
The system uses configuration information for calibration targets and generates calibration reference signals through a host computer. The chip selects hard calibration or soft calibration for error correction based on the mode configuration and stores the calibration configuration parameters in non-volatile memory, supporting two-dimensional calibration strategies for both hard and soft calibration.
It achieves efficient and easy error calibration, balancing calibration accuracy and flexibility, and is applicable to different chip conditions, simplifying system scale.
Smart Images
Figure CN115857619B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, specifically to an asynchronous communication error correction method and storage medium in a differentiated model. Background Technology
[0002] To address the issue of process discreteness in the current integrated circuit field, there is often a discrepancy between the design specifications and the actual tape-out specifications of system clock circuits (such as RC oscillators), or the accuracy of the circuit design specifications is poor, only accurate to a certain range. This can lead to errors (variations) in chip-to-interface communication (based on baud rate calculations using the system clock). Existing variation models typically only offer hardware calibration for asynchronous communication errors. Hardware calibration requires sophisticated hardware circuitry, stringent reference signal requirements, and dedicated reference pins, lacking flexibility. Summary of the Invention
[0003] In view of the above problems, this application provides an asynchronous communication error correction method and storage medium in a differentiated model, which solves the problem that the error calibration of asynchronous communication in existing differentiated models usually adopts hard calibration, which has high requirements for hardware circuits.
[0004] To achieve the above objectives, the inventors provide a method for correcting asynchronous communication errors in a differentiated model, comprising the following steps:
[0005] Configure the calibration target configuration information and import it into the chip and host computer. The calibration target configuration information includes target location, reference configuration, mode configuration and adjustment configuration.
[0006] The host computer generates a calibration reference signal based on the calibration target configuration information and continuously sends it to the chip.
[0007] The chip selects either hard calibration or soft calibration for error correction based on the mode configuration. The hard calibration is clock factor correction, and the soft calibration is baud rate reference line correction.
[0008] When the chip receives the calibration reference signal, it performs error correction adjustments according to the adjustment configuration.
[0009] After the calibration and adjustment are completed, the calibration configuration parameters for error calibration and adjustment are stored in non-volatile memory.
[0010] In some embodiments, the adjustment configuration includes coarse adjustment accuracy, fine adjustment accuracy, and precision adjustment accuracy;
[0011] "Performing error correction adjustments based on the adjusted configuration" specifically includes the following steps:
[0012] When the chip receives a frame of calibration reference signal, it determines whether the error is less than the fine-tuning accuracy;
[0013] If the precision is less than the fine-tuning precision, then fine-tuning is initiated;
[0014] If the error is greater than the fine-tuning precision, then determine whether the error is greater than the coarse-tuning precision.
[0015] If the value exceeds the coarse adjustment precision, then coarse adjustment is initiated.
[0016] If the precision is less than the coarse adjustment precision, then fine adjustment is initiated.
[0017] In some embodiments, the fine-tuning process specifically includes the following steps:
[0018] Record the current error as the minimum error, fine-tune the frequency down one level, and then determine whether the error has decreased;
[0019] If the error decreases, update the current error to the minimum error and return to step: fine-tuning the frequency down one level;
[0020] If the error increases, the fine-tuning frequency is increased by one stop, and then it is determined whether the error has decreased.
[0021] If the error decreases, update the current error to the minimum error and return to step: fine-tuning the frequency by one level;
[0022] If the error increases, the fine-tuning frequency is lowered by one stop to complete the error correction adjustment.
[0023] In some embodiments, initiating coarse tuning includes the following steps:
[0024] Determine if the current frequency exceeds the target value;
[0025] If the error exceeds the limit, the coarse adjustment frequency is lowered by one level. When a frame of calibration reference signal is received, it is determined whether the error is less than the coarse adjustment precision.
[0026] If it is less than, then fine-tuning is initiated;
[0027] If it is greater than, return to step: coarsely adjust the frequency down one level;
[0028] If it does not exceed the limit, the coarse adjustment frequency is increased by one level;
[0029] Upon receiving a frame of calibration reference signal, determine whether the error is less than the coarse adjustment precision.
[0030] If it is less than, then fine-tuning is initiated;
[0031] If it is greater than, return to step: coarsely adjust the frequency by one level.
[0032] In some embodiments, the initiation fine-tuning includes the following steps:
[0033] Determine if the current frequency exceeds the target value;
[0034] If the error exceeds the limit, the fine-tuning frequency is lowered by one level. When a frame of calibration reference signal is received, it is determined whether the error is less than the fine-tuning precision.
[0035] If it is less than, then fine-tuning is initiated;
[0036] If it is greater than, return to step: fine-tune the frequency down one level;
[0037] If it does not exceed the limit, then fine-tune the frequency to increase by one level;
[0038] Upon receiving a calibration reference signal, determine whether the error is less than the fine-tuning precision.
[0039] If it is less than, then fine-tuning is initiated;
[0040] If it is greater than, return to step: fine-tune the frequency up one level.
[0041] In some embodiments, when the chip is undergoing soft calibration, the step "after the calibration adjustment is completed, store the calibration configuration parameters of the error calibration adjustment into non-volatile memory" specifically includes the following steps:
[0042] After the calibration and adjustment are completed, the calibration configuration parameters of the error calibration and adjustment are converted into error factors and stored in non-volatile memory.
[0043] In some embodiments, the reference configuration includes a data mode, data content, and baud rate.
[0044] In some embodiments, the following steps are also included:
[0045] After calibration, the chip sends a feedback signal to the host computer.
[0046] In some embodiments, the calibration reference signal is an eight-bit hexadecimal number 00.
[0047] Another technical solution is also provided: a storage medium storing computer instructions and data, which are executed by a processor to perform the asynchronous communication error correction method in the aforementioned differentiated model.
[0048] Unlike existing technologies, the above technical solution first configures calibration target configuration information during error correction, then imports it into the chip and the host computer. The host computer generates a calibration reference signal based on the reference configuration in the calibration target configuration information and continuously sends it to the chip. The chip selects either hard calibration or soft calibration based on the mode configuration in the calibration target configuration information. Hard calibration corrects the clock factor, while soft calibration corrects the baud rate reference line. After receiving the calibration reference signal, the chip performs error calibration adjustment according to the adjustment configuration. Once calibration is complete, the correction configuration parameters are stored in non-volatile memory. When needed, the correction configuration parameters can be retrieved from the non-volatile memory. Through the two modes of hard and soft calibration, a two-dimensional calibration strategy, the appropriate hard or soft calibration can be selected according to the specific situation of the chip, making it the most widely applicable. It also takes into account the three major advantages of high calibration efficiency, low implementation difficulty, and high calibration accuracy.
[0049] The above description of the invention is merely an overview of the technical solution of this application. In order to enable those skilled in the art to better understand the technical solution of this application and to implement it based on the description and drawings, and to make the above-mentioned objectives and other objectives, features and advantages of this application easier to understand, the following description is provided in conjunction with the specific embodiments and drawings of this application. Attached Figure Description
[0050] The accompanying drawings are only used to illustrate the principles, implementation methods, applications, features, and effects of specific embodiments of this application and other related content, and should not be considered as limitations on this application.
[0051] In the accompanying drawings of the instruction manual:
[0052] Figure 1 This is a schematic diagram of the structure of an asynchronous communication frame as described in a specific implementation.
[0053] Figure 2 This is a flowchart illustrating an asynchronous communication error correction method in the differentiated model described in a specific implementation.
[0054] Figure 3 This is a schematic diagram of another process for the asynchronous communication error correction method in the differentiated model described in the specific implementation;
[0055] Figure 4 This is a schematic diagram of another process for the asynchronous communication error correction method in the differentiated model described in the specific implementation;
[0056] Figure 5 This is a flowchart illustrating the core error calibration algorithm of the asynchronous communication error correction method in the differentiated model described in the specific implementation method.
[0057] Figure 6 This is a flowchart illustrating one specific implementation of the error calibration algorithm.
[0058] Figure 7 This is a schematic diagram of one structure of the storage medium described in a specific embodiment.
[0059] The reference numerals used in the above figures are explained as follows:
[0060] 210. Storage medium,
[0061] 220. Processor. Detailed Implementation
[0062] To illustrate the possible application scenarios, technical principles, implementable specific solutions, and achievable objectives and effects of this application in detail, the following description, in conjunction with the listed specific embodiments and accompanying drawings, provides a detailed explanation. The embodiments described herein are merely illustrative of the technical solutions of this application and are therefore intended to limit the scope of protection of this application.
[0063] In this document, the term "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The term "embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment, nor does it specifically limit its independence or connection with other embodiments. In principle, in this application, as long as there are no technical contradictions or conflicts, the technical features mentioned in each embodiment can be combined in any way to form corresponding implementable technical solutions.
[0064] Unless otherwise defined, the technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the use of related terms herein is merely for the purpose of describing particular embodiments and is not intended to limit this application.
[0065] In the description of this application, the term "and / or" is used to describe the logical relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A exists, B exists, and A and B exist simultaneously. Additionally, the character " / " in this document generally indicates that the preceding and following objects have an "or" logical relationship.
[0066] In this application, terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any actual quantity, hierarchy or order relationship between these entities or operations.
[0067] Unless otherwise specified, the use of terms such as “comprising,” “including,” “having,” or other similar expressions in this application is intended to cover non-exclusive inclusion, which does not exclude the presence of additional elements in a process, method, or product that includes the stated elements, such that a process, method, or product that includes a list of elements may include not only those defined elements but also other elements not expressly listed, or elements inherent to such a process, method, or product.
[0068] As understood in the Examination Guidelines, in this application, expressions such as "greater than," "less than," and "exceeding" are understood to exclude the stated number; expressions such as "above," "below," and "within" are understood to include the stated number. Furthermore, in the description of the embodiments in this application, "multiple" means two or more (including two), and similar expressions related to "multiple" are also understood in this way, such as "multiple groups" and "multiple times," unless otherwise explicitly specified.
[0069] In the description of the embodiments of this application, the space-related expressions used, such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "vertical," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," indicate the orientation or positional relationship based on the orientation or positional relationship shown in the specific embodiments or drawings. They are only for the purpose of describing the specific embodiments of this application or for the reader's understanding, and do not indicate or imply that the device or component referred to must have a specific position, a specific orientation, or be constructed or operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.
[0070] Unless otherwise expressly specified or limited, the terms "installation," "connection," "linking," "fixing," and "setting," as used in the description of the embodiments of this application, should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two components or the interaction between two components. For those skilled in the art to which this application pertains, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.
[0071] Asynchronous communication is a commonly used communication method. Compared to synchronous communication, the time slots between transmitted characters in asynchronous communication can be arbitrary. Of course, the receiving end must be ready to receive at all times (if the receiving host is not powered on, then sending characters is meaningless because the receiving end cannot receive them). The sending end can start sending characters at any time, therefore, start and stop bits must be added at the beginning and end of each character to ensure the receiving end can correctly receive each character. After completing the corresponding operations, the internal processor notifies the sending end that a reply has been received through a callback mechanism. Figure 1 The asynchronous communication frame structure shown is illustrated, where S represents the start bit, D0~D7 represent the communication data content, each frame transmits 8 bits of data, D0 is the low-order bit, D7 is the high-order bit, and T represents the stop bit. This application will discuss this in detail with S = 0 and T = 1. The idle bit is an optional bit (TBD) and can be omitted in most cases.
[0072] Please see Figure 2-4 This embodiment provides a method for correcting asynchronous communication errors in a differentiated model, including the following steps:
[0073] Step S110: Configure calibration target configuration information and import it into the chip and host computer. The calibration target configuration information includes target location, reference configuration, mode configuration and adjustment configuration.
[0074] Step S120: The host computer generates a calibration reference signal based on the calibration target configuration information and continuously sends it to the chip;
[0075] Step S130: The chip selects either hard calibration or soft calibration for error correction according to the mode configuration. The hard calibration is clock factor correction, and the soft calibration is baud rate reference line correction.
[0076] Step S140: When the chip receives the calibration reference signal, it performs error correction adjustment according to the adjustment configuration;
[0077] Step S150: After the correction and adjustment are completed, the correction configuration parameters of the error correction and adjustment are stored in the non-volatile memory.
[0078] When performing error correction, the calibration target configuration information is first configured and then imported into the chip and the host computer. The host computer generates a calibration reference signal based on the reference configuration in the calibration target configuration information and continuously sends it to the chip. The chip selects either hard calibration or soft calibration based on the mode configuration in the calibration target configuration information. Hard calibration is clock factor correction, and soft calibration is baud rate reference line correction. After receiving the calibration reference signal, the chip performs error calibration adjustment according to the adjustment configuration. After calibration is completed, the correction configuration parameters for error correction adjustment are stored in non-volatile memory. When needed, the correction configuration parameters can be retrieved from the non-volatile memory. Through the two modes of hard calibration and soft calibration, a two-dimensional calibration strategy can select the appropriate hard calibration or soft calibration according to the specific situation of the chip, making it the most widely applicable. At the same time, it takes into account the three major advantages of high calibration efficiency, low implementation difficulty, and high calibration accuracy.
[0079] In some embodiments, the adjustment configuration includes coarse adjustment accuracy, fine adjustment accuracy, and precision adjustment accuracy;
[0080] "Performing error correction adjustments based on the adjusted configuration" specifically includes the following steps:
[0081] When the chip receives a frame of calibration reference signal, it determines whether the error is less than the fine-tuning accuracy;
[0082] If the precision is less than the fine-tuning precision, then fine-tuning is initiated;
[0083] If the error is greater than the fine-tuning precision, then determine whether the error is greater than the coarse-tuning precision.
[0084] If the value exceeds the coarse adjustment precision, then coarse adjustment is initiated.
[0085] If the precision is less than the coarse adjustment precision, then fine adjustment is initiated.
[0086] The adjustment configuration includes coarse adjustment accuracy, fine adjustment accuracy, and precision adjustment accuracy. Coarse adjustment accuracy is one level of coarse adjustment, fine adjustment accuracy is one level of fine adjustment accuracy, and precision adjustment accuracy is one level of precision. These accuracy levels can be set according to actual needs, such as 3% for coarse adjustment, 1% for fine adjustment, and 0.5% for precision adjustment. When the chip receives a calibration reference signal, it determines whether the error is less than the fine adjustment accuracy. If it is, fine adjustment is initiated, adjusting according to the fine adjustment accuracy. If the error is greater than the fine adjustment accuracy, it determines whether it is greater than the coarse adjustment accuracy. If it is greater, coarse adjustment is initiated, adjusting according to the coarse adjustment accuracy. If it is less than the coarse adjustment accuracy, fine adjustment is initiated, adjusting according to the fine adjustment accuracy. This improves calibration efficiency and accuracy. In other embodiments, two adjustment methods can be combined, or only one adjustment method can be used, such as a combination of fine and fine adjustment, or only fine adjustment.
[0087] In some embodiments, the fine-tuning process specifically includes the following steps:
[0088] Record the current error as the minimum error, fine-tune the frequency down one level, and then determine whether the error has decreased;
[0089] If the error decreases, update the current error to the minimum error and return to step: fine-tuning the frequency down one level;
[0090] If the error increases, the fine-tuning frequency is increased by one stop, and then it is determined whether the error has decreased.
[0091] If the error decreases, update the current error to the minimum error and return to step: fine-tuning the frequency by one level;
[0092] If the error increases, the fine-tuning frequency is lowered by one stop to complete the error correction adjustment.
[0093] When fine-tuning is initiated, the current error is recorded as the minimum error. The fine-tuning frequency is then lowered by one level. After receiving a frame of calibration reference signal, it is determined whether the error has decreased. If it has decreased, the current error is updated to the minimum error, and the process returns to the step of lowering the fine-tuning frequency by one level to re-determine whether the error has decreased. If the error is determined to have increased, the fine-tuning frequency is raised by one level. Then, upon receiving a frame of calibration reference signal, it is determined whether the error has decreased. If the error is small, the process returns to raising the fine-tuning frequency by one level and re-determining whether the error has decreased. If the error is determined to have increased, the fine-tuning frequency is lowered by one level, completing the error correction and adjustment. This ensures that the error is less than the fine-tuning accuracy. In other embodiments, when initiating fine-tuning, the fine-tuning frequency can first be raised by one level and then lowered by one level.
[0094] In some embodiments, initiating coarse tuning includes the following steps:
[0095] Determine if the current frequency exceeds the target value;
[0096] If the error exceeds the limit, the coarse adjustment frequency is lowered by one level. When a frame of calibration reference signal is received, it is determined whether the error is less than the coarse adjustment precision.
[0097] If it is less than, then fine-tuning is initiated;
[0098] If it is greater than, return to step: coarsely adjust the frequency down one level;
[0099] If it does not exceed the limit, the coarse adjustment frequency is increased by one level;
[0100] Upon receiving a frame of calibration reference signal, determine whether the error is less than the coarse adjustment precision.
[0101] If it is less than, then fine-tuning is initiated;
[0102] If it is greater than, return to step: coarsely adjust the frequency by one level.
[0103] When coarse adjustment is initiated, the system first checks if the current frequency exceeds the target value. If it does, the coarse adjustment frequency is lowered by one level. Then, a frame from the calibration reference chip is received, and the error is checked against the coarse adjustment precision. If the error is less, fine adjustment is initiated. If the error is greater than the coarse adjustment precision, the system returns to lowering the coarse adjustment frequency by one level and continues adjusting the frequency until the error is less than the coarse adjustment precision, at which point fine adjustment is initiated. Conversely, if the current frequency does not exceed the target value, the coarse adjustment frequency is raised by one level. A frame from the calibration reference signal is received, and the error is checked against the coarse adjustment precision. If the error is less, fine adjustment is initiated. If the error is greater, the system returns to the previous step: raising the coarse adjustment frequency by one level and continuing coarse adjustment until the error is less than the coarse adjustment precision, at which point fine adjustment is initiated. The system can determine whether to raise or lower the coarse adjustment frequency by one level based on the target value, allowing for rapid coarse adjustment. In other embodiments, when coarse adjustment is initiated, the coarse adjustment frequency can be lowered by one level first, and then it can be determined whether the error has decreased. If it has decreased, it can be determined whether the error is less than the coarse adjustment frequency. If it is less, fine adjustment is initiated. If it is greater than the coarse adjustment frequency, the coarse adjustment frequency is lowered by one level until the error is less than the coarse adjustment frequency. If the error increases, the coarse adjustment frequency is raised by one level until the error is less than the coarse adjustment frequency.
[0104] In some embodiments, the initiation fine-tuning includes the following steps:
[0105] Determine if the current frequency exceeds the target value;
[0106] If the error exceeds the limit, the fine-tuning frequency is lowered by one level. When a frame of calibration reference signal is received, it is determined whether the error is less than the fine-tuning precision.
[0107] If it is less than, then fine-tuning is initiated;
[0108] If it is greater than, return to step: fine-tune the frequency down one level;
[0109] If it does not exceed the limit, then fine-tune the frequency to increase by one level;
[0110] Upon receiving a calibration reference signal, determine whether the error is less than the fine-tuning precision.
[0111] If it is less than, then fine-tuning is initiated;
[0112] If it is greater than, return to step: fine-tune the frequency up one level.
[0113] When fine-tuning is initiated, the system first checks if the current frequency exceeds the target value. If it does, the frequency is first lowered by one stop. Then, a frame from the calibration reference chip is received, and the error is checked against the fine-tuning precision. If the error is less, fine-tuning is initiated. If the error is greater than the fine-tuning precision, the system returns to lowering the frequency by one stop and continues adjusting the frequency until the error is less than the fine-tuning precision, at which point fine-tuning is initiated. Conversely, if the current frequency does not exceed the target value, the frequency is raised by one stop. A frame from the calibration reference signal is received, and the error is checked against the fine-tuning precision. If the error is less, fine-tuning is initiated. If the error is greater, the system returns to the previous step: raising the frequency by one stop and continuing fine-tuning until the error is less than the fine-tuning precision, at which point fine-tuning is initiated. Fine-tuning can be performed by raising or lowering the frequency by one stop based on the target value, allowing for rapid completion of fine-tuning. In other embodiments, when fine-tuning is initiated, the fine-tuning frequency can be lowered by one level first, and then it can be determined whether the error has decreased. If it has decreased, it can be determined whether the error is less than the fine-tuning frequency. If it is less, fine-tuning is initiated. If it is greater than the fine-tuning frequency, the fine-tuning frequency is lowered by one level until the error is less than the fine-tuning frequency. If the error increases, the fine-tuning frequency is raised by one level until the error is less than the fine-tuning frequency.
[0114] like Figure 5 The core error calibration algorithm of the asynchronous communication error correction method in the differentiated model is analyzed and divided into five stages: target point presetting, coarse adjustment, fine adjustment, precision adjustment, and error factor conversion. The host computer (external) continuously sends data 8'h00 as the calibration reference signal, and the chip (internal) provides feedback 8'h55 upon calibration completion.
[0115] Target pre-setting:
[0116] (coarse tuning interface) freq_ctune = freq_ctune_ts
[0117] (fine tuning interface) freq_ftune = freq_ftune_ts
[0118] (exact tuning interface)freq_etune = freq_etune_ts
[0119] `freq_ctune_ts`, `freq_ftune_ts`, and `freq_etune_ts` are preset theoretical values. For example, assuming `freq_ctune`, `freq_ftune`, and `freq_etune` are all 6 bits wide, `freq_ctune` has a precision of 3%, `freq_ftune` has a precision of 1%, and `freq_etune` has a precision of 0.5%, the preset theoretical intermediate value for the target position is:
[0120] freq_ctune_ts = 6'b01_1111
[0121] freq_ftune_ts = 6'b01_1111
[0122] freq_etune_ts = 6'b01_1111
[0123] All theoretical values are derived from linear relationships, specifically imported from target information (target location).
[0124] Coarse adjustment:
[0125]
[0126] Fine-tuning:
[0127]
[0128] Fine-tuning:
[0129]
[0130] In some embodiments, when the chip is undergoing soft calibration, the step "after the calibration adjustment is completed, store the calibration configuration parameters of the error calibration adjustment into non-volatile memory" specifically includes the following steps:
[0131] After the calibration and adjustment are completed, the calibration configuration parameters of the error calibration and adjustment are converted into error factors and stored in non-volatile memory.
[0132] Hard calibration will be applied to the clock circuit itself. Its advantages are that it directly calibrates the clock output, is convenient to use, and is highly efficient. Its disadvantages are that it requires the support of hardware clock circuit functions (requiring corresponding adjustment functions and interfaces) and generally has limited accuracy. After calibration, the three-level (coarse adjustment, fine adjustment, and fine adjustment) calibration configuration words are directly stored in non-volatile memory. When needed, the configuration words are directly retrieved and loaded into the corresponding interface.
[0133] Soft calibration is applied to the baud rate counter circuit. Its advantages are flexibility and guaranteed accuracy. Its disadvantages are inconvenience, the need for indirect algorithm compensation, and low efficiency. After calibration, the three-level (coarse adjustment, fine adjustment, and fine adjustment) calibration configuration words need to be converted into error factors (percentages) and stored in non-volatile memory. When needed, the error factors need to be retrieved and compensated according to the percentage to obtain accurate results.
[0134] The two components work together in the baud rate generator circuit to optimize the communication scheme.
[0135] In some embodiments, the reference configuration includes a data mode, data content, and baud rate. The data mode is configurable, with four options: 5-bit, 6-bit, 7-bit, and 8-bit. D5, D6, and D7 are also optional bits (TBD). The data content is configurable and ensures only one 0-to-1 data step from the start bit to the end bit. It generates different low-level (calibration sampling level) widths. The baud rate is configurable to adapt to rapid calibration requirements. For example, communication data D[7:0]==8'h00, in 8-bit data mode, will generate a low-level voltage with a 9-bit baud rate width. The communication signal channel between the host computer and the chip is the calibration reference signal channel. For example, when the reference signal baud rate is 115200, in 8-bit data mode, the transmitted data is 8'h00, the calibration clock target is 20MHz and 48MHz, and the sampling period targets are: 20000000*9 / 115200 = 1562.50 and 48000000*9 / 115200 = 3750.00, respectively. The calibration reference signal channel is multiplexed with the communication channel, simplifying the system scale. The calibration reference signal is an eight-bit hexadecimal number 00.
[0136] In some embodiments, the following steps are also included:
[0137] After calibration, the chip sends a feedback signal to the host computer.
[0138] Once calibration is complete, the chip sends a feedback signal to the host computer, notifying it that calibration is finished, and the host computer stops sending calibration reference signals. In other embodiments, however, the chip directly disconnects from the host computer after calibration is complete.
[0139] In some embodiments, such as Figure 6 The flowchart of the error calibration algorithm is shown below:
[0140] S01: Calibrate target configuration, including six types of information: preset target position, reference configuration, mode configuration, coarse adjustment accuracy, fine adjustment accuracy, and precision adjustment accuracy;
[0141] S02: Preset information takes effect, importing on-chip algorithms and host computer;
[0142] S03: After the chip receives a frame of valid data, if the error is less than the fine-tuning precision (e.g., 1%), proceed to S17; otherwise, proceed to S04.
[0143] S04: After the chip receives a frame of valid data, if the error is less than the coarse adjustment accuracy (e.g., 3%), proceed to S05; otherwise, proceed to S11.
[0144] S05: Fine-tuning startup;
[0145] S06: If the frequency exceeds the target value, i.e. nowa_dif[h]=0, it is a positive error, then proceed to S07; otherwise proceed to S08.
[0146] S07: The fine-tuning frequency drops one level; freq_ftune + 6'h1;
[0147] S08: The fine-tuning frequency rises one level; freq_ftune - 6'h1;
[0148] S09: After the chip receives a frame of valid data, if the error is less than the fine-tuning accuracy (such as 1%), go to S17 for fine-tuning, otherwise go to S07 to continue fine-tuning;
[0149] S10: After the chip receives a frame of valid data, if the error is less than the fine-tuning accuracy (such as 1%), go to S17 for fine-tuning, otherwise go to S08 to continue fine-tuning;
[0150] S11: Coarse-tuning starts;
[0151] S12: If the frequency exceeds the target value, that is, nowa_dif[h] = 0, for positive error, go to S13, otherwise go to S14;
[0152] S13: The coarse-tuning frequency drops one level; freq_ctune + 6'h1;
[0153] S14: The coarse-tuning frequency rises one level; freq_ctune - 6'h1;
[0154] S15: After the chip receives a frame of valid data, if the error is less than the coarse-tuning accuracy (such as 3%), go to S05 for fine-tuning, otherwise go to S13 to continue coarse-tuning;
[0155] S16: After the chip receives a frame of valid data, if the error is less than the coarse-tuning accuracy (such as 3%), go to S05 for fine-tuning, otherwise go to S14 to continue fine-tuning;
[0156] S17: Fine-tuning starts; Record the current minimum error dif_r = nowa_dif;
[0157] S18: The precise tuning frequency drops one level; freq_etune + 6'h1;
[0158] S19: If the error decreases nowa_dif < dif_r, update the minimum error dif_r = nowa_dif, and at the same time go to S18, otherwise go to S20;
[0159] S20: The precise tuning frequency rises one level; freq_etune - 6'h1;
[0160] S21: If the error decreases nowa_dif < dif_r, update the minimum error dif_r = nowa_dif, and at the same time go to S20, otherwise go to S22;
[0161] S22: Precise frequency adjustment down one notch; freq_etune+6'h1;
[0162] S23: If it is a soft calibration, then convert it to an error factor;
[0163] S24: Completed.
[0164] A novel asynchronous calibration algorithm is proposed, which combines high calibration efficiency, low implementation difficulty, and high calibration accuracy. Two calibration modes, hard calibration and soft calibration, are presented to maximize the system's applicability. The calibration reference signal channel and communication channel are multiplexed, simplifying system scale. It can be widely applied to processor design, especially in scenarios requiring miniaturization, low cost, low power consumption, and uncontrollable process variation.
[0165] Please see Figure 7 In another embodiment, a storage medium 210 stores computer instructions and data, which are executed by a processor 220 to perform the asynchronous communication error correction method in the differentiated model described above.
[0166] When performing error correction, the calibration target configuration information is first configured and then imported into the chip and the host computer. The host computer generates a calibration reference signal based on the reference configuration in the calibration target configuration information and continuously sends it to the chip. The chip selects either hard calibration or soft calibration based on the mode configuration in the calibration target configuration information. Hard calibration is clock factor correction, and soft calibration is baud rate reference line correction. After receiving the calibration reference signal, the chip performs error calibration adjustment according to the adjustment configuration. After calibration is completed, the correction configuration parameters for error correction adjustment are stored in non-volatile memory. When needed, the correction configuration parameters can be retrieved from the non-volatile memory. Through the two modes of hard calibration and soft calibration, a two-dimensional calibration strategy can select the appropriate hard calibration or soft calibration according to the specific situation of the chip, making it the most widely applicable. At the same time, it takes into account the three major advantages of high calibration efficiency, low implementation difficulty, and high calibration accuracy.
[0167] Finally, it should be noted that although the above embodiments have been described in the text and drawings of this application, this should not limit the scope of patent protection of this application. Any technical solutions that are based on the essential concept of this application and utilize the content described in the text and drawings of this application, resulting in equivalent structural or procedural substitutions or modifications, as well as the direct or indirect application of the technical solutions of the above embodiments to other related technical fields, are all included within the scope of patent protection of this application.
Claims
1. A method for correcting asynchronous communication errors in a differentiated model, characterized in that, Includes the following steps: Configure calibration target configuration information and import it into the chip and host computer. The calibration target configuration information includes target position, reference configuration, mode configuration and adjustment configuration. The reference configuration includes data mode, data content and baud rate. The adjustment configuration includes coarse adjustment accuracy, fine adjustment accuracy and fine adjustment accuracy. The host computer generates a calibration reference signal based on the calibration target configuration information and continuously sends it to the chip. The chip selects either hard calibration or soft calibration for error correction based on the mode configuration. The hard calibration is clock factor correction, and the soft calibration is baud rate reference line correction. When the chip receives the calibration reference signal, it performs error correction adjustments according to the adjustment configuration. After the calibration and adjustment are completed, the calibration configuration parameters for error calibration and adjustment are stored in non-volatile memory.
2. The asynchronous communication error correction method in the differentiated model according to claim 1, characterized in that, The error correction adjustment based on the adjusted configuration specifically includes the following steps: When the chip receives a frame of calibration reference signal, it determines whether the error is less than the fine-tuning accuracy; If the precision is less than the fine-tuning precision, then fine-tuning is initiated; If the error is greater than the fine-tuning precision, then determine whether the error is greater than the coarse-tuning precision. If the value exceeds the coarse adjustment precision, then coarse adjustment is initiated. If the precision is less than the coarse adjustment precision, then fine adjustment is initiated.
3. The asynchronous communication error correction method in the differentiated model according to claim 2, characterized in that, The fine-tuning process specifically includes the following steps: Record the current error as the minimum error, fine-tune the frequency down one level, and then determine whether the error has decreased; If the error decreases, update the current error to the minimum error and return to step: fine-tuning the frequency down one level; If the error increases, the fine-tuning frequency is increased by one stop, and then it is determined whether the error has decreased. If the error decreases, update the current error to the minimum error and return to step: fine-tuning the frequency by one level; If the error increases, the fine-tuning frequency is lowered by one stop to complete the error correction adjustment.
4. The asynchronous communication error correction method in the differentiated model according to claim 2, characterized in that, The coarse-tuning process includes the following steps: Determine if the current frequency exceeds the target value; If it exceeds the limit, the coarse adjustment frequency is lowered by one level. When a frame of calibration reference signal is received, it is determined whether the error is less than the coarse adjustment accuracy. If it is less than, then fine-tuning is initiated; If it is greater than, return to step: coarsely adjust the frequency down one level; If it does not exceed the limit, the coarse adjustment frequency is increased by one level; When a frame of calibration reference signal is received, it is determined whether the error is less than the coarse adjustment accuracy; If it is less than, then fine-tuning is initiated; If it is greater than, return to step: coarsely adjust the frequency by one level.
5. The asynchronous communication error correction method in the differentiated model according to claim 2, characterized in that, The startup fine-tuning includes the following steps: Determine if the current frequency exceeds the target value; If it exceeds the limit, the fine-tuning frequency is lowered by one level. When a frame of calibration reference signal is received, it is determined whether the error is less than the fine-tuning accuracy. If it is less than, then fine-tuning is initiated; If it is greater than, return to step: fine-tune the frequency down one level; If it does not exceed the limit, then fine-tune the frequency to increase by one level; When a frame of calibration reference signal is received, it is determined whether the error is less than the fine-tuning accuracy; If it is less than, then fine-tuning is initiated; If it is greater than, return to step: fine-tune the frequency up one level.
6. The asynchronous communication error correction method in the differentiated model according to claim 1, characterized in that, When the chip undergoes soft calibration, after the aforementioned calibration and adjustment steps are completed, storing the calibration configuration parameters for error calibration and adjustment into non-volatile memory specifically includes the following steps: After the calibration and adjustment are completed, the calibration configuration parameters of the error calibration and adjustment are converted into error factors and stored in non-volatile memory.
7. The asynchronous communication error correction method in the differentiated model according to claim 1, characterized in that, It also includes the following steps: After calibration, the chip sends a feedback signal to the host computer.
8. The asynchronous communication error correction method in the differentiated model according to claim 1, characterized in that, The calibration reference signal is an eight-bit hexadecimal number.
9. A storage medium storing computer instructions and data, characterized in that, The computer instructions and data are executed by the processor to perform the asynchronous communication error correction method in the differentiated model as described in any one of claims 1-8.