In-memory computing circuit, control method and chip
By using decoupling modules and control signal design in the in-memory computing circuit, the bit line voltage nonlinearity problem was solved, the calculation accuracy was improved and the representation of multi-bit data was simplified, thus achieving higher accuracy of the in-memory computing system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING INST OF INTELLIGENT TECH INST OF MICROELECTRONICS OF THE CHINESE ACAD OF
- Filing Date
- 2022-11-30
- Publication Date
- 2026-06-16
AI Technical Summary
In traditional in-memory computing systems, the bit line voltage drops at a non-linear rate, leading to quantization errors in the analog-to-digital conversion circuit, as well as write interference and difficulties in representing multi-bit data.
An in-memory computing circuit is used, and the on/off state of the first switch is controlled by a decoupling module to ensure that the change in the second bit line voltage is linearly related to the calculation result. The decoupling module includes the second and third switches, combined with a transmission gate and an inverter, to control the input mode of the signal to improve linearity.
It reduces the quantization error of the analog-to-digital conversion circuit, improves the accuracy of the in-memory computing system, avoids write interference, and simplifies the representation of multi-bit data.
Smart Images
Figure CN115862705B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to an in-memory computing circuit, control method, and chip. Background Technology
[0002] Using analog circuits to implement in-memory computing systems can achieve extremely high energy efficiency. However, the analog voltage represented by the calculation results is more susceptible to PVT and parasitic parameters, leading to decreased accuracy. Ideally, the calculated analog voltage should have a linear relationship with the actual result. However, in traditional in-memory array structures, the bit line voltage drops non-linearly during bit line discharge, causing quantization errors in the analog-to-digital conversion circuit. Reducing the effective signal range of the analog voltage or decreasing the number of bits in the input data is clearly not a good enough solution. Traditional solutions reduce the word line voltage, which to some extent expands the signal tolerance of transistors in the saturation region. However, its drawbacks are also significant. First, an excessive drop in bit line voltage may cause SRAM cells that originally stored 1s to flip, resulting in "write interference." Second, when the input is multi-bit data, if the word line voltage reflects the input data, its relationship with the square of the discharge current remains non-linear. Furthermore, if pulse width is used to represent multi-bit input data, controlling the pulse height introduces difficulties and interference factors. Summary of the Invention
[0003] The purpose of this invention is to provide an in-memory computing circuit, control method, and chip that makes the bit line voltage and the calculation result linearly related, reduces the quantization error of the analog-to-digital conversion circuit, and improves the accuracy of the in-memory computing system.
[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0005] One aspect of this invention provides an in-memory computing circuit, comprising a transmission line and at least one in-memory computing sub-circuit. Each of the at least one in-memory computing sub-circuit is connected to the transmission line. The transmission line transmits analog signals from the at least one in-memory computing sub-circuit to an analog-to-digital converter (ADC) circuit, which converts the analog signals of the at least one in-memory computing sub-circuit into digital signals. The in-memory computing sub-circuit includes: a storage module with a first bit line and a second bit line connected to its two ends; a first switch connected to the ADC circuit via the transmission line; and a decoupling module, with the second bit line connected to the control terminal of the first switch via the decoupling module. During in-memory computing operations, the storage module controls the on / off state of the first switch via the decoupling module to improve the linearity between the change in the second bit line voltage and the calculation result.
[0006] In some embodiments, the decoupling module includes a second switch and a third switch, wherein the input terminal of the second switch is connected to the second bit line, the output terminal of the second switch is connected to the control terminal of the third switch, and the third switch is connected to the control terminal of the first switch.
[0007] In some embodiments, the in-memory computing sub-circuit further includes a fourth switch and a fifth switch. The input terminal of the fourth switch is connected to a first control signal, and the output terminal is connected to the first bit line. The input terminal of the fifth switch is connected to a second control signal, and the output terminal is connected to the second bit line. The control terminals of the second switch, the fourth switch, and the fifth switch are all connected to a third control signal. When the second switch is turned on, the fourth switch and the fifth switch are turned off. When the fourth switch and the fifth switch are turned on, the second switch is turned off.
[0008] In some embodiments, the second switch uses a second transmission gate, the fourth switch uses a fourth transmission gate, the fifth switch uses a fifth transmission gate, the in-memory computing sub-circuit further includes a first inverter, the third control signal is connected to the input terminal of the first inverter, the first control terminal of the second transmission gate, the second control terminal of the fourth transmission gate and the second control terminal of the fifth transmission gate, and the output terminal of the first inverter is connected to the second control terminal of the second transmission gate, the first control terminal of the fourth gate and the first control terminal of the fifth gate.
[0009] In some embodiments, the first switch is a high-level start switch, and the in-memory calculation sub-circuit further includes a sixth transmission gate. The first control terminal of the sixth transmission gate is connected to the output terminal of the first inverter, the second control terminal of the sixth transmission gate is connected to the third control signal, the input terminal of the sixth transmission gate is connected to the control terminal of the first switch, and the output terminal is grounded. This is used so that when the third switch controls the first switch to turn off, the sixth transmission gate discharges the control terminal of the first switch to ground, thereby improving the accuracy of in-memory calculation.
[0010] In some embodiments, the storage module employs an SRAM storage array, which includes at least one SRAM storage cell. The SRAM storage cell includes a sixth switch, a seventh switch, a second inverter, and a third inverter. The control terminals of the sixth and seventh switches are both connected to word lines. One end of the sixth switch is connected to the first bit line, and the other end is connected to the input terminal of the second inverter and the output terminal of the third inverter. The output terminal of the second inverter and the input terminal of the third inverter are both connected to one end of the seventh switch, and the other end of the seventh switch is connected to the second bit line.
[0011] One aspect of this invention provides a control method for an in-memory computing circuit, applied to the in-memory computing circuit described above. The control method includes an in-memory computing method, comprising: controlling the input of a third control signal to a low level, opening the second transmission gate, and closing the fourth, fifth, and sixth transmission gates; the second transmission gate transmitting the potential state of the second bit line to the third switch; the third switch controlling the on / off state of the first switch according to the potential state of the second bit line; and the transmission line reading the analog signal output by the first switch according to the on / off state of the first switch, and transmitting the analog signal to the analog-to-digital conversion circuit.
[0012] In some embodiments, the control method includes a data writing method, which includes: controlling the third control signal to input a high level, turning off the second transmission gate, and turning on the fourth, fifth, and sixth transmission gates; controlling the first control signal and the second control signal to input two level signals respectively; controlling the word line to turn on the SRAM memory cell to be written, and the first control signal and the second control signal to write the level signals into the SRAM memory cell to be written.
[0013] In some embodiments, the control method includes a data reading method, which includes: controlling the third control signal to input a high level, turning off the second transmission gate, and turning on the fourth, fifth, and sixth transmission gates; controlling both the first and second control signals to input high-level signals; controlling the word line to turn on the SRAM memory cell being read, generating a voltage drop on the first or second bit line, and amplifying the voltage drop to read the result.
[0014] One aspect of this invention provides a chip that includes the in-memory computing circuit described above.
[0015] According to an embodiment of the present invention, an in-memory computing circuit, control method, and chip have at least the following beneficial effects: This application decouples the second bit line from the control terminal of the first switch, thereby improving the linearity of the bit line voltage relative to the calculation result in principle. This ensures that "write interference" will not occur and also facilitates the modulation of discharge speed and input data. Compared with traditional methods, it has the characteristics of high accuracy and convenient adjustment. The bit line voltage and the calculation result have a linear relationship, reducing the quantization error of the analog-to-digital conversion circuit and improving the accuracy of the in-memory computing system.
[0016] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the internal computing circuit of this application according to an embodiment;
[0019] Figure 2 This is a flowchart of the in-memory calculation method according to an embodiment of the present application;
[0020] Figure 3 A flowchart of the data writing method according to an embodiment of this application;
[0021] Figure 4 This is a flowchart of a data reading method according to an embodiment of this application. Detailed Implementation
[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0023] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0024] The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0025] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connection," "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0026] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.
[0027] To quantitatively represent the final simulated multiplication-accumulation result, the working principle of in-memory computation is written as the following expression:
[0028]
[0029] In the formula, the input IN and the weight W are unknown single-bit digital quantities, and the unit drop in bit line voltage ΔV is the value of the bit line voltage. BL This is achieved by discharging the bit line capacitor for a fixed period of time. In this application, the operating voltage is set to 1.2V, the discharge time is determined by a pulse generator, and the bit line capacitor is determined by a set capacitance value. The final output voltage variation range is designed to be between 0.3V and 1.2V.
[0030] In real-world conditions, the rate of decrease in bit line voltage is often influenced by various factors, such as the operating region of the MOSFET, parameter changes due to PVT, and parasitic capacitance of the bit line. Among these factors, the most important is the operating region of the MOSFET, which largely determines the discharge rate in principle. In the linear region, the IV characteristics of a MOSFET are as follows:
[0031]
[0032] In the saturation region, the IV characteristics of a MOSFET are as follows:
[0033]
[0034] It can be seen that the current value of the MOSFET in the saturation region depends only on the overdrive voltage (V). GS -V THFurthermore, the current of a MOS transistor operating in the linear region is also affected by the source-drain voltage difference. In traditional memory array structures, during bit line discharge, the source voltage continuously decreases while the gate voltage remains high. This results in a constant overdrive voltage, but the source-drain voltage decreases, causing the operating region of the NMOS transfer transistor in the SRAM memory cell to transition from the saturation region to the linear region as the bit line voltage decreases. The slower rate of bit line voltage decrease leads to nonlinearity, which in turn causes quantization errors in the analog-to-digital converter (ADC). To mitigate this effect, the lower limit of the operating region can be raised, but this reduces the signal tolerance, placing even greater pressure on the quantization process of the ADC.
[0035] The in-memory computing circuit of this application embodiment is briefly described below:
[0036] According to some embodiments, such as Figure 1 As shown, this application provides an in-memory computing circuit, which includes a transmission line GBL and at least one in-memory computing sub-circuit 10. The at least one in-memory computing sub-circuit 10 is connected to the transmission line GBL. The transmission line GBL transmits the analog signals of the at least one in-memory computing sub-circuit 10 to an analog-to-digital converter (ADC) circuit for converting the analog signals of the at least one in-memory computing sub-circuit 10 into digital signals. The in-memory computing sub-circuit 10 includes:
[0037] A storage module, wherein the two ends of the storage module are respectively connected to a first bit line BL and a second bit line BLB;
[0038] A first switch is connected to an analog-to-digital converter circuit via the transmission line GBL.
[0039] A decoupling module is provided, through which the second bit line BLB is connected to the control terminal of the first switch. During memory calculation operations, the memory module controls the on / off state of the first switch through the decoupling module to improve the linearity between the voltage change of the second bit line BLB and the calculation result.
[0040] In some embodiments of this application, such as Figure 1 As shown, the first switch uses a first MOSFET N1, which is an NMOS transistor. In other embodiments, it can also be a transistor or other device with switching function. This embodiment does not limit the first switch. The source of the first MOSFET N1 is connected to the IN port that outputs a low-level signal, the drain of the first MOSFET N1 is connected to the transmission line GBL, and the gate of the first MOSFET N1 is connected to the decoupling module.
[0041] Based on the above embodiments, if a decoupling module is not provided, when the voltage drop of the second bit line BLB exceeds the threshold voltage of the first MOSFET N1, the current flowing through the first MOSFET N1 will decrease, which will further cause the transmission line GBL to read the analog signal of the first MOSFET N1 as nonlinear. After the transmission line GBL transmits the nonlinear analog signal to the analog-to-digital converter circuit, the result calculated by the analog-to-digital converter circuit deviates significantly from the actual result.
[0042] In this application, the signal of the second bit line BLB controls the on / off state of the first MOS transistor N1 after passing through the decoupling module. After setting the decoupling module, even if the voltage drop rate of the second bit line BLB is nonlinear, the current through the first MOS transistor N1 will remain stable, thereby improving the linearity between the change of the second bit line BLB voltage and the calculation result.
[0043] This application decouples the second bit line BLB from the control terminal of the first MOSFET N1, fundamentally improving the linearity of the bit line voltage relative to the calculated result. This ensures that "write interference" is not encountered and also facilitates the modulation of discharge speed and input data. Compared to traditional methods, it features high accuracy and convenient adjustment.
[0044] The following is in conjunction with the appendix to this instruction manual. Figure 1 The in-memory computing circuit of this application will be further described in detail.
[0045] According to some embodiments, such as Figure 1 As shown, the decoupling module includes a second switch and a third switch. The input terminal of the second switch is connected to the second bit line BLB, and the output terminal is connected to the control terminal of the third switch. The third switch is connected to the control terminal of the first switch.
[0046] Based on the above embodiments, when the voltage of the second bit line BLB changes nonlinearly, the current passing through the first MOS transistor N1 remains unchanged after decoupling through the second switch and the third switch.
[0047] According to some embodiments, such as Figure 1 As shown, the in-memory computing sub-circuit 10 further includes a fourth switch and a fifth switch. The input terminal of the fourth switch is connected to the first control signal BL_CRG, and the output terminal is connected to the first bit line BL. The input terminal of the fifth switch is connected to the second control signal BLB_CRG, and the output terminal is connected to the second bit line BLB. The control terminals of the second switch, the fourth switch, and the fifth switch are all connected to the third control signal RW_CTRL. When the second switch is turned on, the fourth switch and the fifth switch are turned off. When the fourth switch and the fifth switch are turned on, the second switch is turned off.
[0048] Based on the above embodiments, during both reading and writing data, the second switch needs to be turned off, while the fourth and fifth switches are turned on. When reading data, both the first control signal BL_CRG and the second control signal BLB_CRG are input with a high-level signal; the word line WL controls the SRAM storage cell 1 being read to be turned on, and a voltage drop is generated on either the first bit line BL or the second bit line BLB. This voltage drop is amplified to read the data result. When writing data, the first control signal BL_CRG and the second control signal BLB_CRG are input with two level signals respectively; the word line WL controls the SRAM storage cell 1 being written to be turned on, and the first control signal BL_CRG and the second control signal BLB_CRG write the level signals into the SRAM storage cell 1 being written to.
[0049] According to some embodiments, such as Figure 1 As shown, the second switch uses the second transmission gate TG2, the fourth switch uses the fourth transmission gate TG4, and the fifth switch uses the fifth transmission gate TG5. The in-memory calculation sub-circuit 10 also includes a first inverter INV1. The third control signal RW_CTRL is connected to the input terminal of the first inverter INV1, the first control terminal of the second transmission gate TG2, the second control terminal of the fourth transmission gate TG4, and the second control terminal of the fifth transmission gate TG5. The output terminal of the first inverter INV1 is connected to the second control terminal of the second transmission gate TG2, the first control terminal of the fourth transmission gate TG4, and the first control terminal of the fifth transmission gate TG5.
[0050] Based on the above embodiments, during both reading and writing data, it is necessary to control the second transmission gate TG2 to be turned off, and the fourth transmission gate TG4 and the fifth transmission gate TG5 to be turned on. When reading data, both the first control signal BL_CRG and the second control signal BLB_CRG are controlled to input high-level signals to the first bit line BL and the second bit line BLB; the word line WL controls the SRAM memory cell 1 being read to be turned on, generating a voltage drop on either the first bit line BL or the second bit line BLB. This voltage drop is amplified to read the data result. When writing data, the first control signal BL_CRG and the second control signal BLB_CRG are controlled to input two level signals respectively; the word line WL controls the SRAM memory cell 1 being written to be turned on, and the first control signal BL_CRG and the second control signal BLB_CRG write the level signals into the SRAM memory cell 1 being written to.
[0051] According to some embodiments, such as Figure 1As shown, the first switch is a high-level start switch. The in-memory calculation sub-circuit 10 also includes a sixth transmission gate TG6. The first control terminal of the sixth transmission gate TG6 is connected to the output terminal of the first inverter INV1, the second control terminal of the sixth transmission gate TG6 is connected to the third control signal RW_CTRL, the input terminal of the sixth transmission gate TG6 is connected to the control terminal of the first switch, and the output terminal is grounded. This is used so that when the third switch controls the first switch to turn off, the sixth transmission gate TG6 will ground the control terminal of the first switch to improve the accuracy of in-memory calculation.
[0052] Based on the above embodiments, such as Figure 1 As shown, the first switch uses a first MOSFET N1, and the third switch uses a third MOSFET P1. The first MOSFET N1 is an NMOS transistor, and the third MOSFET P1 is a PMOS transistor. Figure 1 As shown, during in-memory computation, the third control signal RW_CTRL is low, the second transmission gate TG2 is turned on, and the fourth transmission gate TG4, the fifth transmission gate TG5 and the sixth transmission gate TG6 are turned off. The gate of the third MOS transistor P1 receives the level signal of the second bit line BLB through the second transmission gate TG2. The source of the third MOS transistor P1 is connected to the power supply VG, and the drain is connected to the gate of the first MOS transistor N1.
[0053] During data reading and writing, the third control signal RW_CTRL is high, the second transmission gate TG2 is off, the third MOSFET P1 is off, the first MOSFET N1 is off, and the fourth transmission gate TG4, the fifth transmission gate TG5, and the sixth transmission gate TG6 are on. During data reading and writing, the sixth transmission gate TG6 discharges the control terminal of the first switch to ground to improve the accuracy of in-memory calculations.
[0054] According to some embodiments, such as Figure 1 As shown, the storage module uses an SRAM storage array, which includes at least one SRAM storage cell 1. The SRAM storage cell 1 includes a sixth switch, a seventh switch, a second inverter INV2, and a third inverter INV3. The control terminals of the sixth and seventh switches are both connected to the word line WL. One end of the sixth switch is connected to the first bit line BL, and the other end is connected to the input terminal of the second inverter INV2 and the output terminal of the third inverter INV3. The output terminal of the second inverter INV2 and the input terminal of the third inverter INV3 are both connected to one end of the seventh switch, and the other end of the seventh switch is connected to the second bit line BLB.
[0055] The sixth and seventh switches both use MOSFETs, and the data is stored at the connection point between the input of the second inverter INV2 and the output of the third inverter INV3.
[0056] The technical solutions of the embodiments of this application are briefly described below:
[0057] According to some embodiments, this application provides a control method for an in-memory computing circuit, applied to the in-memory computing circuit described above. The control method includes an in-memory computing method, which includes:
[0058] Step 101: Control the third control signal RW_CTRL to input a low level, the second transmission gate TG2 is turned on, the fourth transmission gate TG4, the fifth transmission gate TG5 and the sixth transmission gate TG6 are turned off, and the second transmission gate TG2 transmits the potential state of the second bit line BLB to the third switch.
[0059] Step 102: The third switch controls the opening and closing of the first switch according to the potential state of the second bit line BLB;
[0060] Step 103: The transmission line GBL reads the analog signal output by the first switch according to the on / off state of the first switch, and transmits the analog signal to the analog-to-digital conversion circuit.
[0061] Based on the above embodiments, during in-memory computation, when the stored data is 1, the second bit line BLB is at a low level, causing the third MOS transistor P1 to turn on. The VG power supply voltage is transmitted to the gate of the first MOS transistor N1. The VG power supply can be adjusted by an external signal input. The VG power supply signal turns on the first MOS transistor N1. At this time, the input IN port transmits the excitation data multiplied by the weighted data. This data is represented by the width of an inverted pulse. The data size is proportional to the duration of the low level, which is proportional to the time it takes for the transmission line GBL, which is pre-charged to a high level, to discharge to the input IN port. This discharge time is proportional to the voltage drop of the transmission line GBL. By horizontally arranging multiple in-memory computation sub-circuits 10 in parallel to form a computation array sharing the transmission line GBL, the multi-bit multiplication and addition result can be reflected on the transmission line GBL in the form of an analog voltage. This analog voltage is then input to the analog-to-digital converter circuit to realize the conversion of analog signals to digital signals.
[0062] According to some embodiments, the control method includes a data writing method, the data writing method comprising:
[0063] Step 201: Control the third control signal RW_CTRL to be input at a high level, turn off the second transmission gate TG2, and turn on the fourth transmission gate TG4, the fifth transmission gate TG5 and the sixth transmission gate TG6;
[0064] Step 202: Control the first control signal BL_CRG and the second control signal BLB_CRG to input two level signals respectively;
[0065] Step 203: The word line WL controls the SRAM memory cell 1 to be written to to be turned on, and the first control signal BL_CRG and the second control signal BLB_CRG write the level signal into the SRAM memory cell 1 to be written.
[0066] Based on the above embodiments, in some embodiments, the first control signal BL_CRG and the second control signal BLB_CRG are input to two opposite level signals of the first bit line BL and the second bit line BLB. This changes the data stored in a certain SRAM memory cell 1 in the SRAM memory array.
[0067] According to some embodiments, the control method includes a data reading method, the data reading method comprising:
[0068] Step 301: Control the third control signal RW_CTRL to be input at a high level, turn off the second transmission gate TG2, and turn on the fourth transmission gate TG4, the fifth transmission gate TG5 and the sixth transmission gate TG6;
[0069] Step 302: Control both the first control signal BL_CRG and the second control signal BLB_CRG to input high-level signals;
[0070] Step 303: The word line WL controls the SRAM memory cell 1 to be read to be turned on, and the voltage drop generated by the first bit line BL or the second bit line BLB is amplified and the result is read out.
[0071] Based on the above embodiments, the voltage drop is input into the sensitive amplifier SA to obtain the data readout result.
[0072] According to some embodiments, a chip includes in-memory computing circuitry as described above.
[0073] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0074] Although this disclosure has been described with reference to several typical embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Because this disclosure can be embodied in many forms without departing from the spirit or substance of this application, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.
Claims
1. An in-memory computing circuit, characterized in that, The in-memory computing circuit includes a transmission line and at least one in-memory computing sub-circuit. Each of the at least one in-memory computing sub-circuit is connected to the transmission line. The transmission line transmits the analog signals of the at least one in-memory computing sub-circuit to an analog-to-digital converter (ADC) circuit for converting the analog signals of the at least one in-memory computing sub-circuit to digital signals. The in-memory computing sub-circuit includes: A storage module, wherein a first bit line and a second bit line are respectively connected to both ends of the storage module; A first switch, which is connected to the analog-to-digital conversion circuit via the transmission line; A decoupling module is provided, in which the second bit line is connected to the control terminal of the first switch. During memory calculation operations, the memory module controls the on / off state of the first switch through the decoupling module to improve the linearity between the change in the voltage of the second bit line and the calculation result. The decoupling module includes a second switch and a third switch. The input terminal of the second switch is connected to the second bit line, and the output terminal is connected to the control terminal of the third switch. The third switch is connected to the control terminal of the first switch. The in-memory computing sub-circuit further includes a fourth switch and a fifth switch. The input terminal of the fourth switch is connected to the first control signal BL_CRG, and the output terminal is connected to the first bit line. The input terminal of the fifth switch is connected to the second control signal, and the output terminal is connected to the second bit line. The control terminals of the second switch, the fourth switch, and the fifth switch are all connected to the third control signal. When the second switch is turned on, the fourth switch and the fifth switch are turned off. When the fourth switch and the fifth switch are turned on, the second switch is turned off. The second switch uses a second transmission gate, the fourth switch uses a fourth transmission gate, the fifth switch uses a fifth transmission gate, the in-memory computing sub-circuit further includes a first inverter, the third control signal is connected to the input terminal of the first inverter, the first control terminal of the second transmission gate, the second control terminal of the fourth transmission gate and the second control terminal of the fifth transmission gate, and the output terminal of the first inverter is connected to the second control terminal of the second transmission gate, the first control terminal of the fourth gate and the first control terminal of the fifth gate.
2. The in-memory computing circuit according to claim 1, characterized in that, The first switch is a high-level start switch. The in-memory calculation sub-circuit also includes a sixth transmission gate. The first control terminal of the sixth transmission gate is connected to the output terminal of the first inverter. The second control terminal of the sixth transmission gate is connected to the third control signal. The input terminal of the sixth transmission gate is connected to the control terminal of the first switch, and the output terminal is grounded. This is used so that when the third switch controls the first switch to turn off, the sixth transmission gate will ground the control terminal of the first switch to improve the accuracy of in-memory calculation.
3. The in-memory computing circuit according to claim 2, characterized in that, The storage module employs an SRAM storage array, which includes at least one SRAM storage cell. Each SRAM storage cell includes a sixth switch, a seventh switch, a second inverter, and a third inverter. The control terminals of the sixth and seventh switches are both connected to word lines. One end of the sixth switch is connected to the first bit line, and the other end is connected to the input terminal of the second inverter and the output terminal of the third inverter. The output terminal of the second inverter and the input terminal of the third inverter are both connected to one end of the seventh switch, and the other end of the seventh switch is connected to the second bit line.
4. A control method for an in-memory computing circuit, applied to the in-memory computing circuit as described in claim 3, characterized in that, The control method includes an in-memory computation method, which includes: When the third control signal input is low, the second transmission gate is opened, and the fourth, fifth and sixth transmission gates are turned off. The second transmission gate transmits the potential state of the second bit line to the third switch. The third switch controls the opening and closing of the first switch according to the potential state of the second bit line; The transmission line reads the analog signal output by the first switch according to the on / off state of the first switch, and transmits the analog signal to the analog-to-digital conversion circuit.
5. The control method according to claim 4, characterized in that, The control method includes a data writing method, which includes: When the third control signal is input at a high level, the second transmission gate is turned off, and the fourth, fifth, and sixth transmission gates are turned on. The first control signal and the second control signal are respectively input as two level signals; The word line controls the SRAM memory cell being written to to be turned on, and the first control signal and the second control signal write the level signal into the SRAM memory cell being written.
6. The control method according to claim 4, characterized in that, The control method includes a data reading method, which includes: When the third control signal is input at a high level, the second transmission gate is turned off, and the fourth, fifth, and sixth transmission gates are turned on. Both the first control signal and the second control signal are input with a high-level signal; The word line controls the SRAM memory cell being read to be turned on, and the first bit line or the second bit line generates a voltage drop. The voltage drop is amplified and the result is read out.
7. A chip, characterized in that, The chip includes the in-memory computing circuitry as described in any one of claims 1 to 3.