Memory device and method of reducing operating voltage of a memory device

Abstract

According to embodiments of the present application, a memory device including RRAM memory cells configured to form a 0 transistor 1 resistor (0T1R) array structure is provided, in which the access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells can be arranged in a parallel structure to reduce the associated IR drop, thereby enabling reduced write voltage operation. According to other embodiments of the present application, a method of reducing the operating voltage of a memory device is also provided.

Description

Technical Field

[0001] Embodiments of this application relate to memory devices and methods for reducing the operating voltage of memory devices. Background Technology

[0002] Resistive Random Access Memory (RRAM) is a memory technology that uses resistance changes instead of charge to store information bits. Resistance switching in RRAM is performed via SET and RESET operations. In typical RRAM devices, a high write voltage is required to perform SET operations due to the high current and high IR drop along the bit lines / select lines (BL / SL) and selector devices. Therefore, charge pumps are typically used to provide the high write voltage. RRAM devices can also employ high-voltage (HV) devices in multiplexer designs to meet reliability standards. Consequently, RRAM devices may be limited by higher write power consumption, higher area overhead, and difficulty in scaling logic due to the combination of charge pumps and HV devices. Summary of the Invention

[0003] According to one embodiment of this application, a memory device is provided, comprising: an array of resistive random access memory (RAM) cells arranged in rows and columns; a first column select transistor connected to a source line of each RAM cell; and a second column select transistor connected to a bit line of each RAM cell, wherein each RAM cell includes a resistive RAM resistor element directly connected between the source line and the bit line.

[0004] According to another embodiment of this application, a method for reducing the operating voltage of a memory device is provided, comprising: providing a memory array including resistive random access memory (RAM) cells; controlling a plurality of column select transistors to activate the source line and bit line of a selected RAM cell; and programming a resistive RAM element of the selected RAM cell with a write current, wherein the resistive RAM element is directly connected between the source line and the bit line.

[0005] According to another embodiment of this application, a memory device is provided, comprising: an array of resistive random access memory (RAM) cells arranged in rows and columns, each RAM cell including: a resistive RAM resistor element including a first terminal connected to a bit line; and a plurality of access transistors arranged in parallel and including a first source / drain terminal connected to a second terminal of the resistive RAM resistor element, a second source / drain terminal connected to a source line, and a gate terminal connected to a word line, wherein the parallel structure of the plurality of access transistors reduces the IR voltage drop of the write current applied to the resistive RAM resistor element.

[0006] Embodiments of this application relate to resistive memories that operate at low voltage. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings and the detailed description below. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A This is a block diagram of a storage device according to some embodiments.

[0009] Figure 1B This is a diagram of an example memory cell array for a storage device according to some embodiments.

[0010] Figure 1C This is a schematic diagram of the write path of a memory cell according to some embodiments.

[0011] Figure 1D This is another schematic diagram of a write path for a memory cell according to some embodiments.

[0012] Figure 1E This is a diagram illustrating the write operation voltage of a memory cell according to some embodiments.

[0013] Figure 2 An example circuit for regulating write voltage for a memory cell array is shown according to some embodiments.

[0014] Figure 3 An example low-voltage current limiter circuit for a memory cell array is shown according to some embodiments.

[0015] Figure 4 An example write termination circuit for a memory cell array is shown according to some embodiments.

[0016] Figure 5This is a timing diagram of a memory cell array including a write termination circuit according to some embodiments.

[0017] Figure 6 An example low read voltage generator circuit for a memory cell array is shown according to some embodiments.

[0018] Figure 7A An example parallel structure for reducing IR voltage drop is shown according to some embodiments.

[0019] Figure 7B This is a schematic diagram of the write path of a parallel structure according to some embodiments.

[0020] Figure 8 An example method for reducing the operating voltage of a storage device is shown. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various embodiments. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Spatial relation terms are intended to include different orientations of the device in use or operation other than those described in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0023] Some embodiments disclosed herein relate to systems and / or methods for implementing low-voltage operation for memory architectures such as resistive random access memory (RRAM). In one embodiment, the selector device or transistor for each memory cell is bypassed or removed, thereby eliminating its associated IR drop and reducing the minimum voltage required to perform a write operation. Advantageously, the memory architecture can implement a non-charge pump design and / or eliminate HV devices to reduce area overhead and logic processing.

[0024] Figure 1AThis is a block diagram of a memory device 101 according to some embodiments. The memory device 101 includes one or more memory cell arrays 100 composed of memory cells 110. In some instances, the memory cells 110 are RRAM memory cells, which will be discussed further below. A row of memory cells 110 (e.g., memory cells 110a-110b or 110c-110d) is operatively coupled to word line WL1 or word line WL2, respectively, while a column of memory cells 110 (e.g., 110a-110c or 110b-110d) is operatively coupled to bit line BL1 or bit line BL2 and select line SL1 or select line SL2, respectively. The memory cells 110 are associated with addresses that can be defined by the intersection of word line WL1 or word line WL2 with bit line BL1 or bit line BL2 and / or select line SL1 or select line SL2.

[0025] The memory cell array 100 may be coupled to support circuitry configured to read data from and / or write data to the memory cells 110. In some embodiments, the support circuitry includes a word line decoder 102, a bit line decoder 103, a select line decoder 104, and / or sensing circuitry 105. The word line decoder 102 is configured to selectively apply a signal (e.g., current and / or voltage) to one of the word lines WL1-WL2 based on a first address ADDR1; the bit line decoder 103 is configured to selectively apply a signal to one of multiple bit lines BL1-BL2 based on a second address ADDR2; and the select line decoder 104 is configured to selectively apply a signal to one of multiple select lines SL1-SL2 based on a third address ADDR3. In some embodiments, the second address ADDR2 and the third address ADDR3 may be the same address.

[0026] Memory cell 110 may include an RRAM cell with a variable resistive element for storing data bits. In a typical 1 transistor 1 resistor (1T1R) RRAM array, each memory cell 110 may include an access transistor 112 and an RRAM resistive element 114. The RRAM resistive element 114 has a resistance state that can switch between a low resistance state and a high resistance state to indicate the data value (e.g., "1" or "0") stored within the RRAM resistive element 114. As described in more detail below, according to some aspects of this disclosure, the access transistor 112 of memory cell 110 is bypassed by a conductive element such as metal line 130 to reduce the minimum voltage required to perform a write operation. Although for ease of illustration, Figure 1A A single access transistor 112, RRAM resistor element 114, and metal line 130 are shown relative to a single memory cell 110a, but it should be understood that this concept applies to multiple or all memory cells 110 of memory device 101.

[0027] Figure 1B This is a schematic diagram of a portion of an example memory cell array 100 for a storage device according to some embodiments. (As in conjunction with...) Figure 1A As indicated, the memory cell array 100 includes a grid of memory cells 110 arranged in rows and / or columns (for ease of illustration and explanation, in...). Figure 1B The image shows a row with one memory cell 110 in each column 1-M.

[0028] Resistance switching in RRAM is performed via write operations called set and reset operations. For example, a "set" voltage can be applied to memory cell 110 to change the variable-resistance dielectric layer from a first resistivity (e.g., a high-resistance state (HRS) corresponding to logic "0") to a second resistivity (e.g., a low-resistance state (LRS) corresponding to logic "1"). Similarly, a "reset" voltage can be applied to memory cell 110 to change the variable-resistance dielectric layer back from the second resistivity to the first resistivity. Each memory cell 110 can operate as a three-terminal device including a bit line (BL), a select line or source line (SL), and a word line (WL). Memory cell array 100 includes column select transistors 202 / 204 to switch or connect a local BL or local SL to a global bit line (GBL) or global source line (GSL) to connect the selected memory cell 110 to write circuitry (e.g., regarding...). Figure 2 Current storage devices incorporate charge pumps to provide sufficiently high voltages to perform write operations, and also incorporate high-voltage devices in multiplexers or logic to reliably handle high-voltage write signals.

[0029] Therefore, in one embodiment, the memory cell array 100 is configured to bypass the access transistors 112 of the memory cells 110, effectively removing them from the memory cells. In some examples, conductive elements such as metal lines 130 may connect the source / drain terminals of each access transistor 112 to bypass the access transistor 112, thereby forming an 0 transistor 1 resistor (OT1R) RRAM array. Other conductive elements connecting the source / drain terminals of each access transistor 112 are within the scope of this disclosure. Advantageously, the IR voltage drop associated with the access transistor 112 during write operations is eliminated, thus reducing the minimum voltage required to perform the write and also reducing area overhead without altering the front-end device. Alternatively or additionally, the access transistor 112, word lines (WL), and / or WL driver circuitry, as indicated substantially by dashed lines 150, may be removed to further reduce area overhead. For example, regarding Figure 1A This could mean removing one or more word lines (e.g., WL1, WL2, etc.) and / or word line decoder 102 (or components thereof, such as charge pumps and / or high-voltage devices in a multiplexer design).

[0030] Figure 1C This is a schematic diagram of the write path of memory cell 110 according to some embodiments. Figure 1D This is another schematic diagram of the write path of memory cell 110 according to some embodiments. Figure 1E This is a graph illustrating the write operation voltage of memory cell 110 according to some embodiments. For example... Figure 1E As shown in bar chart 170, the typical write voltage VWRITE can be considered as four voltages: a first voltage (V_RBL) 171 associated with the bit line (BL), a second voltage (V_RSL) 172 associated with the source line (SL), a third voltage (V_selector) 173 associated with the access transistor 112, and a fourth voltage (VRRAM) 174 associated with the minimum voltage used to change the resistivity of the RRAM resistive element 114. As a result, the minimum write voltage VWRITE (represented by dashed line 176) can be higher than the supply voltage (VDIO) represented by dashed line 178 (see...). Figure 2 Therefore, conventional resistive memory devices combine charge pumps and high-voltage devices to provide and handle high write voltages.

[0031] In contrast, by combining metal line 130 to bypass access to transistor 112 (e.g., as... Figure 1C As shown), the IR voltage drop of the third voltage (V_selector) 173 is eliminated, thereby achieving the minimum operating voltage 178 of the memory device (e.g., as shown). Figure 1E The reduction (as shown). Since the metal line 130 effectively removes the access transistor 112 from the circuit, the word line WL is also unnecessary and can therefore be optionally removed, such as... Figure 1B As shown by the dashed line 150 in the diagram. Alternative or additional locations, such as... Figure 1D As shown, a similar result can be obtained by removing access transistor 112, as indicated by dashed circle 175, such that RRAM resistor element 114 is directly connected between BL / SL (e.g., there is no intermediate device such as access transistor 112 between RRAM resistor element 114 and either BL or SL). Figure 1E As shown in bar graph 180, the write voltage (e.g., Figure 1B and 1C The VWRITE in the circuit can be reduced to a level below the supply voltage VDIO 178, as shown by arrow 182. This is in addition to the related support circuitry (e.g., Figure 1AThe elimination of charge pumps and high-voltage devices in the word line decoder 102, bit line decoder 103, select line decoder 104, sensing circuit 105, etc., as shown herein, provides a comprehensive test structure for the element characteristics of the RRAM resistive elements 114 of the memory cell array 100. Furthermore, the fast operation and low power capability are advantageous for specific applications such as electronic fuse applications. Figure 1C The circuitry for -D illustrates how the reduced voltage is achieved, but the typical minimum operating voltage is not shown. Furthermore, note that while WL can be removed, it is not necessary to remove it in some embodiments.

[0032] Figure 2 An exemplary regulating write voltage circuit 200 according to some embodiments is shown, which is configured to output for, for example Figure 1A and Figure 1B The VWRITE voltage of the memory cell array 100 shown is used for the memory cell array. The write voltage regulation circuit 200 can be implemented with the memory cell array 100, wherein the access transistor 112 is connected via metal line 130 (e.g., ...). Figure 1C ) is bypassed or removed (e.g.) Figure 1D This is used to form an OT1R array capable of low-voltage operation. For example... Figure 2 As shown, each memory cell 110 of a given row of M cells can receive a write operation (e.g., SET / RESET) by sending a signal Ysel_SL / Ysel_BL to the gate of the column select transistor 202 / 204 and a RESET signal to the reset transistor 205 of the appropriate column.

[0033] In one embodiment, a first terminal of memory cell 110 is connected to the source line (SL) between the first SL select transistor 202-1 and the second SL select transistor 202-2, and a second terminal of memory cell 110 is connected to the bit line (BL) between the first BL select transistor 204-1 and the second BL select transistor 204-2. That is, the first pair of select transistors 202-1 / 204-1 may include PMOS transistors connected between the global source line / global bit line (GBL / GSL) and memory cell 110, and the second pair of select transistors 202-2 / 204-2 may include NMOS transistors connected between memory cell 110 and ground. The first pair of select transistors 202-1 / 204-1 can be connected to write select transistor 206 via corresponding source / drain (S / D) terminals.

[0034] The write voltage regulation circuit 200 is configured to provide a write voltage VWRITE and a corresponding write current Iwrite to the memory array 100 via a write select transistor 206. The write voltage regulation circuit 200 includes an operational amplifier (op amp) 230 and a write drive transistor 232 (e.g., PMOS) arranged in a closed loop. A first input (e.g., an inverting input) of the operational amplifier 230 receives a reference voltage Vref_write from an I / O circuit (not shown). The output of the operational amplifier 230 is coupled to the gate of the write drive transistor 232. The write drive transistor 232 includes a first S / D terminal connected to a power supply (VDIO) and a second S / D terminal connected to a second input (e.g., a non-inverting input) of the operational amplifier 230 via node 234 to form a closed loop. Node 234 also connects the second S / D terminal of the write drive transistor 232 to the S / D terminal of the write select transistor 206.

[0035] Therefore, operational amplifier 230 outputs a gate voltage to the gate of write drive transistor 232 based on the value of the reference voltage Vref_write, thereby causing the write voltage regulation circuit 200 to output a write voltage VWRITE to the selected memory cell 110. Due to the positive feedback loop, if VWRITE is lower than Vref_write, the output of operational amplifier 230 saturates to the negative power rail (e.g., ground), thereby turning on the write drive transistor 232 to provide VWRITE equal to or based on the power supply VDIO. Otherwise, if VWRITE is higher than Vref_write, the output of operational amplifier 230 saturates to the positive power rail, thereby turning off the write drive transistor 232 to reduce VWRITE. Thus, the write voltage regulation circuit 200 is advantageously configured to provide a stable write voltage for the previously described low-voltage RRAM structure over a wide range of power supply voltage VDIO. That is, if VWRITE is equal to the power supply VDIO and the power supply VDIO is too high, the write voltage regulation circuit 200 can prevent stress from being applied to the RRAM resistive element 114 of the selected memory cell 110. Based on the corresponding Ysel_BL and Ysel-SL signals at the gate terminals of transistors 202 and 204, the write voltage VWRITE output by the regulated write voltage circuit 200 is applied to the appropriate source line SL and / or bit line BL of array 100.

[0036] Figure 3An example low-voltage current limiter circuit 300 for a memory cell array 100 according to some embodiments is shown. As described in more detail below, the low-voltage current limiter circuit 300 is configured to operate the second SL select transistor 202-2 and the bottom transistor 302 to write the RRAM resistive element 114 to a stable state while preventing over-SET. The low-voltage current limiter circuit 300 can be implemented with the memory cell array 100, wherein the access transistor 112 is bypassed or removed via metal line 130 to form an OT1R array capable of low-voltage operation as described above. Figure 3 As shown, the write current Iwrite flows from memory cell 110 to the second SL select transistor 202-2, and then flows to the bottom transistor 302 as it travels to ground.

[0037] The low-voltage current limiter circuit 300 includes a current source 312 configured to provide a reference current to a diode-connected first transistor 314 (e.g., an NMOS). Specifically, the first transistor 314 includes a first S / D terminal connected to the current source 312, a second S / D terminal connected to ground, and a gate connected to its first S / D terminal and also connected to the gate of a second transistor 320 (e.g., an NMOS) to form a current mirror circuit. The second transistor 320 includes a first S / D terminal connected to ground and a second S / D terminal connected to the first S / D terminal of a diode-connected third transistor 322 (e.g., a PMOS).

[0038] The third transistor 322 includes a second S / D terminal connected to the power supply VDIO, and a gate connected to its first S / D terminal and also to the gate of the fourth transistor 330 (e.g., PMOS) to form a current mirror circuit. The fourth transistor 330 includes a first S / D terminal connected to the power supply VDIO and a second S / D terminal connected to the first node 331. Therefore, the reference current provided by the current source 312 is mirrored at the first node 331. The first node 331 is connected to the first S / D terminal of the fifth transistor 341 (e.g., NMOS). The first node 331 is also connected via a second node 332 to the gate of the bottom transistor 302 to prevent excessive SET of the write current Iwrite, as described below.

[0039] The fifth transistor 341 is arranged in a closed loop with the operational amplifier 370. Specifically, the first input (e.g., a non-inverting input) of the operational amplifier 370 receives a reference voltage Vref from an I / O circuit (not shown). The output of the operational amplifier 370 is connected to the gate of the fifth transistor 341. The output of the operational amplifier 370 is also connected to a buffer 350 to route its output voltage VY to the gate of the second SL selection transistor 202-2 of the memory cell array 100. For example, for a selected column 1-M, the voltage applied to the gate of its corresponding second SL selection transistor 202-2 is equal to the output voltage of the operational amplifier 370. Each second SL selection transistor 202-2 is connected in series with the bottom transistor 302 of the memory cell array 100 previously described. The fifth transistor 341 includes a second S / D terminal connected to the second input (e.g., an inverting input) of the operational amplifier 370 via a third node 333 to form a closed loop.

[0040] The third node 333 also connects the second S / D terminal of the fifth transistor 341 to the first S / D terminal of the sixth transistor 342 (e.g., NMOS). The sixth transistor 342 includes a second S / D terminal connected to ground and a gate connected to the second node 332 and the bottom transistor 302. Therefore, a closed-loop connection to the first S / D terminal of the fifth transistor 341 is formed between the gates of the sixth transistor 342 and the bottom transistor 302, causing the current flowing through the bottom transistor 302 to mirror the current flowing through the sixth transistor 342.

[0041] Due to the negative feedback loop, the voltage at the third node 333 follows Vref, and the drain-source voltages of the sixth transistor 342 and the mirrored bottom transistor 302 also follow Vref. Therefore, the operational amplifier 370 is configured to adjust the gate voltage VG of the bottom transistor 302 to limit the write current Iwrite. That is, Vref is selected to provide a bias VG to the gate of the bottom transistor 302 so that the bottom transistor 302 operates in the saturation region. Therefore, the bottom transistor 302 acts as a variable resistor and limits the current allowed to flow along the source line SL during SET operation. For example, for a Vref of 0.1V, the write current gradually saturates after reaching the 0.1V voltage level, thereby writing the RRAM resistive element 114 to a steady state while preventing over-SET and limiting the increase in write bias due to a head space overhead of approximately 0.1V. In some embodiments, the low-voltage current limiter circuit 300 is global and is configured to generate gate voltage VG and output voltage VY for all columns of the memory cell array 100. For ease of illustration and explanation, Figure 3 A row with one memory cell 110 in each column 1-M is shown, but it should be understood that multiple rows and multiple memory cells 100 can exist in each column 1-M, such as... Figure 1A As shown.

[0042] Figure 4 An example write termination circuit 400 for a memory cell array 100 according to some embodiments is shown. The write termination circuit 400 is configured to write the RRAM resistive element 114 to a stable state and prevent excessive SET / RESET. The write termination circuit 400 can be implemented with the memory cell array 100, wherein the access transistor 112 is bypassed or removed via metal line 130 to form an OTIR array capable of low-voltage operation as previously described. Figure 4 As shown, the write termination circuit 400 includes a first transistor 461 (e.g., PMOS) and a second transistor 462 (e.g., NMOS) connected in series, with a node 463 connecting their respective drains. The source of the first transistor 461 is connected to the power supply VDIO, and the source of the second transistor 461 is grounded. The write termination circuit 400 also includes a buffer 470, whose input is connected to node 463 and whose output is connected to a delay circuit 480 to provide a write termination signal WRITE_B.

[0043] The gate of PMOS transistor 461 is connected to the output of operational amplifier 230 of the write voltage regulation circuit 200. Therefore, the write termination circuit 400 is configured to generate a reference current Iref_write based on the write current Iwrite. After determining the target value to be written to the RRAM resistor element 114 during the write operation (e.g., based on a threshold voltage detected at node 463 using Iref_write), the write termination circuit 400 outputs a write termination signal WRITE_B to the gate of the write select transistor 206 to turn off the write operation by turning off the write select transistor 206. By using the threshold voltage at node 463 as a proxy for turning off the write select transistor 206, the write termination circuit 400 advantageously writes the RRAM resistor element 114 to a stable state and prevents excessive SET / RESET. Furthermore, the write termination voltage has no header space overhead and does not increase the write bias because it is based on the reference current Iref_write.

[0044] Figure 5 This is a timing diagram 500 of a memory cell array 100 including a write termination circuit 400 according to some embodiments. At time T1, a SET operation is initiated. Thereafter, for example, at transistor 202-1 of the selected memory cell (see example...) Figure 4The column select signal YE received at the gate terminal of the RRAM resistor element 114 is asserted at time T2, causing the selected memory RRAM resistor element 114 cell to receive (e.g., via SL and / or BL) a write current Icell that increases over time. At some point, at time T3, the write termination circuit 400 detects that the write current Icell has reached its target value (e.g., via Vdetect at node 463) and switches the write termination signal WRITE_B (e.g., assertion logic high) to the gate of the write select transistor 206 to disable the write operation. This prevents the write current Icell from causing excessive SET / RESET to the RRAM resistor element 114.

[0045] Figure 6 An exemplary low read voltage generator circuit 600 for memory cells, such as memory cells 110 of a memory cell array 100, is shown according to some embodiments. The low read voltage generator circuit 600 may be implemented with the memory cell array 100, wherein access transistors 112 are bypassed or removed via metal lines 130 to form an OTIR array capable of low-voltage operation as described above. Additionally, as... Figure 6 As shown, the memory cell array 100 may include one or more read paths (e.g., left / right RRAM cells and corresponding read paths via BL_L and BL_R) and a reference path connected to a sense amplifier circuit 610 configured to read the bit value of the RRAM resistive element 114.

[0046] The memory cell array 100 may include a clamping transistor 612, a bit line (BL) read transistor 631, and a reference select transistor 632 to connect desired RRAM read paths and reference paths. For example, to read the left RRAM cell 114-1 in a left / right pair (114-1 / 114-2), the first BL read transistor 631-1 is turned on to connect the left RRAM cell to the sense amplifier circuit 610, and the second BL read transistor 631-2 is turned off. Furthermore, the first reference select transistor 632-1 is turned off and the second reference select transistor 632-2 is turned on to connect a reference circuit 620 to a second terminal of the sense amplifier circuit 610. The right RRAM cell of the pair can be read using the opposite switch. The reference circuit 620 includes an adjustable resistor 622, which can be adjusted to simulate a selected RRAM cell. The reference circuit 620 can operate in an OT1R configuration, for example, combined with... Figure 1C and Figure 1D The described structure enables the sense amplifier circuit 610 to be configured to track process, voltage, and temperature (PVT) variations along the read path of the memory cell array 100.

[0047] A low read voltage generator circuit 600 is connected to the gate of a clamping transistor 612 to control the read voltage level for the selected left / right side. For example, a first clamping transistor 612-1 is connected between a first terminal of the sense amplifier circuit 610 and the left read path, and a second clamping transistor 612-2 is connected between a second terminal of the sense amplifier circuit 610 and the right read path. As described in more detail below, the low read voltage generator circuit 600 is configured to maintain a low read voltage and prevent read interference when the read voltage becomes too high.

[0048] The low read voltage generator circuit 600 includes a first transistor 641 (e.g., PMOS) with its first S / D terminal connected to a power supply VDIO, and a second S / D terminal connected to the first S / D terminal of a second transistor 642 (e.g., NMOS). The second transistor 642 is arranged in a closed loop with an operational amplifier 650. Specifically, a first input (e.g., a non-inverting input) of the operational amplifier 650 receives a read control voltage Vread from an I / O circuit (not shown). The output of the operational amplifier 650 is connected to the gate of the second transistor 642. The output of the operational amplifier 650 is also connected to the gate of a clamping transistor 612 to turn them on, and its output clamp voltage VCL. The second transistor 642 includes a second S / D terminal connected via node 643 to the second input (e.g., an inverting input) of the operational amplifier 650 to form a closed loop.

[0049] The low read voltage generator circuit 600 also includes a reference circuit 660 connected between node 643 and ground. The reference circuit 660 includes one or more adjustable resistors 662 to adjust the reference current to a desired value. Similar to the reference circuit 620 of the memory cell array 100, this second reference circuit 660 can be used with the OT1R RRAM cell structure and adjust the adjustable resistor 662 to simulate selected RRAM cells and track process, voltage, and temperature (PVT) variations in the read path of the memory cell array 100. In other words, the adjustable resistor 662 can be adjusted to compensate for PVT variations in various components of the RRAM cell read path (e.g., BL, SL, access transistors, resistive elements, etc.). Due to the negative feedback loop, the voltage at node 643 follows the read control voltage Vread. Therefore, the low read voltage generator circuit 600 is configured to maintain a low read voltage (e.g., approximately 0.1V) and prevent read interference when the read voltage becomes too high.

[0050] Figure 7A An example parallel structure 700 for reducing IR voltage drop is shown according to some embodiments. Figure 7B This is a schematic diagram of the write path of a parallel structure 700 according to some embodiments. Figure 7A and Figure 7B Showing the combination Figure 1C and Figure 1D The described alternative structure for 0T1R is used to reduce the minimum operating write voltage. It is not a bypass or elimination of... Figure 1C and Figure 1D The illustrated access transistor 112 provides an alternative access transistor arrangement to reduce IR drop. In one embodiment, the access transistors 112 of the memory cell array 100 (e.g., a row of access transistors 112-1 to 112-N) are arranged in parallel such that their gates are connected to a common word line (WL), their first S / D terminals are connected to a common terminal of an RRAM resistor element 114, and their second S / D terminals are connected to a common terminal of a select line (SL). The other end of the RRAM resistor element 114 is connected to a bit line (BL). Thus, by using a plurality of access transistors 112-1...112-N connected in parallel, the IR drop 773 associated with a single access transistor 112 is reduced, thereby lowering the minimum operating voltage while maintaining the ability to perform write operations using WL control.

[0051] Figure 8 An example method 800 for reducing the operating voltage of a memory device is illustrated. At operation 802, a memory array (e.g., memory cell array 100) comprising RRAM memory cells is provided. At operation 804, a plurality of column select transistors 202 / 204 are controlled to activate the source line and bit line of a selected RRAM memory cell. At operation 806, an RRAM resistive element 114 of the selected RRAM memory cell is programmed with a write current, wherein the RRAM resistive element 114 is directly connected between the source line and the bit line.

[0052] That is, the IR drop typically associated with the access transistor (e.g., access transistor 112) of the RRAM memory cell is reduced, and a reduced write current / voltage can be generated for the RRAM memory cell based on the reduced IR drop. In one embodiment, reducing the IR drop includes bypassing the access transistor by connecting metal lines 130 across the source / drain terminals of the access transistor. In another embodiment, reducing the IR drop includes removing the access transistor from the RRAM memory cell. In yet another embodiment, reducing the IR drop includes arranging the access transistor in a parallel configuration.

[0053] At operation 808, the write voltage is stabilized over a wide range of supply voltages (e.g., by regulated write voltage circuit 200). At operation 810, current limiter circuit 300 is used to prevent excessive settling during write operations. At operation 812, write termination circuit 400 is used to prevent excessive settling / resetting during write operations. At operation 814, sense amplifier circuit 610 with process, voltage, and temperature (PVT) tracking is used to avoid read interference during read operations (e.g., by low read voltage generator circuit 600).

[0054] Therefore, the various embodiments disclosed herein provide a memory device including an array of RRAM memory cells arranged in rows and columns, a first column select transistor connected to a source line of each RRAM memory cell, and a second column select transistor connected to a bit line of each RRAM memory cell, wherein each RRAM memory cell includes an RRAM resistive element directly connected between the source line and the bit line. In one embodiment, the memory device further includes a metal line bridging the source / drain terminals of the access transistor of each RRAM memory cell, wherein the metal line bypasses the access transistor to directly connect the RRAM resistive element between the source line and the bit line. In another embodiment, there is no access transistor between the source line and the bit line for each RRAM memory cell.

[0055] In the aforementioned memory device, the memory device further includes: an access transistor of the resistive random access memory cell connected between the source line and the bit line of each resistive random access memory cell; and a metal line connecting the source / drain terminals of the access transistor, wherein the metal line bypasses the access transistor to directly connect the resistive random access memory resistor element of each resistive random access memory cell between the source line and the bit line.

[0056] In the aforementioned memory device, the memory device further includes: a write voltage regulation circuit, comprising: an operational amplifier configured to receive a reference write voltage signal at a first input terminal; and a write drive transistor including a gate terminal connected to the output of the operational amplifier, a first source / drain terminal configured to receive a power supply voltage, and a second source / drain terminal connected via a node to a second input terminal of the operational amplifier to form a positive feedback loop, wherein the node is operatively connected via a write select transistor to the bit line and source line of a resistive random access memory cell.

[0057] The memory device further includes a low-voltage current limiter circuit. The low-voltage current limiter circuit includes: an operational amplifier configured to receive a reference voltage signal at a first input terminal; a first transistor including a first gate terminal connected to the output of the operational amplifier, a first source / drain terminal connected to a current mirror circuit, and a second source / drain terminal connected to a second input terminal of the operational amplifier via a first node to form a negative feedback loop; and a second transistor including a third source / drain terminal connected to the first node, a fourth source / drain terminal connected to ground, and a second gate terminal connected to the third gate terminal of a bottom transistor of a resistive random access memory (RAM) cell array via a second node, wherein the second node is connected to the current mirror circuit, wherein the output of the operational amplifier is connected to the fourth gate terminal of a select transistor connected in series with the bottom transistor, and wherein the low-voltage current limiter circuit is configured to control the select transistor and the bottom transistor to prevent over-setting of selected RAM cells.

[0058] In the aforementioned memory device, the memory device further includes a write termination circuit. The write termination circuit includes: a first transistor and a second transistor connected in series, with a node between them connected to their respective drain terminals, wherein a first gate terminal of the first transistor is connected to a write voltage regulation circuit for generating a reference write current; and a buffer including an input connected to the node and an output connected to a second gate terminal of a write select transistor of the resistive random access memory cell array, wherein the write termination circuit is configured to provide a write inhibit signal to the write select transistor in response to a threshold of detected write operation to prevent over-set / reset.

[0059] The memory device further includes a low read voltage generator circuit connected to the gate of a clamping transistor of a resistive random access memory cell. The low read voltage generator circuit is configured to control the clamping transistor to define the read voltage of the resistive random access memory cell in order to avoid read interference during read operations by utilizing a sense amplifier circuit with process, voltage, and temperature (PVT) tracking.

[0060] In the aforementioned memory device, word lines and associated write circuitry are removed from the memory device.

[0061] The memory device described above also includes metal lines connecting the source / drain terminals of the access transistors of the resistive random access memory cells.

[0062] According to a further disclosed embodiment, a method for reducing the operating voltage of a memory device includes: providing a memory array including RRAM memory cells, controlling a plurality of column select transistors to activate the source line and bit line of a selected RRAM memory cell, and programming an RRAM resistive element of the selected RRAM memory cell with a write current, wherein the RRAM resistive element is directly connected between the source line and the bit line.

[0063] In the above method, the method for reducing the operating voltage of the memory device further includes providing a metal line across the source / drain terminals of the access transistor of each resistive random access memory cell, wherein the metal line bypasses the access transistor to directly connect the resistive random access memory resistive element between the source line and the bit line.

[0064] In the above methods, the method of reducing the operating voltage of the memory device further includes: removing the access transistor between the source line and the bit line.

[0065] In the above method, the method for reducing the operating voltage of the memory device further includes: providing a reference write voltage signal at the first input terminal of the operational amplifier; and generating a write voltage using a write drive transistor arranged in a positive feedback loop with the operational amplifier.

[0066] The above method further includes: providing a reference write voltage signal at the first input terminal of the operational amplifier; and generating a write voltage using a write drive transistor arranged in a positive feedback loop with the operational amplifier; and the method further includes: activating a write select transistor to provide a write current to a selected resistive random access memory cell based on the write voltage.

[0067] In the above methods, the method of reducing the operating voltage of the memory device further includes: providing a reference write voltage signal at a first input terminal of the operational amplifier; and generating a write voltage using a write drive transistor arranged in a positive feedback loop with the operational amplifier; the method of reducing the operating voltage of the memory device further includes: activating a write select transistor to provide a write current to a selected resistive random access memory cell based on the write voltage; and the method of reducing the operating voltage of the memory device further includes: providing a reference write current based on the reference write voltage signal; detecting that a threshold is reached during writing to the selected resistive random access memory cell based on the reference write current; and if the threshold is reached, applying a write termination signal to the write select transistor to prevent over-setting of the selected resistive random access memory cell.

[0068] In the above method, the method for reducing the operating voltage of the memory device further includes: providing a reference write voltage signal at the first input terminal of the operational amplifier; and generating a write voltage using a write drive transistor arranged in a positive feedback loop with the operational amplifier. The method for reducing the operating voltage of the memory device further includes: providing a reference current through a current mirror circuit; providing a reference write voltage signal at the first input terminal of the operational amplifier; generating an output voltage using a first transistor arranged in a negative feedback loop with the operational amplifier; generating a gate voltage using a second transistor connected in series with the first transistor and the current mirror circuit; and applying the output voltage and the gate voltage to the select transistor and the bottom transistor, respectively, to limit the write current and prevent over-set / reset of the selected resistive random access memory cell.

[0069] In the above method, the method for reducing the operating voltage of the memory device further includes: controlling the gate terminal of the clamping transistor of the resistive random access memory cell to define the read voltage of the resistive random access memory cell, and using a sense amplifier circuit with process, voltage, and temperature (PVT) tracking to avoid read interference during read operations.

[0070] According to other disclosed embodiments, a memory device includes an array of RRAM memory cells arranged in rows and columns. Each RRAM memory cell includes: an RRAM resistive element including a first terminal connected to a bit line; and a plurality of access transistors arranged in parallel and including a first S / D terminal connected to a second terminal of the RRAM resistive element, a second S / D terminal connected to a source line, and a gate terminal connected to a word line, wherein the parallel arrangement of the plurality of access transistors reduces the IR voltage drop of the write current applied to the RRAM resistive element.

[0071] In the aforementioned memory device, a parallel structure of multiple access transistors is arranged between the resistive element and the source line of the resistive random access memory.

[0072] In the aforementioned memory device, the gate terminals of multiple access transistors are connected together.

[0073] This disclosure outlines various embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A memory device, comprising: An array of resistive random access memory cells arranged in rows and columns; The first column of select transistors connected to the source line of each resistive random access memory cell; as well as The second column of select transistors is connected to the bit lines of each resistive random access memory cell. Each resistive random access memory cell includes: A resistive element of a resistive random access memory directly connected between the source line and the bit line; The access transistor of the resistive random access memory cell connected between the source line and the bit line of each resistive random access memory cell; and A metal line connecting the source / drain terminals of the access transistor, wherein the metal line bypasses the access transistor to directly connect the resistive random access memory resistor element of each resistive random access memory cell between the source line and the bit line.

2. The memory device according to claim 1, further comprising: An adjustment write voltage circuit is configured to provide a write voltage to the resistive random access memory cell array.

3. The memory device according to claim 2, wherein, The adjustable write voltage circuit includes a closed-loop operational amplifier and a write drive transistor.

4. The memory device according to claim 1, further comprising: The circuit for adjusting the write voltage includes: An operational amplifier is configured to receive a reference write voltage signal at its first input terminal; and A write drive transistor includes a gate terminal connected to the output of the operational amplifier, a first source / drain terminal configured to receive a power supply voltage, and a second source / drain terminal connected via a node to a second input terminal of the operational amplifier to form a positive feedback loop, wherein the node is operatively connected via a write select transistor to the bit line and the source line of a resistive random access memory cell.

5. The memory device according to claim 1, further comprising: The low-voltage current limiter circuit includes: An operational amplifier is configured to receive a reference voltage signal at its first input terminal; The first transistor includes a first gate terminal connected to the output of the operational amplifier, a first source / drain terminal connected to a current mirror circuit, and a second source / drain terminal connected to the second input terminal of the operational amplifier via a first node, to form a negative feedback loop; and The second transistor includes a third source / drain terminal connected to the first node, a fourth source / drain terminal connected to ground, and a second gate terminal connected to the third gate terminal of the bottom transistor of the resistive random access memory cell array via the second node. The second node is connected to the current mirror circuit. The output of the operational amplifier is connected to the fourth gate terminal of the selection transistor, which is connected in series with the bottom transistor. The low-voltage current limiter circuit is configured to control the selection transistor and the bottom transistor to prevent over-setting of the selected resistive random access memory cell.

6. The memory device according to claim 1, further comprising: Write termination circuitry, including: A first transistor and a second transistor are connected in series, with their respective drain terminals connected at a node between them. The first gate terminal of the first transistor is connected to a circuit that regulates the write voltage to generate a reference write current. The buffer includes an input connected to the node and an output connected to the second gate terminal of the write select transistor of the resistive random access memory array. The write termination circuit is configured to provide a write inhibit signal to the write select transistor in response to a threshold of a detected write operation, in order to prevent over-set / reset.

7. The memory device of claim 1, further comprising a low read voltage generator circuit connected to the gate of a clamping transistor of a resistive random access memory cell, the low read voltage generator circuit being configured to control the clamping transistor to define a read voltage for the resistive random access memory cell to avoid read interference during read operations by utilizing a sense amplifier circuit with process, voltage, and temperature tracking.

8. The memory device according to claim 1, wherein: Remove word lines and associated write circuitry from the memory device.

9. The memory device of claim 1, further comprising a write termination circuit configured to write the resistive random access memory resistive element to a stable state and prevent over-set / reset.

10. A method for reducing the operating voltage of a memory device, comprising: Provides a memory array including resistive random access memory cells; Control multiple column selection transistors to activate the source line and bit line of the selected resistive random access memory cell; as well as The resistive random access memory (RAM) resistor element of the selected resistive RAM memory cell is programmed using a write current, wherein the RAM resistor element is directly connected between the source line and the bit line, and a metal line is provided across the source / drain terminals of the access transistor of each RAM memory cell, wherein the metal line bypasses the access transistor to directly connect the RAM resistor element between the source line and the bit line.

11. The method of claim 10, wherein: The resistive random access memory's resistive elements are written to a stable state by a write termination circuit, preventing over-setting / resetting.

12. The method according to claim 10, wherein: Write voltage is supplied to the resistive random access memory cell array by adjusting the write voltage circuit.

13. The method of claim 10, further comprising: A reference write voltage signal is provided at the first input terminal of the operational amplifier; as well as The write voltage is generated using a write drive transistor arranged in a positive feedback loop with the operational amplifier.

14. The method of claim 13, further comprising: The write select transistor is activated to provide the write current to the selected resistive random access memory cell based on the write voltage.

15. The method of claim 14, further comprising: A reference write current is provided based on the reference write voltage signal; Based on the reference write current, a threshold is detected during the writing of the selected resistive random access memory cell. as well as If the threshold is reached, a write stop signal is applied to the write select transistor to prevent over-setting of the selected resistive random access memory cell.

16. The method of claim 13, further comprising: A reference current is provided through a current mirror circuit; A reference write voltage signal is provided at the first input terminal of the operational amplifier; The first transistor, arranged in the negative feedback loop with the operational amplifier, is used to generate the output voltage; A gate voltage is generated using a second transistor connected in series with the first transistor and the current mirror circuit; as well as The output voltage and the gate voltage are applied to the select transistor and the bottom transistor, respectively, to limit the write current and prevent over-set / reset of the selected resistive random access memory cell.

17. The method of claim 10, further comprising: The gate terminal of the clamping transistor of the resistive random access memory cell is controlled to define the read voltage of the resistive random access memory cell, and a sense amplifier circuit with process, voltage and temperature tracking is used to avoid read interference during read operations.

18. A memory device, comprising: An array of resistive random access memory (RAM) cells arranged in rows and columns, each RAM cell comprising: A resistive element of a resistive random access memory includes a first terminal connected to a bit line; and Multiple access transistors are arranged in parallel with each other and include a first source / drain terminal connected to a second terminal of the resistive element of the resistive random access memory, a second source / drain terminal connected to a source line, and a gate terminal connected to a word line. The parallel structure formed between the plurality of access transistors reduces the IR voltage drop of the write current applied to the resistive elements of the resistive random access memory. The parallel structure formed by the plurality of access transistors is disposed between the resistive random access memory resistor element and the source line.

19. The memory device according to claim 18, wherein, The parallel structure formed by the plurality of access transistors reduces the minimum operating voltage of the memory device.

20. The memory device of claim 18, wherein, The gate terminals of the plurality of access transistors are connected together.

Images