power supply circuit

Abstract

The power supply circuit of the embodiment includes: a first transistor that is turned on and off according to a control signal supplied to its gate, supplying an output based on an input power supply voltage to a load or stopping the supply of the output to the load; a second transistor, one end of the current path of which is connected to the gate of the first transistor and the other end of which is connected to a reference potential point, and is turned on and off according to the level of the gate voltage of the second transistor; a capacitor connected between the input terminal of the power supply voltage and the gate of the second transistor; and a voltage holding circuit connected between the gate of the second transistor and the reference potential point to hold the gate voltage of the second transistor.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-155252 (filed on September 24, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to power supply circuits. Background Technology

[0003] In the past, pull-down resistors were sometimes used in power supply circuits to prevent inrush current.

[0004] To cope with the rapid changes in surge voltage generated by the input voltage, the resistance value of the pull-down resistor needs to be reduced. However, this results in increased power consumption. Summary of the Invention

[0005] The implementation provides a power supply circuit that can suppress increased power consumption while preventing the generation of inrush current.

[0006] The power supply circuit of the embodiment includes: a first transistor that is turned on and off according to a control signal supplied to its gate, supplying an output based on an input power supply voltage to a load or stopping the supply of the output to the load; a second transistor, one end of the current path of which is connected to the gate of the first transistor and the other end of which is connected to a reference potential point, and is turned on and off according to the level of the gate voltage of the second transistor; a capacitor connected between the input terminal of the power supply voltage and the gate of the second transistor; and a voltage holding circuit connected between the gate of the second transistor and the reference potential point to hold the gate voltage of the second transistor. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the power supply circuit according to the first embodiment of the present invention.

[0008] Figure 2 It is a circuit diagram representing the associated technology of the power supply circuit.

[0009] Figure 3 This is a circuit diagram illustrating the second embodiment of the present invention.

[0010] Figure 4 This is a circuit diagram illustrating the third embodiment of the present invention.

[0011] Figure 5 This is a circuit diagram illustrating the fourth embodiment of the present invention. Detailed Implementation

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0013] (First Embodiment)

[0014] Figure 1 This is a block diagram illustrating a power supply circuit according to the first embodiment of the present invention. In this embodiment, by providing a second transistor that pulls down the gate voltage of the first transistor constituting the main switch, a capacitor that transmits the impulse voltage, and a voltage holding circuit that holds the voltage based on the impulse voltage transmitted through the capacitor, power consumption is suppressed while preventing the generation of inrush current.

[0015] Figure 2 This is a circuit diagram illustrating the associated techniques used in power supply circuits. Furthermore, in Figure 1 and Figure 2 The same label is assigned to the same constituent element, and repeated descriptions of the same constituent element are omitted.

[0016] Figure 2 The power supply circuit shown includes an NMOS transistor T1 that forms the main switch and a pull-down resistor R1. The negative terminal of the voltage source So1 is connected to a reference potential point, generating a power supply voltage Vin at the positive terminal. The power supply voltage Vin from the voltage source So1 is supplied to the drain of the transistor T1 via the input terminal IN of the power supply circuit.

[0017] The source of transistor T1 is connected to the output terminal OUT of the power supply circuit. A load (not shown) is connected to the output terminal OUT. A control signal Vgate is applied to the gate of transistor T1. This control signal Vgate controls whether the power supply circuit supplies output Vout to the load or stops supplying output Vout to the load. With a high-level (hereinafter referred to as H-level) control signal Vgate, transistor T1 is turned on, and output Vout based on the power supply voltage Vin is supplied to the load. Conversely, with a low-level (hereinafter referred to as L-level) control signal Vgate, transistor T1 is turned off, and the supply of output Vout based on the power supply voltage Vin to the load is stopped.

[0018] Now, suppose that with the control signal Vgate at level L, a surge voltage is generated at the power supply voltage Vin. When this happens, due to the parasitic capacitance Cgd between the gate and drain of transistor T1, the gate voltage of transistor T1 may become high, causing transistor T1 to turn on and allowing a large current (rush current) to flow through the load. Therefore, in... Figure 2 In the associated technology, a pull-down resistor R1 is connected between the gate of transistor T1 and the reference potential point.

[0019] exist Figure 2In the example, there is no problem when the surge voltage of the power supply voltage Vin changes slowly (low throughput). However, when the surge voltage of the power supply voltage Vin changes rapidly (high throughput), the resistance value of the pull-down resistor R1 needs to be significantly reduced to minimize the rise in the gate voltage of transistor T1. When this is done, a relatively large current will flow steadily from the gate of transistor T1 through the pull-down resistor R1 to the reference potential point, increasing power consumption.

[0020] (constitute)

[0021] Therefore, in this embodiment, a switching circuit based on NMOS transistor T2 is used instead of pull-down resistor R1.

[0022] exist Figure 1 In the diagram, a current path for transistor T2 is connected between the gate of transistor T1 and the reference potential point. The drain of transistor T2 is connected to the gate of transistor T1, the source is connected to the reference potential point, and the gate is connected to node A.

[0023] Node A is connected to the positive input terminal of voltage source So1 via capacitor C1 and input terminal IN. That is, the power supply voltage Vin, which is input to the power supply circuit, is applied to one end of capacitor C1, and the other end is connected to node A. Through capacitor C1, which acts as a high-pass filter, abrupt changes in the power supply voltage Vin are transmitted to node A.

[0024] Furthermore, the current paths of PMOS transistors T3 and T4 are connected in series between node A and the reference potential. Specifically, the source of transistor T3 is connected to node A, and its gate and drain are both connected to the source of transistor T4. Conversely, the gate and drain of transistor T4 are both connected to the reference potential. Both transistors T3 and T4 function as diodes.

[0025] The forward voltages of transistors T3 and T4 are set to be higher than the voltage required to turn on transistor T2. The two diodes formed by transistors T3 and T4 function as a voltage holding circuit to maintain the voltage at node A for a certain period. For example, although related to the structure of transistors T3 and T4, it is possible to maintain the voltage at node A, i.e., the forward voltages of transistors T3 and T4, for approximately 1 m seconds using transistors T3 and T4.

[0026] Capacitor C1, transistor T2, and transistors T3 and T4 function as a protective circuit to prevent surge current caused by impulse voltage.

[0027] Furthermore, generally speaking, the surge voltage generated by the power supply voltage Vin is on the order of several μs. For example, suppose that the voltage that constitutes... Figure 1A circuit board (not shown) for the power supply circuit (hereinafter referred to as the power supply board) is mounted on another circuit board (not shown), and transistor T1 is connected to the bus of the other circuit board. When hot-swapping is supported, a surge voltage of the power supply voltage Vin may sometimes be generated at the source of transistor T1 when the power supply board is mounted on another circuit board. The duration of this surge voltage in the power supply voltage Vin during hot-swapping is at most 1 millisecond. The voltage holding period implemented by the voltage holding circuit of this embodiment is set to be sufficiently long than the period during which the surge voltage is generated.

[0028] (effect)

[0029] Next, the operation of this implementation method will be explained.

[0030] The power supply voltage Vin of voltage source So1 is supplied to the drain of transistor T1. By changing the level of control signal Vgate, transistor T1 is turned on and off, thereby controlling the supply of output Vout to the load corresponding to the power supply voltage Vin.

[0031] (Normally)

[0032] Now, let's assume the power supply voltage Vin is under normal conditions without any surge voltage. The gate of transistor T1 (node ​​A) is connected to the reference potential point via the current paths of transistors T3 and T4. Under normal conditions, the power supply voltage Vin does not change drastically; therefore, the voltage at node A is the reference potential. Thus, transistor T2 is off, and transistor T1 is switched on and off according to the level of the control signal Vgate.

[0033] When the control signal Vgate is at level L, transistor T1 is off, and the output Vout based on the power supply voltage Vin is stopped from supplying the load. When the control signal Vgate is at level H, transistor T1 is turned on, and the output Vout based on the power supply voltage Vin is supplied to the load.

[0034] (When an impulse voltage is generated)

[0035] Now, assume the control signal Vgate is at level L. Here, we assume an impulse voltage is generated at the power supply voltage Vin. This impulse voltage generated by Vin is instantaneously transmitted to node A through capacitor C1. Node A is connected to the reference potential point via the current paths of transistors T3 and T4, and node A becomes the sum of the forward voltages of transistors T3 and T4. Through the voltage holding function of transistors T3 and T4, the voltage of node A is held for a predetermined period (hereinafter referred to as the holding period). In this case, the voltage of node A is higher than the threshold voltage of transistor T2. During the holding period, transistor T2 is turned on, allowing a large current to flow from the gate of transistor T1 to the reference potential point through the current path of transistor T2.

[0036] Due to the parasitic capacitance Cgd of transistor T1, the gate voltage of transistor T1 will increase due to the surge voltage generated by the power supply voltage Vin. However, with transistor T2 turning on, a large current flows from the gate of transistor T1 to the reference potential, suppressing the rise in the gate voltage of transistor T1 even under the condition of a high-throughput surge voltage. The period during which the power supply voltage Vin generates a surge voltage ends within the holding period; therefore, transistor T1 will not turn on due to the surge voltage generated by the power supply voltage Vin.

[0037] In this way, even if a surge voltage is generated in the power supply voltage Vin, a large current can be prevented from flowing in the load while the control signal Vgate is at the L level.

[0038] In addition, under normal conditions, transistor T2 is cut off, and no current flows from the gate of transistor T2 to the reference potential point, so the power consumption does not increase.

[0039] Thus, in this embodiment, even if a high-throughput-rate surge voltage is generated, it is possible to reliably prevent large currents from flowing through the load. Furthermore, under normal circumstances, power consumption does not increase.

[0040] For example, this embodiment can be used as a protection circuit for hot-swapping. Furthermore, while this embodiment describes an example of preventing inrush current caused by surge voltage in the power supply circuit, it can also be applied to prevent inrush current generated by surge voltages in electronic fuses, linear regulators, DC / DC converters, gate drivers, etc.

[0041] (Second Implementation)

[0042] Figure 3 This is a circuit diagram illustrating the second embodiment of the present invention. Figure 3 China and Figure 1The same components are assigned the same reference numerals and their descriptions are omitted. In this embodiment, the voltage holding circuit composed of transistors T3 and T4 is constructed using one or more diodes.

[0043] In this embodiment, instead of transistors T3 and T4, one diode D1 or two or more diodes D1, D2, ..., Dn (hereinafter, one or more diodes will be referred to as diode D) are used. This is consistent with... Figure 1 The implementation methods differ. When using a single diode D1 as diode D, the anode of diode D1 is connected to node A, and the cathode is connected to a reference potential point. When using two or more diodes as diode D, the anode of each diode D is connected to the cathode of the preceding diode, and the cathode is connected to the anode of the following diode. The anode of the primary diode D1 is connected to node A, and the cathode of the final diode Dn is connected to a reference potential point.

[0044] The sum of the forward voltages of diode D, which forms the voltage holding circuit, is set to be higher than the voltage required to turn on transistor T2. Furthermore, the voltage holding period at node A, implemented by diode D, is set to be sufficiently long than the period during which the surge voltage is generated.

[0045] Capacitor C1, transistor T2, and diode D function as a protective circuit to prevent surge currents caused by impulse voltages.

[0046] In this embodiment, the same effect as in the first embodiment is achieved.

[0047] That is, the surge voltage generated by the power supply voltage Vin is instantaneously transmitted to node A through capacitor C1. Through diode D, the voltage at node A is maintained at the voltage required to turn on transistor T2. The voltage at node A is maintained by diode D for a longer period than the period during which the surge voltage is generated, during which transistor T2 is turned on. Therefore, even if a surge voltage with a high throughput rate is generated by the power supply voltage Vin during the L level period of the control signal Vgate, transistor T1 is prevented from turning on. This prevents a large current from flowing through the load due to the surge voltage. Furthermore, under normal conditions, transistor T2 is off, and no current flows from the gate of transistor T2 to the reference potential point, thus not increasing power consumption.

[0048] Thus, in this embodiment, the same effect as in the first embodiment can be obtained.

[0049] (Third Implementation)

[0050] Figure 4 This is a circuit diagram illustrating the third embodiment of the present invention. Figure 4 China and Figure 1 Identical components are assigned the same reference numerals and their descriptions are omitted. In this embodiment, the voltage holding circuit composed of transistors T3 and T4 is constructed using Zener diodes.

[0051] In this embodiment, a Zener diode ZD is used instead of transistors T3 and T4, which is consistent with... Figure 1 The implementation methods differ. In the Zener diode ZD, the anode is connected to node A, and the cathode is connected to the reference potential point.

[0052] The Zener voltage of the Zener diode ZD, which serves as a voltage holding circuit, is set to be higher than the voltage required to turn on transistor T2. Furthermore, the holding period of the voltage at node A, implemented by the Zener diode ZD, is set to be sufficiently long than the period during which the surge voltage is generated.

[0053] Capacitor C1, transistor T2, and Zener diode ZD function as a protective circuit to prevent surge currents caused by impulse voltages.

[0054] In this embodiment, the same effect as in the first embodiment is achieved.

[0055] That is, the surge voltage generated by the power supply voltage Vin is instantaneously transmitted to node A through capacitor C1. Through Zener diode ZD, the voltage at node A is maintained at the voltage required to turn on transistor T2. The voltage at node A is maintained by Zener diode ZD for a longer period than the period during which the surge voltage is generated, during which transistor T2 is turned on. Therefore, even if a surge voltage with a high throughput rate is generated by the power supply voltage Vin during the L level period of the control signal Vgate, transistor T1 is prevented from turning on. This prevents a large current from flowing through the load due to the surge voltage. Furthermore, under normal conditions, transistor T2 is off, and no current flows from the gate of transistor T2 to the reference potential point, thus not increasing power consumption.

[0056] Thus, in this embodiment, the same effect as in the first embodiment can be obtained.

[0057] (Fourth implementation)

[0058] Figure 5 This is a circuit diagram illustrating the fourth embodiment of the present invention. Figure 5 China and Figure 3 The same components are assigned the same reference numerals and their descriptions are omitted. This embodiment differs from the previous embodiments in that it includes a function to stop the operation of the protection circuit. Furthermore, Figure 5 This indicates an example applied to the second embodiment, but this embodiment can also be applied to the first and third embodiments.

[0059] This embodiment differs from the previous embodiments by including an additional charge pump circuit CP, PMOS transistor T5, and NMOS transistors T6 and T7. In this embodiment, the control signal Vgate is generated by the charge pump circuit CP and transistors T5 and T6. For transistor T1 to conduct, the control signal Vgate needs to be a voltage higher than the supply voltage Vin. The supply voltage Vin is supplied to the charge pump circuit CP. The charge pump circuit CP uses the supply voltage Vin to generate and output a voltage higher than Vin.

[0060] A current path for transistors T5 and T6 is connected in series between the output terminal of the charge pump circuit CP and the reference potential point. Specifically, the source of transistor T5 is connected to the output of the charge pump circuit CP, and its drain is connected to the gate of transistor T1, where an output control signal is provided. Similarly, the drain of transistor T6 is connected to the gate of transistor T1, and its source is connected to the reference potential point, where an output control signal is provided.

[0061] When the output control signal is at level H, transistor T5 is off, transistor T6 is on, the control signal Vgate becomes level L, and transistor T1 is off. That is, when an output control signal of level H is supplied to the gates of transistors T5 and T6, the supply of output Vout to the load is stopped. In other words, the output control signal of level H effectively turns the main switch off.

[0062] When the output control signal is at level L, transistor T5 is turned on and transistor T6 is turned off. The control signal Vgate becomes level H through the output of the charge pump circuit CP, and transistor T1 becomes turned on. That is, when the level L output control signal is supplied to the gates of transistors T5 and T6, the output Vout is supplied to the load. In other words, the level L output control signal turns the main switch on (ON).

[0063] Node A is connected to the reference potential point via the current path of transistor T7. The drain of transistor T7 is connected to node A, the source is connected to the reference potential point, and a protection control signal is provided at the gate.

[0064] When the protection control signal is at level L, transistor T7 is off, and for node A, transistor T7 has no effect. That is, in this case, by generating a surge voltage at the supply voltage Vin, the voltage at node A is maintained during the hold period at the voltage that would turn on transistor T2. As a result, as described above, despite the surge voltage, transistor T1 is prevented from conducting, thus preventing large currents from flowing to the load.

[0065] However, in other words, during the period when the voltage at node A is maintained at the voltage required to turn on transistor T2 through the protection circuit, even if an output control signal at level L to turn on the main switch is supplied to the gates of transistors T5 and T6, the control signal Vgate remains at level L and cannot supply Vout to the load. For example, if the holding period is too long, even if the main switch becomes on, the output Vout will not be output. Transistor T7 prevents such malfunction of the protection circuit.

[0066] In this embodiment, the protection control signal is at level L during the period when the power supply voltage Vin generates an impulse voltage, and at level H during other periods. For example, the protection control signal may be set to level L for a predetermined period from the generation of the impulse voltage. Alternatively, the protection control signal may be set to level H during the period of the level L output control signal that turns on the main switch.

[0067] When the protection control signal is at level H, transistor T7 is turned on, causing the potential of node A to drop to the reference potential. Consequently, transistor T2 is turned off, preventing the gate voltage of transistor T1 from dropping. That is, in this case, transistor T1 is turned on and off according to the control signal Vgate corresponding to the level of the output control signal, and the supply of output Vout to the load is controlled.

[0068] In this configuration, when the protection control signal is at level L, the effect of generating an impulse voltage is the same as in the embodiments described above. That is, in this case, the voltage rise of the control signal Vgate is prevented by the protection circuit, the transistor T1 remains off, and a large current is prevented from flowing to the load.

[0069] On the other hand, for example, during the period when the L-level output control signal that turns on the main switch is applied to the gates of transistors T5 and T6, the protection control signal becomes H-level. In this case, transistor T7 turns on, the potential of node A becomes the reference potential, and transistor T2 turns off. Thus, according to the L-level output control signal, the control signal Vgate becomes H-level, and transistor T1 turns on. In this way, by turning on the main switch, the output Vout can be supplied to the load.

[0070] Thus, in this embodiment, the operation of the protection circuit can be stopped, and the supply of output Vout to the load can be made possible without the protection circuit malfunctioning.

[0071] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A power supply circuit, comprising: The first transistor has its drain connected to the input terminal of the power supply voltage and its source connected to the output terminal. It is turned on and off according to the control signal supplied to the gate, and supplies the output based on the input power supply voltage to the load connected to the output terminal, or stops the supply of the output to the load. The second transistor has its drain connected to the gate of the first transistor and its source connected to a reference potential point. It is turned on and off according to the level of the gate voltage of the second transistor. A capacitor is connected between the input terminal of the power supply voltage and the gate of the second transistor; as well as A voltage holding circuit, connected between the gate of the second transistor and a reference potential point, maintains the gate voltage of the second transistor, which is turned on by the voltage transmitted to the gate of the second transistor through the capacitor, for a certain period of time. It comprises a third transistor connected by a diode and a fourth transistor connected by a diode. The source of the third transistor is connected to the gate of the second transistor, and the gate and drain of the third transistor are connected together. The source of the fourth transistor is connected to the gate and drain of the third transistor, and the gate and drain of the fourth transistor are connected together to the reference potential point.

2. The power supply circuit according to claim 1, The voltage holding circuit replaces the third and fourth transistors and is composed of multiple diodes as two or more cascaded diodes. In the multiple diodes, the anode of each stage diode is connected to the cathode of the preceding stage diode, and the cathode is connected to the anode of the following stage diode. The anode of the primary diode is connected to the gate of the second transistor, and the cathode of the final stage diode is connected to the reference potential point.

3. The power supply circuit according to claim 1 or 2, It also includes a fifth transistor, one end of the current path of which is connected to the gate of the second transistor and the other end is connected to a reference potential point. The gate is provided with a protection control signal, and is turned on or off according to the voltage level of the protection control signal.

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