A ring oscillator circuit

Abstract

The application provides a ring oscillator circuit, comprising: a bias circuit and a delay circuit; the bias circuit is used for generating a first bias current and a second bias current, the first bias current is inversely proportional to a voltage drop resistance in the bias circuit and is proportional to a square root of a reference current; in the delay circuit, a first input end of a delay control circuit is used for obtaining the first bias current, and a second input end is used for obtaining the second bias current; a first capacitor is arranged in the delay control circuit, so that a rising delay time of an output end of the delay control circuit is proportional to the first capacitor, inversely proportional to the first bias current and proportional to a flip threshold of a delay inverter in the delay control circuit, wherein the flip threshold of the delay inverter is proportional to the square root of the reference current, so that an oscillation period of the ring oscillator circuit is mainly determined by the proportion of the resistance, the capacitance and the square root of the reference current in the circuit, and the relationship between the oscillation period and the size of the reference current is weakened.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically to a ring oscillator circuit. Background Technology

[0002] Synchronous sequential logic circuits require clock triggering. Communication protocols demand extremely precise level transition times for digital logic circuits, making a high-precision and stable clock essential. Oscillator circuits are a common method for generating clock signals in integrated circuits. Common oscillator circuits that provide clock signals to chips include the following:

[0003] One method is to use a quartz crystal oscillator. The quartz crystal oscillator on the circuit board occupies a large area and weight of the circuit system. The usage rate of large-area circuits represented by quartz crystal oscillators is decreasing day by day.

[0004] One type is the relaxation oscillator. The basic principle is to apply a triangular wave excitation to the input of the hysteresis comparator, so that the output of the hysteresis comparator continuously switches between high and low levels to generate a clock signal, which is usually at a low frequency.

[0005] A ring oscillator is a common circuit that can generate high-frequency clock signals within integrated circuits. The basic principle of a ring oscillator is that an odd number of inverters connected in series form a positive feedback loop, causing oscillation. The oscillation period is the sum of the delays of the inverters, which is twice the oscillation period. An existing ring circuit structure is as follows: Figure 1 As shown, a loop is formed by connecting an inverter with a delay control and an even number of inverters in series. Only one node in the inverter loop has a large capacitive load, so the oscillation period is mainly determined by the rise delay of the delay control unit.

[0006]

[0007] In the above formula, V TH2 refer to Figure 1 In the publicly disclosed circuit, M P2 and M N2 The flip-flop threshold of the inverter is determined by the oscillation period, which is inversely proportional to the reference current. A clock signal with a duty cycle close to 50% can be obtained by cascading a divider (composed of D flip-flops) after the oscillator.

[0008] In existing technical solutions, the oscillation time t of the ring oscillator r1 It will be significantly affected by the reference current I REF The magnitude of the current source has a significant impact. Furthermore, current analog electronics technology struggles to create a reference current source unaffected by manufacturing processes, power supply voltage, and temperature. Summary of the Invention

[0009] In view of this, embodiments of the present invention provide a ring oscillator circuit to reduce the degree to which the oscillation time of the ring oscillator is affected by the reference current.

[0010] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0011] A ring oscillator circuit, comprising:

[0012] Bias circuit and delay circuit;

[0013] The bias circuit is used to generate a first bias current and a second bias current, wherein the first bias current is inversely proportional to the voltage drop resistor in the bias circuit, and the first bias current is also directly proportional to the square root of the reference current of the ring oscillator circuit.

[0014] The delay circuit includes:

[0015] Delay control circuit, inverter cascade circuit and frequency divider;

[0016] The first input terminal of the delay control circuit is used to obtain the first bias current, and the second input terminal of the delay control circuit is used to obtain the second bias current. The delay control circuit is equipped with a first capacitor. Through the first capacitor, the rise delay time of the output terminal of the delay control circuit is proportional to the first capacitor, inversely proportional to the first bias current, and proportional to the flip threshold of the delay inverter in the delay control circuit. The flip threshold of the delay inverter is proportional to the square root of the reference current.

[0017] The input terminal of the inverter cascade circuit is connected to the output terminal of the delay control circuit. The output terminal of the inverter cascade circuit is connected to the control terminal of the delay control circuit and the input terminal of the frequency divider. The output terminal of the frequency divider serves as the output terminal of the ring oscillator circuit.

[0018] Optionally, in the above-described ring oscillator circuit, the bias circuit includes:

[0019] The bias circuit includes: a first current mirror circuit, a second current mirror circuit, a voltage follower, and a voltage drop resistor;

[0020] The first output terminal of the second current mirror circuit is used to provide a first bias current, and the second output terminal of the second current mirror circuit is connected to the first output terminal of the voltage follower. The magnitude of the first bias current is inversely proportional to the voltage drop resistor.

[0021] The first current mirror circuit is used to provide a reference current, a second bias current, and a third bias current;

[0022] The third bias current is connected to the target node and is used to generate a stable node voltage at the target node.

[0023] The non-inverting input of the voltage follower is connected to the target node, and the non-inverting output of the voltage follower is connected to the voltage drop resistor. This is used to generate and output a reference current that matches the resistance value of the voltage drop resistor based on the virtual short effect.

[0024] Optionally, in the above-described ring oscillator circuit, the delay control circuit includes:

[0025] A first inverter, the input of which is used to obtain the first bias current;

[0026] A time-delay inverter, the input of which is used to obtain the second bias current;

[0027] The first capacitor is disposed between the first inverter and the delay inverter, such that the delay time for the output voltage of the first inverter to rise from 0 to the flip threshold of the delay inverter 2 is proportional to the boost capacitor and the voltage drop resistor.

[0028] The inverter cascade circuit includes: an odd number of inverters connected in series, wherein the input terminal of the first inverter in the odd number of inverter cascades is connected to the output terminal of the delay inverter, and the output terminal of the last inverter cascade is connected to the control terminal of the first inverter.

[0029] The input terminal of the frequency divider is connected to the output terminal of the cascaded inverter at the end.

[0030] Optionally, in the above-described ring oscillator circuit, the first current mirror circuit includes:

[0031] First field-effect transistor, second field-effect transistor, third field-effect transistor, and reference current source;

[0032] The control terminals of the first field-effect transistor, the second field-effect transistor, and the third field-effect transistor are interconnected, and the control terminal of the first field-effect transistor is connected to the output terminal of the first field-effect transistor.

[0033] The reference current source is connected to the output terminal of the first field-effect transistor;

[0034] The input terminals of the first field-effect transistor, the second field-effect transistor, and the third field-effect transistor are connected to a DC power supply.

[0035] Optionally, in the above-described ring oscillator circuit, the second current mirror circuit includes:

[0036] The fourth and fifth field-effect transistors;

[0037] The control terminals of the fourth and fifth field-effect transistors are interconnected, and the control terminal of the fourth field-effect transistor is connected to the output terminal of the fifth field-effect transistor.

[0038] Optionally, in the above-described ring oscillator circuit, the voltage follower includes:

[0039] First operational amplifier and first transistor;

[0040] The non-inverting input of the first operational amplifier is connected to the target node;

[0041] The control terminal of the first transistor is connected to the output terminal of the first operational amplifier;

[0042] The output terminal of the first transistor is connected to the inverting input terminal of the first operational amplifier and grounded through a voltage drop resistor.

[0043] Optionally, in the above-described ring oscillator circuit, the bias circuit further includes:

[0044] Second transistor;

[0045] The control terminal and input terminal of the second transistor are connected to the target node;

[0046] The output terminal of the second transistor is grounded.

[0047] Optionally, in the above-described ring oscillator circuit, the first inverter includes:

[0048] The third transistor, the fourth transistor, and the first capacitor;

[0049] The control terminals of the third transistor and the fourth transistor are interconnected. The input terminal of the third transistor is used to obtain the first bias current. The output terminal of the third transistor is connected to the input terminal of the fourth transistor, and the output terminal of the fourth transistor is grounded.

[0050] The first terminal of the first capacitor is connected to the input terminal of the fourth transistor, and the second terminal of the first capacitor is connected to the output terminal of the fourth transistor.

[0051] Optionally, in the above-described ring oscillator circuit, the delay inverter includes:

[0052] The fifth transistor;

[0053] The input terminal of the fifth transistor is used to obtain the second bias current;

[0054] The control terminal of the fifth transistor is connected to the output terminal of the first inverter;

[0055] The output terminal of the fifth transistor is grounded.

[0056] Optionally, in the above ring oscillator circuit, each cascaded inverter includes:

[0057] The sixth and seventh transistors;

[0058] The control terminals of the sixth transistor and the seventh transistor are interconnected. The input terminal of the sixth transistor is connected to the DC power supply. The output terminal of the sixth transistor is connected to the input terminal of the seventh transistor. The output terminal of the seventh transistor is grounded. The control terminals of the sixth transistor and the seventh transistor serve as the input terminals of the cascaded inverters. The output terminal of the sixth transistor serves as the output terminal of the cascaded inverters.

[0059] Optionally, in the above-described ring oscillator circuit, the voltage drop resistor is an adjustable resistor.

[0060] Optionally, in the above-described ring oscillator circuit, the first capacitor is an adjustable capacitor.

[0061] Based on the above technical solution, in the solution provided by the embodiments of the present invention, the oscillation period of the ring oscillator circuit is mainly determined by the resistance, capacitance, and reference current I in the circuit. REF The ratio of the square root of the equation weakens the correlation between the oscillation period and the reference current I. REF The relationship between sizes. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0063] Figure 1 This is a schematic diagram of a ring oscillator circuit structure in the prior art;

[0064] Figure 2 This is a schematic diagram of the ring oscillator circuit disclosed in the embodiments of this application;

[0065] Figure 3 This is a schematic diagram of the specific structure of the bias circuit A in the ring oscillator circuit disclosed in the embodiment of this application;

[0066] Figure 4 This is a schematic diagram of the specific structure of the delay circuit B in the ring oscillator circuit disclosed in the embodiment of this application;

[0067] Figure 5 This is a schematic diagram of the voltage changes at nodes V1 and V2 in the delay circuit B disclosed in this application embodiment. Detailed Implementation

[0068] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0069] To address the issue that the oscillation time of a ring oscillator is significantly affected by the reference current I... REF To address the issue of the influence of magnitude, this application discloses a ring oscillator circuit, see [link to relevant documentation]. Figure 2 The ring oscillator circuit includes:

[0070] Bias circuit A and delay circuit B;

[0071] The bias circuit A is used to generate a first bias current I1 and a second bias current I2, wherein the first bias current I1 is inversely proportional to the voltage drop resistor R0 within the bias circuit A, and the first bias current is also related to the reference current I of the ring oscillator circuit. REF It is directly proportional to the square root;

[0072] The delay circuit B includes:

[0073] Delay control circuit B1, inverter cascade circuit B2, and frequency divider B3;

[0074] The first input terminal of the delay control circuit B1 is used to acquire the first bias current I1, and the second input terminal of the delay control circuit B1 is used to acquire the second bias current I2. The delay control circuit B1 is equipped with a first capacitor C1. Through the first capacitor C1, the rise delay time of the output terminal of the delay control circuit is proportional to the first capacitor and inversely proportional to the first bias current I1. That is, the rise delay time of the output terminal of the delay control circuit is proportional to the first capacitor and the voltage drop resistor, and proportional to the switching threshold of the delay inverter in the delay control circuit. The switching threshold of the delay inverter is proportional to the square root of the reference current.

[0075] The input terminal of the inverter cascade circuit B2 is connected to the output terminal of the delay control circuit B1. The output terminal of the inverter cascade circuit is connected to the control terminal of the delay control circuit and the input terminal of the frequency divider B3. The output terminal of the frequency divider B3 serves as the output terminal of the ring oscillator circuit.

[0076] In the above-described solution provided by the embodiments of the present invention, by configuring a voltage drop resistor and a first capacitor in the ring oscillator circuit, the rise delay time of the output terminal of the delay control circuit is proportional to the first capacitor and the voltage drop resistor. This makes the oscillation period of the ring oscillator circuit mainly determined by the ratio of the voltage drop resistor, the first capacitor, the transistor turn-on threshold, and the current mirror in the circuit, thus weakening the dependence of the oscillation period on the reference current I of the ring oscillator circuit. REF The relationship between sizes.

[0077] In the following specific embodiments, this application also discloses the specific structures of the bias circuit A and the delay circuit B.

[0078] See Figure 3 The bias circuit A includes: a first current mirror circuit 101, a second current mirror circuit 102, and a voltage follower 103;

[0079] The first output terminal of the second current mirror circuit 102 is used to provide a first bias current I1, and the second output terminal of the second current mirror circuit 102 is connected to the output terminal of the voltage follower 103.

[0080] The first current mirror circuit 101 is used to provide a reference current I. REF The second bias current I2 and the third bias current I3;

[0081] The third bias current I3 is connected to the target node O and is used to generate a stable node voltage at the target node O.

[0082] The non-inverting input terminal of the voltage follower 103 is connected to the target node O, and the voltage follower 103 is used to generate a reference current at its output terminal.

[0083] See Figure 4 The delay control circuit B1 includes:

[0084] The first delay inverter 201 is used to obtain the first bias current I1.

[0085] Delay inverter 202, the input terminal of which is used to obtain the second bias current I2;

[0086] A first capacitor C1 is provided between the first delay inverter 201 and the delay inverter 202.

[0087] The inverter cascade circuit B2 includes:

[0088] An odd number of inverters are cascaded in series 203, the input terminal of the first inverter cascade 203 is connected to the output terminal of the delay inverter 202, and the output terminal of the last inverter cascade 203 is connected to the control terminal of the first delay inverter 201.

[0089] Frequency divider B3, the input of which is connected to the output of the inverter cascade 203 at the end, and the output of frequency divider B3 serves as the output of the ring oscillator circuit.

[0090] See Figure 3 The first current mirror circuit 101 includes:

[0091] The first field-effect transistor M m0 The second field-effect transistor M m1 The third field-effect transistor M m2 and a reference current source, the reference current source being used to provide a reference current I REF ;

[0092] The first field-effect transistor M m0 The second field-effect transistor M m1 and the third field-effect transistor M m2 The control terminals are interconnected, and the first field-effect transistor M m0 The control terminal and the first field-effect transistor M m0 Connect to the output terminal;

[0093] The reference current source and the first field-effect transistor M m0 Connect to the output terminal;

[0094] The first field-effect transistor M m0 The second field-effect transistor M m1 and the third field-effect transistor M m2 The input terminal is connected to the DC power supply V. DD Connected.

[0095] See Figure 3 In the above embodiments, the first field-effect transistor M m0 The control terminal (gate) and output terminal (drain) are connected in a diode configuration, forming the first field-effect transistor M. m0 The second field-effect transistor M m1 The third field-effect transistor M m2The control terminals (gates) are connected together to form a current mirror circuit. The reference current source is connected to the first field-effect transistor M. m0 The gate and drain of the transistor are connected, and the first current mirror circuit 101 generates two bias currents: a second bias current I2 and a third bias current I3. In this embodiment, the first field-effect transistor M... m0 The second field-effect transistor M m1 The third field-effect transistor M m2 The width-to-length ratio can be 1:m:n, where m and n are greater than 0. In this case, the second bias current I2 = mI REF The third bias current I3 = nI REF .

[0096] See Figure 3 The third field-effect transistor M m2 The drain of the current is connected to the target node O, causing the third bias current I3 to generate a stable node voltage VGS,REF at the target node O. (See also...) Figure 3 In order to generate a stable node voltage VGS,REF at the target node O by the third bias current I3, in this scheme, the bias circuit A also includes a second transistor M. n0 The second transistor M n0 The gate and drain are connected, causing the third bias current I3 to flow through the diode-connected second transistor M. n0 A stable node voltage VGS,REF is generated, and its value can be expressed as:

[0097]

[0098] Wherein, the μ n Indicates the second transistor M n0 The electron mobility, the c ox Indicates the second transistor M n0 The capacitance per unit area of ​​the gate oxide layer, where W represents the capacitance of the second transistor M. n0 The channel width, where L represents the second transistor M. n0 The channel length, where N0 represents the second transistor M. n0 The V t,N0 Indicates the second transistor M n0 threshold voltage

[0099] See Figure 3 The voltage follower 103 includes:

[0100] First operational amplifier OP and first transistor M p0 ;

[0101] The non-inverting input of the first operational amplifier OP is connected to the target node O;

[0102] The first transistor M p0 The control terminal is connected to the output terminal of the first operational amplifier OP;

[0103] The first transistor M p0 The output terminal is connected to the inverting input terminal of the first operational amplifier OP, and grounded through the voltage drop resistor R0.

[0104] See Figure 3 In the technical solution disclosed in the embodiments of this application, the first operational amplifier OP and the first transistor M P0 The voltage follower 103 is formed by connecting the non-inverting input of the first operational amplifier OP to the second transistor M. N0 The gate and drain are connected, and the inverting input is connected to the first transistor M. p0 The source and the common terminal of the voltage drop resistor R0 are connected, and the output terminal of the first operational amplifier OP is connected to the first transistor M. p0 The gate is connected. Utilizing the virtual short effect of the first operational amplifier OP, the voltages at the non-inverting and inverting input terminals of the first operational amplifier OP are equal. The aforementioned node voltage VGS,REF generates a reference current through the voltage follower 103 across the voltage drop resistor R0. This reference current is amplified by a factor of k by the current mirror of the second current mirror circuit 102 to obtain the first bias current I1.

[0105] As can be seen from this formula, the first bias current I1 and the reference current I REF The value of the voltage drop resistor R0 is directly proportional to the square root of the current and the magnification k of the current mirror, and inversely proportional to the value of the voltage drop resistor R0. In the above formula, R0 is the resistance value of the voltage drop resistor.

[0106] See Figure 3 The second current mirror circuit 102 includes:

[0107] Fourth field-effect transistor M m3 and the fifth field-effect transistor M m4 ;

[0108] The fourth field-effect transistor M m3 and the fifth field-effect transistor M m4 The control terminals are interconnected, and the fourth field-effect transistor M is... m3 The control terminal and the fifth field-effect transistor M m4 Connect the output terminal.

[0109] See Figure 4 The third transistor M in the delay control circuit B1P1 Fourth transistor M N1 This constitutes the first delay inverter 201. The fifth transistor M... N2 and the aforementioned switching transistor M m1 A delay-delay inverter 202 is constructed, with the first capacitor C1 disposed between the first delay inverter 201 and the delay-delay inverter 202. Each inverter cascade 203 in the inverter cascade circuit includes: a sixth transistor M. p3 and the seventh transistor M m3 ;

[0110] The third transistor M P1 and the fourth transistor M N1 The control terminals are interconnected, and the third transistor M P1 The input terminal is used to obtain the first bias current I1, and the third transistor M P1 The output terminal is connected to the fourth transistor M N1 The fourth transistor M is connected to the input terminal. N1 The output terminal is grounded;

[0111] The first terminal of the first capacitor C1 is connected to the fourth transistor M N1 The input terminal of the first capacitor C1 is connected to the second terminal of the fourth transistor M. N1 Connect the output terminal.

[0112] The fifth transistor M N2 The input terminal is used to obtain the second bias current I2;

[0113] The fifth transistor M N2 The control terminal is connected to the output terminal of the first delay inverter 201;

[0114] The fifth transistor M N2 The output terminal is grounded.

[0115] The sixth transistor M p3 and the seventh transistor M m3 The control terminals are interconnected, and the sixth transistor M is connected. p3 The input terminal is connected to the DC power supply V DD Connected, the sixth transistor M p3 The output terminal is connected to the seventh transistor M m3 The seventh transistor M is connected to the input terminal. m3 The output terminal of the sixth transistor M is grounded. p3 and the seventh transistor M m3 The control terminal serves as the input terminal of the inverter cascade 203, and the sixth transistor M p3The output terminal is used as the output terminal of the inverter cascade 203.

[0116] In the above scheme, the switching threshold of the delay inverter 2 is approximately equal to the gate-source voltage of the fifth transistor MN2 when it enters the saturation region, and its value is:

[0117] As can be seen from this formula, the switching threshold of the delay inverter 2 is related to the reference current I. REF It is proportional to the square root.

[0118] N2 represents the fifth transistor M. N2 V t,N2 For the fifth transistor M N2 The threshold voltage, μ in the formula n Indicates the fifth transistor M N2 The electron mobility, the c ox Indicates the fifth transistor M N2 The gate oxide capacitance per unit area, where W represents the fifth transistor M. N2 The channel width, where L represents the fifth transistor M. N2 The length of the channel.

[0119] The voltage at node V1 rises from potential 0 to V TH2 The delay is:

[0120] As can be seen from the formula, the rise delay time of the output terminal of the delay control circuit is directly proportional to the first capacitor, inversely proportional to the first bias current, and directly proportional to the switching threshold of the delay inverter in the delay control circuit, wherein the switching threshold of the delay inverter is directly proportional to the square root of the reference current.

[0121] As can be seen, in the ring oscillator circuit disclosed in the embodiments of this application, the resistance value of the voltage drop resistor R0 and the capacitance value of the first capacitor C1 can be appropriately set to make t r1 Much larger than other delays tod in the oscillation period, the oscillation period T is determined by the rise delay of the delay circuit B, thus achieving a weak correlation between the oscillation period and the magnitude of the reference current. Specifically, the waveforms of the voltages V1 and V2 at key nodes in the circuit are as follows: Figure 5 As shown.

[0122] In the technical solutions disclosed in the embodiments of this application, in order to adjust the t according to requirements r1 The voltage drop resistor is an adjustable resistor. The first capacitor C1 is an adjustable capacitor.

[0123] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0124] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A ring oscillator circuit, characterized in that, include: Bias circuit and delay circuit; The bias circuit is used to generate a first bias current and a second bias current, wherein the first bias current is inversely proportional to the voltage drop resistor in the bias circuit, and the first bias current is also directly proportional to the square root of the reference current of the ring oscillator circuit. The delay circuit includes: Delay control circuit, inverter cascade circuit and frequency divider; The first input terminal of the delay control circuit is used to obtain the first bias current, and the second input terminal of the delay control circuit is used to obtain the second bias current. The delay control circuit is equipped with a first capacitor. Through the first capacitor, the rise delay time of the output terminal of the delay control circuit is proportional to the first capacitor, inversely proportional to the first bias current, and proportional to the flip threshold of the delay inverter in the delay control circuit. The flip threshold of the delay inverter is proportional to the square root of the reference current. The input terminal of the inverter cascade circuit is connected to the output terminal of the delay control circuit. The output terminal of the inverter cascade circuit is connected to the control terminal of the delay control circuit and the input terminal of the frequency divider. The output terminal of the frequency divider serves as the output terminal of the ring oscillator circuit.

2. The ring oscillator circuit according to claim 1, characterized in that, The bias circuit includes: The bias circuit includes: a first current mirror circuit, a second current mirror circuit, a voltage follower, and a voltage drop resistor; The first output terminal of the second current mirror circuit is used to provide a first bias current, and the second output terminal of the second current mirror circuit is connected to the first output terminal of the voltage follower. The magnitude of the first bias current is inversely proportional to the voltage drop resistor. The first current mirror circuit is used to provide a reference current, a second bias current, and a third bias current; The third bias current is connected to the target node and is used to generate a stable node voltage at the target node. The non-inverting input of the voltage follower is connected to the target node, and the non-inverting output of the voltage follower is connected to the voltage drop resistor. This is used to generate and output a reference current that matches the resistance value of the voltage drop resistor based on the virtual short effect.

3. The ring oscillator circuit according to claim 1, characterized in that, The delay control circuit includes: A first inverter, the input of which is used to obtain the first bias current; A time-delay inverter, the input of which is used to obtain the second bias current; The first capacitor is disposed between the first inverter and the delay inverter, such that the delay time for the output voltage of the first inverter to rise from 0 to the flip threshold of the delay inverter 2 is proportional to the boost capacitor and the voltage drop resistor. The inverter cascade circuit includes: an odd number of inverters connected in series, wherein the input terminal of the first inverter in the odd number of inverter cascades is connected to the output terminal of the delay inverter, and the output terminal of the last inverter cascade is connected to the control terminal of the first inverter. The input terminal of the frequency divider is connected to the output terminal of the cascaded inverter at the end.

4. The ring oscillator circuit according to claim 2, characterized in that, The first current mirror circuit includes: First field-effect transistor, second field-effect transistor, third field-effect transistor, and reference current source; The control terminals of the first field-effect transistor, the second field-effect transistor, and the third field-effect transistor are interconnected, and the control terminal of the first field-effect transistor is connected to the output terminal of the first field-effect transistor. The reference current source is connected to the output terminal of the first field-effect transistor; The input terminals of the first field-effect transistor, the second field-effect transistor, and the third field-effect transistor are connected to a DC power supply.

5. The ring oscillator circuit according to claim 4, characterized in that, The second current mirror circuit includes: The fourth and fifth field-effect transistors; The control terminals of the fourth and fifth field-effect transistors are interconnected, and the control terminal of the fourth field-effect transistor is connected to the output terminal of the fifth field-effect transistor.

6. The ring oscillator circuit according to claim 5, characterized in that, The voltage follower includes: First operational amplifier and first transistor; The non-inverting input of the first operational amplifier is connected to the target node; The control terminal of the first transistor is connected to the output terminal of the first operational amplifier; The output terminal of the first transistor is connected to the inverting input terminal of the first operational amplifier and grounded through a voltage drop resistor.

7. The ring oscillator circuit according to claim 6, characterized in that, The bias circuit further includes: Second transistor; The control terminal and input terminal of the second transistor are connected to the target node; The output terminal of the second transistor is grounded.

8. The ring oscillator circuit according to claim 3, characterized in that, The first inverter includes: The third transistor, the fourth transistor, and the first capacitor; The control terminals of the third transistor and the fourth transistor are interconnected. The input terminal of the third transistor is used to obtain the first bias current. The output terminal of the third transistor is connected to the input terminal of the fourth transistor, and the output terminal of the fourth transistor is grounded. The first terminal of the first capacitor is connected to the input terminal of the fourth transistor, and the second terminal of the first capacitor is connected to the output terminal of the fourth transistor.

9. The ring oscillator circuit according to claim 8, characterized in that, The delay inverter includes: The fifth transistor; The input terminal of the fifth transistor is used to obtain the second bias current; The control terminal of the fifth transistor is connected to the output terminal of the first inverter; The output terminal of the fifth transistor is grounded.

10. The ring oscillator circuit according to claim 9, characterized in that, Each inverter cascade includes: The sixth and seventh transistors; The control terminals of the sixth transistor and the seventh transistor are interconnected. The input terminal of the sixth transistor is connected to a DC power supply. The output terminal of the sixth transistor is connected to the input terminal of the seventh transistor. The output terminal of the seventh transistor is grounded. The control terminals of the sixth transistor and the seventh transistor serve as the input terminals of the cascaded inverters. The output terminal of the sixth transistor serves as the output terminal of the cascaded inverters.

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