An asynchronous BiSS-C protocol decoding method based on FPGA
The FPGA's baud rate clock module, BiSS-C data decoding module, and CRC check module solve the problem of parsing encoder position information transmitted via the BiSS-C protocol under asynchronous clock conditions, achieving accurate data decoding and verification.
Patent Information
- Application Number
- CN202211374397.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-04
- Publication Date
- 2025-09-09
- Estimated Expiration
- 2042-11-04
AI Technical Summary
Under asynchronous clock, FPGA cannot effectively parse the encoder position information transmitted by the BiSS-C protocol, and there is a lack of relevant literature and data support in China.
An FPGA-based asynchronous BiSS-C protocol decoding method is adopted, including a baud rate clock module, a BiSS-C data decoding module and a CRC check module. The correct analysis of the encoder position data is achieved through sampling, decoding and verification.
Effective parsing of encoder position information transmitted via the BiSS-C protocol is achieved under an asynchronous clock, ensuring data accuracy and integrity.
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Figure CN115866076B_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of grating encoder data acquisition, and in particular relates to an asynchronous BiSS-C protocol decoding method based on FPGA. Background Art
[0002] The BISS communication protocol is a full-duplex synchronous serial bus communication protocol designed specifically for real-time, bidirectional, high-speed sensor communication. The current version of the BISS communication protocol is BISS-C. In servo systems, encoders mostly use the BISS-C protocol. In the BISS-C protocol, the communicating parties are the master and the slave, respectively. The encoder acts as the slave, while the servo drive or motion controller acts as the master. The master reads the position information collected by the encoder using the BISS-C protocol. The BISS-C protocol has two communication modes: sensor mode and register mode. In sensor mode, the master can only read sensor information sent by the slave, while in register mode, it can obtain all available information from the slave and set slave parameters.
[0003] Existing technologies for processing the BiSS-C protocol in FPGAs are all based on synchronous clocks, meaning the BiSS-C protocol's master signal (MA) serves as the FPGA's operating clock. However, in some applications, the master signal (MA) bypasses the FPGA and is instead sent to the encoder by the encoder's rotation control board. In these cases, the FPGA must interpret the BiSS-C position data using an asynchronous clock. However, no relevant literature in China explains how to handle this situation. Furthermore, there is no detailed public documentation in China regarding FPGA software implementations of BiSS-C protocol decoding. Summary of the Invention
[0004] The present invention overcomes one of the deficiencies of the prior art and provides an FPGA-based asynchronous BiSS-C protocol decoding method to solve the problem of using FPGA to parse encoder position information transmitted by the BiSS-C protocol under an asynchronous clock.
[0005] According to one aspect of the present disclosure, the present invention provides an asynchronous BiSS-C protocol decoding method based on an FPGA, wherein the FPGA includes a baud rate clock module, a BiSS-C data decoding module, and a CRC check module. The method includes:
[0006] The encoder position data transmitted by the SLO line is sampled by the baud rate clock module;
[0007] Based on the BiSS-C data protocol, the BiSS-C data decoding module is used to decode the encoder position data transmitted by the SLO line to obtain decoded data of the encoder position data;
[0008] When the encoder position data decoding completion flag is detected, the CRC check module moves the decoded data of the encoder position data into the register to obtain the CRC check code of the encoder position data, compares the CRC code of the encoder position data and the CRC check code, and if the two are consistent, obtains the encoder position data.
[0009] In one possible implementation, the using the baud rate clock module to sample the encoder position data transmitted on the SLO line includes:
[0010] Dividing the system clock signal of the baud rate clock module to obtain the baud rate clock signal of the baud rate clock module;
[0011] The encoder position data transmitted on the SLO line is sampled based on the frequency of the baud rate clock signal of the baud rate clock module.
[0012] In one possible implementation, decoding the encoder position data transmitted on the SLO line using the BiSS-C data decoding module based on the BiSS-C data protocol includes:
[0013] Setting a state machine of the BiSS-C data decoding module based on a data frame format of the BiSS-C data protocol;
[0014] Decoding the encoder position data transmitted on the SLO line using the state machine of the BiSS-C data decoding module;
[0015] The state machine includes a WAIT state, an IDLE state, an ACK state, a START state, a ZERO state and a DATA state.
[0016] In one possible implementation, decoding the encoder position data transmitted on the SLO line using the state machine of the BiSS-C data decoding module includes:
[0017] When a system reset signal is detected, the state machine enters the WAIT state, and when the input signal of the SLO line is 1, the state machine jumps to the IDLE state;
[0018] In the IDLE state, when the input signal of the SLO line is 0, the state machine jumps to the ACK state;
[0019] In the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the START state;
[0020] In the START state, when the start bit of the encoder position data frame is detected, the state machine jumps to the ZERO state;
[0021] In the ZERO state, when the "0" bit of the encoder position data frame is detected, the state machine jumps to the DATA state;
[0022] In the DATA state, at the rising edge of the baud rate clock signal, the encoder position data transmitted by the SLO line is received bit by bit, and the encoder position data is shifted into the shift register for latching in the order of high bit first to obtain the decoded data of the encoder position data.
[0023] In a possible implementation, in the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the START state; in the START state, when the start bit of the encoder position data frame is detected, the state machine jumps to the ZERO state; including:
[0024] Wherein, the START state includes the START1 state and the START2 state;
[0025] In the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the START1 state;
[0026] On the rising edge of the baud rate clock signal, the baud rate clock count signal baud_counter is increased by 1. When the baud rate clock count signal baud_counter is 7, the SLO line input signal level is sampled as the flag bit bit_samp;
[0027] When the baud rate clock signal (baud_pulse) is 1 and the baud rate clock count signal baud_counter is greater than 8, when the flag bit bit_samp is 1, the state machine jumps from the START1 state to the START2 state;
[0028] At the rising edge of the baud rate clock signal, the time count value cnt of the START2 state is increased by 1. When the SLO line input signal level is 0 and the time count value cnt of the START2 state is less than 20, the flag bit bit_samp is the start bit of the encoder position data frame, and the state machine jumps to the ZERO state.
[0029] In one possible implementation, the "0" bit of the encoder position data frame includes:
[0030] In the ZERO state, the baud rate clock count signal baud_counter is increased by 1 on the rising edge of the baud rate clock signal. When the baud rate clock count signal baud_counter is greater than 8, the flag bit bit_samp is 0, and the flag bit bit_samp is used as the 0th bit of the encoder position data frame.
[0031] In one possible implementation, in the DATA state, at the rising edge of the baud rate clock signal, receiving the encoder position data transmitted by the SLO line bit by bit includes:
[0032] In the DATA state, at the rising edge of the baud rate clock signal, the encoder position data transmitted by the SLO line is received bit by bit. When one bit of encoder position data is received, the DATA data bit count value bit_counter is increased by 1, and the DATA data bit count value bit_counter is cyclically increased from 0 to 33.
[0033] In a possible implementation, the encoder position data and the decoded data of the encoder position data include: 26-bit encoder position data, 1 error bit, 1 warning bit, and a 6-bit CRC code.
[0034] In one possible implementation, when the encoder position data decoding completion flag is detected, the CRC check module shifts the decoded data of the encoder position data into a register to obtain a CRC check code of the encoder position data, compares the CRC code of the encoder position data and the CRC check code, and obtains the encoder position data if the two are consistent, including:
[0035] P1: When the encoder position data decoding completion flag is detected, the data register is initialized, and the 26-bit encoder position data, 1 error bit, and 1 warning bit of the decoded encoder position data are stored in the data register, and the last 6 bits of the data register are filled with 0;
[0036] P2: Shift the data in the data register left by one bit, read in new data and place it into the lowest bit of the data register. When the shifted-out bit data is 1, perform an XOR operation on the data in the data register and the generated polynomial.
[0037] P3: Repeat step P2 until all 26 bits of data are processed and the content in the data register is the CRC check code;
[0038] P4: Compare the CRC code and CRC check code of the encoder position data. If the two are consistent and the error bit is 1, the encoder position data is output.
[0039] In a possible implementation, the frequency of the baud rate clock signal of the baud rate clock module is 16 times the frequency of the BiSS-C protocol clock MA.
[0040] The present invention discloses an FPGA-based asynchronous BiSS-C protocol decoding method. The FPGA includes a baud rate clock module, a BiSS-C data decoding module, and a CRC check module. The baud rate clock module samples encoder position data transmitted on the SLO line. Based on the BiSS-C data protocol, the BiSS-C data decoding module decodes the encoder position data transmitted on the SLO line to obtain decoded encoder position data. Upon detecting a decode completion flag for the encoder position data, the CRC check module shifts the decoded encoder position data into a register to obtain a CRC check code for the encoder position data. The CRC code of the encoder position data and the CRC check code are compared. If the two match, the encoder position data is obtained. This method solves the problem of using an FPGA to parse encoder position information transmitted via the BiSS-C protocol under an asynchronous clock. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] The accompanying drawings are used to provide a further understanding of the technical solution of this application or the prior art and constitute a part of the specification. Among them, the drawings that express the embodiments of this application are used together with the embodiments of this application to explain the technical solution of this application, but do not constitute a limitation of the technical solution of this application.
[0042] Figure 1 A schematic diagram of a module of an FPGA according to an embodiment of the present disclosure is shown;
[0043] Figure 2 A flowchart of an asynchronous BiSS-C protocol decoding method based on FPGA according to an embodiment of the present disclosure is shown;
[0044] Figure 3 FIG2 shows a schematic diagram of a jump module of a state machine of a BiSS-C data decoding module according to an embodiment of the present disclosure;
[0045] Figure 4 A ModelSim simulation state transition diagram according to an embodiment of the present disclosure is shown;
[0046] Figure 5 A schematic diagram of simulation results of inputting 3 frames of correct encoder position data according to an embodiment of the present disclosure is shown;
[0047] Figure 6 FIG1 is a schematic diagram of simulation results of inputting 1 frame of correct encoder position data and 2 frames of erroneous encoder position data according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0048] The following will describe the implementation methods of the present invention in detail with reference to the accompanying drawings and examples, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve corresponding technical effects can be fully understood and implemented accordingly. The embodiments of this application and the various features in the embodiments can be combined with each other without conflict, and the technical solutions formed are all within the scope of protection of the present invention.
[0049] In addition, the steps shown in the flowchart of the accompanying drawings can be executed in a computer such as a set of computer-executable instructions. Also, although a logical order is shown in the flowchart, in some cases, the steps shown or described can be performed in a different order than here.
[0050] Figure 1 A module schematic diagram of an FPGA according to an embodiment of the present disclosure is shown.
[0051] like Figure 1 As shown, the FPGA software includes a baud rate clock module, a BiSS-C data decoding module, and a CRC check module. The baud rate clock module has three signal interfaces: system clock signal clk, system reset signal reset_n, and baud rate clock signal baud_pulse. The BiSS-C data decoding module has five signal interfaces: system clock signal clk, system reset signal reset_n, baud rate clock signal baud_pulse, SLO line serial data rxd, and decoded output data bissc_in. The CRC check module has four signal interfaces: system clock signal clk, system reset signal reset_n, decoded output data bissc_in, and check output data bissc_out.
[0052] Figure 2 The flowchart of the asynchronous BiSS-C protocol decoding method based on FPGA according to an embodiment of the present disclosure is shown; the method utilizes Figure 1 The asynchronous decoding of the FPGA is shown as Figure 2 As shown, the method may include:
[0053] Step S1: using the baud rate clock module to sample the encoder position data transmitted by the SLO line.
[0054] The encoder position data and the decoded data of the encoder position data include: 26-bit encoder position data, 1 error bit, 1 warning bit, and 6-bit CRC code.
[0055] The baud rate clock module's system clock signal clk is divided to obtain the baud rate clock module's baud rate clock signal baud_pulse. The encoder position data transmitted on the SLO line is sampled based on the frequency of the baud rate clock signal baud_pulse of the baud rate clock module. The frequency of the baud rate clock signal baud_pulse of the baud rate clock module can be 16 times the frequency of the BiSS-C protocol clock MA, which can be used to perform 16-fold sampling of the encoder position data transmitted on the SLO line. For example, if the frequency of the system clock clk is 50 MHz and the frequency of the BiSS-C protocol clock MA is 1 MHz, then the frequency of the baud rate clock signal baud_pulse is 16 MHz.
[0056] Step S2: Based on the BiSS-C data protocol, the BiSS-C data decoding module is used to decode the encoder position data transmitted on the SLO line to obtain decoded data of the encoder position data.
[0057] The BiSS-C data decoding module includes a state machine for decoding encoder position data transmitted on the SLO line. The state machine is configured based on the data frame format of the BiSS-C data protocol. Specifically, the state machine transitions according to the BiSS-C data frame format. The state machine is then used to decode the encoder position data transmitted on the SLO line. The encoder position data can be serial data (the SLO line transmits serial data).
[0058] In one example, decoding encoder position data transmitted on the SLO line using the state machine of the BiSS-C data decoding module may include:
[0059] When a system reset signal is detected, the state machine enters the WAIT state, and when the input signal of the SLO line is 1, the state machine jumps to the IDLE state;
[0060] In the IDLE state, when the input signal of the SLO line is 0, the state machine jumps to the ACK state;
[0061] In the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the START state;
[0062] In the START state, when the start bit of the encoder position data frame is detected, the state machine jumps to the ZERO state;
[0063] In the ZERO state, when the "0" bit of the encoder position data frame is detected, the state machine jumps to the DATA state;
[0064] In the DATA state, at the rising edge of the baud rate clock signal, the encoder position data transmitted by the SLO line is received bit by bit, and the encoder position data is shifted into the shift register for latching in the order of high bit first to obtain the decoded data of the encoder position data.
[0065] Figure 3 A schematic diagram of a jump module of a state machine of a BiSS-C data decoding module according to an embodiment of the present disclosure is shown.
[0066] Specifically, Figure 3 As shown, the state machine may include a WAIT state, an IDLE state, an ACK state, a START state, a ZERO state, a DATA state, a TIMEOUT state, and a FINISH state.
[0067] The BiSS-C data decoding module's state machine defaults to the WAIT state. When the system reset signal reset_n is asserted, the state machine enters the WAIT state. In the WAIT state, if the SLO line input signal level rxd is 1, the state machine transitions to the IDLE state; otherwise, it remains in the WAIT state. In the IDLE state, if the SLO line input signal level rxd is 0, the state machine transitions to the ACK state; otherwise, it remains in the IDLE state. After entering the ACK state, if the SLO line input signal rxd is 1, the state machine transitions to the START state; otherwise, it remains in the ACK state.
[0068] The START state includes the START1 state and the START2 state. In the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the START1 state.
[0069] Define a baud clock count signal, baud_counter. On each rising edge of the baud clock signal, baud_counter is incremented by 1. When baud_counter reaches 7, the SLO line input signal level is sampled as flag bit_samp. For example, the baud clock count signal, baud_counter, cycles from 0 to 15, meaning each baud clock count signal, baud_counter, corresponds to a sampled value of the encoder position data. The seventh sampled value is the median value of the encoder position data; this median value represents the level of that bit of data. Define a median sampling flag, bit_samp. When the median value of the SLO line input serial data is 1, flag bit_samp is set to 1.
[0070] When the baud rate clock signal (baud_pulse) is 1 and the baud rate clock count signal baud_counter is greater than 8, when the flag bit bit_samp is 1, the state machine jumps from the START1 state to the START2 state, otherwise the state jumps to WAIT;
[0071] In the START2 state, the time count value cnt is defined as the START2 state count value. The time count value cnt of the START2 state is increased by 1 at the rising edge of the baud rate clock signal. When the SLO line input signal level is 0 and the time count value cnt of the START2 state is less than 20, it means that the START2 state lasts for half the time of 1 bit of data, and the sum of the durations of the START1 state and the START2 state is equal to the Start bit transmission time. The flag bit bit_samp is the start bit of the encoder position data frame, and the state machine jumps to the ZERO state; otherwise, the flag bit_samp is invalid, and the state machine jumps to the WAIT state.
[0072] In the ZERO state, the baud rate clock count signal baud_counter is increased by 1 on the rising edge of the baud rate clock signal. When the baud rate clock count signal baud_counter is greater than 8, the flag bit bit_samp is 0, and the flag bit bit_samp is used as the 0th bit of the encoder position data frame, and the state machine jumps to the DATA state.
[0073] In the DATA state, the DATA state needs to detect the 26-bit position data, 1 Error bit, 1 Warn bit, and 6 CRC bits of the encoder position data frame input by the SLO, totaling 34 bits of data.
[0074] In the DATA state, at the rising edge of the baud rate clock signal, the encoder position data transmitted by the SLO line is received bit by bit. When one bit of encoder position data is received, the count value bit_counter is increased by 1, and the count value bit_counter is cyclically incremented from 0 to 33. For example, in the DATA state, the signal bit_counter is defined as the data bit count. Each time a bit of data is received, the value of the data bit count value bit_counter is increased by 1, and the count value bit_counter is cyclically incremented from 0 to 33. The signal bit_counter_grt is defined as the data bit count value bit_counter. When the value of the data bit count value bit_counter is greater than 33, bit_counter_grt is set to 1, indicating that 34 bits of valid data have been received. The next state direction is determined by judging whether the value of the signal bit_counter_grt is 1. If bit_counter_grt is 1, the state machine jumps to the WAIT state, otherwise it stays in the DATA state and continues to receive data. In the DATA state, when the rising edge of the baud rate clock arrives, the encoder position data transmitted by the SLO line enters the shift register in sequence, with the most significant bit first. The shift register stores the data by shifting left one by one. The shift register has a bit width of 34, which is used to store 26 bits of encoder position data, 1 error bit, 1 warning bit, and 6 CRC check bits. In particular, the data in the shift register is latched before output to obtain the decoded data of the encoder position data. After the shift register has latched the data, the shift register latch signal is high.
[0075] Through the above process, the decoded data of the encoder position data transmitted by the SLO line can be obtained and latched into the shift register for verification and comparison by the CRC verification module in step S3.
[0076] Step S3: When the encoder position data decoding completion flag is detected, the CRC check module moves the decoded data of the encoder position data into the register to obtain the CRC check code of the encoder position data, compares the CRC code of the encoder position data and the CRC check code, and if the two are consistent, obtains the encoder position data.
[0077] Specifically, they can be:
[0078] Step P1: When the encoder position data decoding completion flag is detected, the data register is initialized, and the 26-bit encoder position data, 1 error bit, and 1 warning bit of the decoded encoder position data are stored in the data register, and the last 6 bits of the data register are filled with 0;
[0079] Step P2: Shift the data in the data register left by one bit, read in new data and place it into the lowest bit of the data register. When the shifted-out bit data is 1, perform an XOR operation on the data in the data register and the generated polynomial; if the shifted-out bit data is 0, do nothing.
[0080] Step P3: Repeat step P2 until all 26 data bits are processed and the content in the data register is the CRC check code;
[0081] Step P4: Compare the CRC code of the encoder position data and the CRC check code. If the two are consistent and the error bit is 1, the encoder position data is output; otherwise, this frame of data is discarded and the next frame of data is checked.
[0082] Figure 4 A ModelSim simulation state transition diagram according to an embodiment of the present disclosure is shown; Figure 5 A schematic diagram of simulation results of inputting 3 frames of correct encoder position data according to an embodiment of the present disclosure is shown; Figure 6 FIG1 is a schematic diagram of simulation results of inputting 1 frame of correct encoder position data and 2 frames of erroneous encoder position data according to an embodiment of the present disclosure.
[0083] For example, ModelSim is used to simulate and verify the above-mentioned FPGA-based asynchronous BiSS-C protocol decoding method. Figure 4 As shown in the state transition diagram of the BiSS-C data decoding module, we can see the decoding effect of the BiSS-C data decoding module when the encoder position data is transmitted correctly. Assume that the three frames of valid serial data at the rxd end of the SLO line input signal are 60H, 480H, and 81H. After calculation, their corresponding CRC check codes are 24H, 1EH, and 1EH. The error bit is 1, and the three frames of signals transmitted by the SLO line are: 18393FH, 12027BFH, and 2067BFH. Figure 5 It can be seen that the CRC check output data biss_out signal output of the module is 60H, 480H, and 81H, that is, the correct three frames of data are obtained. Next, the decoding effect of the BiSS-C data decoding module is verified when the encoder position data transmission error occurs. For example, the first frame of data remains unchanged at 60E4H, the error bit of the second frame of data is changed to 0, and the CRC check code of the third frame of data is changed to EH. At this time, only the first frame of serial data (encoder position data) input by the SLO line is correct. The ModelSim simulation results are as follows: Figure 6 The simulation results show that the output terminal of the bissc_out signal of the CRC check module is 60H, that is, after passing through the CRC check module, only one frame of correct data is output, and the two frames of incorrectly transmitted data are discarded. The simulation results are correct.
[0084] The present invention discloses an FPGA-based asynchronous BiSS-C protocol decoding method. The FPGA includes a baud rate clock module, a BiSS-C data decoding module, and a CRC check module. The baud rate clock module samples encoder position data transmitted on the SLO line. Based on the BiSS-C data protocol, the BiSS-C data decoding module decodes the encoder position data transmitted on the SLO line to obtain decoded encoder position data. Upon detecting a decode completion flag for the encoder position data, the CRC check module shifts the decoded encoder position data into a register to obtain a CRC check code for the encoder position data. The CRC code of the encoder position data and the CRC check code are compared. If the two match, the encoder position data is obtained. This method solves the problem of using an FPGA to parse encoder position information transmitted via the BiSS-C protocol under an asynchronous clock.
[0085] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.
Claims
1. An asynchronous BiSS-C protocol decoding method based on FPGA, characterized in that: The FPGA includes a baud rate clock module, a BiSS-C data decoding module and a CRC check module, and the method includes: The encoder position data transmitted by the SLO line is sampled by the baud rate clock module; Based on the BiSS-C data protocol, the BiSS-C data decoding module is used to decode the encoder position data transmitted by the SLO line to obtain decoded data of the encoder position data; When the encoder position data decoding completion flag is detected, the CRC check module shifts the decoded data of the encoder position data into the register to obtain the CRC check code of the encoder position data, compares the CRC code of the encoder position data with the CRC check code, and obtains the encoder position data if the two are consistent; The method of using the baud rate clock module to sample the encoder position data transmitted by the SLO line includes: Dividing the system clock signal of the baud rate clock module to obtain the baud rate clock signal of the baud rate clock module; sampling encoder position data transmitted on the SLO line based on the frequency of the baud rate clock signal of the baud rate clock module; The BiSS-C data protocol is based on the BiSS-C data decoding module, which decodes the encoder position data transmitted by the SLO line, including: Setting a state machine of the BiSS-C data decoding module based on a data frame format of the BiSS-C data protocol; Decoding the encoder position data transmitted on the SLO line using the state machine of the BiSS-C data decoding module; Wherein, the state machine includes WAIT state, IDLE state, ACK state, START state, ZERO state and DATA state; The state machine of the BiSS-C data decoding module is used to decode the encoder position data transmitted by the SLO line, including: When a system reset signal is detected, the state machine enters the WAIT state, and when the input signal of the SLO line is 1, the state machine jumps to the IDLE state; In the IDLE state, when the input signal level of the SLO line is 0, the state machine jumps to the ACK state; In the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the START state; In the START state, when the start bit of the encoder position data frame is detected, the state machine jumps to the ZERO state; In the ZERO state, when the "0" bit of the encoder position data frame is detected, the state machine jumps to the DATA state; In the DATA state, at the rising edge of the baud rate clock signal, the encoder position data transmitted by the SLO line is received bit by bit, and the encoder position data is shifted into the shift register for latching in the order of high bit first to obtain the decoded data of the encoder position data; The baud rate clock module has three signal interfaces: system clock signal clk, system reset signal reset_n, and baud rate clock signal baud_pulse. The BiSS-C data decoding module has five signal interfaces: system clock signal clk, system reset signal reset_n, baud rate clock signal baud_pulse, SLO line serial data rxd, and decoded output data bissc_in. The CRC check module has four signal interfaces: system clock signal clk, system reset signal reset_n, decoded output data bissc_in, and check output data bissc_out. In the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the START state; in the START state, when the start bit of the encoder position data frame is detected, the state machine jumps to the ZERO state; including: Wherein, the START state includes the START1 state and the START2 state; In the ACK state, when the input signal level of the SLO line is 1, the state machine jumps to the START1 state; On the rising edge of the baud rate clock signal, the baud rate clock count signal baud_counter is increased by 1. When the baud rate clock count signal baud_counter is 7, the SLO line input signal level is sampled as the flag bit bit_samp; When the baud rate clock signal (baud_pulse) is 1 and the baud rate clock count signal baud_counter is greater than 8, when the flag bit bit_samp is 1, the state machine jumps from the START1 state to the START2 state; At the rising edge of the baud rate clock signal, the time count value cnt of the START2 state is increased by 1. When the SLO line input signal level is 0 and the time count value cnt of the START2 state is less than 20, the flag bit bit_samp is the start bit of the encoder position data frame, and the state machine jumps to the ZERO state.
2. The asynchronous BiSS-C protocol decoding method according to claim 1, characterized in that: The "0" bit of the encoder position data frame includes: In the ZERO state, the baud rate clock count signal baud_counter is increased by 1 on the rising edge of the baud rate clock signal. When the baud rate clock count signal baud_counter is greater than 8, the flag bit bit_samp is 0, and the flag bit bit_samp is used as the 0th bit of the encoder position data frame.
3. The asynchronous BiSS-C protocol decoding method according to claim 1, wherein: In the DATA state, at the rising edge of the baud rate clock signal, the encoder position data transmitted by the SLO line is received bit by bit, including: In the DATA state, at the rising edge of the baud rate clock signal, the encoder position data transmitted by the SLO line is received bit by bit. When one bit of encoder position data is received, the DATA data bit count value bit_counter is increased by 1, and the DATA data bit count value bit_counter is cyclically increased from 0 to 33.
4. The asynchronous BiSS-C protocol decoding method according to claim 3, characterized in that: The encoder position data and the decoded data of the encoder position data include: 26-bit encoder position data, 1-bit error bit, 1-bit warning bit, and 6-bit CRC code.
5. The asynchronous BiSS-C protocol decoding method according to claim 4, characterized in that: When the encoder position data decoding completion flag is detected, the CRC check module moves the decoded data of the encoder position data into a register to obtain a CRC check code of the encoder position data, compares the CRC code of the encoder position data and the CRC check code, and obtains the encoder position data if the two are consistent, including: P1: When the encoder position data decoding completion flag is detected, the data register is initialized, and the 26-bit encoder position data, 1 error bit, and 1 warning bit of the decoded encoder position data are stored in the data register, and the last 6 bits of the data register are filled with 0; P2: Shift the data in the data register left by one bit, read in new data and place it into the lowest bit of the data register. When the shifted-out bit data is 1, perform an XOR operation on the data in the data register and the generated polynomial. P3: Repeat step P2 until all 26 bits of data are processed and the content in the data register is the CRC check code; P4: Compare the CRC code and CRC check code of the encoder position data. If the two are consistent and the error bit is 1, the encoder position data is output.
6. The asynchronous BiSS-C protocol decoding method according to claim 1, characterized in that: The frequency of the baud rate clock signal of the baud rate clock module is 16 times the frequency of the BiSS-C protocol clock MA.