Heater device with memory unit and its operation method

Abstract

A heater device with a memory cell includes a first transistor, a second transistor, a memory cell, and a heater. A first terminal of the second transistor is electrically connected to a first terminal of the first transistor. The memory cell is electrically connected to a second terminal of the first transistor. The heater is electrically connected to a second terminal of the second transistor.

Description

Technical Field

[0001] This disclosure relates to a heater device, and more particularly to a heater device having a memory unit and a method of operating the same. Background Technology

[0002] Known printer devices use heater control circuits to heat the inkjet head's heater, enabling the inkjet head to print the desired image. However, adding functionality to the printer device, such as memory blocks, increases the number of signals, pins, circuit area, and cost. Therefore, a new circuit structure design is needed to address these issues. Summary of the Invention

[0003] This disclosure provides a heater device with a memory cell, including a first transistor, a second transistor, a memory cell, and a heater. A first terminal of the second transistor is electrically connected to a first terminal of the first transistor. The memory cell is electrically connected to a second terminal of the first transistor. The heater is electrically connected to a second terminal of the second transistor.

[0004] This disclosure provides a method for operating a heater device having a memory cell. The heater device has a recording mode, a reading mode, and a heating mode. The heater device includes a plurality of heater circuits, each heater circuit including a first transistor and a second transistor, and a memory cell and a heater electrically connected to the first transistor and the second transistor, respectively. The method includes the following steps: In the recording mode, at least one of the first transistors is selectively turned on according to a first signal, such that a first current generated by the voltage coupled to the two terminals of the first transistor passes through the memory cell. In the reading mode, the first transistors are sequentially turned on to determine the state of the memory cell. In the heating mode, at least one of the second transistors is selectively turned on according to a second signal, such that a second current generated by the voltage coupled to the two terminals of the second transistor passes through the heater. Attached Figure Description

[0005] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0006] Figure 1 This is a schematic diagram of a heater device with a memory unit according to an embodiment of the present disclosure.

[0007] Figure 2 This is a schematic diagram of a heater device with a memory unit according to an embodiment of the present disclosure.

[0008] Figure 3 This is a schematic diagram of a heater device with a memory unit according to an embodiment of the present disclosure.

[0009] Figure 4 This is a schematic diagram of a heater device with a memory unit according to an embodiment of the present disclosure.

[0010] Figure 5 This is a flowchart of a method for operating a heater device having a memory unit according to an embodiment of the present disclosure.

[0011] Figure 6 This is a flowchart of a method for operating a heater device having a memory unit according to another embodiment of the present disclosure.

[0012] Figures 1-6 The attached figures are numbered as follows:

[0013] 100, 200, 300, 400: Heater devices with memory units

[0014] 110, 210, 310, 410_1~410_N: Heater circuit

[0015] 120: Memory Unit

[0016] 130: Heater

[0017] 140, 430: Logic control circuit

[0018] 420_1~420_N: Selector switch

[0019] M1, M2, M3, M4, M5, M6: Transistors

[0020] V1, V2, V3, V4: Reference voltage signals

[0021] SLS: Selection Signal

[0022] ADS: Address Signal

[0023] DS: Data signal

[0024] S502~S506, S602~S606: Steps Detailed Implementation

[0025] To make the objectives, features, or advantages of this disclosure more apparent, embodiments are described below in conjunction with the accompanying drawings. For ease of understanding and for the sake of brevity, many of the drawings in this disclosure may depict only a portion of the entire device, and specific components in the drawings are not drawn to scale.

[0026] This disclosure provides different embodiments to illustrate the technical features of different implementations of this disclosure. The configuration, quantity, and size of the components in the embodiments are for illustrative purposes only and are not intended to limit this disclosure. Furthermore, if component reference numerals appear repeatedly in the embodiments and accompanying drawings, it is for simplification and does not imply any correlation between different embodiments.

[0027] Furthermore, the use of ordinal numbers such as "first" and "second" in the specification and claims to modify the components of the claims does not imply or represent any prior ordinal number of the claimed component, nor does it represent the order of one claimed component with another, or the order of manufacturing methods. The use of these multiple ordinal numbers is only to enable a claimed component with a certain name to be clearly distinguished from another claimed component with the same name.

[0028] In this disclosure, features of various embodiments can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with each other.

[0029] The term "comprising" as used throughout the specification and claims is an open-ended term and should therefore be interpreted as "comprising but not limited to".

[0030] Furthermore, "connection" and "coupling" herein include any direct and indirect means of connection. Therefore, when a component or membrane is described as "connected" to another component or membrane, it can be directly connected to this other component or membrane, or there may be an intercalating component or membrane between them. When a component is described as "directly connected" to another component or membrane, there is no intercalating component or membrane between them. If a first device in a circuit described herein is coupled to a second device, it means that the first device can be directly electrically connected to the second device. When the first device is directly electrically connected to the second device, the first device and the second device are connected only through wires or passive components (such as resistors, capacitors, etc.), and no other electronic components are connected between the first device and the second device.

[0031] Figure 1 This is a schematic diagram of a heater device with a memory cell according to an embodiment of the present disclosure. In this embodiment, the heater device 100 with a memory cell can be disposed on a silicon (Si) wafer substrate, a glass substrate, or a polyimide (PI) substrate, but the present disclosure is not limited thereto. Please refer to... Figure 1 The heater device 100 with a memory unit includes a heater circuit 110, and the heater circuit 110 may include at least transistor M1, transistor M2, memory unit 120 and heater 130.

[0032] The first terminal of transistor M2 can be electrically connected to the first terminal of transistor M1. Memory cell 120 can be electrically connected to the second terminal of transistor M1. Heater 130 can be electrically connected to the second terminal of transistor M2.

[0033] In this embodiment, transistor M1 is, for example, an N-type transistor, but this disclosure is not limited thereto. The first terminal of transistor M1 can be the gate terminal, the second terminal of transistor M1 (i.e., the second terminal of transistor M1 electrically connected to memory cell 120) can be the drain terminal, and the third terminal of transistor M1 can be the source terminal. Furthermore, the second terminal (e.g., the drain terminal) of transistor M1 can receive a reference voltage signal V1 (e.g., a high voltage signal) through memory cell 120, and the third terminal (e.g., the source terminal) of transistor M1 can receive a reference voltage signal V2 (e.g., a low voltage signal). In some embodiments, transistor M1 can also be a P-type transistor.

[0034] In this embodiment, transistors M1 and M2 can be transistors with the same doping type. That is, transistor M2 is, for example, an N-type transistor, but this disclosure is not limited thereto. The first terminal of transistor M2 can be the gate terminal, the second terminal of transistor M2 (i.e., the second terminal of transistor M2 electrically connected to heater 130) can be the drain terminal, and the third terminal of transistor M2 can be the source terminal. In addition, the second terminal (e.g., the drain terminal) of transistor M2 can receive a reference voltage signal V3 (e.g., a high voltage signal) through heater 130, and the third terminal (e.g., the source terminal) of transistor M2 can receive a reference voltage signal V4 (e.g., a low voltage signal). In some embodiments, transistor M2 can also be a P-type transistor.

[0035] In some embodiments, the memory cell 120 is, for example, a fuse, but this disclosure is not limited thereto. When current flows through the memory cell 120, the heater circuit 110 can perform a recording operation to burn out the memory cell 120, thus creating an open circuit. Conversely, when no current flows through the memory cell 120, the heater circuit 110 does not perform a recording operation, thus preventing the memory cell 120 from becoming an open circuit. Furthermore, the material of the memory cell 120 can be, for example, indium tin oxide (ITO), polysilicon, aluminum (Al), copper (Cu), nickel (Ni), molybdenum (Mo), or indium zinc oxide (IZO), but this disclosure is not limited thereto.

[0036] In some embodiments, heater 130 may be a resistor or other suitable heating component, but this disclosure is not limited thereto. When current flows through heater 130, heater circuit 110 may perform heating operation, causing the inkjet head at that location to perform inkjet operation (e.g., print the desired pattern). When no current flows through heater 130, heater circuit 110 does not perform heating operation.

[0037] In addition, the heater device 100 also includes a logic control circuit 140. The logic control circuit 140 can be electrically connected to the first terminal of transistor M1 and the first terminal of transistor M2. Furthermore, the heater device 100 may also include a control circuit (not shown) and a power supply circuit (not shown). The control circuit can be electrically connected to the terminal of the reference voltage signal V1 and the logic control circuit 140. The power supply circuit can be electrically connected to the terminals of the reference voltage signals V2, V3, and V4 and the control circuit, and the control circuit can control the power supply circuit to provide the reference voltage signals V2, V3, and V4. In this embodiment, the control circuit is, for example, a microcontroller unit (MCU), and the power supply circuit is, for example, a power supply chip, but this disclosure is not limited thereto.

[0038] In this embodiment, the heater device 100 may include a recording mode, a reading mode, and a heating mode, but this disclosure is not limited thereto. In the recording mode, the logic control circuit 140 can generate a first signal (e.g., a high voltage signal) to the first terminal (e.g., the gate terminal) of transistor M1 to turn on transistor M1. The control circuit can also provide a reference voltage signal V1 and control the power supply circuit to provide a reference voltage signal V2. This causes the current generated by the voltage signals (e.g., reference voltage signals V1 and V2) coupled to the two terminals of transistor M1 to flow through the memory cell 120, performing a recording operation on the memory cell 120, for example, burning out the memory cell 120 to create an open circuit. On the other hand, when the logic control circuit 140 does not generate the first signal (e.g., a high voltage signal) to the first terminal (e.g., the gate terminal) of transistor M1, transistor M1 will turn off, and no current will flow through the memory cell 120. Therefore, no recording operation will be performed on the memory cell 120, making the memory cell 120 non-open circuit.

[0039] Furthermore, in recording mode, the control circuit can selectively disconnect the voltage signals coupled to the two terminals of transistor M2. That is, the control circuit can control the power supply circuit to stop providing reference voltage signals V3 and V4, thus preventing current from flowing through heater 130 and stopping heater circuit 110 from heating. This reduces the power consumption of heater device 100.

[0040] Next, in read mode, logic control circuit 140 controls transistor M1 to turn on (or turn on) so that control circuit can determine the state of memory cell 120. That is, when logic control circuit controls transistor M1 to turn on, control circuit can stop providing reference voltage signal V1, and control circuit can read memory cell 120 through the endpoint of reference voltage signal V1, and determine whether memory cell 120 is open or closed based on the read result. In some embodiments, open circuit is represented by, for example, "0", and closed circuit is represented by, for example, "1", but this disclosure is not limited thereto. In another embodiment, open circuit is represented by, for example, "1", and closed circuit is represented by, for example, "0". Therefore, the read result of control circuit can be "0" or "1", and this read result can be used as an identifier for the inkjet head of the printer device to prevent the printer device from downgrading to use older firmware or software, or as a batch identification for product parameters. In this way, heater device 100 can have a memory function to increase ease of use.

[0041] Furthermore, in read mode, the control circuit can selectively disconnect the voltage signals coupled to the two terminals of transistor M2. That is, the control circuit can control the power supply circuit to stop providing reference voltage signals V3 and V4, thus preventing current from flowing through heater 130 and stopping the heater circuit 110 from performing heating operations. This reduces the power consumption of the heater device 100.

[0042] Subsequently, in the heating mode, the logic control circuit 140 can generate a second signal (e.g., a high voltage signal) to the first terminal (e.g., the gate terminal) of transistor M2 to turn on transistor M2, and the control circuit can control the power supply circuit to provide reference voltage signals V3 and V4, so that the current generated by the voltage signals (e.g., reference voltage signals V3 and V4) coupled to the two terminals of transistor M2 flows through heater 130, causing heater circuit 110 to perform heating operation. On the other hand, when the logic control circuit 140 does not generate a second signal (e.g., a high voltage signal) to the first terminal (e.g., the gate terminal) of transistor M2, transistor M2 will be turned off and no current will flow through heater 130, so heater circuit 110 will not perform heating operation.

[0043] In addition, during heating mode, the control circuit can selectively disconnect the voltage signal coupled to the two terminals of transistor M1. That is, the control circuit can stop providing the reference voltage signal V1 and control the power supply circuit to stop providing the reference voltage signal V2, thereby reducing the power consumption of the heater device 100.

[0044] In this embodiment, the first terminals of transistor M1 and transistor M2 are electrically connected to each other and receive the same signal, but this disclosure is not limited thereto. In some embodiments, the first terminals of transistor M1 and transistor M2 can be separated and receive different signals, which can also achieve the same memory function.

[0045] Figure 2 This is a schematic diagram of a heater device with a memory unit according to an embodiment of the present disclosure. Please refer to... Figure 2 The heater device 200 with a memory unit includes a heater circuit 210, and the heater circuit 210 may include at least transistor M3, transistor M4, memory unit 120, and heater 130. In this embodiment, memory unit 120 and heater 130 are connected to... Figure 1 The memory unit 120 and heater 130 are the same or similar, see reference. Figure 1 The embodiments are described in detail here, so they will not be repeated here.

[0046] The first terminal of transistor M4 can be electrically connected to the first terminal of transistor M3. Memory cell 120 can be electrically connected to the second terminal of transistor M3. Heater 130 can be electrically connected to the second terminal of transistor M4.

[0047] In this embodiment, transistor M3 is, for example, a P-type transistor, but this disclosure is not limited thereto. The first terminal of transistor M3 can be the gate terminal, the second terminal of transistor M3 (i.e., the second terminal of transistor M3 electrically connected to memory cell 120) can be the drain terminal, and the third terminal of transistor M3 can be the source terminal. Furthermore, the second terminal (e.g., the drain terminal) of transistor M3 can receive a reference voltage signal V2 (e.g., a low voltage signal) through memory cell 120, and the third terminal (e.g., the source terminal) of transistor M3 can receive a reference voltage signal V1 (e.g., a high voltage signal). In some embodiments, transistor M3 can also be an N-type transistor.

[0048] In this embodiment, transistors M3 and M4 can be transistors with different doping types. That is, transistor M4 is, for example, an N-type transistor, but this disclosure is not limited thereto. The first terminal of transistor M4 can be the gate terminal, the second terminal of transistor M4 (i.e., the second terminal of transistor M4 electrically connected to heater 130) can be the drain terminal, and the third terminal of transistor M4 can be the source terminal. In addition, the second terminal (e.g., the drain terminal) of transistor M4 can receive a reference voltage signal V3 (e.g., a high voltage signal) through heater 130, and the third terminal (e.g., the source terminal) of transistor M4 can receive a reference voltage signal V4 (e.g., a low voltage signal). In some embodiments, transistor M4 can also be a P-type transistor.

[0049] In addition, the heater device 200 also includes a logic control circuit 140. The logic control circuit 140 can be electrically connected to the first terminal of transistor M3 and the first terminal of transistor M4. Furthermore, the logic control circuit 140 can control whether to provide reference voltage signals V1, V2, V3, and V4. In this embodiment, the operation flow of the heater device 200 is the same as or similar to that of the heater device 100, and can be referred to... Figure 1 The embodiments are described in detail here, so they will not be repeated here.

[0050] In this embodiment, the first terminals of transistor M3 and transistor M4 are electrically connected to each other and receive the same signal, but this disclosure is not limited thereto. In some embodiments, the first terminals of transistor M3 and transistor M4 can be separated and receive different signals, which can also achieve the same memory function.

[0051] Figure 3 This is a schematic diagram of a heater device with a memory unit according to an embodiment of the present disclosure. Please refer to... Figure 3 The heater device 300 with a memory unit includes a heater circuit 310, and the heater circuit 310 may include at least transistor M5, transistor M6, memory unit 120, and heater 130. In this embodiment, memory unit 120 and heater 130 are connected to... Figure 1 The memory unit 120 and heater 130 are the same or similar, see reference. Figure 1 The embodiments are described in detail here, so they will not be repeated here.

[0052] The first terminal of transistor M6 can be electrically connected to the first terminal of transistor M5. Memory cell 120 can be electrically connected to the second terminal of transistor M5 and the third terminal of transistor M6. Heater 130 can be electrically connected to the second terminal of transistor M6.

[0053] In this embodiment, transistor M5 is, for example, a P-type transistor, but this disclosure is not limited thereto. The first terminal of transistor M5 can be the gate terminal, the second terminal of transistor M5 (i.e., the second terminal of transistor M5 electrically connected to memory cell 120) can be the drain terminal, and the third terminal of transistor M5 can be the source terminal. Furthermore, the second terminal (e.g., the drain terminal) of transistor M5 can receive a reference voltage signal V4 (e.g., a low voltage signal) through memory cell 120, and the third terminal (e.g., the source terminal) of transistor M5 can receive a reference voltage signal V1 (e.g., a high voltage signal). In some embodiments, transistor M5 can also be an N-type transistor.

[0054] In this embodiment, transistors M5 and M6 can be transistors with different doping types. That is, transistor M6 is, for example, an N-type transistor, but this disclosure is not limited thereto. The first terminal of transistor M6 can be the gate terminal, the second terminal of transistor M6 (i.e., the second terminal of transistor M6 electrically connected to heater 130) can be the drain terminal, and the third terminal of transistor M6 can be the source terminal. In addition, the second terminal (e.g., the drain terminal) of transistor M6 can receive a reference voltage signal V3 (e.g., a high voltage signal) through heater 130, and the third terminal (e.g., the source terminal) of transistor M6 can receive a reference voltage signal V4 (e.g., a low voltage signal). In some embodiments, transistor M6 can also be a P-type transistor.

[0055] In addition, the heater device 300 also includes a logic control circuit 140. The logic control circuit 140 can be electrically connected to the first terminal of transistor M5 and the first terminal of transistor M6. Furthermore, the logic control circuit 140 can control whether to provide reference voltage signals V1, V2, V3, and V4. In this embodiment, the operation flow of the heater device 300 is the same as or similar to that of the heater device 100, and can be referred to... Figure 1 The embodiments are described in detail here, so they will not be repeated here.

[0056] In this embodiment, the first terminal of transistor M5 and the first terminal of transistor M6 are electrically connected to each other and receive the same signal, but this disclosure is not limited thereto. In some embodiments, the first terminals of transistor M5 and transistor M6 can be separated and receive different signals, which can also achieve the same effect of having a memory function.

[0057] Figure 4 This is a schematic diagram of a heater device with a memory unit according to an embodiment of the present disclosure. Please refer to... Figure 4The heater device 400 with a memory unit includes a plurality of heater circuits 410_1 to 410_N, a plurality of selection switches 420_1 to 420_N, and a logic control circuit 430, wherein N is a positive integer greater than 1. In some embodiments, the heater circuits 410_1 to 410_N may be Figure 1 heater circuit 110 Figure 2 heater circuit 210, Figure 3 The heater circuit 310 or a combination thereof is described, but this disclosure is not limited thereto. Furthermore, the internal circuitry and connections of the heater circuits 410_1 to 410_N can be found in [reference needed]. Figure 1 , Figure 2 or Figure 3 The embodiments are described in detail here, so they will not be repeated here.

[0058] Selector switches 420_1 to 420_N are electrically connected to heater circuits 410_1 to 410_N, respectively. For example, selector switch 420_1 is electrically connected to heater circuit 410_1, selector switch 420_2 is electrically connected to heater circuit 410_2, ..., selector switch 420_N is electrically connected to heater circuit 410_N.

[0059] The logic control circuit 430 is electrically connected to the heater circuits 410_1 to 410_N via selection switches 420_1 to 420_N. Furthermore, the logic control circuit 430 can be electrically connected to the first terminal of the first transistor (e.g., transistor M1, transistor M3, or transistor M5) and the first terminal of the second transistor (e.g., transistor M2, transistor M4, or transistor M6) of the heater circuits 410_1 to 410_N. Additionally, the heater device 400 control circuit may also include a control circuit (not shown) and a power supply circuit (not shown). The control circuit can be electrically connected to the terminal of the reference voltage signal V1 and the logic control circuit 430. The power supply circuit can be electrically connected to the terminals of the reference voltage signals V2, V3, and V4 and the control circuit, and the control circuit can control the power supply circuit to provide the reference voltage signals V2, V3, and V4. In addition, the logic control circuit 430 can receive the selection signal SLS, the address signal ADS, and the data signal DS, and control the selection switches 420_1 to 420_N to open or close according to the selection signal SLS, the address signal ADS, and the data signal DS, so as to perform corresponding operations on the heaters 410_1 to 410_N.

[0060] exist Figure 4In this embodiment, the number of selection signal SLS, address signal ADS, and data signal DS is one, but this disclosure is not limited to this. In some embodiments, the number of selection signal SLS, address signal ADS, and data signal DS can be multiple, and the number of selection signal SLS, address signal ADS, and data signal DS can be increased or decreased according to the number of heater circuits 410_1 to 410_N, but this disclosure is not limited to this. That is, when the number of heater circuits 410_1 to 410_N increases, the number of selection signal SLS, address signal ADS, and data signal DS can increase accordingly. When the number of heater circuits 410_1 to 410_N decreases, the number of selection signal SLS, address signal ADS, and data signal DS can decrease accordingly.

[0061] In this embodiment, the heater device 400 may include a recording mode, a reading mode, and a heating mode, but this disclosure is not limited thereto. In the operation of the heater device 400, in the recording mode, the logic control circuit 430 may generate a first signal (e.g., a high voltage signal or a low voltage signal) to at least one of the heater circuits 410_1 to 410_N, such as heater circuit 410_1, based on the selection signal SLS, the address signal ADS, and the data signal DS. Next, a first signal is provided to the first terminal (e.g., the gate terminal) of the first transistor (e.g., transistor M1, transistor M3, or transistor M5) of the heater circuit 410_1 to turn on the first transistor (e.g., transistor M1, transistor M3, or transistor M5) of the heater circuit 410_1. The control circuit can provide a reference voltage signal V1 and control the power supply circuit to provide a reference voltage signal V2 or a reference voltage signal V4, so that the current generated by the voltage signals (e.g., reference voltage signal V1 and reference voltage signal V2 or reference voltage signal V1 and reference voltage signal V4) coupled to the two terminals of the first transistor (e.g., transistor M1, transistor M3, or transistor M5) of the heater circuit 410_1 passes through the memory cell 120 of the heater circuit 410_1 to perform a recording operation on the memory cell 120 of the heater circuit 410_1, for example, burning out the memory cell 120 of the heater circuit 410_1 to present an open circuit. On the other hand, when the logic control circuit 430 does not generate a first signal (e.g., a high voltage signal or a low voltage signal) to the heater circuits 410_2 to 410_N, the first transistor (e.g., transistor M1, transistor M3, or transistor M5) of the heater circuits 410_2 to 410_N will be turned off and no current will flow through the memory cell 120 of the heater circuits 410_2 to 410_N. Therefore, no recording operation will be performed on the memory cell 120 of the heater circuits 410_2 to 410_N, and it will be non-open circuit.

[0062] In addition, in recording mode, the control circuit can selectively disconnect the voltage signals coupled to both terminals of the second transistors (e.g., transistor M2, transistor M4) of the heater circuits 410_1 to 410_N, or the voltage signals coupled to one terminal of the second transistor (e.g., transistor M6). That is, the control circuit can control the power supply circuit to stop providing the reference voltage signal V3 and reference voltage signal V4 or the reference voltage signal V3, so as to reduce the power consumption of the heater device 400.

[0063] Next, in read mode, the logic control circuit 430 sequentially turns on the first transistors (e.g., transistor M1, transistor M3, or transistor M5) of the heater circuits 410_1 to 410_N, so that the control circuit can determine the state of the memory cells 120 of the heater circuits 410_1 to 410_N. That is, when the first transistors (e.g., transistor M1, transistor M3, or transistor M5) of the heater circuits 410_1 to 410_N are turned on, the control circuit can sequentially read the memory cells 120 of the heater circuits 410_1 to 410_N through the endpoint of the reference voltage signal V1, and determine whether the state of the memory cells 120 of the heater circuits 410_1 to 410_N is open or closed based on the reading result. In this embodiment, the state of the memory cell 120 of the heater circuit 410_1 is open, while the state of the memory cells 120 of the heater circuits 420_2 to 420_N is closed. Therefore, the reading result of the control circuit is, for example, "01…1" or "10…0", and this reading result can be used as an identifier for the inkjet head of the printer device to prevent the printer device from downgrading to use old firmware or software, or as a batch identification for product parameters. In this way, the heater device 400 can have a memory function to increase ease of use.

[0064] In addition, in read mode, the control circuit can selectively disconnect the voltage signal coupled to both terminals of the second transistors (e.g., transistor M2, transistor M4) of heater circuits 410_1 to 410_N, or the voltage signal coupled to one terminal of the second transistor (e.g., transistor M6). That is, the control circuit can control the power supply circuit to stop providing reference voltage signal V3 and reference voltage signal V4, or reference voltage signal V3, to reduce the power consumption of heater device 400.

[0065] Subsequently, in the heating mode, the logic control circuit 430 can generate a second signal (e.g., a high voltage signal) to at least one of the heater circuits 410_1 to 410_N, such as heater circuit 410_1, based on the selection signal SLS, the address signal ADS, and the data signal DS. Next, the second signal is provided to the gate of the second transistor (e.g., transistor M2, transistor M4, or transistor M6) of heater circuit 410_1 to turn on the second transistor (e.g., transistor M2, transistor M4, or transistor M6) of heater circuit 410_1, and the control circuit controls the power supply circuit to provide reference voltage signals V3 and V4, so that the current generated by the voltage signals (e.g., reference voltage signals V3 and V4) coupled to the two terminals of the second transistor (e.g., transistor M2, transistor M4, or transistor M6) of heater circuit 410_1 flows through the heater 130 of heater circuit 410_1, so that heater circuit 410_1 performs heating operation. On the other hand, when the logic control circuit 430 does not generate a second signal (e.g., a high voltage signal) to the heater circuits 410_2 to 410_N, the second transistors (e.g., transistor M2, transistor M4, or transistor M6) of the heater circuits 410_2 to 410_N will be turned off and no current will flow through the heaters 130 of the heater circuits 410_2 to 410_N, so the heater circuits 410_2 to 410_N will not perform heating operations.

[0066] In addition, during heating mode, the control circuit can selectively disconnect the voltage signals coupled to both terminals of the first transistors (e.g., transistor M1, transistor M3) of the heater circuits 410_1 to 410_N, or the voltage signal coupled to one terminal of the first transistor (e.g., transistor M5). That is, the control circuit can stop providing the reference voltage signal V1 and control the power supply circuit to stop providing the reference voltage signal V2, thereby reducing the power consumption of the heater device 400.

[0067] Figure 5 This is a flowchart of a method for operating a heater device having a memory cell according to an embodiment of the present disclosure. In this embodiment, the heater device has a recording mode, a reading mode, and a heating mode. The heater device includes a plurality of heater circuits, and each heater circuit includes a first transistor and a second transistor, and a memory cell and a heater respectively electrically connected to the first transistor and the second transistor. In step S502, in the recording mode, at least one of the plurality of first transistors is selectively turned on according to a first signal, such that a first current generated by the voltage coupled to the two terminals of the first transistor passes through the memory cell.

[0068] In step S504, in read mode, the first transistors are sequentially turned on to determine the state of the memory cell. In step S506, in heating mode, at least one of the second transistors is selectively turned on according to the second signal, so that a second current generated by the voltage coupled to the two terminals of the second transistor passes through the heater.

[0069] Figure 6 This is a flowchart of a method for operating a heater device having a memory unit according to an embodiment of the present disclosure. In this embodiment, steps S502, S504, and S506 are... Figure 5 Steps S502, S504, and S506 are the same or similar, and can be referred to Figure 5 The embodiments are described in detail here, so they will not be repeated here.

[0070] In step S602, in the recording mode, the voltage coupled to the two terminals of the second transistor is disconnected. In step S604, in the reading mode, the voltage signal coupled to the two terminals of the second transistor is disconnected. In step S606, in the heating mode, the voltage signal coupled to the two terminals of the first transistor is disconnected.

[0071] In summary, the heater device with a memory unit and the method for operating the heater device with a memory unit according to the embodiments of this disclosure are achieved by electrically connecting the first terminal of the second transistor to the first terminal of the first transistor, electrically connecting the memory unit to the second terminal of the first transistor, and electrically connecting the heater to the second terminal of the second transistor. Furthermore, in the recording mode, the first transistor is turned on according to a first signal, causing a first current generated by the voltage signal coupled to the two terminals of the first transistor to flow through the memory unit. In the reading mode, the first transistor is turned on to determine the state of the memory unit. In the heating mode, the second transistor is turned on according to a second signal, causing a second current generated by the voltage signal coupled to the two terminals of the second transistor to flow through the heater. In this way, the heater device can have a memory function, reduce the power consumption of the heater device, reduce the number of signals used, reduce the number of pins, or reduce the circuit area used, thereby increasing ease of use.

[0072] While this disclosure is provided above with reference to embodiments, it is not intended to limit the scope of this disclosure. Anyone skilled in the art can replace, recombine, mix, or make adjustments, combinations, modifications, and refinements to the features of several different embodiments to complete other embodiments without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A heater device having memory cells, characterized by, The method comprises: a first transistor; a second transistor, a first end of the second transistor and a first end of the first transistor are directly electrically connected to each other and receive the same signal, wherein the first end of the first transistor is a gate end, and the first end of the second transistor is a gate end; a memory unit, electrically connected to a second end of the first transistor; and a heater, electrically connected to a second end of the second transistor.

2. The heater apparatus with memory cells according to claim 1, wherein, The first transistor is an N-type transistor, and the second end of the first transistor to which the memory unit is electrically connected is a drain end.

3. The heater apparatus with memory cells according to claim 2, wherein, The drain end of the first transistor receives a high voltage signal through the memory unit, and a source end of the first transistor receives a low voltage signal.

4. The heater apparatus with memory cells as claimed in claim 1, wherein, The first transistor is a P-type transistor, and the second end of the first transistor to which the memory unit is electrically connected is a drain end.

5. The heater device with memory cells according to claim 4, wherein, The drain end of the first transistor receives a low voltage signal through the memory unit, and a source end of the first transistor receives a high voltage signal.

6. The heater apparatus with memory cells as claimed in claim 1, wherein, The first transistor and the second transistor are transistors of the same doping type.

7. The heater apparatus with memory cells of claim 1, wherein, The first transistor and the second transistor are transistors of different doping types.

8. The heater apparatus with memory cells of claim 1, wherein, The memory unit is further electrically connected to a third end of the second transistor.

9. The heater apparatus with memory cells of claim 1, wherein, The memory unit is a fuse.

10. The heater apparatus with memory cells of claim 1, wherein, Further comprising a logic control circuit, electrically connected to the first end of the first transistor and the second transistor.

11. A method for operating a heater device having memory cells, the heater device having a programming mode, a reading mode and a heating mode, the heater device comprising a plurality of heater circuits, each heater circuit comprising a first transistor and a second transistor, and a memory cell and a heater electrically connected to the first transistor and the second transistor, respectively, wherein a first terminal of the second transistor and a first terminal of the first transistor are directly electrically connected to each other and receive the same signal, the first terminal of the first transistor being a gate terminal, the first terminal of the second transistor being a gate terminal, characterized in that, The method comprises: In the recording mode, selectively open at least one of the plurality of first transistors according to a first signal, so that a first current generated by a voltage signal coupled to two ends of the first transistor passes through the memory unit; In the reading mode, sequentially open the plurality of first transistors to determine the state of the plurality of memory units; and In the heating mode, selectively open at least one of the plurality of second transistors according to a second signal, so that a second current generated by a voltage signal coupled to two ends of the second transistor passes through the heater.

12. The method of operating a heater device having memory cells of claim 11, wherein, In the recording mode, disconnect the voltage signal coupled to the two ends of the plurality of second transistors.

13. The method of operating a heater device having memory cells of claim 11, wherein, In the reading mode, disconnect the voltage signal coupled to the two ends of the plurality of second transistors.

14. The method of operating a heater device having memory cells of claim 11, wherein, In the heating mode, disconnect the voltage signal coupled to the two ends of the plurality of first transistors.

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