A semiconductor device detection method, storage medium, device and system

Abstract

This invention provides a semiconductor device testing method, storage medium, device, and system, comprising at least: initiating detection; setting the detection voltage of an ATE (Automatic Test Equipment) device to low and high levels respectively; testing the semiconductor device; acquiring waveforms of a first signal and a second signal by the ATE device; removing DC components and combining them to obtain a third signal; setting the connection point between the ATE device and the transmission path to an open circuit state; superimposing the waveform of the third signal with the waveform of the signal reflected to the ATE device by the ATE device to obtain a fourth signal; stopping the superposition when the amplitude of the fourth signal waveform reaches a preset full-amplitude value; and outputting the detection result by detecting the rise time and fall time of the fourth signal waveform. The signal waveform conforms to the full-amplitude value, ensuring that the rise time and fall time can be accurately acquired within the same waveform, avoiding distortion, and providing objective and accurate results. The operation is simple, highly practical, and can greatly improve the yield of the device under test.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing, and in particular to a semiconductor device testing method, storage medium, equipment, and system. Background Technology

[0002] As the complexity of integrated circuits continues to increase, the requirements for judging the output results on ATE (automatic test equipment) also increase.

[0003] Traditionally, ATE test results are obtained by comparing the output of the device under test with the expected output using the comparator inside the ATE test equipment. Based on the comparison result, the result is determined whether the device under test passes (PASS) or fails (FAIL), so as to screen the device under test at the front end and avoid a large number of defective products during mass production.

[0004] However, as integrated circuits become increasingly miniaturized, circuit structures become more complex, and device sizes shrink, leading to increasingly complex circuit outputs and placing higher demands on the interpretation of ATE (Automatic Test Equipment) output results. Typically, integrated circuits integrate multiple clock domains and protocols, and the testing program consists of numerous test items. The execution, jumps, and classification information between tests are interwoven. If the testing program is generated entirely according to the software-defined waterfall process, it will consume a significant amount of development time. Due to the large number of test items, errors are easily introduced during the testing program development process, causing debugging failures. This is especially true for tests with over a thousand test items, where the workload is enormous, the increased error rate negatively impacts the testing results. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device testing method, storage medium, device and system to solve the problems in the prior art where the signal waveform obtained by testing the device under test through ATE equipment is difficult to reach full amplitude, the rise time and fall time are difficult to calculate within the same waveform, and the signal waveform is distorted due to transmission lines.

[0006] To achieve the above and other related objectives, the present invention provides a semiconductor device detection method, the semiconductor device detection method comprising:

[0007] Start the detection, set the detection voltage of the ATE equipment to low level and high level respectively, and detect the semiconductor device. The ATE equipment collects the waveforms of the first signal and the second signal fed back from the semiconductor device through the transmission path. After removing the DC component from the second signal, it is combined with the first signal to obtain the third signal.

[0008] The connection point between the ATE device and the transmission path is set to an open circuit state, so that the third signal is reflected back and forth between the semiconductor device and the ATE device, and the ATE device calculates the signal waveform reflected back to the ATE device.

[0009] The waveform of the third signal is superimposed with the waveform of the signal reflected to the ATE device to obtain the fourth signal. The superposition stops when the amplitude of the fourth signal waveform reaches the preset full amplitude value.

[0010] The detection result is output by detecting the rise time and fall time of the waveform of the fourth signal.

[0011] Optionally, the step of obtaining the third signal is to combine the rising edge of the first signal with the falling edge of the second signal that has completed the DC component reduction operation to obtain the third signal; or to combine the falling edge of the first signal with the rising and falling edges of the second signal that has completed the DC component reduction operation to obtain the third signal.

[0012] Optionally, the steps for detecting rise time and fall time are as follows: obtaining the time it takes for the waveform of the fourth signal to rise from the first threshold to the second threshold, and comparing it with a preset rise time; obtaining the time it takes for the waveform of the fourth signal to fall from the second threshold to the first threshold, and comparing it with a preset fall time.

[0013] Optionally, the first threshold is set within a range of 5% to 35% of the full amplitude, and the second threshold is set within a range of 65% to 95% of the full amplitude.

[0014] Optionally, the preset rise time, the preset fall time, and the full amplitude value are obtained through simulation verification or based on back-end process settings.

[0015] Optionally, it is determined whether the rise time of the waveform of the fourth signal is less than or equal to a preset rise time and whether the fall time of the waveform of the fourth signal is less than or equal to a preset fall time. If yes, a qualified result is output; otherwise, a unqualified result is output.

[0016] The present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the semiconductor device detection method.

[0017] The present invention provides a semiconductor device testing device, which includes at least a processor and a memory, wherein the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory, so that the semiconductor device testing device performs the semiconductor device testing method.

[0018] This invention provides a semiconductor device testing system, which includes at least an ATE device and a signal processing module, wherein: the ATE device is used for communication connection with the semiconductor device under test; the signal processing module is disposed inside the ATE device and is used to configure the detection parameters of the semiconductor device, so that the ATE device executes the semiconductor device testing method.

[0019] As described above, the semiconductor device testing method, storage medium, apparatus, and system of the present invention have the following beneficial effects:

[0020] 1) The semiconductor device testing method, storage medium, device and system of the present invention obtain signal waveforms that conform to the full amplitude value, so that the rise time and fall time can be accurately obtained within the same waveform, avoiding signal waveform distortion caused by transmission lines, and making the judgment of the device under test objective and accurate.

[0021] 2) The semiconductor device testing method, storage medium, equipment and system of the present invention are easy to operate, highly practical and can greatly improve the yield of the tested device. Attached Figure Description

[0022] Figure 1 The diagram shown illustrates the principle of rise and fall times in this invention.

[0023] Figure 2 The diagram shown is an exemplary signal transmission link of a device under test according to the present invention.

[0024] Figure 3 The diagram shown is a waveform schematic for an exemplary rise time detection according to the present invention.

[0025] Figure 4 The diagram shown is a waveform schematic for an exemplary fall time detection according to the present invention.

[0026] Figure 5 The diagram shows a detection waveform of an exemplary ATE device according to the present invention.

[0027] Figure 6 The diagram shows a functional flow chart of the semiconductor device testing method of the present invention.

[0028] Figure 7 The diagram shows the operation of the second signal DC component reduction according to the present invention.

[0029] Figure 8 The diagram shows the operation of obtaining the fourth signal by performing a superposition operation according to the present invention.

[0030] Figure 9 The diagram shown illustrates the transmission line reflection principle of the semiconductor device detection method of the present invention.

[0031] Figure 10 The diagram shown is a schematic representation of the semiconductor device detection system of the present invention.

[0032] Component designation explanation

[0033] 101 Semiconductor Devices

[0034] 102 ATE equipment

[0035] 121 Signal Processing Module

[0036] Steps S1 to S4 Detailed Implementation

[0037] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] Please see Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. The illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0039] Figure 1 The definitions of rise time and fall time are shown. TR is an abbreviation for Rising Time, which refers to the rise time of a signal waveform; TF is an abbreviation for Falling Time, which refers to the fall time of a signal waveform. Depending on the specific application of the device under test, the time it takes for a signal to rise from 20% to 80% of its full amplitude can be defined as the rise time, and the time it takes for a signal to fall from 80% to 20% of its full amplitude can be defined as the fall time.

[0040] Figure 2This diagram illustrates the signal transmission link of the device under test (DUT). DUT stands for Device Under Test; TX stands for Transmit; Rs is the internal resistance of the DUT; transmission line 1 is a microstrip or stripline line on the LB (Load Board, a dedicated circuit board connecting the DUT and the ATE equipment); transmission line 2 is a coaxial transmission line inside the ATE equipment; Rt is the internal terminating resistor of the ATE equipment; and Vt is the internal sensing voltage of the ATE equipment, which is typically programmable. The characteristic impedance of transmission line 2 is usually 50 ohms. If Rs is also 50 ohms, then only the characteristic impedance and Rt of transmission line 1 need to be 50 ohms for the entire transmission link to be matched. However, if the DUT's Rs is not 50 ohms, but the characteristic impedance of transmission line 2 is 50 ohms, then a transmission link mismatch exists. In this case, the DUT's TX output rate is generally low, and the resistance of Rs is greater than 50 ohms. When detecting rise and fall times, a capacitor of a certain value, such as 50pF, is required to be connected to the transmitting end of the device under test (DUT). However, in ATE testing, transmission line 1 after TX is generally considered equivalent to a capacitor of a certain value. Rt is then set to a high-impedance state. Therefore, obtaining the rise and fall times of the DUT on the ATE equipment under such a transmission link mismatch becomes a challenge.

[0041] Figure 3 A waveform diagram for rise time detection is shown, wherein the waveform diagram is composed of... Figure 2 The signal transmission link of the device under test is obtained. At this time, Rs is 50 ohms, and the characteristic impedance and Rt of transmission line 1 are both set to 50 ohms, that is, the impedance is ignored. Figure 2 In the case of impedance mismatch at point A, Vt is set to low level, the rise time is detected, and the result is obtained from the ATE device. Figure 3 The waveforms shown are: Vo is the output voltage of the DUT, and Vs is the full-amplitude voltage.

[0042] Figure 4 A waveform diagram for fall time detection is shown, wherein the waveform diagram is composed of... Figure 2 The signal transmission link of the device under test is obtained. At this time, Rs is 50 ohms, and the characteristic impedance and Rt of transmission line 1 are both set to 50 ohms, that is, the impedance is ignored. Figure 2 In the case of impedance mismatch at point A, Vt is set to high level, the fall time is detected, and the result is obtained from the ATE device. Figure 4 The displayed waveform is composed of Figure 4 It can be seen that the waveform contains a DC component, which is due to the high level.

[0043] from Figure 3 and Figure 4It can be seen that the output voltage Vo of the DUT is not full-scale and is reduced by a certain proportion. The detected rise time and fall time are inaccurate because even if the rise time and fall time are calculated proportionally, the equivalent capacitance on transmission line 2 must be considered, resulting in inaccurate results. In addition, the rise time and fall time are not within the same waveform, making it inconvenient to observe and calculate.

[0044] If Figure 2 If Rt is set to a high-impedance state, then Vt has no effect, resulting in the following: Figure 5 The diagram showing the ATE detection waveform is because... Figure 2 There is an impedance discontinuity between points A and C, causing the signal to reflect back and forth between points A and C. When the reflected waveforms are superimposed, the waveform acquired by the ATE device is distorted. Moreover, when the signal reflection and reversal rate is too high, the output voltage Vo will still be less than the full-amplitude voltage Vs, resulting in inaccurate rise and fall times.

[0045] Therefore, the present invention provides a semiconductor device testing method, storage medium, device and system, as detailed below:

[0046] like Figure 6 As shown, this embodiment provides a semiconductor device detection method, which includes at least:

[0047] S1: As Figure 6 As shown, the detection is started, and the detection voltage of the ATE equipment is set to low level and high level respectively to detect the semiconductor device. The ATE equipment collects the waveforms of the first signal and the second signal fed back from the semiconductor device through the transmission path. After the DC component of the second signal is removed, it is combined with the first signal to obtain the third signal.

[0048] Specifically, as an example, the detection voltage of the ATE device is set to a low level. The ATE device generates an excitation signal, which is sent to the semiconductor device under test (DUT) via a transmission path. The DUT outputs a first signal to the ATE device, and the ATE device acquires the waveform of the first signal. Alternatively, the detection voltage of the ATE device is set to a high level. The ATE device generates an excitation signal, which is sent to the DUT via a transmission path. The DUT outputs a second signal to the ATE device, and the ATE device acquires the waveform of the second signal. Since the second signal contains a DC component, a DC component subtraction operation is performed on the second signal. The waveform of the second signal after the DC component subtraction operation is as follows: Figure 7 As shown, the second signal, which completes the DC component reduction operation, is combined with the first signal to obtain the third signal. The waveform of the third signal is as follows: Figure 8 As shown.

[0049] Specifically, as an example, such as Figure 6 As shown, the steps to obtain the third signal are: combining the rising edge of the first signal with the falling edge of the second signal after the DC component reduction operation to obtain the third signal; or combining the falling edge of the first signal with the rising and falling edges of the second signal after the DC component reduction operation to obtain the third signal, the waveform of the third signal being as follows. Figure 8 As shown. It should be noted that semiconductor devices can be chips, integrated circuits, or specific equipment, etc. The method of obtaining the third signal is set according to the specific properties of the semiconductor device, which will not be elaborated here.

[0050] S2: As Figure 6 As shown, the connection point between the ATE device and the transmission path is set to an open circuit state, so that the third signal is reflected back and forth between the semiconductor device and the ATE device, and the ATE device calculates the signal waveform reflected back to the ATE device.

[0051] Specifically, as an example, such as Figure 9 As shown, based on the principle of signal reflection in the transmission path, the reason for setting the connection point between the ATE device and the transmission path to an open circuit state is to ensure that the signal reflects back and forth between the semiconductor device and the ATE device. It should be noted that as long as signal reflection between the semiconductor device and the ATE device can be guaranteed, the setting method includes, but is not limited to, setting the connection point between the ATE device and the transmission line to an open circuit state. This should be based on the actual application scenario and specific technical means, and will not be elaborated upon here. It should be further explained that the principle of signal reflection between the device under test and the ATE device is as follows... Figure 9 As shown, ΓA and ΓB are the reflection coefficients of the device under test and the ATE equipment, respectively. V1 is the signal voltage output by the semiconductor device, V2 is the signal voltage of V1 after reflection by the ATE equipment, and so on to obtain signal voltages such as V3, V4, V5, and V6.

[0052] The new signal voltage V is obtained by superimposing the signals reflected to the ATE device. B This yields four formulas, which are:

[0053] Formula 1: V B =V1+V2+V3+V4+V5+V6+…;

[0054] Formula 2: V1 = Vin, where Vin is the signal voltage output from the semiconductor device;

[0055] Formula 3: Vn=Vn-1*ΓB, where n=2 or 4 or 6 or 8 or…, that is, n is an even number;

[0056] Formula 4: Vm=Vm-1*ΓA, where m=3 or 5 or 7 or 9 or…, that is, m is an odd number;

[0057] According to the above formula, setting the connection point between the ATE device and the transmission path to an open circuit state can ensure that ΓB is the total reflection coefficient.

[0058] S3: As Figure 6 As shown, the waveform of the third signal is superimposed with the waveform of the signal reflected to the ATE device to obtain the fourth signal. The superposition stops when the amplitude of the fourth signal waveform reaches a preset full amplitude value. It should be noted that the superposition operation is performed based on Formula 1 in step S2.

[0059] S4: As Figure 6 As shown, the detection result is output by detecting the rise time and fall time of the waveform of the fourth signal.

[0060] Specifically, as an example, such as Figure 6 As shown, the steps for detecting rise time and fall time are as follows: First, the time it takes for the waveform of the fourth signal to rise from a first threshold to a second threshold is obtained and compared with a preset rise time; second, the time it takes for the waveform of the fourth signal to fall from the second threshold to the first threshold is obtained and compared with a preset fall time. More specifically, the first threshold is set within the range of 5% to 35% of the full amplitude, and the second threshold is set within the range of 65% to 95% of the full amplitude. Further, the preset rise time, the preset fall time, and the full amplitude are obtained through simulation verification or based on back-end process settings. Further still, it is determined whether the rise time of the fourth signal waveform is less than or equal to the preset rise time and whether the fall time of the fourth signal waveform is less than or equal to the preset fall time. If yes, a pass / fail result is output; otherwise, a fail / fail result is output. It should be noted that the settings of the preset rise time, preset fall time, and full amplitude should be based on the semiconductor device and the detection environment, which will not be elaborated here.

[0061] The semiconductor device testing method provided in this embodiment enables the rise time and fall time of semiconductor devices to be detected within the same waveform, reducing the number of tests and improving testing efficiency. At the same time, it can strengthen the control of the front-end process and prevent defective products from entering the back-end process, thereby preventing a large number of defective products from occurring.

[0062] When the aforementioned semiconductor device testing method is implemented as a software functional unit and sold or applied as an independent product, it can be stored in a single computer-readable storage medium, or in multiple computers, servers, or network devices, as long as the storage medium can be accessed. Any device is applicable and not limited to this embodiment. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements all or part of the steps of the semiconductor device testing method provided in this embodiment. The computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, private clouds, public clouds, read-only memory (ROM), and random access memory (RAM).

[0063] If the aforementioned semiconductor device testing method is implemented as a device and sold or applied as an independent product, it constitutes a semiconductor device testing device. This device includes at least a processor and a memory, wherein the memory stores a computer program; the processor executes the computer program stored in the memory, causing the semiconductor device testing device to perform all or part of the steps of the semiconductor device testing method. This semiconductor device testing device includes any device capable of executing the semiconductor device testing method, such as a quantum computer, a biocomputer, an industrial control computer, a tablet, or a mobile phone.

[0064] If the aforementioned semiconductor device testing method is implemented as a system and sold or applied as an independent product, it constitutes a semiconductor device testing system, such as... Figure 10 As shown, the semiconductor device testing system includes at least an ATE device 102 and a signal processing module 121. The ATE device 102 is used for communication with the semiconductor device under test 101. The signal processing module 121 is located inside the ATE device 102 and is used to configure the detection parameters of the semiconductor device 101, enabling the ATE device 102 to execute all or part of the steps of the semiconductor device testing method. It should be noted that if the semiconductor device 101 and the ATE device are connected via a transmission line, the characteristic impedance of the transmission line must be equal to the value of the terminating resistor inside the ATE device, typically 50 ohms. To obtain an accurate third signal waveform, there must be no reflection between the transmission line and the ATE device 102.

[0065] In summary, the semiconductor device testing method, storage medium, device, and system of the present invention include at least the following steps: initiating detection; setting the detection voltage of the ATE device to low and high levels respectively; detecting the semiconductor device; having the ATE device acquire waveforms of a first signal and a second signal fed back from the semiconductor device via the transmission path; performing a DC component removal operation on the second signal and combining it with the first signal to obtain a third signal; setting the connection point between the ATE device and the transmission path to an open circuit state, causing the third signal to reflect back and forth between the semiconductor device and the ATE device; having the ATE device calculate the waveform of the signal reflected back to the ATE device; superimposing the waveform of the third signal with the waveform of the signal reflected back to the ATE device to obtain a fourth signal; stopping the superposition when the amplitude of the fourth signal waveform reaches a preset full amplitude value; and outputting a detection result by detecting the rise time and fall time of the fourth signal waveform. The semiconductor device testing method, storage medium, device, and system of the present invention obtain signal waveforms that conform to the full amplitude value, enabling accurate acquisition of the rise time and fall time within the same waveform, avoiding signal waveform distortion caused by transmission lines, and ensuring objective and accurate judgment of the device under test. The semiconductor device testing method, storage medium, equipment, and system of the present invention are simple to operate, highly practical, and can greatly improve the yield of the tested devices. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0066] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of detecting a semiconductor device, characterized by, The semiconductor device detection method at least comprises: starting detection, setting the ATE device detection voltage to low and high respectively, detecting the semiconductor device, collecting the first signal and the second signal fed back from the semiconductor device through the transmission path by the ATE device, synthesizing the first signal and the second signal after removing the direct current component of the second signal to obtain the third signal; setting the connection point of the ATE device and the transmission path to an open circuit state, making the third signal reflect back and forth between the semiconductor device and the ATE device, and calculating the signal waveform reflected to the ATE device by the ATE device; superimposing the waveform of the third signal and the signal waveform reflected to the ATE device to obtain the fourth signal, comprising: V B = V1+ V2+ V3+ V4+ V5+ V6+…, where V B is the new signal voltage resulting from the superposition of each signal reflected to the ATE device; V1=Vin, wherein Vin is the signal voltage output from the semiconductor device; Vn=Vn-1*ΓB, wherein n is an even number greater than 0, and ΓB is the reflection coefficient of the ATE device; Vm=Vm-1*ΓA, wherein m is an odd number greater than 1, and ΓA is the reflection coefficient of the semiconductor device; stopping superimposition when the amplitude of the fourth signal waveform reaches a preset full amplitude; obtaining the rising time and the falling time detection output by detecting the rising time and the falling time of the fourth signal waveform.

2. The semiconductor device inspection method according to claim 1, characterized by: The step of obtaining the third signal is to synthesize the rising edge of the first signal and the falling edge of the second signal after removing the direct current component to obtain the third signal, or to synthesize the falling edge of the first signal and the rising edge of the second signal after removing the direct current component to obtain the third signal.

3. The semiconductor device inspection method according to claim 1, characterized by: The step of rising time and falling time detection is to obtain the time when the waveform of the fourth signal rises from the first threshold value to the second threshold value, and compare it with the preset rising time; and obtain the time when the waveform of the fourth signal falls from the second threshold value to the first threshold value, and compare it with the preset falling time.

4. The semiconductor device inspection method according to claim 3, wherein: The setting range of the first threshold value is 5% to 35% of the full amplitude, and the setting range of the second threshold value is 65% to 95% of the full amplitude.

5. The semiconductor device inspection method according to claim 4, characterized by: The preset rising time, the preset falling time and the full amplitude are obtained through simulation verification or based on back-end process setting.

6. The method of claim 1, wherein: If the rising time of the fourth signal waveform is less than or equal to the preset rising time and the falling time of the fourth signal waveform is less than or equal to the preset falling time, output the detection qualified result, otherwise, output the detection unqualified result.

7. A computer readable storage medium storing a computer program, characterized in that: The computer program is executed by the processor to realize the semiconductor device detection method of any one of claims 1-6.

8. A semiconductor device inspection apparatus characterized by comprising: The semiconductor device detection device at least comprises a processor and a memory, wherein: the memory is used to store a computer program; and the processor is used to execute the computer program stored in the memory, so that the semiconductor device detection device executes the semiconductor device detection method of any one of claims 1-6.

9. A semiconductor device inspection system characterized by comprising: The semiconductor device detection system comprises at least an ATE device and a signal processing module, wherein the ATE device is configured to be connected with the semiconductor device to be detected; the signal processing module is arranged in the ATE device and is configured to configure the detection parameters of the semiconductor device and make the ATE device execute the semiconductor device detection method according to any one of claims 1-6.

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