A data transmission circuit and method based on a network on chip

Abstract

This invention discloses a data transmission circuit and method based on an on-chip network. The data buffer of this invention is used to buffer data to be transmitted received from a data receiving port. The data buffer includes multiple data buffer units and is connected to at least two pointer queues. Each pointer queue corresponds to a target direction and buffers pointers to data to be transmitted toward its corresponding target direction. Each pointer is a position number of each data buffer unit in the data buffer and is used to read data to be transmitted from the data buffer unit. This circuit reduces the time delay during data transmission and conserves data buffer resources.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically to a data transmission circuit and data transmission method based on a network-on-a-chip. Background Technology

[0002] In a System-on-Chip (SoC), a network-on-chip (NoC) is used to enable communication between subsystems. Specifically, the NoC architecture includes multiple subsystems (i.e., computing cores), which are interconnected through Broadcast Routers (BRs). Each BR can receive and transmit data in each direction. The receiving port is represented by RX, and each BR can receive data from four directions, i.e., each BR includes four RXs: RX0, RX1, RX2, and RX3. The transmitting port is represented by TX, and each BR can transmit data in four directions, i.e., each BR includes four TXs: TX0, TX1, TX2, and TX3. Each RX in each direction corresponds to a splitter, which is used to send the data received in that direction to the TXs in the other three directions. Each splitter includes a data buffer, and the RX stores the received data in the splitter's data buffer after receiving data and before transmitting it.

[0003] In existing technology, when data received by the RX needs to be multicast, multiple copies are made when the data enters the data buffer. These copies are then arranged sequentially within the data buffer. Simultaneously, the pointers and direction information corresponding to the data to be multicast are stored in a pointer queue. To implement multicast, the pointers in the pointer queue must be searched sequentially from beginning to end to determine the first pointer in each direction, which is then dequeued simultaneously. The corresponding data is then read from the data buffer based on these pointers, and the read data is sent to the corresponding TX side according to the direction information, thus achieving data multicast. When data is sent to only one direction, the first pointer in that direction also needs to be searched in the pointer queue. Therefore, implementing multicast requires multiple copies of the data, consuming data buffer resources. Furthermore, each dequeue requires searching the pointer queue from beginning to end to determine the pointer for each direction. If the pointer queue is deep, this search method can lead to circuit time delays. Additionally, the need to update the pointers sequentially after each dequeue also contributes to circuit time delays.

[0004] In summary, reducing circuit time delay and conserving data buffer resources are problems that need to be solved during data transmission. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a data transmission circuit and a data transmission method based on an on-chip network, which can reduce the time delay of the circuit during data transmission and save data buffer resources.

[0006] In a first aspect, embodiments of the present invention provide a data transmission circuit based on an on-chip network, the circuit comprising:

[0007] A data buffer, used to cache data to be sent received from the data receiving port, the data buffer comprising multiple data buffer units, and the data buffer connected to at least two pointer queues;

[0008] At least two pointer queues, each pointer queue corresponding to a target direction, and each pointer queue buffers pointers to data to be sent to its corresponding target direction;

[0009] The pointer is the position number of each data buffer unit in the data buffer, and the pointer is used to read the data to be sent from the data buffer unit in the data buffer.

[0010] Optionally, the circuit may also include:

[0011] The direction buffer includes multiple direction buffer units, each of which corresponds to the data buffer unit and is used to cache the target direction marker of the data to be sent in the data buffer unit.

[0012] Optionally, the pointer queue is a first-in, first-out (FIFO) queue.

[0013] Optionally, the direction buffer further includes a fast lookup circuit for finding direction buffer units in the direction buffer where the target direction mark is empty. The direction buffer units where the target direction mark is empty are used to write the target direction mark of the newly received data to be sent in the data buffer.

[0014] Secondly, embodiments of the present invention provide a method for data transmission based on an on-chip network, the method comprising:

[0015] Receive data to be sent;

[0016] The data to be sent is buffered into an empty data buffer unit in the data buffer, wherein the empty data buffer unit is located at any position in the data buffer;

[0017] Obtain the target direction marker of the data to be sent, determine the first pointer queue from at least two pointer queues based on the target direction marker, and push the pointer of the data to be sent into the first pointer queue, wherein the pointer is the position number of the data buffer unit of the data to be sent in the data buffer.

[0018] Optionally, the target direction mark of the data to be sent is saved to the direction buffer unit corresponding to the data buffer unit, wherein the direction buffer unit is an idle unit in the direction buffer.

[0019] Optionally, the pointer queue is a first-in, first-out (FIFO) queue, and in response to a pointer being dequeued from the pointer queue, the method further includes:

[0020] The data to be sent in the data buffer is obtained according to the pointer dequeued.

[0021] Optionally, the method further includes:

[0022] The data to be sent is transmitted through the data output port in the target direction corresponding to the pointer queue.

[0023] Optionally, in response to a pointer being dequeued from the pointer queue, the method further includes:

[0024] According to the dequeue pointer, retrieve the data to be sent from the first data buffer unit; wherein, the first data buffer unit is the data buffer unit in the data buffer indicated by the dequeue pointer;

[0025] Set the value of the target direction marker corresponding to the second pointer queue in the direction buffer unit corresponding to the first data buffer unit to 0, wherein the second pointer queue is the pointer queue where the dequeued pointer is located.

[0026] Optionally, in response to all values ​​in the corresponding target direction marker in the direction buffer unit being set to 0, the method further includes:

[0027] The direction buffer unit is determined to be empty.

[0028] Optionally, the method further includes:

[0029] The data buffer unit corresponding to the direction buffer unit receives new data to be sent.

[0030] The direction buffer unit stores the target direction marker of the new data to be sent.

[0031] Optionally, the method further includes:

[0032] Locate the direction buffer cell in the direction buffer where the target direction is marked as empty;

[0033] The second data buffer unit is determined to be free, wherein the second data buffer unit is the data buffer unit corresponding to the direction buffer unit marked as empty in the target direction.

[0034] Optionally, the depth of the data buffer, the direction buffer, and the pointer queue is all 8.

[0035] Thirdly, embodiments of the present invention provide an integrated circuit, the integrated circuit including multiple cores, an on-chip network, and a data transmission circuit based on the on-chip network as described in the first aspect and any one of the possibilities of the first aspect.

[0036] Fourthly, embodiments of the present invention provide a board card that includes the integrated circuit described in the third aspect.

[0037] Fifthly, embodiments of the present invention provide a server, the server including the board from the fourth aspect.

[0038] This invention employs a data buffer to cache data to be transmitted received from a data receiving port. The data buffer comprises multiple data buffer units and is connected to at least two pointer queues. Each pointer queue corresponds to a target direction and caches pointers to data to be transmitted toward its corresponding target direction. The pointers are position numbers of each data buffer unit within the data buffer and are used to read data to be transmitted from those units. Through this circuitry, for each target direction, pointers can be retrieved sequentially from their respective pointer queues, and data to be transmitted can be read from the data buffer units in the data buffer based on these pointers. This solves the delay problem in existing technologies caused by searching for the corresponding data pointer based on the target direction information of the data to be transmitted. Furthermore, when implementing data multicast, the data does not need to be copied multiple times; only one copy needs to be stored in the data buffer. When a pointer is dequeued from each pointer queue, the data is directly read from the data buffer unit corresponding to the dequeued pointer.

[0039] Furthermore, the target direction marker of the data to be sent can be cached in the corresponding direction buffer. The direction buffer pushes the corresponding pointer into the pointer queue corresponding to the direction to be sent according to the target direction marker. When any data output port needs to output the data to be sent corresponding to the pointer, it only needs to look up the data in the data buffer according to the pointer. The data buffer and the direction buffer do not need to follow the first-in-first-out principle. As long as the pointer queue follows the first-in-first-out principle, the transmission order of the data to be sent is guaranteed. Attached Figure Description

[0040] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0041] Figure 1 This is a schematic diagram of the internal circuit structure of a BR in the prior art;

[0042] Figure 2 This is a schematic diagram of a pointer queue enqueue in the existing technology;

[0043] Figure 3 This is a schematic diagram of a pointer queue dequeue in the prior art;

[0044] Figure 4 This is a schematic diagram of a data buffer in the prior art;

[0045] Figure 5 This is a schematic diagram of a data transmission circuit based on an on-chip network in an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of a data buffer in an embodiment of the present invention;

[0047] Figure 7 This is a schematic diagram of a fast lookup circuit in an embodiment of the present invention;

[0048] Figure 8 This is a schematic diagram of a directional buffer in an embodiment of the present invention;

[0049] Figure 9 This is a schematic diagram of a pointer queue in an embodiment of the present invention;

[0050] Figure 10(a) is a schematic diagram of a data transmission circuit based on an on-chip network in an embodiment of the present invention;

[0051] Figure 10(b) is a schematic diagram of a data transmission circuit based on an on-chip network in an embodiment of the present invention;

[0052] Figure 10(c) is a schematic diagram of a data transmission circuit based on an on-chip network in an embodiment of the present invention;

[0053] Figure 11 This is a flowchart of a data transmission method based on an on-chip network according to an embodiment of the present invention;

[0054] Figure 12 This is a flowchart of a data transmission method based on an on-chip network according to an embodiment of the present invention;

[0055] Figure 13 This is a flowchart of a data transmission method based on an on-chip network according to an embodiment of the present invention;

[0056] Figure 14 This is a flowchart of a data transmission method based on an on-chip network according to an embodiment of the present invention;

[0057] Figure 15 This is a flowchart of a data transmission method based on an on-chip network according to an embodiment of the present invention. Detailed Implementation

[0058] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0059] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0060] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0061] In the description disclosed in this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description disclosed in this invention, unless otherwise stated, "a plurality of" means two or more.

[0062] In a System-on-Chip (SoC), an On-Chip Network (NoC) is used to enable communication between subsystems. Specifically, the SoC comprises multiple banks, and each bank further includes multiple subsystems (i.e., computing cores). These subsystems are interconnected through Broadcast Routers (BRs), and the internal circuit structure of each BR is as follows: Figure 1As shown, for example, a BR can receive and transmit data in each direction. The receiving port is represented by RX, and each BR can receive data from four directions, i.e., each BR includes four RXs: RX0, RX1, RX2, and RX3. The transmitting port is represented by TX, and each BR can transmit data in four directions, i.e., each BR includes four TXs: TX0, TX1, TX2, and TX3. Each RX in each direction corresponds to a splitter, used to send the data received in that direction to the TXs in the other three directions. Therefore, the BR also includes four splitters: Splitter0, Splitter1, Splitter2, and Splitter3. These splitters can also be called distribution modules. Each TX in each direction corresponds to an arbiter, used to arbitrate data sent from the other three directions. Therefore, the BR also includes four arbiters: Arbiter0, Arbiter1, Arbiter2, and Arbiter3. Furthermore, each TX in each direction can receive data from three directions, and each received data corresponds to a buffer, which is a First-In-First-Out (FIFO) queue. If the BR also includes 12 FIFOs (output FIFOs), then each direction's TX has 3 FIFOs, used to buffer data from the other three directions, and the connection between each FIFO and the Arbiter in that direction forms a channel. Specifically, the data transmission process after entering the BR is as follows: First, it passes through the splitter distribution module. The splitter can distribute the data to the target direction's FIFO according to the shortest path routing principle. Data that needs to be routed to the same TX direction is converged on the TX side. That is, the three FIFOs in the target direction converge the data from the three directions' RX, and the data in each FIFO has the same RX and TX directions. After convergence, the Arbiter in the target direction schedules the data in its corresponding three FIFOs, and after scheduling, it is sent to the TX port for output.

[0063] Specifically, the splitter distribution module includes a data buffer and a pointer queue. The data buffer stores data received by the RX corresponding to the splitter, and the pointer queue stores the transmission direction of the data in the data buffer. Specifically, the pointer queue contains pointers and direction information. The pointer is used to retrieve data at the corresponding position in the data buffer, and the direction information indicates the target direction to which the data retrieved at that position is sent. For example, writing pointer 0 and direction 0 to the pointer queue indicates that the data at position 0 in the data buffer needs to be sent in the TX0 direction represented by direction 0; writing pointer 1 and direction 0 to the pointer queue indicates that the data at position 1 in the data buffer needs to be sent in the TX0 direction represented by direction 0.

[0064] If the data buffer has a depth of 8 (i.e., 8 positions, corresponding to pointers 0-7 respectively), then... Figure 2 As described above, during enqueueing, pointers 0 and direction0, 1 and direction1, 2 and direction1, 3 and direction3, 4 and direction3, 5 and direction0, 6 and direction2, and 7 and direction1 are enqueued sequentially. Here, direction0-direction3 represent the directions to be sent (TX0-TX3), respectively. Specifically, Figure 2The different background formats indicate different TX directions. The data in positions 0 and 5 of the data buffers corresponding to pointers 0 and 5 are destined for TX0; the data in positions 1, 2, and 7 of the data buffers corresponding to pointers 1, 2, and 7 are destined for TX1; the data in positions 3 and 4 of the data buffers corresponding to pointers 3 and 4 are destined for TX3; and the data in position 6 of the data buffer corresponding to pointer 6 is destined for TX2. If the first pointer in each direction (TX0-TX3) could be dequeued simultaneously—that is, pointers 0, 1, 3, and 6, along with their corresponding direction information, could be retrieved from the pointer queue at the same time—the data in positions 0, 1, 3, and 6 of the data buffers corresponding to pointers 0, 1, 3, and 6 could be simultaneously sent to TX0, TX1, TX3, and TX2 respectively. However, each dequeue requires searching the pointer queue from front to back to obtain the first pointer in each direction, causing a time delay. Furthermore, after a pointer is dequeued, the positions of the remaining pointers in the pointer queue need to be updated. This means moving the remaining pointers forward so that, after the position update, the remaining pointers are stored consecutively from the beginning of the pointer queue. Each pointer can only move one position at a time. For example, ... Figure 3 As shown, when pointers 0, 1, 3, and 6 are dequeued simultaneously, pointers 2, 4, 5, and 7 need to be moved forward, which requires a total of 4 moves and will also cause a time delay.

[0065] Meanwhile, in existing technology, when the splitter distribution module distributes data from the RX side to the TX side FIFO according to the shortest path routing principle, the specific steps are as follows: When data received by the RX needs to be multicast, multiple copies are made when the data enters the splitter's data buffer. These copies are then arranged sequentially in the data buffer, and finally, the multiple copies are read out and sent to the corresponding TX directions. For example, as... Figure 4As shown, splitter0 is the distribution module corresponding to RX0. The data d1 received by RX0 needs to be sent to three directions: TX1, TX2, and TX3. Therefore, three copies of d1 need to be stored in the data buffer of splitter0, consuming more resources in the data buffer. If the three d1 values ​​are stored in positions 0, 1, and 2 of the data buffer respectively, then the pointer queue of splitter0 stores pointer 0 and direction1, pointer 1 and direction2, and pointer 2 and direction3 sequentially. Reading pointer 0 and direction1 from the pointer queue sends d1 from position 0 of the data buffer to TX1; reading pointer 1 and direction2 from the pointer queue sends d1 from position 1 of the data buffer to TX2; and reading pointer 2 and direction3 from the pointer queue sends d1 from position 2 of the data buffer to TX3.

[0066] In summary, reducing circuit delays during data transmission and conserving data buffer resources are problems that need to be addressed.

[0067] In this embodiment of the invention, to solve the above problems, a data transmission circuit based on an on-chip network is proposed, specifically as follows: Figure 5 As shown, Figure 5 This is a schematic diagram of a data transmission circuit based on a network-on-chip according to an embodiment of the present invention. The data transmission circuit based on a network-on-chip is located inside the splitter distribution module and specifically includes: a data buffer 501, a direction buffer 502, and at least two pointer queues 503.

[0068] The data buffer 501 is used to buffer data to be transmitted received from the receive data port (RX). The data buffer includes multiple data buffer units and is connected to at least two pointer queues. For example, the data buffer has a depth of 8, and the bit width of the data to be transmitted can be 1024 bits. The data to be transmitted can be buffered in any free data buffer unit within the data buffer, with each data buffer unit corresponding to a data buffer location. For example, Figure 6 As shown, assuming that the data buffer units corresponding to positions 2 and 4 of the data buffer are free, the received data to be sent can be buffered in either position 2 or position 4.

[0069] The receiving data port (RX) receives the data to be transmitted and simultaneously acquires the target direction marker of the data to be transmitted. This target direction marker indicates the direction to which the data to be transmitted needs to be sent. For example, in the case of four target directions, the target direction marker can be represented by a 4-bit binary number, where each bit can be represented by direction[3:0]. Direction[0] represents the target direction TX0, direction[1] represents the target direction TX1, direction[2] represents the target direction TX2, and direction[3] represents the target direction TX3. The value of direction[3:0] is either 0 or 1. When the value of direction[3:0] is 0, it indicates that the data to be transmitted does not need to be sent to the corresponding target direction; when the value of direction[3:0] is 1, it indicates that the data to be transmitted needs to be sent to the corresponding target direction. This embodiment of the invention does not limit this; it is determined according to the actual situation.

[0070] In one possible implementation, when multiple bits in the 4-bit target direction marker are 1, it indicates that the data to be sent is multicast data and needs to be sent to multiple target directions.

[0071] For example, if the target direction marker of the 4 bits is 1100, it indicates that the data to be sent needs to be sent to TX0 and TX1, or it indicates that the data to be sent needs to be sent to TX2 and TX3; if the value of the 4 bits is 0111, it indicates that the data to be sent needs to be sent to TX1, TX2 and TX3, or it indicates that the data to be sent needs to be sent to TX0. Specifically, it is determined according to the meaning represented by 0 or 1. This embodiment of the invention does not limit it, and it is determined according to the actual situation. In the subsequent processing of this invention, 0 is used to indicate that no sending is required, and 1 is used to indicate that sending is required, so as to avoid confusion.

[0072] The direction buffer 502 includes multiple direction buffer units, each corresponding to a data buffer unit, used to cache the target direction marker of the data to be sent in the data buffer unit. In this invention, the target direction marker cached in the direction buffer units facilitates real-time querying of the transmission status of the data to be sent in each direction. For example, at time T0, the target direction marker of the data d2 to be sent stored in the direction buffer unit is 0111 (0 indicates that data d2 does not need to be sent to TX3), indicating that data d2 has not yet been sent to the TX0, TX1, and TX2 directions; then, the pointer of data d2 is dequeued from the TX0 pointer queue, and after data d2 is obtained according to the dequeued pointer and sent to the TX0 direction, the target direction marker of data d2 in the direction buffer unit changes to 0110. Therefore, at time T1, the target direction marker of the data d2 to be sent stored in the direction buffer unit is 0110, indicating that data d2 has not yet been sent to the TX1 and TX2 directions.

[0073] In one possible implementation, since each direction buffer unit has a corresponding data buffer unit, when the data buffer unit is written with data to be transmitted, the target direction marker of the data to be transmitted is simultaneously written to the corresponding direction buffer unit. Similarly, when the target direction marker in the direction buffer unit is empty (all values ​​in the target direction marker are set to 0), it indicates that the direction buffer unit is in an idle state, and the corresponding data buffer unit is also in an idle state. New data can be written to this idle data buffer unit. For example, if at time T2, the target direction marker of the data d2 to be transmitted stored in the direction buffer unit is 0000, indicating that data d2 has completed data transmission in all directions, then marking the direction buffer unit as idle and its corresponding data buffer unit is also idle, allows for the writing of new data to be transmitted. Therefore, the 4-bit target direction marker cached in the direction buffer unit can also be used to determine whether the data buffer unit is occupied, resulting in a simple implementation with minimal resource consumption.

[0074] In other possible implementations, for multicast propagation, a monitoring module for the data buffer status can be set up. For example, the number n of multicast directions can be recorded. If data needs to be sent to TX0, TX1, and TX2, then n=3 is marked. When the data buffer unit has been read once, n=n-1 is set until n=0, at which point the data buffer unit is considered idle and new data to be sent is written. Alternatively, a timer mechanism can be set up so that the data buffer unit is marked as idle after a certain period of time (e.g., 0.002s) of data has been written to it.

[0075] Specifically, the direction buffer further includes a fast lookup circuit for searching for direction buffer units in the direction buffer where the target direction marker is empty. These empty direction buffer units are used to write the target direction marker of the newly received data to be sent from the data buffer. The fast lookup circuit is as follows: Figure 7 As shown, located inside the direction buffer, assuming that the direction buffer includes 8 direction buffer units, each direction buffer unit is connected to a NOR gate 701 to determine the state of the direction buffer. In each direction buffer unit, the 4-bit target direction mark is passed through the NOR gate 701, and the 4-bit target direction value is NORed to generate a 1-bit signal. Then the state of the 8 direction buffer units can be represented by an 8-bit signal. For example, the generated 8-bit value is 11011010, where the value 0 indicates that the corresponding direction buffer unit is occupied, and the value 1 indicates that the corresponding direction buffer unit is in an idle state.

[0076] For example, the direction buffer units in the direction buffer are sequentially numbered from front to back as the first direction buffer unit, the second direction buffer unit, ..., the eighth direction buffer unit, and the position numbers of the first direction buffer unit, the second direction buffer unit, ..., the eighth direction buffer unit are 0, 1, 2, 3, 4, 5, 6, and 7, respectively. The last value 0 in 11011010 indicates that the first direction buffer unit is occupied, and the first value 1 in 11011010 indicates that the eighth direction buffer unit is idle. The other bits are not described in detail and are the same as described above.

[0077] like Figure 7As shown, the fast lookup circuit also includes a first AND gate 702, connected to each of the NOR gates 701, for the purpose of determining the first free position among the eight direction buffer units. Specifically, the 8-bit data 11011010 generated by the aforementioned NOT gate 701 is subtracted by 1 and then inverted bitwise, where the inverted value after subtraction is 00100110. Then, the first AND gate 702 performs a bitwise AND operation between 00100110 and 11011010 to obtain an 8-bit one-hot code signal value 00000010, thus determining the first value 1 appearing in the 8-bit data 11011010 in the order of 0 to 7, that is, the second to last bit "1" in 11011010, to determine the free position of the direction buffer. The fast lookup circuit also includes multiple second AND gates 703 and multiple OR gates 704. The second AND gates 703 and multiple OR gates 704 are used to determine the free position number of the free direction buffer unit. The free position number is represented by a binary value. Specifically, since each bit in 00000010 represents a direction buffer, each bit is extended to 3 bits by the second AND gate 703 to match the number of bits in the direction buffer unit number. For example, the last bit "0" in 00000010 is extended to "000" and ANDed with the last direction buffer unit number "000" by the OR gate 704. The second bit "1" in 00000010 is extended to "111" by the second AND gate 703 and ANDed with the second-to-last direction buffer unit number "001" by the OR gate 704. Then, the result is ORed. The operation for other direction buffers is the same as above. That is, after expanding each bit in the 8-bit array to 3 bits, each pair of bits is ORed, and the results are ORed again until an operational structure is obtained, which is the final free position number. Free position number = (000&000)|(111&001)|(000&010)|(000&011)|(000&100)|(000&101)|(000&110)|(000&111) = 001. Finally, this 3-bit binary number is converted into a decimal number to determine the position where the free position number is decimal 1.

[0078] In this embodiment of the invention, when an idle direction buffer unit is found in the direction buffer and its corresponding data buffer unit is also idle, the data to be sent can be cached in the idle data buffer unit, and the target direction mark of the data to be sent can also be cached in the corresponding idle direction buffer unit.

[0079] In one possible implementation, the fast lookup circuit can simultaneously search all the direction buffer cells in the direction buffer, resulting in a fast lookup speed.

[0080] For example, when the depth of the data buffer is 8, the depth of the direction buffer is also 8. Each direction buffer unit corresponds to a data buffer unit. The data buffer does not need to store received data to be sent in sequence; newly received data to be sent can be cached in any free data buffer unit. Similarly, the direction buffer does not need to store the target direction marker of the data to be sent in sequence; the target direction marker corresponding to newly received data to be sent can be cached in the direction buffer unit corresponding to any free data buffer unit. It is sufficient that after data is cached in a certain data buffer unit, the target direction marker of that data is cached in the direction buffer unit corresponding to that data buffer unit.

[0081] Specifically, such as Figure 8 As shown, it is assumed that for each direction buffer unit, its position in the direction buffer is the same as the position of its corresponding data buffer unit in the data buffer. If position 2 of the direction buffer is found to be free, then position 2 of the corresponding data buffer is free. At the same time, the received data to be sent is cached in position 2 of the data buffer, and the 4-bit value corresponding to the target direction mark of the data to be sent is cached in position 2 of the direction buffer.

[0082] At least two pointer queues 503 are provided, each pointer queue (pointer FIFO) corresponding to a target direction. Each pointer queue buffers pointers to data to be sent in its corresponding target direction. The pointer is the position number of the data to be sent in the data buffer, representing the storage address of the data in the data buffer. Therefore, the data to be sent can be read from the direction buffer unit of the data buffer using the pointer. Based on the pointers buffered in each pointer queue, the data to be sent in the target direction corresponding to that pointer queue can be found in the data buffer.

[0083] In one possible implementation, the pointer queue also has a depth of 8 and a bit width of 3 bits.

[0084] Taking four pointer queues as an example, corresponding to TX0, TX1, TX2, and TX3 respectively, each pointer queue caches pointers to the data to be sent in its corresponding target direction, stored in a data buffer. Specifically, the TX1 pointer queue caches pointers to the data buffer units corresponding to the data to be sent in the TX1 direction, used to retrieve the data to be sent in the TX1 direction from the data buffer; the TX2 pointer queue caches pointers to the data buffers to the TX2 direction, used to retrieve the data to be sent in the TX2 direction from the data buffer; and the TX3 pointer queue caches pointers to the data buffers to the TX3 direction, used to retrieve the data to be sent in the TX3 direction from the data buffer.

[0085] In one possible implementation, since each of the direction buffer units corresponds to a data buffer unit—for example, position 0 of the data buffer unit corresponds to position 0 of the direction buffer unit—the pointer corresponding to position 0 is pointer 0. Similarly, the pointer corresponding to position 1 of the data buffer unit is pointer 1, position 2 is pointer 2, position 3 is pointer 3, position 4 is pointer 4, position 5 is pointer 5, position 6 is pointer 6, and position 7 is pointer 7, and so on. Figure 9 The received data to be sent is cached in position 2 of the data buffer unit, and the target direction mark of the data to be sent is cached in position 2 of the direction buffer. If the value of all 4 bits of the target direction mark is 1, it means that the data to be sent needs to be sent to four target directions: TX0, TX1, TX2 and TX3. Then, pointer 2 is written into the four pointer queues respectively.

[0086] Specifically, the pointer queue is a first-in, first-out (FIFO) queue. The purpose of designing the pointer queue as a FIFO queue is to ensure that data sent in the same direction is kept in order, guaranteeing that data entering the data buffer first in the same direction will definitely leave the data buffer first.

[0087] In one possible embodiment, when a pointer is dequeued from the pointer queue, the data to be sent in the first data buffer unit is obtained according to the dequeued pointer; wherein, the first data buffer unit is the data buffer unit in the data buffer indicated by the dequeued pointer.

[0088] In one possible embodiment, when a pointer is dequeued from the pointer queue, the value in the target direction marker corresponding to the second pointer queue in the direction buffer unit corresponding to the first data buffer unit is set to 0, wherein the second pointer queue is the pointer queue where the dequeued pointer is located.

[0089] For example, as long as any pointer queue is not empty and the downstream is capable of receiving data, the pointer to be dequeued can be read from the pointer queue, and data can be retrieved from the data buffer according to the position indicated by the pointer and sent downstream; and the direction buffer is updated according to the dequeued pointer; the specific update method is to set the value of the target direction corresponding to the pointer queue where the dequeued pointer is located in the direction buffer to 0, indicating that the data to be sent is taken out from the data buffer and sent to the target direction corresponding to that value. For example, if the pointer read from the TX0 pointer queue is pointer 3, then the data to be sent at position 3 will be read from the data buffer and sent to the TX0 direction, and the direction[0] at position 3 in the direction buffer will be set to 0, that is, the value direction[0] corresponding to the TX0 pointer queue will be set to 0.

[0090] If the pointer read from the TX1 pointer queue is pointer 3, then the data to be sent at position 3 in the data buffer will be read out and sent to the TX1 direction, and the direction[1] at position 3 in the direction buffer will be set to 0, that is, the value direction[1] corresponding to the TX1 pointer queue will be set to 0.

[0091] In one possible embodiment, when all values ​​in the target direction marker in the direction buffer unit are set to 0, the direction buffer unit is determined to be empty. The direction buffer unit can be set to empty, and then new data to be sent can be received.

[0092] The data transmission process will be fully explained below through two specific examples. Specific Implementation Example 1

[0094] If all data buffers, direction buffers, and pointer queues are empty, the data receiving port RX3 receives the data to be transmitted. This data needs to be sent to three target directions: TX0, TX1, and TX2. The data to be transmitted is buffered at position 0 of the data buffer. At this time, position 0 of the direction buffer is empty. The target direction marker 4'b0111 of the data to be transmitted is buffered at position 0 of the direction buffer, and pointer 0 is pushed into the pointer queues of the three target directions: TX0, TX1, and TX2. In the target direction marker 4'b0111, the three "1"s in "0111" represent the target directions of TX2, TX1, and TX0 respectively, and the "0"s in "0111" indicate that the data does not need to be sent to TX3. If the downstream of TX0, TX1, and TX2 all have receiving capabilities, pointer 0 will be read simultaneously from the pointer queues of the three target directions. Based on the pointer 0 read from the three target directions, the data to be transmitted is read from position 0 of the data buffer, and the data read multiple times is sent to TX0, TX1, and TX2 respectively. While acquiring the data to be sent, the 0th, 1st, and 2nd bits of the direction value (4'b0111) at position 0 in the direction buffer are all set to 0, becoming 4'b0000, indicating that the position is released as an empty position.

[0095] If neither the downstream of target directions TX1 nor TX2 has receiving capability, and only the downstream of target transmission TX0 has receiving capability, then only pointer 0 will be read from the pointer queue of TX0. That is, only the data to be sent will be retrieved from the data buffer based on pointer 0 of TX0, and the read data will be sent to TX0 respectively. At the same time, the 0 bit of the direction value (4'b0111) at position 0 in the direction buffer will be set to 0, becoming 4'b0110, indicating that the data to be sent for multicast has been sent in the target direction TX0, but has not yet been sent in the target directions TX1 and TX2.

[0096] Therefore, whether multicast data can be sent to the target direction simultaneously depends on the receiving capability of the downstream of each target direction. If the downstream of each target direction can receive the data, then the multicast data can be sent simultaneously. Specific Implementation Example 2

[0098] The data transmission process is described using a complete schematic diagram, as shown in Figures 10(a), 10(b), and 10(c). In Figure 10(a), position 3 (the third data buffer unit) of the data buffer is empty, while other positions buffer data to be sent. The data buffered in other positions is not specifically represented in the diagram; it is simply indicated by black squares. Similarly, position 3 (the third direction buffer unit) of the direction buffer is empty, while other positions buffer target direction markers. The target direction markers buffered in other positions are not specifically represented in the diagram; they are simply indicated by black squares. All four pointer queues have an empty last unit, while the other positions buffer pointers. The pointers buffered in other positions are not specifically represented in the diagram; they are simply indicated by black squares.

[0099] At this time, the data receiving port receives the data to be sent, A, which needs to be sent to three target directions, TX1, TX2 and TX3. Since position 3 of the direction buffer is empty, as shown in Figure 10(b), 4'b1110 is buffered in position 3 of the direction buffer. At the same time, the data to be sent, A, is buffered in position 3 of the data buffer.

[0100] Since the data to be sent needs to be sent to three target directions TX1, TX2 and TX3, and data A is cached at position 3 in the data buffer, as shown in Figure 10(c), pointer 3 is pushed into the pointer queues of the three target directions TX1, TX2 and TX3, that is, pointer 3 is written to the last position in the pointer queues of the three target directions.

[0101] In this embodiment of the invention, the processing procedure for the received data to be sent is described in detail, as follows: Figure 11 As shown, Figure 11 This is a flowchart of a data transmission method based on an on-chip network according to an embodiment of the present invention, which specifically includes the following steps:

[0102] Step S1100: Receive the data to be sent.

[0103] Step S1101: Buffer the data to be sent into an empty data buffer unit in the data buffer, wherein the empty data buffer unit is located at any position in the data buffer.

[0104] Step S1102: Obtain the target direction marker of the data to be sent, determine the first pointer queue from at least two pointer queues based on the target direction marker, and push the pointer of the data to be sent into the first pointer queue, wherein the pointer is the position number of the data buffer unit of the data to be sent in the data buffer.

[0105] Furthermore, the number of the first pointer queue can be one or more. For non-multicast data, the pointer of the data only needs to be pushed into one pointer queue, and the number of the first pointer queue is one. For multicast data, that is, the data needs to be sent to multiple target directions, the pointer of the data is pushed into the pointer queues corresponding to the multiple target directions respectively, and the number of the first pointer queue is multiple.

[0106] In one possible implementation, when a direction buffer is added during data processing, a complete description is provided, as follows: Figure 12 As shown, Figure 12 This is a flowchart of a data transmission method based on an on-chip network according to an embodiment of the present invention, which specifically includes the following steps:

[0107] Step S1200: Receive the data to be sent.

[0108] Step S1201: Obtain the target direction marker of the data to be sent.

[0109] Step S1202: Buffer the data to be sent into an empty data buffer unit in the data buffer, wherein the empty data buffer unit is located at any position in the data buffer.

[0110] Step S1203: Save the target direction mark of the data to be sent to the direction buffer unit corresponding to the data buffer unit, wherein the direction buffer unit is an idle unit in the direction buffer.

[0111] Step S1204: Obtain the target direction marker of the data to be sent, determine the first pointer queue from at least two pointer queues based on the target direction marker, and push the pointer of the data to be sent into the first pointer queue, wherein the pointer is the position number of the data buffer unit of the data to be sent in the data buffer.

[0112] In one possible implementation, in response to the dequeueing of pointers from the pointer queue, such as Figure 13 As shown, it also includes the following steps:

[0113] Step S1205: Obtain the data to be sent from the data buffer according to the dequeue pointer.

[0114] In one possible implementation, such as Figure 14 As shown, the following steps are included after step S1205:

[0115] Step S1206: Send the data to be sent through the data output port in the target direction corresponding to the pointer queue.

[0116] In one possible implementation, such as Figure 15 As shown, in response to the dequeueing of a pointer from the pointer queue, step S1206 further includes the following steps:

[0117] Step S1207: Set the value of the target direction marker corresponding to the second pointer queue in the direction buffer unit to 0.

[0118] The second pointer queue is the pointer queue where the dequeued pointer is located.

[0119] Step S1208: In response to all values ​​in the target direction marker in the direction buffer unit being set to 0, the direction buffer unit is determined to be empty.

[0120] In one possible implementation, the data buffer unit corresponding to the direction buffer unit receives new data to be sent.

[0121] In one possible implementation, the direction buffer unit stores the target direction marker of the new data to be sent.

[0122] In one possible implementation, the method further includes:

[0123] Locate the direction buffer unit in the direction buffer where the target direction is marked as empty. Further, determine that the second data buffer unit is free, wherein the second data buffer unit is the data buffer unit corresponding to the direction buffer unit where the target direction is marked as empty.

[0124] In this embodiment of the invention, when implementing data multicast, when the data buffer receives data to be multicast, the data does not need to be copied multiple times. Instead, the target direction marker of the data to be sent is cached in the corresponding direction buffer. The direction buffer pushes the corresponding pointer into the pointer queue corresponding to the direction to be sent according to the target direction marker. When any data output port needs to output the data to be sent corresponding to the pointer, it only needs to look up the data in the data buffer according to the pointer. The data buffer and the direction buffer do not need to follow the first-in-first-out principle. As long as the pointer queue follows the first-in-first-out principle, the transmission order of the data to be sent is guaranteed.

[0125] In this embodiment of the invention, there is also a special case: when the pointer queue for any target direction is empty, but the RX data interface port has data to be sent in that target direction, a bypass path can be used. There is no need to cache the data to be sent in the data buffer, nor is there any need to process the direction buffer and the pointer queue accordingly.

[0126] Specifically, the straight-through principle includes the following three situations:

[0127] Scenario 1: If the data to be sent is non-multicast data, as long as the pointer queue corresponding to the target direction of the data to be sent is empty, that is, there is no need to wait for other prior data to be sent to the target direction, the data to be sent can be sent directly to the data output port without going through the data buffer. That is, for non-multicast data, if the pointer queue corresponding to its target direction is empty, the non-multicast data can take the straight-through path.

[0128] Scenario 2: If the data to be sent is multicast data, and if the data to be sent in any one target direction cannot be directly transmitted (b), then the data to be sent in other target directions also cannot be directly transmitted. That is, for multicast data, if the pointer queues corresponding to multiple target directions are all empty, then the multicast data can take a direct transmission path.

[0129] For example, if the direction[3:0] of the data to be sent is 4'b0011, it means that the data to be sent needs to be sent to the TX0 and TX1 directions. At this time, as long as the pointer queue of TX0 or TX1 is not empty, the data to be sent cannot be passed through in TX0 and TX1. It must enter the data buffer and then be scheduled before it can be sent to the corresponding target direction.

[0130] Scenario 3: When there is a direct path for data to be sent in a certain target direction, other data to be processed in other target directions still need to enter the data buffer and then be scheduled before being sent to the corresponding target direction. That is, for multiple pointer queues, when the data to be sent (multicast or non-multicast data) in the target direction corresponding to one or more pointer queues goes through the direct path, the remaining pointer queues can transmit data normally (i.e., the normally transmitted data does not go through the direct path).

[0131] This invention provides an integrated circuit, which includes multiple cores, an on-chip network, and a data transmission circuit based on the on-chip network.

[0132] This invention provides a board card that includes the integrated circuit.

[0133] This invention provides a server, which includes the aforementioned board.

[0134] As those skilled in the art will recognize, various aspects of the embodiments of the present invention can be implemented as a system, method, or computer program product. Therefore, various aspects of the embodiments of the present invention can take the form of a completely hardware implementation, a completely software implementation (including firmware, resident software, microcode, etc.), or an implementation combining software and hardware aspects, which may generally be referred to herein as a "circuit," "module," or "system." Furthermore, various aspects of the embodiments of the present invention can take the form of a computer program product implemented in one or more computer-readable media having computer-readable program code implemented thereon.

[0135] Any combination of one or more computer-readable media can be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, (but not limited to) an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination thereof. More specific examples (not an exhaustive list) of computer-readable storage media will include: an electrical connection having one or more wires, a portable computer floppy disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable optical disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the context of embodiments of the present invention, a computer-readable storage medium can be any tangible medium capable of containing or storing a program used by or in conjunction with an instruction execution system, device, or apparatus.

[0136] Computer-readable signal media may include propagated data signals having computer-readable program code implemented therein, such as in baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium that is not a computer-readable storage medium and can communicate, propagate, or transmit a program used by or in conjunction with an instruction execution system, device, or apparatus.

[0137] Program code implemented on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, fiber optic cable, RF, or any suitable combination thereof.

[0138] Computer program code for performing operations relating to various aspects of embodiments of the present invention can be written in any combination of one or more programming languages, including: object-oriented programming languages ​​such as Java, Smalltalk, C++, etc.; and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The program code can be executed as a standalone software package entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet provided by an Internet service provider).

[0139] The flowchart illustrations and / or block diagrams of the methods, apparatus (systems), and computer program products according to embodiments of the present invention describe various aspects of the embodiments of the present invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions (executed via the processor of the computer or other programmable data processing apparatus) create means for implementing the functions / actions specified in the flowchart and / or block diagram blocks or blocks.

[0140] These computer program instructions may also be stored in a computer-readable medium that can direct a computer, other programmable data processing apparatus or other means to operate in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing that includes instructions that implement the functions / actions specified in flowchart and / or block diagram blocks or blocks.

[0141] Computer program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operable steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide for implementing the functions / actions specified in flowchart and / or block diagram blocks or blocks.

[0142] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A data transmission circuit based on an on-chip network, characterized in that, The circuit includes: A data buffer, used to cache data to be sent received from the data receiving port, the data buffer comprising multiple data buffer units, and the data buffer connected to at least two pointer queues; A direction buffer includes multiple direction buffer units, each of which corresponds to a data buffer unit and is used to cache the target direction marker of the data to be sent in the data buffer unit. The target direction marker is used to indicate at least one target direction to which the data to be sent needs to be sent. At least two pointer queues, each pointer queue corresponding to a target direction, each pointer queue buffers pointers to data to be sent to its corresponding target direction, wherein each pointer queue corresponds to a target direction, and each pointer is buffered into at least one corresponding pointer queue according to the target direction mark corresponding to each pointer; The pointer is the position number of each data buffer unit in the data buffer, and the pointer is used to read the data to be sent from the data buffer unit in the data buffer.

2. The circuit as described in claim 1, characterized in that, The pointer queue is a first-in, first-out (FIFO) queue.

3. The circuit as described in claim 2, characterized in that, The direction buffer also includes a fast lookup circuit for finding direction buffer units in the direction buffer where the target direction mark is empty. The direction buffer units where the target direction mark is empty are used to write the target direction mark of the newly received data to be sent in the data buffer.

4. A method for data transmission based on an on-chip network, characterized in that, The method includes: Receive the data to be transmitted and the target direction marker of the data to be transmitted; The data to be sent is buffered into an empty data buffer unit in the data buffer, wherein the empty data buffer unit is located at any position in the data buffer; The target direction marker of the data to be sent is obtained. Based on the target direction marker, a first pointer queue is determined from at least two pointer queues. The pointer of the data to be sent is pushed into the first pointer queue. The pointer is the position number of the data buffer unit of the data to be sent in the data buffer. The target direction marker is used to indicate at least one target direction to which the data to be sent needs to be sent. Each pointer queue corresponds to one target direction. Each pointer queue buffers the pointers of the data to be sent to its corresponding target direction. The number of the first pointer queues is one or more.

5. The method as described in claim 4, characterized in that, The method also includes: The target direction marker of the data to be sent is saved to the direction buffer unit corresponding to the data buffer unit, wherein the direction buffer unit is an idle unit in the direction buffer.

6. The method as described in claim 5, characterized in that, The pointer queue is a first-in, first-out (FIFO) queue. In response to a pointer being dequeued from the pointer queue, the method further includes: According to the dequeue pointer, retrieve the data to be sent from the first data buffer unit; wherein, the first data buffer unit is the data buffer unit in the data buffer indicated by the dequeue pointer; Set the value of the target direction marker corresponding to the second pointer queue in the direction buffer unit corresponding to the first data buffer unit to 0, wherein the second pointer queue is the pointer queue where the dequeued pointer is located.

7. The method as described in claim 5 or 6, characterized in that, The method also includes: Locate the direction buffer cell in the direction buffer where the target direction is marked as empty; The second data buffer unit is determined to be free, wherein the second data buffer unit is the data buffer unit corresponding to the direction buffer unit marked as empty in the target direction.

8. An integrated circuit, characterized in that, The integrated circuit includes multiple cores, an on-chip network, and a data transmission circuit as described in any one of claims 1-3.

9. A board card, the board card including the integrated circuit as claimed in claim 8.

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