A smart configuration circuit for electronic module parameters
By using a combination of FPGA chip, EEPROM, and flash memory chip in the electronic module parameter configuration circuit, the interface modules and signal conditioning are enriched, solving the problems of poor interface adaptability and insufficient scalability of existing storage solutions. This achieves efficient and flexible parameter configuration and signal processing, improving the reliability and applicability of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- YIZHANG RENCHUANG ELECTRONIC TECHNOLOGY CO LTD
- Filing Date
- 2025-08-26
- Publication Date
- 2026-06-30
AI Technical Summary
Existing electronic module parameter configuration circuits suffer from poor interface compatibility and insufficient scalability of storage solutions, resulting in poor configuration flexibility, low storage resource utilization efficiency, and increased costs.
The circuit employs an FPGA chip as the main control module, combined with EEPROM and flash memory chip parameter storage modules, rich device interfaces and signal conditioning modules, enhancing the flexibility and scalability of the circuit. It also optimizes storage device switching through multiplexers and data buffers, and supports multiple interface protocols and functional expansions.
It achieves efficient and flexible parameter configuration, supports multiple interface protocols, improves storage resource utilization efficiency, simplifies the configuration process, is suitable for mobile devices and scenarios where wiring is inconvenient, and enhances signal acquisition accuracy and system reliability.
Smart Images
Figure CN224436889U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of electronic module parameter configuration circuit technology, specifically an intelligent configuration circuit for electronic module parameters. Background Technology
[0002] In modern electronic devices, especially industrial control, communication equipment, and IoT terminals, various functional modules are widely used. Before being put into use, these modules typically require configuration parameters to be written according to their specific application scenarios, hardware versions, or performance requirements. Therefore, a reliable, efficient, and flexible parameter configuration circuit is crucial for the production, debugging, and maintenance of electronic devices.
[0003] Currently, common electronic module parameter configuration circuits in existing technologies mainly adopt an architecture centered on a microcontroller unit (MCU) with an external parameter memory. This architecture has the following significant drawbacks:
[0004] The current parameter storage schemes are too simplistic and fail to meet the diverse storage requirements of different parameters. A single memory solution cannot simultaneously optimize for both frequent parameter modifications and large-scale data storage, resulting in poor configuration flexibility, low storage resource utilization efficiency, or increased costs.
[0005] The existing configuration circuits offer only one standard interface, such as UART or I2C. This necessitates additional conversion tools when dealing with host debugging devices that have different interfaces, such as USB and Ethernet. This increases the complexity of the configuration process, reduces configuration efficiency on the production line, and hinders convenient remote configuration and maintenance.
[0006] Circuit functions are fixed, resulting in poor expandability and flexibility. MCU-based solutions have fixed peripheral interfaces and functions at the time of chip selection, making it difficult to adapt to new interface protocols or add new monitoring functions through hardware upgrades.
[0007] Therefore, there is an urgent need in this field for a parameter configuration circuit that can solve the problems of poor interface adaptability and insufficient scalability of the above-mentioned storage solutions, thereby achieving efficient and flexible electronic module parameter configuration. Utility Model Content
[0008] To address the above problems, this utility model provides an intelligent configuration circuit for electronic module parameters, which solves the problems of poor interface adaptability and insufficient scalability of storage solutions.
[0009] To achieve the above objectives, the technical solution adopted by this utility model is as follows:
[0010] An intelligent configuration circuit for electronic module parameters includes:
[0011] The main control module uses an FPGA chip (U1); the parallel data ports D0~D7 of the FPGA chip (U1) are connected to the data ports D0~D7 of the EEPROM chip (U2) through the data bus DB1, and the address ports A0~A15 of the FPGA chip (U1) are connected to the address ports A0~A7 of the EEPROM chip (U2) through the address bus AB1.
[0012] The parameter storage module includes an EEPROM chip (U2) and a flash memory chip (U3); the chip select terminal CS1 of the EEPROM chip (U2) is connected to the first chip select port CS1 of the FPGA chip (U1), and the chip select terminal CS2 of the flash memory chip (U3) is connected to the second chip select port CS2 of the FPGA chip (U1).
[0013] The device interface module integrates a USB interface J1, an Ethernet interface J2, and a USB transceiver (U16). The differential signal lines of the USB interface J1 are connected to the differential signal terminals of the USB transceiver (U16). The UTMI interface data lines U1~U8 of the USB transceiver (U16) are connected to the USB control port USB1 of the FPGA chip (U1). The medium (U3) gateway interface signal lines MDC and MDIO of the Ethernet interface J2 are connected to the Ethernet control port ETH1 of the FPGA chip (U1).
[0014] The USB signal conditioning module consists of an operational amplifier (U4A) and a voltage comparator (U4B). The non-inverting and inverting inputs of the operational amplifier (U4A) are connected to the differential signal terminals DP and DM of the USB transceiver (U16), respectively, and the output terminal OUT1 is connected to the ADC port ADC1 of the FPGA chip (U1). The non-inverting input +IN of the voltage comparator (U4B) is connected to the reference voltage source Vref, the inverting input -IN is connected to the differential signal terminal DM of the USB transceiver (U16), and the output terminal OUT2 is connected to the general-purpose input port GPIO1 of the FPGA chip (U1).
[0015] The clock synchronization module has a built-in crystal oscillator Y1 and a phase-locked loop chip (U5); the output terminal of the crystal oscillator Y1 is connected to the reference clock input terminal CLK_IN of the phase-locked loop chip (U5), and the output terminal CLK_OUT of the phase-locked loop chip (U5) is connected to the global clock terminal GCLK of the FPGA chip (U1);
[0016] The anomaly detection module includes a window comparator (U10) and a watchdog chip (U1)1; the input terminal VIN of the window comparator (U10) is connected to the power monitoring point Vmon, and the output terminal ALARM is connected to the interrupt terminal INT of the FPGA chip (U1); the feed terminal WD_IN of the watchdog chip (U11) is connected to the timer output terminal TIMER_OUT of the FPGA chip (U1).
[0017] The power management module includes a linear regulator (U13) and a switching regulator (U14); the input terminal VIN1 of the linear regulator (U13) is connected to the external power supply VEXT, and the output terminal VOUT1 is connected to the core voltage terminal VCORE of the FPGA chip (U1); the input terminal VIN2 of the switching regulator (U14) is connected to the external power supply VEXT, and the output terminal VOUT2 is connected to the power supply terminal VCC_IO of the device interface module.
[0018] The current detection module includes a sampling resistor Rsense and an instrumentation amplifier (U17); the sampling resistor Rsense is connected in series in the input circuit of the external power supply VEXT, the input terminals +IN and -IN of the instrumentation amplifier (U17) are connected in parallel across the sampling resistor Rsense, and the output terminal OUT is connected to the second ADC port ADC2 of the FPGA chip (U1).
[0019] The beneficial effects of this technical solution are as follows: using FPGA as the main control core, its hardware programmable characteristics enable the circuit to flexibly implement complex parameter configuration, logic control and signal processing algorithms through software; EEPROM is suitable for storing key configuration parameters that need to be modified frequently, ensuring the non-volatility and reliability of data; flash memory provides a large capacity for storing firmware programs or historical data, taking into account the storage characteristics requirements of different parameters; rich and complete interfaces facilitate data interaction and remote configuration with the host computer.
[0020] As a further improvement to the above technical solution: the parameter storage module further includes a multiplexer (U6), the address input terminals SEL0 and SEL1 of the multiplexer (U6) are respectively connected to the general output ports GP1 and GP2 of the FPGA chip (U1), the first output terminal OUT1 is connected to the chip select terminal CS1 of the EEPROM chip (U2), and the second output terminal OUT2 is connected to the chip select terminal CS2 of the flash memory chip (U3).
[0021] The beneficial effects of this technical solution are: it allows the system to connect to more peripheral devices, while making the switching control of storage devices more flexible and efficient.
[0022] As a further improvement to the above technical solution: the EEPROM chip (U2) and the flash memory chip (U3) share the data bus DB1; the parameter storage module also includes a data buffer (U7), the data input terminals DI0~DI7 of the data buffer (U7) are connected to the data bus DB1, the data output terminals DO0~DO7 are connected to the data terminals D0~D7 of the flash memory chip (U3), and the enable terminal EN is connected to the status output terminal STAT of the multiplexer (U6).
[0023] The beneficial effects of this technical solution are: it eliminates the potential conflicts that may occur when EEPROM and flash memory chips share a data bus; the buffer plays an isolation and driving role, ensuring the stability and signal integrity of the data bus when switching between multiple devices.
[0024] As a further improvement to the above technical solution: the device interface module further includes a (U3) line communication unit, which includes a Bluetooth chip (U8) and an antenna ANT1; the radio frequency terminal RF of the Bluetooth chip U8 is connected to the antenna ANT1, the serial data transmitting terminal TXD is connected to the UART receiving port RX1 of the FPGA chip (U1), the serial data receiving terminal RXD is connected to the UART transmitting port TX1 of the FPGA chip (U1), and the power supply terminal VCC is connected to the output terminal VOUT2 of the switching regulator (U14).
[0025] The beneficial effects of this technical solution are: it frees configuration and debugging from the constraints of cables, making it more convenient and suitable for mobile devices or scenarios where wiring is inconvenient.
[0026] As a further improvement to the above technical solution: the USB signal conditioning module also includes a programmable gain amplifier (U9); the input terminals IN+ and IN- of the programmable gain amplifier (U9) are respectively connected to the differential signal terminals DP and DM of the USB transceiver (U16), the output terminal OUT is connected to the non-inverting input terminal of the operational amplifier (U4A), and the gain control terminals G0 and G1 are connected to the configuration port P2 of the FPGA chip (U1).
[0027] The beneficial effects of this technical solution are: it enables the FPGA to dynamically adjust the amplification factor according to the USB signal strength, so that the back-end ADC always works at the optimal range, significantly improving the dynamic range and accuracy of signal acquisition.
[0028] As a further improvement to the above technical solution: the clock synchronization module also includes a temperature compensation circuit; the temperature compensation circuit is composed of a thermistor RT1 and a compensation capacitor C1 connected in parallel, with its first end connected to the first frequency adjustment terminal TUNE1 of the crystal oscillator Y1 and its second end connected to the second frequency adjustment terminal TUNE2 of the crystal oscillator Y1.
[0029] The beneficial effect of this technical solution is that it compensates for the frequency drift of the crystal oscillator caused by changes in ambient temperature.
[0030] As a further improvement to the above technical solution: a clock divider (U15) is also provided between the clock synchronization module and the FPGA chip (U1); the input terminal CLK_IN of the clock divider (U15) is connected to the output terminal CLK_OUT of the phase-locked loop chip (U5), and the output terminal CLK_DIV is connected to the auxiliary clock terminal AUX_CLK of the FPGA chip (U1).
[0031] The beneficial effects of this technical solution are: it provides an independent auxiliary clock source with a different frequency for the FPGA. (U3) can generate a low-frequency clock by occupying the PLL resources inside the FPGA, which can be used for low-power standby, timing and other tasks.
[0032] As a further improvement to the above technical solution: the anomaly detection module also includes an optocoupler (U12); the anode of the light-emitting diode of the optocoupler (U12) is connected to the output terminal ALARM of the window comparator (U10) through a current-limiting resistor R2, and the cathode of the light-emitting diode is grounded; the open collector output terminal of the optocoupler (U12) is connected to the isolation interrupt terminal ISO_INT of the FPGA chip (U1), and is connected to the isolation power supply VISOSO2 through a pull-up resistor R3.
[0033] The beneficial effects of this technical solution are: preventing high voltage, ground wire noise, or surge impact from damaging the expensive main control chip.
[0034] As a further improvement to the above technical solution: the power management module also includes a current monitoring circuit; the current monitoring circuit includes a sampling resistor R4 and a differential amplifier (U18); the sampling resistor R4 is connected in series in the input VIN1 circuit of the linear regulator (U13); the non-inverting input and the inverting input of the differential amplifier (U18) are connected in parallel across the sampling resistor R4, and the output is connected to the third ADC port ADC3 of the FPGA chip (U1).
[0035] The beneficial effects of this technical solution are: it provides the system with the ability to calculate power consumption and detect anomalies such as load short circuits and power consumption surges, thereby enhancing the refinement and proactivity of power management.
[0036] As a further improvement to the above technical solution, a monitoring module is also included; the monitoring module adopts a power monitoring chip (U19), whose first voltage detection terminal VSENSE1 is connected to the output terminal VOUT1 of the linear regulator (U13), the second voltage detection terminal VSENSE2 is connected to the output terminal VOUT2 of the switching regulator (U14), and the reset output terminal RST is connected to the power-on reset terminal PORST of the FPGA chip (U1).
[0037] The beneficial effect of this technical solution is that it ensures the reliability of system startup and operation. Attached Figure Description
[0038] Figure 1 This is a block diagram showing the connection of the circuit modules;
[0039] Figure 2 This is a block diagram of the internal logic design for an FPGA. Detailed Implementation
[0040] To enable those skilled in the art to better understand the technical solution, the present invention will be described in detail below with reference to the embodiments. The description in this part is only exemplary and explanatory, and should not be used to limit the scope of protection of the present invention in any way.
[0041] Example 1:
[0042] This embodiment provides a basic implementation method for an intelligent configuration circuit for electronic module parameters.
[0043] The main control module uses an FPGA chip (U1) of model XC7A35T-1FTG256C. The eight-bit parallel data ports D0 to D7 of this chip are connected to the data ports D0 to D7 of the EEPROM chip (U2) of model AT28C256 in the parameter storage module via an eight-bit wide data bus DB1. The lower eight-bit address ports A0 to A7 of the FPGA chip (U1) are connected to the address ports A0 to A7 of the EEPROM chip (U2) via an address bus. The higher eight-bit address ports A8 to A15 of the FPGA chip (U1) are left floating.
[0044] The parameter storage module includes the aforementioned EEPROM chip (U2) and a W25Q128JVSIQ flash memory chip (U3). The chip select pin CS1 of the EEPROM chip (U2) is directly connected to the first chip select port CS1 of the FPGA chip (U1). The chip select pin CS2 of the flash memory chip (U3) is directly connected to the second chip select port CS2 of the FPGA chip (U1). The data pins D0 to D7 of the flash memory chip (U3) are connected to the eight general-purpose I / O ports P3 to P10 of the FPGA chip (U1) via a separate eight-bit data bus DB2.
[0045] The device interface module integrates a USB Type-B interface J1, an RJ45 Ethernet interface J2 (model HR911105A), and a USB transceiver (U16) (model USB3300). The differential signal lines D (positive) and D (negative) of the USB interface J1 are directly connected to the differential signal terminals DP and DM of the USB transceiver (U16). The eight-bit data lines of the UTMI+ interface of the USB transceiver (U16) are connected to the USB control port USB1 of the FPGA chip (U1). The media (U3) gateway signal lines MDC and MDIO of the Ethernet interface J2 are connected to the Ethernet control port ETH1 of the FPGA chip (U1).
[0046] The clock synchronization module integrates a 50 MHz crystal oscillator Y1 and a CDCE62005RGZR phase-locked loop (PLL) chip (U5). The output of crystal oscillator Y1 is connected to the reference clock input CLK_IN of the PLL chip (U5). The output CLK_OUT of the PLL chip (U5) outputs a 100 MHz clock signal, which is connected to the global clock input GCLK of the FPGA chip (U1).
[0047] The anomaly detection module includes a window comparator (U10) of model LM339DR and a watchdog chip (U11) of model MAX6816EUT-T. The input VIN of the window comparator (U10) is connected to a power monitoring point Vmon for monitoring a 3.3-volt I / O power supply. Its output ALARM is connected to the external interrupt input INT1 of the FPGA chip (U1). The feed signal input WDI of the watchdog chip (U11) is connected to the general purpose output port GPIO5 of the FPGA chip (U1). The timeout output RST of the watchdog chip (U11) is connected to the reset input RST of the FPGA chip (U1).
[0048] The power management module includes an AMS1117-1.0 linear regulator (U13) and an MP2359DJ-LF-Z switching regulator (U14). The linear regulator (U13) has its input VIN1 connected to an external 5.0-volt power supply VEXT, and its output VOUT1 outputs 1.0 volts, which is connected to the core voltage terminal VCORE of the FPGA chip (U1). The switching regulator (U14) has its input VIN2 connected to the external 5.0-volt power supply VEXT, and its output VOUT2 outputs 3.3 volts, which is connected to the power supply terminal VCC_IO of the device interface module.
[0049] The current sensing module includes a 0.005-ohm sampling resistor Rsense and an INA210AIDCKR differential amplifier (U17). The sampling resistor Rsense is connected in series in the loop between the output VOUT1 of the linear regulator (U13) and the VCORE terminal of the FPGA chip (U1). The non-inverting and inverting inputs of the differential amplifier (U17) are connected in parallel across the sampling resistor Rsense, and its output OUT is connected to the second ADC port ADC2 of the FPGA chip (U1).
[0050] Example 2:
[0051] This embodiment describes the parameter storage module and the device interface module based on embodiment 1.
[0052] The parameter storage module adds data sharing functionality. The EEPROM chip (U2) and flash memory chip (U3) share the data bus DB1. A single-channel dual-channel analog switch (U6), model SN74LVC1G3157DBVR, is added to the parameter storage module to control the chip select signal path of the EEPROM chip (U2). The common terminal of the analog switch (U6) is connected to the first chip select port CS1 of the FPGA chip (U1). The two independent channels of the analog switch (U6) are connected to the chip select terminals CS1 of the EEPROM chip (U2) and CS2 of the flash memory chip (U3), respectively. The channel selection terminal SEL of the analog switch (U6) is connected to the general-purpose output port GPIO6 of the FPGA chip (U1).
[0053] The parameter storage module also includes a bidirectional data buffer (U7) of model 74LVC245APW. The A-side bus (A0 to A7) of the data buffer (U7) is connected to the shared data bus DB1. The B-side bus (B0 to B7) of the data buffer (U7) is connected to the data terminals (D0 to D7) of the flash memory chip (U3). The output enable terminal (OE) of the data buffer (U7) is connected to the general-purpose output port GPIO7 of the FPGA chip (U1). The direction control terminal (DIR) of the data buffer (U7) is connected to the general-purpose output port GPIO8 of the FPGA chip (U1). When the FPGA accesses the EEPROM, GPIO7 outputs a high level, and the buffer (U7) is in a high-impedance state. When the FPGA accesses the Flash memory, GPIO7 outputs a low level to enable the buffer, and the data flow is controlled by the DIR terminal.
[0054] The device interface module adds a (U3) line communication unit. This unit contains a Bluetooth chip U8 (model CC2541F256RHAR) and a chip antenna ANT1 (model ANT-2.4-CW-HWR). The RF_OUT terminal of the Bluetooth chip (U8) is connected to the antenna ANT1 via a 10Ω resistor in series and a 2.2pF capacitor in parallel. Its serial data transmit terminal TXD is connected to the UART receive port UART1_RX of the FPGA chip (U1), and its serial data receive terminal RXD is connected to the UART transmit port UART1_TX of the FPGA chip (U1). The power supply terminal VCC of the Bluetooth chip (U8) is connected to the output terminal VOUT2 of the switching regulator (U1)4, and is powered by a 3.3-volt power supply.
[0055] Example 3
[0056] This embodiment describes the anomaly detection module, clock synchronization module, and power management module based on embodiment 1.
[0057] The anomaly detection module adds a TLP281-4(GB-TP) optocoupler (U12). The anode of the LED of the optocoupler (U12) is connected to the output terminal ALARM of the window comparator (U10) through a 1.0 kΩ current-limiting resistor R2, while the cathode of the LED is directly grounded. The open-collector output of the optocoupler (U12) is connected to the isolation interrupt input terminal ISO_INT of the FPGA chip (U1), and is connected to the 3.3-volt isolation power supply VISO output from an isolation power supply module of model B0505S-1WR2 through a 4.7 kΩ pull-up resistor R3.
[0058] A temperature compensation circuit is added to the clock synchronization module. This circuit consists of a 10 kΩ thermistor RT1 with a B value of 3950Ω and an NPO compensation capacitor C1 with a capacitance of 10 picofarads connected in parallel. The first terminal of this parallel network is connected to the first frequency adjustment terminal TUNE1 of the crystal oscillator Y1, and the second terminal is connected to the second frequency adjustment terminal TUNE2 of the crystal oscillator Y1.
[0059] The power management module adds an input current monitoring circuit. This circuit includes a 0.1-ohm sampling resistor R4 and a differential amplifier (U18) of model INA199A2DCKR. The sampling resistor R4 is connected in series in the input VIN1 circuit of the linear regulator (U13). The non-inverting and inverting inputs of the differential amplifier (U18) are connected in parallel across the sampling resistor R4, and its output OUT is connected to the third ADC port ADC3 of the FPGA chip (U1).
[0060] The circuit also includes a monitoring module. This module uses a power monitoring chip (U1)9, model MAX6746US46D3+T. Its first voltage detection terminal, VSENSE1, is connected to the output terminal VOUT1 of the linear regulator (U13) through a voltage divider network consisting of 10kΩ resistors R5 and R6, monitoring the 1.0V core voltage. Its second voltage detection terminal, VSENSE2, is connected to the output terminal VOUT2 of the switching regulator (U14) through a voltage divider network consisting of 20kΩ resistors R7 and R8, monitoring the 3.3V I / O voltage. The reset output terminal RST of the power monitoring chip (U19) is connected to the power-on reset terminal PORST of the FPGA chip (U1).
[0061] After the circuits in the three embodiments described above are powered on, the power management module first completes the startup and supplies power to each module. The monitoring module continuously monitors the core voltage and IO voltage, and releases a reset signal after the voltage stabilizes. The FPGA chip (U1) is released from the reset state and reads the configuration parameters from the EEPROM chip (U2) to complete its own initialization. After initialization, the main control module receives external configuration commands through the device interface module and reads, writes, verifies, and performs new operations on the device parameters in the parameter storage module according to the command content. The anomaly detection module monitors the power status throughout the process, the current detection module monitors the power consumption in real time, and the watchdog chip (U11) monitors the program running status, all working together to ensure the reliability and security of the configuration process.
[0062] It should be noted that, in this document, the terms "comprising," "including," and any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Specific examples have been used in this document to illustrate the principles and implementation methods of the present invention. These examples are merely for the purpose of helping to understand the method and core ideas of the present invention. The above descriptions are only preferred embodiments of the present invention. It should be pointed out that, due to the limitations of written expression and the objective existence of infinite specific structures, those skilled in the art can make several improvements, modifications, or variations without departing from the principles of the present invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, variations, or combinations, or the direct application of the concept and technical solution of the present invention to other situations without modification, should all be considered within the scope of protection of the present invention.
Claims
1. An intelligent configuration circuit for electronic module parameters, characterized in that, include: The main control module uses an FPGA chip (U1); the parallel data ports D0~D7 of the FPGA chip (U1) are connected to the data ports D0~D7 of the EEPROM chip (U2) through the data bus DB1, and the address ports A0~A15 of the FPGA chip (U1) are connected to the address ports A0~A7 of the EEPROM chip (U2) through the address bus AB1. The parameter storage module includes an EEPROM chip (U2) and a flash memory chip (U3); the chip select terminal CS1 of the EEPROM chip (U2) is connected to the first chip select port CS1 of the FPGA chip (U1), and the chip select terminal CS2 of the flash memory chip (U3) is connected to the second chip select port CS2 of the FPGA chip (U1). The device interface module integrates a USB interface J1, an Ethernet interface J2, and a USB transceiver (U16). The differential signal lines of the USB interface J1 are connected to the differential signal terminals of the USB transceiver (U16). The UTMI interface data lines U1~U8 of the USB transceiver (U16) are connected to the USB control port USB1 of the FPGA chip (U1). The medium (U3) gateway interface signal lines MDC and MDIO of the Ethernet interface J2 are connected to the Ethernet control port ETH1 of the FPGA chip (U1). The USB signal conditioning module consists of an operational amplifier (U4A) and a voltage comparator (U4B). The non-inverting and inverting inputs of the operational amplifier (U4A) are connected to the differential signal terminals DP and DM of the USB transceiver (U16), respectively, and the output terminal OUT1 is connected to the ADC port ADC1 of the FPGA chip (U1). The non-inverting input +IN of the voltage comparator (U4B) is connected to the reference voltage source Vref, the inverting input -IN is connected to the differential signal terminal DM of the USB transceiver (U16), and the output terminal OUT2 is connected to the general-purpose input port GPIO1 of the FPGA chip (U1). The clock synchronization module has a built-in crystal oscillator Y1 and a phase-locked loop chip (U5); the output terminal of the crystal oscillator Y1 is connected to the reference clock input terminal CLK_IN of the phase-locked loop chip (U5), and the output terminal CLK_OUT of the phase-locked loop chip (U5) is connected to the global clock terminal GCLK of the FPGA chip (U1); The anomaly detection module includes a window comparator (U10) and a watchdog chip (U1)1; the input terminal VIN of the window comparator (U10) is connected to the power monitoring point Vmon, and the output terminal ALARM is connected to the interrupt terminal INT of the FPGA chip (U1); the feed terminal WD_IN of the watchdog chip (U11) is connected to the timer output terminal TIMER_OUT of the FPGA chip (U1). The power management module includes a linear regulator (U13) and a switching regulator (U14); the input terminal VIN1 of the linear regulator (U13) is connected to the external power supply VEXT, and the output terminal VOUT1 is connected to the core voltage terminal VCORE of the FPGA chip (U1); the input terminal VIN2 of the switching regulator (U14) is connected to the external power supply VEXT, and the output terminal VOUT2 is connected to the power supply terminal VCC_IO of the device interface module. The current detection module includes a sampling resistor Rsense and an instrumentation amplifier (U17); the sampling resistor Rsense is connected in series in the input circuit of the external power supply VEXT, the input terminals +IN and -IN of the instrumentation amplifier (U17) are connected in parallel across the sampling resistor Rsense, and the output terminal OUT is connected to the second ADC port ADC2 of the FPGA chip (U1).
2. The intelligent configuration circuit for electronic module parameters according to claim 1, characterized in that, The parameter storage module also includes a multiplexer (U6). The address input terminals SEL0 and SEL1 of the multiplexer (U6) are connected to the general output ports GP1 and GP2 of the FPGA chip (U1), respectively. The first output terminal OUT1 is connected to the chip select terminal CS1 of the EEPROM chip (U2), and the second output terminal OUT2 is connected to the chip select terminal CS2 of the flash memory chip (U3).
3. The intelligent configuration circuit for electronic module parameters according to claim 1, characterized in that, The EEPROM chip (U2) and the flash memory chip (U3) share the data bus DB1; the parameter storage module also includes a data buffer (U7), the data input terminals DI0~DI7 of the data buffer (U7) are connected to the data bus DB1, the data output terminals DO0~DO7 are connected to the data terminals D0~D7 of the flash memory chip (U3), and the enable terminal EN is connected to the status output terminal STAT of the multiplexer (U6).
4. The intelligent configuration circuit for electronic module parameters according to claim 1, characterized in that, The device interface module also includes a (U3) line communication unit, which includes a Bluetooth chip U8 and an antenna ANT1. The radio frequency (RF) terminal of the Bluetooth chip (U8) is connected to the antenna ANT1, the serial data transmission terminal (TXD) is connected to the UART receiving port (RX1) of the FPGA chip (U1), the serial data receiving terminal (RXD) is connected to the UART transmitting port (TX1) of the FPGA chip (U1), and the power supply terminal (VCC) is connected to the output terminal (VOUT2) of the switching regulator (U14).
5. The intelligent configuration circuit for electronic module parameters according to claim 1, characterized in that, The USB signal conditioning module also includes a programmable gain amplifier (U9); the input terminals IN+ and IN- of the programmable gain amplifier (U9) are connected to the differential signal terminals DP and DM of the USB transceiver (U16) respectively, the output terminal OUT is connected to the non-inverting input terminal of the operational amplifier (U4A), and the gain control terminals G0 and G1 are connected to the configuration port P2 of the FPGA chip (U1).
6. The intelligent configuration circuit for electronic module parameters according to claim 1, characterized in that, The clock synchronization module also includes a temperature compensation circuit; the temperature compensation circuit is composed of a thermistor RT1 and a compensation capacitor C1 connected in parallel, with its first end connected to the first frequency adjustment terminal TUNE1 of the crystal oscillator Y1 and its second end connected to the second frequency adjustment terminal TUNE2 of the crystal oscillator Y1.
7. The intelligent configuration circuit for electronic module parameters according to claim 1, characterized in that, A clock divider (U15) is also provided between the clock synchronization module and the FPGA chip (U1); the input terminal CLK_IN of the clock divider (U15) is connected to the output terminal CLK_OUT of the phase-locked loop chip (U5), and the output terminal CLK_DIV is connected to the auxiliary clock terminal AUX_CLK of the FPGA chip (U1).
8. The intelligent configuration circuit for electronic module parameters according to claim 1, characterized in that, The anomaly detection module also includes an optocoupler (U12); the anode of the light-emitting diode of the optocoupler (U12) is connected to the output terminal ALARM of the window comparator (U10) through a current-limiting resistor R2, and the cathode of the light-emitting diode is grounded; the open collector output terminal of the optocoupler (U12) is connected to the isolation interrupt terminal ISO_INT of the FPGA chip (U1), and is connected to the isolation power supply VISOSO2 through a pull-up resistor R3.
9. The intelligent configuration circuit for electronic module parameters according to claim 1, characterized in that, The power management module also includes a current monitoring circuit; the current monitoring circuit includes a sampling resistor R4 and a differential amplifier (U18); the sampling resistor R4 is connected in series in the input VIN1 circuit of the linear regulator (U13); the non-inverting input and the inverting input of the differential amplifier (U18) are connected in parallel across the sampling resistor R4, and the output is connected to the third ADC port ADC3 of the FPGA chip (U1).
10. The intelligent configuration circuit for electronic module parameters according to claim 1, characterized in that, It also includes a monitoring module; the monitoring module uses a power monitoring chip (U19), whose first voltage detection terminal VSENSE1 is connected to the output terminal VOUT1 of the linear regulator (U13), the second voltage detection terminal VSENSE2 is connected to the output terminal VOUT2 of the switching regulator (U14), and the reset output terminal RST is connected to the power-on reset terminal PORST of the FPGA chip (U1).