Array substrate and display panel

Abstract

The present disclosure relates to the field of display technologies, and particularly to an array substrate and a display panel, which are used to optimize the encapsulation effect of a display device and extend the service life. Among them, the array substrate includes a substrate; a gate driving circuit and a plurality of control signal lines disposed on the substrate and located in the peripheral region, and the plurality of control signal lines are electrically connected to the gate driving circuit; each of at least one of the control signal lines is provided with at least one break; at least one connecting pattern, each connecting pattern corresponding to a break and being electrically connected to both ends of the control signal line provided with the break at the break; the orthographic projection of the connecting pattern on the substrate is staggeredly arranged with the orthographic projection of the corresponding break on the substrate. The above array substrate increases the area through which UV light can penetrate in the region where the plurality of control signal lines are located, thereby enhancing the curing degree of the sealant corresponding to the positions of the plurality of control signal lines, and thus optimizing the encapsulation effect of the display device.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to an array substrate and a display panel. Background Art

[0002] With the continuous development of electronic products, the requirements for the refresh rate of display devices are getting higher and higher. For example, for display devices adopting Touch and Display Driver Integration (TDDI) technology, a high refresh rate has become a new benchmark for improving the competitiveness of TDDI products. To increase the refresh rate, it is necessary to reduce the load of the gate driving circuit, and increasing the number of control signal lines electrically connected to the gate driving circuit is a way to reduce the load of the gate driving circuit.

[0003] However, if the distance between adjacent two clock control signal lines remains unchanged, as the number of control signal lines increases, the border size of the display device will become larger, which does not meet the current demand for narrow borders of electronic products. If the border size of the display device remains unchanged, as the number of control signal lines increases, the yield of the electronic product will decrease and the service life will be shortened. Summary of the Invention

[0004] Embodiments of the present disclosure provide an array substrate and a display panel, aiming to increase the area available for UV light (ultraviolet light) to penetrate in the area where multiple control signal lines are located on the premise of meeting the narrow border requirement, thereby enhancing the curing degree of the sealant corresponding to the positions of the multiple control signal lines, optimizing the encapsulation effect of the display panel, extending the service life, and improving the product yield.

[0005] To achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, an array substrate is provided, which has a display area and a peripheral area. The array substrate includes a substrate, a gate driving circuit, multiple control signal lines, and at least one connection pattern.

[0007] Wherein, the gate driving circuit and the multiple control signal lines are disposed on the substrate and located in the peripheral area, and the multiple control signal lines are electrically connected to the gate driving circuit. The multiple control signal lines are arranged in parallel along a first direction, and each control signal line extends along a second direction, and the first direction and the second direction intersect; each of at least one control signal line is provided with at least one break.

[0008] Each connection pattern corresponds to a break and is electrically connected to both ends of the control signal line with the break at the break. The orthographic projection of the connection pattern on the substrate is staggeredly arranged with the orthographic projection of the corresponding break on the substrate, and the orthographic projection of the connection pattern on the substrate at least partially overlaps with the orthographic projection of the set control signal line on the substrate. The set control signal line is one of the other control signal lines among the multiple control signal lines except the control signal line electrically connected to the connection pattern.

[0009] In some embodiments, the control signal line electrically connected to the connection pattern is adjacent to the set control signal line.

[0010] In some embodiments, along the first direction, the part of the set control signal line corresponding to the connection pattern is continuous.

[0011] In some embodiments, the connection pattern includes a first connection part and two second connection parts. The orthographic projection of the first connection part on the substrate overlaps with the orthographic projection of the set control signal line on the substrate. The two second connection parts are respectively arranged on both sides of the first connection part and are both electrically connected to the first connection part; one of the two second connection parts is electrically connected to one end of the control signal line with the break at the break, and the other of the two second connection parts is electrically connected to the other end of the control signal line with the break at the break.

[0012] In some embodiments, the dimension of the first connection part along the first direction is less than or equal to the width of the set control signal line; and / or, the dimension of the first connection part along the second direction is equal to the sum of the dimensions of the break and the two second connection parts along the second direction.

[0013] In some embodiments, the array substrate includes a gate conductive layer, a first insulating layer, and a source-drain conductive layer sequentially stacked on the substrate, and a first via is provided in the first insulating layer. The multiple control signal lines are provided on the gate conductive layer, and the at least one connection pattern is provided on the source-drain conductive layer. Each connection pattern passes through the first via and is electrically connected to the end of the control signal line with the break at the break.

[0014] In some embodiments, the array substrate includes a gate conductive layer, a first insulating layer, a source-drain conductive layer, a second insulating layer, and a first electrode layer that are sequentially stacked on the substrate. A second via hole penetrating through the first insulating layer and the second insulating layer is provided in the first insulating layer and the second insulating layer, and a third via hole is provided in the second insulating layer. The plurality of control signal lines are provided on the gate conductive layer, and the at least one connection pattern is provided on the source-drain conductive layer. The array substrate further includes at least one auxiliary connection pattern provided on the first electrode layer; each auxiliary connection pattern passes through the second via hole and is electrically connected to the end of the control signal line with a break at the break, and also passes through the third via hole and is electrically connected to the connection pattern.

[0015] In some embodiments, the gate driving circuit includes a plurality of shift registers arranged in parallel and cascaded along a second direction. Each control signal line includes a plurality of signal line segments arranged in parallel and sequentially electrically connected along the second direction. Along a first direction, each signal line segment corresponds to a shift register; among the control signal lines with breaks, at least one signal line segment has at least one break.

[0016] In some embodiments, among the control signal lines with breaks, each signal line segment has one break.

[0017] In some embodiments, the size of the break along the second direction is H, where L is the length of the signal line segment, y% is the target increased light transmittance of the periodic region where the signal line segment is located, and x% is the reference light transmittance of the periodic region when the control signal line is not designed with a break. The size of the periodic region along the first direction is the sum of the size of a signal line segment corresponding to a shift register along the first direction and the size of the gap between two adjacent signal line segments along the first direction; the size of the periodic region along the second direction is L.

[0018] In some embodiments, at least two control signal lines are provided with breaks; the breaks corresponding to the same shift register and belonging to different control signal lines are staggered from each other in the second direction.

[0019] In some embodiments, the array substrate further includes at least one auxiliary line. The at least one auxiliary line is made of the same material as the at least one connection pattern and is provided in the same layer; the auxiliary line extends along the first direction, and one end of the auxiliary line is electrically connected to the connection pattern, and the other end is electrically connected to the shift register corresponding to the signal line segment electrically connected to the connection pattern.

[0020] In some embodiments, each control signal line is provided with at least one break.

[0021] In some embodiments, the at least one control signal line is provided with a plurality of breaks. In the same control signal line, the distance between the centers of two adjacent breaks along the second direction is equal, and / or the sizes of the plurality of breaks along the second direction are equal.

[0022] On the other hand, a display panel is provided, including the array substrate according to any one of the above embodiments.

[0023] The array substrate and the display panel provided by the embodiments of the present disclosure have the following beneficial effects:

[0024] By providing breaks on the control signal line electrically connected to the gate driving circuit and providing connection patterns at the breaks, the disconnected control signal lines are electrically connected by the connection patterns; at the same time, the connection patterns at both ends of the break of the connected control signal line overlap with other control signal lines. For the control signal line provided with a break, this is equivalent to moving a part of the signal line above (or below) other control signal lines on the premise of ensuring the signal path of this signal line, thereby reducing the light-shielding area of the control signal line. That is, the area available for UV light to pass through in the peripheral area where multiple control signal lines are located is increased, which is beneficial to enhancing the curing effect of the sealant corresponding to the position of the control signal line, thereby optimizing the encapsulation effect of the display panel, extending the service life of the display panel, and improving the product yield. Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual sizes of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present disclosure.

[0026] Figure 1 It is a top view of a display device provided according to some embodiments;

[0027] Figure 2 It is along Figure 1 A cross-sectional view taken along the section line AA' in

[0028] Figure 3 It is a driving architecture diagram of an array substrate provided according to some embodiments;

[0029] Figure 4 It is Figure 3 An equivalent circuit diagram corresponding to the area within the dashed box M in

[0030] Figure 5 It is along Figure 1Another cross-sectional view of the hatching line AA' in

[0031] Figure 6 is Figure 4 A structural diagram corresponding to the area where the dashed box N is located in

[0032] Figure 7 is Figure 4 Another structural diagram corresponding to the area where the dashed box N is located in

[0033] Figure 8 is Figure 4 Another structural diagram corresponding to the area where the dashed box N is located in

[0034] Figure 9 is Figure 4 Another structural diagram corresponding to the area where the dashed box N is located in

[0035] Figure 10 is Figure 9 An enlarged view corresponding to the area where the dashed box Q is located in

[0036] Figure 11 is Figure 9 Another enlarged view corresponding to the area where the dashed box Q is located in

[0037] Figure 12 A top view of an array substrate provided according to some embodiments;

[0038] Figure 13 is Figure 12 A structural diagram corresponding to the area where the dashed box E is located in

[0039] Figure 14 is Figure 12 Another structural diagram corresponding to the area where the dashed box E is located in

[0040] Figure 15 is along Figure 10 A cross-sectional view of the hatching line BB' in

[0041] Figure 16 is along Figure 11 A cross-sectional view of the hatching line CC' in

[0042] Figure 17 Another top view of an array substrate provided according to some embodiments. Detailed implementation manners

[0043] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided by the present disclosure fall within the scope of protection of the present disclosure.

[0044] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", are interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example", or "some examples", etc. are intended to indicate that the specific features, structures, materials, or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any suitable manner.

[0045] When describing some embodiments, the expressions "electrically connected" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "point connection" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0046] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0047] As used herein, "approximate" or "substantially" includes the stated value and the average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system).

[0048] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0049] Figure 1 The top view structure of a display device 100 is shown. As Figure 1 shown, some embodiments of the present disclosure provide a display device 100, which may be any device that displays images whether moving (e.g., video) or stationary (e.g., still images) and whether text or not. More specifically, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rear view cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Figure 1 In the following, the display device 100 is taken as an example of a mobile phone for illustration.

[0050] The display device 100 includes a display panel 200, which may be a liquid crystal display panel (Liquid Crystal Display, abbreviated as LCD).

[0051] Figure 2 Shown is Figure 1 the cross-sectional structure of the display panel 200 in the cross-section line AA'. As Figure 2 shown, the display panel 200 is an LCD display panel, and the display panel 200 includes an array substrate 300, a counter substrate 400, and a liquid crystal layer 500 disposed between the array substrate 300 and the counter substrate 400. The array substrate 300 and the counter substrate 400 are bonded together by a sealing glue 600 in a cell manner, thereby defining the liquid crystal layer 500 within the region surrounded by the sealing glue 600. The sealing glue 600 is disposed in the peripheral region of the array substrate 300 (refer toFigure 3 the area indicated by reference numeral S in

[0052] Among them, in some embodiments, the counter substrate 400 includes a color filter layer 401. In this case, the counter substrate 400 can also be referred to as a color filter substrate (abbreviated as CF). Among them, the color filter layer 401 at least includes a red photoresist unit, a green photoresist unit, and a blue photoresist unit. The red photoresist unit, the green photoresist unit, and the blue photoresist unit are respectively directly opposite to the sub-pixels on the array substrate 300. The counter substrate 400 further includes a black matrix pattern 402, and the black matrix pattern 402 is used to separate the red photoresist unit, the green photoresist unit, and the blue photoresist unit. The color filter layer 401 and the black matrix pattern 402 are disposed on the substrate 403.

[0053] The array substrate 300 includes a substrate 1 and a circuit layer 301 disposed on the substrate 1. A plurality of sub-pixels are provided in the circuit layer 301. As Figure 2 shown, each sub-pixel is provided with a thin film transistor 302 and a pixel electrode 303. The thin film transistor 302 includes a source Sc, a drain Dr, a gate Gt, an active layer ACT, and a gate insulating layer GI. The source Sc and the drain Dr are respectively in contact with the active layer ACT; the pixel electrode 303 is electrically connected to the drain Dr of the thin film transistor 302. Among them, the film layer where the source Sc and the drain Dr are located is the source-drain conductive layer, the film layer where the gate Gt is located is the gate conductive layer, and the film layer where the pixel electrode 303 is located is the first electrode layer. The gate conductive layer is insulated from the source-drain conductive layer by the gate insulating layer GI, and the source-drain conductive layer is insulated from the first electrode layer by a passivation layer PVX.

[0054] It should be noted that Figure 2 in the figure, the thin film transistor 302 is taken as an example of a bottom-gate thin film transistor for illustration. In some other embodiments, the thin film transistor can be a top-gate thin film transistor. In this case, the gate of the thin film transistor is located on the side of the active layer away from the substrate, and a gate insulating layer is provided between the active layer and the gate conductive layer where the gate is located, and an interlayer dielectric layer (ILD) is provided between the gate conductive layer and the source-drain conductive layer where the source and the drain are located.

[0055] In some embodiments, as Figure 2 shown, the circuit layer 301 further includes a common electrode 304. The pixel electrode 303 and the common electrode 304 can be disposed on the same layer. In this case, both the pixel electrode 303 and the common electrode 304 are comb structures including a plurality of strip-shaped sub-electrodes. The pixel electrode 303 and the common electrode 304 can also be disposed on different layers. In this case, as Figure 2 shown, an insulating layer 305 is provided between the pixel electrode 303 and the common electrode 304. Figure 2Figure 0 schematically shows the pixel electrode 303 being closer to the substrate 1 relative to the common electrode 304. In some other embodiments, the pixel electrode may also be disposed away from the substrate relative to the common electrode.

[0056] In addition, as Figure 2 shown, the display panel 200 may further include a first polarizer 700 disposed on a side of the counter substrate 400 away from the liquid crystal layer 500, and a second polarizer 800 disposed on a side of the array substrate 300 away from the liquid crystal layer 500.

[0057] Figure 3 Figure 9 shows the driving architecture of the array substrate 300. As Figure 3 shown, the above-mentioned array substrate 300 includes: a display area (active area, AA; abbreviated as AA area; also referred to as the effective display area) and a peripheral area S disposed around the AA area in a circle.

[0058] Among them, the array substrate 300 is provided with sub-pixels (sub pixel) P of multiple colors in the AA area. The sub-pixels of the multiple colors may at least include a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel. The first color, the second color, and the third color are the three primary colors (for example, red, green, and blue).

[0059] For the convenience of description, in the present disclosure, the above-mentioned multiple sub-pixels P are described by taking the arrangement in a matrix form as an example. In this case, the sub-pixels P arranged in a row along the horizontal direction are called the same row of sub-pixels; the sub-pixels P arranged in a row along the vertical direction Y are called the same column of sub-pixels. A row of sub-pixels can be connected to a gate line GL, and a column of sub-pixels can be connected to a data line DL.

[0060] Figure 4 Figure 21 shows Figure 3 the equivalent circuit diagram within the area shown by the dashed box M in Figure 23. As Figure 4 shown, in the AA area, a pixel circuit (also referred to as a pixel driving circuit) is provided in each sub-pixel P. The pixel circuit includes a thin film transistor 302 and a capacitor C. Two electrodes of the capacitor C can be respectively constituted by the pixel electrode 303 and the common electrode 304 (as Figure 2 shown). The gate of the thin film transistor 302 is connected to the gate line GL, the source is connected to the data line DL, and the drain is connected to the capacitor C, for transmitting the data signal on the data line DL to the capacitor C. The gates of the thin film transistors 302 of the pixel circuits in the same row are connected to the same gate line GL, and the sources of the thin film transistors 302 of the pixel circuits in the same column are connected to the same data line DL.

[0061] It should be noted that Figure 4Only one pixel circuit including a thin-film transistor and a capacitor is taken as an example for illustration; in other embodiments, a pixel circuit may include multiple thin-film transistors and one capacitor; or, a pixel circuit may include multiple thin-film transistors and multiple capacitors.

[0062] As Figure 3 shown, a gate driving circuit G and a data driving circuit D are provided in the peripheral area S of the array substrate 300. Among them, the gate driving circuit G is electrically connected to the sub-pixels P through gate lines GL, and the data driving circuit D is electrically connected to the sub-pixels P through data lines DL to drive the sub-pixels P in the AA area for display.

[0063] It should be noted that Figure 3 only the case where the data driving circuit D is provided on the substrate 1 is taken as an example for illustration. In some other embodiments, the data driving circuit D may be provided on the circuit board of the display device 100.

[0064] Optionally, the above-mentioned gate driving circuit G may be a GOA (Gate Driver on Array) circuit, that is, the above-mentioned gate driving circuit G is directly integrated in the array substrate 300 of the display panel 200.

[0065] It should be noted that Figure 3 only for illustration, taking the gate driving circuit G being provided on one side of the peripheral area S of the array substrate 300, that is, single-sided driving, as an example. Optionally, the gate driving circuit G may be provided on two sides along the horizontal direction (such as Figure 3 the direction X in) of the peripheral area S of the array substrate 300 respectively. The pixel circuits are driven row by row in sequence from both sides by the two gate driving circuits G simultaneously, that is, double-sided driving. Optionally, the gate driving circuit G may be provided on two sides along the horizontal direction of the peripheral area S of the array substrate 300 respectively. The pixel circuits are driven row by row in sequence from both sides alternately by the two gate driving circuits G, that is, cross driving. The following embodiments of the present disclosure are all described taking the single-sided driving of the gate driving circuit G as an example.

[0066] As Figure 4 shown, the gate driving circuit G includes shift registers (RS1, RS2... RS N ) arranged in parallel along the second direction Y and cascaded in N stages. In this case, in some embodiments, the display panel 200 includes shift registers (RS1, RS2... RS N ) cascaded in N stages, which are respectively connected to N gate lines (GL1, GL2... GL N ) in the pixel circuit one by one, where N is a positive integer.

[0067] Optionally, the shift register is further provided with a signal input terminal I and a signal output terminal O. Among them, the signal input terminal I of the initial one or more stages of the shift register (such as Figure 4 RS1 in

[0068] is) is connected to the start signal terminal STV. In addition, the signal input terminal I of any other stage of the shift register is connected to the signal output terminal O of the shift register located in its previous stage.

[0068] As Figure 4 shown, the array substrate 300 further includes a plurality of control signal lines 2 electrically connected to the gate driving circuit G. The plurality of control signal lines 2 are arranged in parallel along the first direction X, and each control signal line 2 extends along the second direction Y.

[0069] In an optional embodiment, the first direction X and the second direction Y are arranged crosswise. For example, the first direction X and the second direction Y may be perpendicular to each other. For example, the first direction X may be the horizontal direction of the display device 100, and the second direction Y may be the vertical direction of the display device 100; or, the first direction X may be the horizontal direction of the display device 100, and the second direction Y may be the vertical direction of the display device 100; or, the first direction X may be the row direction in which the sub-pixels P of the display device 100 are arranged, and the second direction Y may be the column direction in which the sub-pixels P of the display device 100 are arranged.

[0070] It should be noted that in the multiple drawings of the present disclosure, only the case where the first direction X is the row direction in which the sub-pixels P are arranged and the second direction Y is the column direction in which the sub-pixels P are arranged is taken as an example for illustration. In the present disclosure, the technical solutions obtained by rotating the drawings by 90 degrees are also within the protection scope of the present disclosure.

[0071] In some embodiments, the control signal line 2 includes at least one of a clock signal line (CLK), a high voltage signal line (VGH), a low voltage signal line (VGL), and a start signal line (STV). Among them, the clock signal line is used to transmit a clock signal to the gate driving circuit G, the high voltage signal line and the low voltage signal line respectively transmit a high level voltage signal and a low level voltage signal to the gate driving circuit G, and the start signal line is used to transmit a start signal to the signal input terminal I of the initial one or more stages of the shift register in the gate driving circuit G.

[0072] Exemplarily, the array substrate 300 includes a plurality of clock signal lines, and the clock signal lines may appear in pairs. For example, the array substrate 300 includes clock signal lines CLKA and CLKB at the same time, and the two respectively transmit a pair of clock signals Clka and Clkb that are substantially opposite in time sequence. Thus, the array substrate 300 includes at least one pair of clock signal lines as described above. Hereinafter, the control signal line 2 for which the break design is performed may be one or more of the plurality of clock signal lines.

[0073] In some embodiments, as Figure 4 shown, each control signal line 2 is electrically connected to the gate driving circuit G. Optionally, along the first direction X, each control signal line 2 is simultaneously electrically connected to a plurality of shift registers arranged in parallel along the second direction Y, so as to transmit the signal corresponding to each control signal line 2 to each shift register.

[0074] In the manufacturing process of the display panel 200, it is necessary to cure the sealant 600 located between the array substrate 300 and the counter substrate 400 to achieve effective bonding between the array substrate 300 and the counter substrate 400. During the curing process of the sealant 600, the sealant 600 has been coated between the array substrate 300 and the counter substrate 400, and the curing of the sealant requires light (such as UV light) to irradiate the sealant 600 from the side of the array substrate 300. Therefore, the UV light must pass through the array substrate 300 to irradiate the sealant 600.

[0075] Figure 5 For Figure 1 a cross-sectional view along the section line AA' in Figure 5 which shows the process of curing the sealant 600 in the display panel 200 under UV light irradiation, Figure 5 the third direction Z in

[0076] is the irradiation direction of the UV light. As

[0077] shown, the position where the control signal line 2 is located corresponds to the position where the sealant 600 is located. In the curing process of the sealant 600, the UV light irradiates the sealant 600 through the gaps between the plurality of control signal lines 2, thereby achieving curing.

[0078] Therefore, the size of the gap between adjacent control signal lines 2 has a great influence on the curing effect of the sealant 600. On the premise of keeping the display panel 200 meeting the narrow border requirement, as the number of control signal lines 2 increases, the gap between adjacent control signal lines 2 will become narrower, which will lead to a decrease in the transmittance of the UV light (ultraviolet light) that needs to pass through the gap between adjacent control signal lines, resulting in incomplete curing of the sealant 600, reducing the bonding effect between the array substrate 300 and the counter substrate 400, affecting the service life of the display panel 200, and reducing the product yield of the display panel 200. Figure 6 、 Figure 7 、 Figure 8 and Figure 9As shown, in some embodiments, the array substrate 300 includes a plurality of control signal lines 2 and at least one connection pattern 3. Each of at least one control signal line 2 is provided with at least one break K; each connection pattern 3 corresponds to a break K and is electrically connected to both ends of the control signal line 2 provided with the break K at the break K; the orthographic projection of the connection pattern 3 on the substrate 1 is staggeredly arranged with the orthographic projection of the corresponding break K on the substrate 1, and the orthographic projection of the connection pattern 3 on the substrate 1 at least partially overlaps with the orthographic projection of the set control signal line 20 on the substrate 1.

[0079] Wherein, the set control signal line 20 is one of the other control signal lines 2 among the plurality of control signal lines 2 except the control signal line 2 electrically connected by the connection pattern 3.

[0080] The control signal line 2 is disconnected through the break K, and the two disconnected parts are electrically connected through the connection pattern 3. Therefore, each break K corresponds to and is electrically connected to a connection pattern 3. The connection pattern 3 and the break K are staggeredly arranged, so that the break K is exposed for the UV light to pass through, increasing the UV light irradiation area received by the sealant 600 and optimizing the curing effect of the sealant 600.

[0081] In order to stagger the connection pattern 3 and the break K, at least a part of the connection pattern 3 overlaps and is insulated from any other control signal line 2 except the control signal line 2 electrically connected to the connection pattern 3, and the control signal line 2 that overlaps and is insulated from the connection pattern 3 is the set control signal line 20. The connection pattern 3 overlaps and is insulated from the set control signal line 20, so that on the premise of ensuring the electrical connection of the two disconnected parts of the control signal line 2, the connection pattern 3 is arranged above or below the existing light-shielding component (set control signal line 20), avoiding the connection pattern 3 from increasing the light-shielding area, thereby further increasing the transmittance of the UV light and realizing the full curing of the sealant 600.

[0082] In an exemplary embodiment, the connection pattern 3 and the control signal line 2 are in different film layers, and the connection pattern 3 and its corresponding control signal line 2 are electrically connected through a via hole, and an insulating layer is provided between the connection pattern 3 and its corresponding set control signal line 20.

[0083] In an exemplary embodiment, the part where the set control signal line 20 overlaps and is insulated from the connection pattern 3 is continuous, that is, the part where the set control signal line 20 overlaps and is insulated from the connection pattern 3 is not provided with a break K. For example, when the set control signal line 20 is also provided with a break K, the break K is staggeredly arranged with the part where the set control signal line 20 overlaps and is insulated from the connection pattern 3, avoiding the connection pattern 3 from blocking the break K on the set control signal line 20.

[0084] Such as Figures 6 - 8As shown, in an exemplary embodiment, at least one break K is provided on each control signal line 2. In this way, the light transmission area of a certain amount of UV light can be increased for each control signal line 2, which is beneficial to further improving the light transmittance of the peripheral area S where the control signal line 2 is located, so as to ensure the sufficient curing of the sealant 600, enhance the bonding effect between the array substrate 300 and the counter substrate 400, extend the service life of the display device 100, and improve the product yield of the display device 100.

[0085] As Figure 6 shown, in an exemplary embodiment, the control signal line 2 electrically connected to the connection pattern 3 is disposed adjacent to the set control signal line 20. In this way, the portion of the connection pattern 3 overlapping with the control signal line 2 is not too far from the control signal line 2 to which the connection pattern 3 is electrically connected, which is beneficial to simplifying the structure, reducing the intersection of the connection pattern 3 with other control signal lines 2 (control signal lines 2 other than the set control signal line 20 and the control signal line 2 to which the connection pattern 3 is electrically connected), thereby reducing the gap between adjacent control signal lines blocked by the connection pattern 3, and thus reducing the light shielding area and further increasing the UV light transmittance; on the other hand, reducing the number of control signal lines 2 overlapping with the connection pattern 3, thereby reducing the parasitic capacitance generated by the intersection and overlap of the connection pattern and the control signal line 2, and avoiding affecting the charging rate of the gate driving circuit G.

[0086] As Figure 6 shown, for example, a first break K1 is provided on the first control signal line 21, and the first connection pattern 31 is electrically connected to both ends of the first control signal line 21 at the first break K1. At this time, the second control signal line 22 adjacent to the first control signal line 21 serves as the set control signal line 20 of the first control signal line 21, and a portion of the first connection pattern 31 overlaps with the second control signal line 22 (i.e., the set control signal line 20) and is insulated.

[0087] As Figure 7 shown, in an exemplary embodiment, at least one control signal line 2 is provided between the control signal line 2 electrically connected to the connection pattern 3 and the set control signal line 20, wherein the connection pattern 3 overlaps with the set control signal line 20 and is insulated.

[0088] As Figure 7 shown, for example, a first break K1 is provided on the first control signal line 21, and the first connection pattern 31 is electrically connected to both ends of the first control signal line 21 at the first break K1. At this time, the second control signal line 22 serves as the set control signal line 20 of the first control signal line 21, and a portion of the first connection pattern 31 overlaps with the second control signal line 22 (i.e., the set control signal line 20) and is insulated.

[0089] In an exemplary embodiment, any two control signal lines 2 can be each other's set control signal lines 20.

[0090] As Figure 8 shown, two adjacent control signal lines 2 can be each other's set control signal lines 20. For example, the first control signal line 21 and the second control signal line 22 are arranged adjacent to each other. A first break K1 is provided on the first control signal line 21, and a second break K2 is provided on the second control signal line 22. The first connection pattern 31 corresponds to the first break K1, and the second connection pattern 32 corresponds to the second break K2. At this time, the second control signal line 22 serves as the set control signal line 20 of the first control signal line 21, and a part of the first connection pattern 31 overlaps with the second control signal line 22 and is insulated. The first control signal line 21 serves as the set control signal line 20 of the second control signal line 22, and a part of the second connection pattern 32 overlaps with the first control signal line 21 and is insulated.

[0091] In some embodiments, by controlling the relative positional relationship between the connection pattern 3 and the set control signal line 20, as well as the shape and size of the connection pattern 3, the curing requirements of different positions of the sealant 600 can be met, so that the sealant 600 cures evenly and has a high curing efficiency, thereby improving the bonding strength between the array substrate 300 and the counter substrate 400 and extending the service life of the display panel 200.

[0092] In an exemplary embodiment, the set control signal line 20 is closer to the gate driving circuit G than the control signal line 2 electrically connected to the connection pattern 3; or, the set control signal line 20 is farther from the gate driving circuit G than the control signal line 2 electrically connected to the connection pattern 3; or, some of the set control signal lines 20 are closer to the gate driving circuit G than the control signal line 2 electrically connected to the connection pattern 3, and at the same time, some of the set control signal lines 20 are farther from the gate driving circuit G than the control signal line 2 electrically connected to the connection pattern 3.

[0093] As Figure 9 shown, in an exemplary embodiment, some of the control signal lines 2 are provided with at least one break K, and some of the control signal lines 2 are not provided with a break K. For example, a break K is provided on the first control signal line 21, and no break is provided on the second control signal line 22. More breaks K can be opened on the control signal line 2 corresponding to the area where the sealant 600 is not easily cured, and the setting of the break K can be reduced on the control signal line 2 corresponding to the area where the sealant 600 has a high curing efficiency and a fast curing speed, so as to selectively simplify the operation process when manufacturing the connection pattern 3 on the premise of meeting the curing requirements.

[0094] As Figure 9As shown, in an exemplary embodiment, at least one control signal line 2 is provided with a plurality of breaks K. In the same control signal line 2, the distance d1 along the second direction Y between the centers ho of two adjacent breaks K (for example, when the break K is rectangular, the center ho is the intersection of the two diagonals of the break K) is equal. Thus, the sealing frame adhesive 600 is cured sufficiently and uniformly in the second direction Y, improving the curing effect of the sealing frame adhesive 600.

[0095] As Figure 9 shown, in an exemplary embodiment, the dimensions H of the plurality of breaks K along the second direction Y are equal. In an exemplary embodiment, the dimensions W1 of the breaks K belonging to different control signal lines 2 along the first direction X are equal. Controlling the lengths and / or widths of the breaks K to be equal at different positions further improves the uniformity of the curing degree of the sealing frame adhesive 600 and optimizes the curing effect of the sealing frame adhesive 600.

[0096] Optionally, in the same control signal line 2, the distance d1 along the second direction Y between the centers ho of two adjacent breaks K is equal, the dimensions H of the plurality of breaks K along the second direction Y are equal, and the dimensions W1 of the breaks K belonging to different control signal lines 2 along the first direction X are equal, so that the breaks K are uniformly arranged and the areas of all the breaks K are equal, thereby realizing uniform irradiation of the sealing frame adhesive 600 with UV light and further improving the uniformity of the curing of the sealing frame adhesive 600.

[0097] As Figure 10 and Figure 11 shown, in an exemplary embodiment, the connection pattern 3 includes a first connection portion 3A and two second connection portions 3B. Among them, the orthographic projection of the first connection portion 3A on the substrate 1 overlaps with the orthographic projection of the set control signal line 20 on the substrate 1; the two second connection portions 3B are respectively arranged on both sides of the first connection portion 3A and are both electrically connected to the first connection portion 3A; one of the two second connection portions 3B is electrically connected to one end of the control signal line 2 provided with the break K at the break K, and the other of the two second connection portions 3B is electrically connected to the other end of the control signal line 2 provided with the break K at the break K.

[0098] In the above design, the two second connection parts 3B are respectively electrically connected to the two parts of the control signal line 2 disconnected by the break K, and the two second connection parts 3B are both arranged overlapping with the control signal line 2, so that the two second connection parts 3B are staggered from the break K on the control signal line 2 to which they are electrically connected, avoiding the two second connection parts 3B blocking the break K and increasing the transmittance of UV light. The orthographic projection of the first connection part 3A on the substrate 1 overlaps with the orthographic projection of the set control signal line 20 on the substrate 1, which is equivalent to moving a part of the original control signal line 2 above (or below) other control signal lines 2, so that the part of the break K that is vacated can transmit light. The electrical connection at both ends ensures that the control signal line 2 can achieve a path through the connection pattern 3 on the premise of setting the break K.

[0099] Optionally, the first connection part 3A and the two second connection parts 3B are integrally formed, thereby simplifying the preparation process of the connection pattern 3.

[0100] As Figure 10 and Figure 11 shown, in the exemplary embodiment, the dimension d2 of the first connection part 3A along the second direction Y is equal to the sum of the dimension H of the break K along the second direction Y and the dimension d3 of the two second connection parts 3B along the second direction Y.

[0101] As Figure 10 and Figure 11 shown, in the exemplary embodiment, the dimension d4 of the first connection part 3A along the first direction X is equal to the width W1 of the set control signal line 20. The adaptive dimension design of the connection pattern 3 according to the dimension of the control signal line 2 ensures that the first connection part 3A has as large an area as possible without increasing the additional light-shielding area, thereby reducing the overall resistance of the control signal line 2 and the connection pattern 3, and thus reducing the circuit load.

[0102] In the exemplary embodiment, the dimension of the first connection part 3A along the first direction X is less than the width W1 of the set control signal line 20. Thus, on the premise of ensuring that the first connection part 3A does not increase the additional light-shielding area, more process margins for manufacturing the first connection part 3A are provided, reducing the process difficulty; on the other hand, the overlapping area between the connection pattern 3 and the set control signal line 20 is reduced, thereby reducing the parasitic capacitance between the two, and thus reducing the influence on the charging rate of the gate drive circuit G.

[0103] As Figure 12 shown, in the exemplary embodiment, each control signal line 2 includes a plurality of signal line segments 2' arranged side by side along the second direction Y and electrically connected in sequence. Along the first direction X, each signal line segment 2' corresponds to a shift register (such as Figure 12 RS1 or RS2 or RS3 in

[0104] Optionally, each signal segment 2' of a control signal line 2 is electrically connected to its corresponding shift register, so as to ensure that each shift register can receive the signal output by the control signal line 2.

[0105] Optionally, multiple signal segments 2' in a control signal line 2 are evenly arranged.

[0106] Optionally, in the control signal line 2 provided with a break K, at least one signal segment 2' is provided with at least one break K.

[0107] Optionally, in the control signal line 2 provided with a break K, each signal segment 2' is provided with a break K. Each signal segment 2' is provided with a break K, so as to ensure that the sealant 600 corresponding to each signal segment 2' is irradiated by UV light, thereby ensuring uniform curing of the sealant 600.

[0108] Optionally, at least two control signal lines 2 are provided with breaks K; the breaks corresponding to the same shift register and belonging to different control signal lines 2 are staggeredly arranged in the second direction Y.

[0109] As Figure 13 and Figure 14 shown, in an exemplary embodiment, the array substrate 300 further includes at least one auxiliary line 4, and the auxiliary line 4 is used to electrically connect the shift register and the control signal line 2. When the control signal line 2 includes multiple signal segments 2', the auxiliary line 4 is used to electrically connect the shift register and the signal segment 2' corresponding to the shift register in the control signal line 2, so as to realize the electrical connection between the control signal line 2 and multiple shift registers.

[0110] Optionally, when a break K is provided in the signal segment 2' corresponding to the shift register, the auxiliary line 4 for electrically connecting the shift register and the signal segment 2' can be electrically connected through a connection pattern 3 corresponding to the break K to realize the electrical connection with the signal segment 2'. That is, one end of the auxiliary line 4 is electrically connected to the connection pattern 3, and the other end is electrically connected to the shift register corresponding to the signal segment 2' electrically connected to the connection pattern 3.

[0111] In this case, the auxiliary line 4 can extend along the first direction X to facilitate the electrical connection between the auxiliary line 4, the connection pattern 3 and the shift register.

[0112] When the connection pattern 3 includes a first connection portion 3A and two second connection portions 3B, one end of the auxiliary line 4 is electrically connected to the first connection portion 3A of the connection pattern 3; or, one end of the auxiliary line 4 is electrically connected to one of the second connection portions 3B of the connection pattern 3.

[0113] Optionally, the auxiliary line 4 is made of the same material as and is disposed on the same layer as the connection pattern 3, thereby simplifying the manufacturing process. On this basis, the auxiliary line 4 and the connection pattern 3 are integrally formed. Optionally, in the control signal line 2 provided with the break K, each signal line segment 2' is provided with an auxiliary line 4 corresponding to the break K, so that each signal line segment 2' of the control signal line 2 is electrically connected to its corresponding shift register.

[0114] Optionally, at least two control signal lines 2 are provided with breaks K, and each break K is correspondingly provided with an auxiliary line 4; the breaks K corresponding to the same shift register and belonging to different control signal lines 2 are staggered from each other in the second direction Y, so that the auxiliary lines 4 corresponding to the breaks K are staggered from each other.

[0115] As Figure 13 shown, in an optional embodiment, each break K and the corresponding connection pattern 3 are correspondingly provided with an auxiliary line 4. For example, the break K and the corresponding connection pattern 3 are only provided at the position where the shift register is electrically connected on the control signal line 2, and the auxiliary line 4 is electrically connected to the connection pattern 3.

[0116] As Figure 14 shown, in an optional embodiment, some breaks K are correspondingly provided with an auxiliary line 4. That is, in addition to providing the break K at the position where the shift register is electrically connected on the control signal line 2, connection patterns 3 that are not electrically connected to the shift register and their corresponding breaks K are additionally provided, so as to increase the number of breaks K, increase the area through which the UV light passes, accelerate the curing speed of the sealing adhesive 600, and optimize the curing effect.

[0117] Figure 15 shows Figure 10 a cross-sectional view along the section line BB' in Figure 15 As shown, in an exemplary embodiment, the array substrate 300 includes a gate conductive layer 5, a first insulating layer 6, and a source-drain conductive layer 7 that are sequentially stacked on the substrate 1. Please refer to Figure 2 , as described above, the gate conductive layer 5 is the film layer where the gate Gt of the thin film transistor 302 is located, and the source-drain conductive layer 7 is the film layer where the source Sc and the drain Dr of the thin film transistor 302 are located. In the case where the thin film transistor 302 is a bottom-gate thin film transistor, the first insulating layer 6 can be, for example, a gate insulating layer GI (refer to Figure 2 ); in the case where the thin film transistor is a top-gate thin film transistor, the first insulating layer can be, for example, an interlayer insulating layer (not shown in the figure).

[0118] A first via hole H1 is provided in the first insulating layer 6. A plurality of control signal lines 2 are provided on the gate conductive layer 5, and at least one connection pattern 3 is provided on the source-drain conductive layer 7. Each connection pattern 3 passes through the first via hole H1 and is electrically connected to the end of the control signal line 2 provided with a break K at the break K.

[0119] Figure 16 shows Figure 11 a cross-sectional view along the section line CC' in. As Figure 16 shown, in an exemplary embodiment, the array substrate 300 includes a gate conductive layer 5, a first insulating layer 6, a source-drain conductive layer 7, a second insulating layer 8, and a first electrode layer 9 that are sequentially stacked on the substrate 1. Please refer to Figure 2 , as described above, the gate conductive layer 5 is the film layer where the gate Gt of the thin film transistor 302 is located, the source-drain conductive layer 7 is the film layer where the source Sc and the drain Dr of the thin film transistor 302 are located, and the first electrode layer 9 may be, for example, the film layer where the pixel electrode 303 is located. In the case where the thin film transistor 302 is a bottom-gate thin film transistor, the first insulating layer 6 may be, for example, a gate insulating layer GI (refer to Figure 2 ); in the case where the thin film transistor is a top-gate thin film transistor, the first insulating layer may be, for example, an interlayer insulating layer (not shown in the figure). The second insulating layer 8 may be, for example, a passivation layer PVX (refer to Figure 2 ).

[0120] A second via hole H2 penetrating through the first insulating layer 6 and the second insulating layer 8 is provided in the first insulating layer 6 and the second insulating layer 8, and a third via hole H3 is provided in the second insulating layer 8. A plurality of control signal lines 2 are provided on the gate conductive layer 5, and at least one connection pattern 3 is provided on the source-drain conductive layer 7. The array substrate 300 further includes at least one auxiliary connection pattern 9', which is provided on the first electrode layer 9. Each auxiliary connection pattern 9' passes through the second via hole H2 and is electrically connected to the end of the control signal line 2 provided with a break K at the break K, and also passes through the third via hole H3 and is electrically connected to the connection pattern 3. The second via hole H2 and the third via hole H3 are formed in the patterning process of the second insulating layer 8, that is, the second via hole H2 and the third via hole H3 are formed in the same patterning process as the contact hole for electrically connecting the first electrode layer 9 and the drain Dr (or the source Sc) of the thin film transistor 302. Therefore, through the design of the auxiliary connection pattern 9' in the embodiment of the present disclosure, the electrical connection between the connection pattern 3 and the control signal line 2 can be realized without additionally increasing the patterning process.

[0121] Based on any of the above embodiments, the curing degree of the sealant 600 is related to the gap size between adjacent control signal lines 2 and the size of the break K. The transmittance of the UV light can be controlled by designing the size of the break K along the second direction Y (i.e., the length of the break K), so as to meet different requirements for the curing degree of the sealant 600.

[0122] AsFigure 17 As shown, a period region S' is set to be able to accommodate the region where a signal line segment 2' corresponding to the same shift register is located and the gap region between the adjacent signal line segments 2' provided on one side of the control signal line 2. The length of the period region S' is the length L of the signal line segment 2', and the width of the period region S' is the sum of the width W1 of the signal line segment 2' and the gap width W2 between two adjacent control signal lines 2. The length of a signal line segment 2' is L, the width of a control signal line 2 is W1, the gap width between two adjacent control signal lines 2 is W2, the length of the break K is H, the reference transmittance of UV light in a period region S' without setting the break K is x%, and the target transmittance of UV light expected to be improved by setting the break K is y%. Herein, the length refers to the dimension along the second direction Y, and the width refers to the dimension along the first direction X.

[0123] The transmittance of UV light in a period region S' is the ratio of the area of the gap available for UV light to pass through in this region (including the area of the gap between adjacent control signal lines 2 in the period region S' and the area of the break K) to the total area of the period region S'. Thus, it can be obtained that:

[0124] The transmittance of UV light in a period region S' without setting the break K is the ratio of the area of the gap between adjacent control signal lines 2 in the period region S' to the total area of the period region S', that is:

[0125] Then it can be obtained that W1 = (W1 + W2) × (1 - x%)

[0126] The transmittance of UV light to be improved by setting the break K is the ratio of the area of the opening in the period region S' to the total area of the period region S', that is:

[0127]

[0128] Then it can be deduced that the length of the break K is:

[0129]

[0130] It can be seen therefrom that the length of the break K can be designed according to the UV light transmittance x% before setting the break K and the target improved UV light transmittance y%.

[0131] Exemplarily, assume that L is 225.6 μm, the transmittance x% is 15%, and the minimum transmittance required for the effective curing of the sealing adhesive 600 is 20%. Therefore, the target improved transmittance y% is 5%. Then, according to the above calculation formula, it can be obtained that the length H of the break K is 13.3 μm.

[0132] Since a connection pattern 3 needs to be set to electrically connect the two disconnected parts after the control signal line 2 is provided with a break K, and the connection pattern 3 cannot block the break K, at least a part of the connection pattern 3 is overlapped with the set control signal line 20. Since both the connection pattern 3 and the set control signal line 20 have current passing through, a parasitic capacitance will be generated between the connection pattern 3 and the set control signal line 20 with a facing area after the overlapping setting.

[0133] The set array substrate 300 has R periodic regions S', where R is a positive integer, and a break K is provided in each periodic region S'. When the break K is not provided, the total parasitic capacitance in all the periodic regions S' is Cst1, the total area that can form a parasitic capacitance in all the periodic regions S' when the break K is not provided is S1, and the parasitic capacitance per unit area in all the periodic regions S' when the break K is not provided is Cst2. Then, it can be known that:

[0134]

[0135] The calculation formula for capacitance is: where ε is the relative dielectric constant between the two capacitor plates that generate the capacitance, d is the plate spacing between the two capacitor plates that generate the capacitance, and S is the plate area that generates the capacitance.

[0136] Since the first insulating layer 6 is between the two capacitor plates that generate the parasitic capacitance in all the periodic regions S' when the break K is not provided, and the first insulating layer 6 is also between the connection pattern 3 and the set control signal line 20, therefore, when the break K is not provided, the plate spacing d when generating the parasitic capacitance in all the periodic regions S' and when generating the parasitic capacitance between the connection pattern 3 and the set control signal line 20 is the thickness of the first insulating layer 6, and the relative dielectric constant ε is also the relative dielectric constant of the first insulating layer 6. Therefore, the parasitic capacitance per unit area when generating the parasitic capacitance between the connection pattern 3 and the set control signal line 20 is the same as the parasitic capacitance per unit area in all the periodic regions S' when the break K is not provided, and both are Cst2.

[0137] Therefore, it can be obtained that the parasitic capacitance generated between the connection pattern 3 and the set control signal line 20 in one periodic region S' is:

[0138] Cst3 = Cst2 × S2

[0139] Then, the parasitic capacitance generated between the connection pattern 3 and the set control signal line 20 in all the periodic regions S' is:

[0140] Cst3 × R = Cst2 × S2 × R

[0141] Let the parasitic capacitance generated between the setting connection pattern 3 and the setting control signal line 20 be Cst3, and the area of the connection pattern 3 that can generate parasitic capacitance be S2. Since the overlapping area of the connection pattern 3 and the setting control signal line 20 is less than the area of the break K, or is approximately equal to the area of the break K, the plate area when generating the parasitic capacitance between the connection pattern 3 and the setting control signal line 20 can be the area of the break K, that is:

[0142] S2 = W1×H

[0143] It can be seen from this that the change rate V of the parasitic capacitance formed between the connection pattern 3 and the setting control signal line 20 after setting the break K is:

[0144]

[0145] Exemplarily, Cst1 is 1200 pF, S1 is 8.3×10 6 μm 2 ², then Cst2 is 1.44×10 -4 pF / μm 2 ². Assuming W1 is 25.5 μm, then V is R×H×3.06×10 -6 %. That is, within one period region S’, the change rate of the parasitic capacitance formed between the connection pattern 3 and the setting control signal line 20 after setting the break K is only 2.7×10 -5 % of the length H of the break K. It can be seen that the value of the change rate is very small, that is, the influence of the setting of the connection pattern 3 on the parasitic capacitance can be ignored.

[0146] Exemplarily, assuming R is 960, when x% is 15% and the target transmittance y% is 5%, H is 13.3 μm, then V is 3.9%. That is, within 960 period regions S’, the change rate of the parasitic capacitance formed between the connection pattern 3 and the setting control signal line 20 after setting the break K is only 3.9%. The value of this change rate is very small and hardly affects the charging rate of the gate driving circuit G.

[0147] It can be seen from this that in the embodiments of the present disclosure, by setting the break K, the transmittance of UV light can be increased, the curing effect of the sealant 600 can be optimized, and the service life of the display panel 200 can be extended without affecting the charging rate of the gate driving circuit G.

[0148] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An array substrate, characterized in that, It includes a display area and a peripheral area; the array substrate includes: A substrate; A gate driving circuit and a plurality of control signal lines disposed on the substrate and located in the peripheral area, the plurality of control signal lines being electrically connected to the gate driving circuit; the plurality of control signal lines are arranged in parallel along a first direction, and each control signal line extends along a second direction, the first direction and the second direction intersecting; the control signal lines include at least one of a clock signal line, a high voltage signal line, a low voltage signal line, and a start signal line; the gate driving circuit includes a plurality of shift registers arranged in parallel and cascaded along the second direction; the control signal lines, the gate driving circuit, and the display area are arranged along the first direction; each of at least one control signal line is provided with at least one break; At least one connection pattern, each connection pattern corresponding to a break and being electrically connected to both ends of the control signal line provided with the break at the break; the connection pattern includes a groove, and along the thickness direction of the array substrate, the groove overlaps with the break; the connection pattern and the control signal line are in different film layers, and the connection pattern and its corresponding control signal line are electrically connected through a via.

2. The array substrate according to claim 1, wherein The orthographic projection of the connection pattern on the substrate is staggeredly arranged with the orthographic projection of the corresponding break on the substrate, and the orthographic projection of the connection pattern on the substrate at least partially overlaps with the orthographic projection of a set control signal line on the substrate; The set control signal line is one of the other control signal lines among the plurality of control signal lines except the control signal line electrically connected by the connection pattern.

3. The array substrate according to claim 2, wherein The control signal line electrically connected by the connection pattern is adjacent to the set control signal line.

4. The array substrate according to claim 2, wherein Along the first direction, the part of the set control signal line corresponding to the connection pattern is continuous.

5. The array substrate according to claim 2, wherein The connection pattern includes: A first connection portion, the orthographic projection of the first connection portion on the substrate overlapping with the orthographic projection of the set control signal line on the substrate; Two second connection portions, respectively disposed on both sides of the first connection portion and both electrically connected to the first connection portion; one of the two second connection portions is electrically connected to one end of the control signal line provided with the break at the break, and the other of the two second connection portions is electrically connected to the other end of the control signal line provided with the break at the break.

6. The array substrate according to claim 5, wherein The dimension of the first connection portion along the first direction is less than or equal to the width of the set control signal line; and / or, The dimension of the first connection portion along the second direction is equal to the sum of the dimensions of the break and the two second connection portions along the second direction.

7. The array substrate according to claim 2, wherein The array substrate includes a gate conductive layer, a first insulating layer, and a source-drain conductive layer sequentially stacked on the substrate, and a first via is provided in the first insulating layer; The plurality of control signal lines are disposed on the gate conductive layer, the at least one connection pattern is disposed on the source-drain conductive layer, and each connection pattern passes through the first via and is electrically connected to the end of the control signal line provided with the break at the break.

8. The array substrate according to claim 2, wherein The array substrate includes a gate conductive layer, a first insulating layer, a source-drain conductive layer, a second insulating layer, and a first electrode layer that are sequentially stacked on the substrate. A second via hole penetrating through the first insulating layer and the second insulating layer is provided in the first insulating layer and the second insulating layer, and a third via hole is provided in the second insulating layer; The plurality of control signal lines are provided on the gate conductive layer, and the at least one connection pattern is provided on the source-drain conductive layer; The array substrate further includes at least one auxiliary connection pattern provided on the first electrode layer; each auxiliary connection pattern passes through the second via hole and is electrically connected to the end of the control signal line with a break at the break, and also passes through the third via hole and is electrically connected to the connection pattern.

9. The array substrate according to claim 2, wherein Each control signal line includes a plurality of signal line segments arranged side by side along the second direction and electrically connected in sequence. Along the first direction, each signal line segment corresponds to a shift register; Among the control signal lines with breaks, at least one signal line segment has at least one break.

10. The array substrate according to claim 9, wherein, Among the control signal lines with breaks, each signal line segment has one break.

11. The array substrate according to claim 10, wherein The size of the fracture along the second direction is H. Wherein, L is the length of the signal line segment, y% is the target increased light transmittance of the periodic region where the signal line segment is located, and x% is the reference light transmittance of the periodic region when no fracture design is performed on the control signal line. The size of the periodic region along the first direction is the sum of the size of a signal line segment corresponding to a shift register along the first direction and the size of the gap between two adjacent signal line segments along the first direction; the size of the periodic region along the second direction is L.

12. The array substrate according to claim 10, wherein At least two control signal lines are provided with breaks; The breaks corresponding to the same shift register and belonging to different control signal lines are staggered from each other in the second direction.

13. The array substrate according to claim 9, wherein The array substrate further includes: At least one auxiliary line, which is made of the same material as the at least one connection pattern and is provided in the same layer; the auxiliary line extends along the first direction, and one end of the auxiliary line is electrically connected to the connection pattern, and the other end is electrically connected to the shift register corresponding to the signal line segment electrically connected to the connection pattern.

14. The array substrate according to any one of claims 1 to 13, characterized in that, Each control signal line is provided with at least one break.

15. The array substrate according to any one of claims 1 to 13, characterized in that The at least one control signal line is provided with a plurality of breaks; In the same control signal line, the distance between the centers of two adjacent breaks along the second direction is equal, and / or the sizes of the plurality of breaks along the second direction are equal.

16. A display panel, characterized in that, Including: The array substrate according to any one of claims 1 to 15; A counter substrate disposed opposite to the array substrate; Sealant, provided in the peripheral region of the array substrate and located between the array substrate and the counter substrate to bond the array substrate and the counter substrate; Wherein, the orthographic projection of the sealant on the substrate of the array substrate covers the orthographic projection of the plurality of control signal lines of the array substrate on the substrate.

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