Decoding circuit, source driving circuit and device

Abstract

The present disclosure provides a decoding circuit, a source driver circuit and a device. The decoding circuit includes a pre-decoder and a decoding array. First, the pre-decoder pre-decodes a first data signal to determine a gamma voltage to be output, and outputs a second data signal and a third data signal corresponding to the gamma voltage to be output. Then, at least a first switch in the decoding array can be turned on under the control of the second data signal, and a second switch is turned on under the control of the third data signal, so as to output the gamma voltage to be output. Thus, the decoding circuit only needs at most two switches to output one gamma voltage, and a plurality of gamma voltages can also share one second switch. The number of switches in the decoding circuit is small, and the size and power consumption of the decoding circuit are small.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a decoder, a source driver circuit, and a device. Background Art

[0002] A source driver circuit can generate and output corresponding driving voltages according to picture data to be displayed to drive a display panel for display. As the display resolution increases, the number of bits of the digital signal that the source driver circuit needs to parse becomes larger, and the number of transistors in the decoding circuit in the source driver circuit for decoding the digital signal output by the timing controller (TCON) into corresponding gamma voltages also becomes larger. Especially for a full-form decoding circuit, for each additional bit of the data signal, the number of transistors that need to be added is extremely large. Summary of the Invention

[0003] The present disclosure provides a decoding circuit, a source driver circuit, and a device. The specific solutions are as follows:

[0004] An embodiment of one aspect of the present disclosure provides a decoding circuit, including: a pre-decoder and a decoding array connected in sequence;

[0005] The pre-decoder is configured to pre-decode an n-bit first data signal to be decoded to determine a gamma voltage to be output, and output an n-bit second data signal and an n-bit third data signal corresponding to the gamma voltage, where n is an integer greater than 1;

[0006] The decoding array includes a plurality of first switch groups and a plurality of second switches respectively connected to a plurality of gamma voltages. Each first switch group includes a plurality of first switches. One end of each first switch is connected to a gamma voltage, and the other ends of the plurality of first switches in each first switch group are respectively connected to one end of a second switch. The other ends of the plurality of second switches are connected to each other. The decoding array is configured to respectively decode the second data signal and the third data signal to control at least one first switch and one second switch to conduct, and output the gamma voltage to be output.

[0007] An embodiment of another aspect of the present disclosure provides a source driver circuit, including a gamma voltage generation circuit, the decoding circuit as described above, and an amplifier connected in sequence;

[0008] The gamma voltage generation circuit is configured to generate a gamma voltage, and the amplifier is configured to amplify the gamma voltage output by the decoding circuit.

[0009] An embodiment of another aspect of the present disclosure provides a display driver integrated circuit (DDIC), including the source driver circuit as described in the above aspect.

[0010] Another embodiment of the present disclosure provides a device, including the above-described source driver circuit and display panel.

[0011] In the decoding circuit, source driver circuit and device according to the embodiments of the present disclosure, the decoding circuit includes a pre-decoder and a decoding array. First, the pre-decoder pre-decodes the first data signal to determine the gamma voltage to be output, and outputs a second data signal and a third data signal corresponding to the gamma voltage to be output. Then, at least a first switch in the decoding array can be turned on under the control of the second data signal, and a second switch is turned on under the control of the third data signal, so as to output the gamma voltage to be output. Thus, the decoding circuit only needs at most two switches to output one gamma voltage, and a plurality of gamma voltages can also share one second switch. The number of switches in the decoding circuit is small, and the size and power consumption of the decoding circuit are small.

[0012] Additional aspects and advantages of the present disclosure will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily understood from the following description of the embodiments in conjunction with the drawings, wherein:

[0014] Figure 1 is a schematic structural diagram of a decoding circuit provided by an embodiment of the present disclosure;

[0015] Figure 2 is a schematic structural diagram of another decoding circuit provided by an embodiment of the present disclosure;

[0016] Figure 3 is a schematic structural diagram of a pre-decoder provided by an embodiment of the present disclosure;

[0017] Figure 4 is a schematic structural diagram of yet another decoding circuit provided by an embodiment of the present disclosure;

[0018] Figure 5 is a schematic structural diagram of yet another decoding circuit provided by an embodiment of the present disclosure;

[0019] Figure 6 is a schematic structural diagram of a source driver circuit provided by an embodiment of the present disclosure;

[0020] Figure 7 is a schematic structural diagram of a device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Embodiments disclosed in the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where like or similar reference numerals denote like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present disclosure and should not be construed as limiting the present disclosure.

[0022] In the present disclosure, in view of the problem that as the number of bits of the data signal to be parsed gradually increases, the number of transistors in the decoding circuit also increases sharply, which not only causes the size of the driving circuit to be too large, but also increases the complexity and difficulty of controlling the decoding circuit, a decoding circuit is proposed. By using a pre-decoder to pre-decode the first data signal to be decoded first to determine the gamma voltage to be output, and then outputting a second signal for controlling the conduction of the switch branch connected to the gamma voltage, thus, the conduction of one switch branch in the decoding array can be controlled to output the corresponding gamma voltage. Thereby, the number of transistors (switches) used in the decoding circuit is reduced.

[0023] Figure 1 It is a schematic structural diagram of a decoding circuit provided by an embodiment of the present disclosure. As Figure 1 shown, the decoding circuit provided by the present disclosure includes: a pre-decoder 11 and a decoding array 12 connected in sequence.

[0024] Among them, the pre-decoder 11 is configured to pre-decode an n-bit first data signal to be decoded to determine the gamma voltage to be output, and output an n-bit second data signal and an n-bit third data signal corresponding to the gamma voltage;

[0025] The decoding array 12 includes a plurality of first switch groups 121 and a plurality of second switches 122. Each first switch group 121 includes a plurality of first switches (1211). One end of each first switch is connected to a gamma voltage. The other ends of the plurality of first switches in each first switch group 121 are respectively connected to one end of a second switch 122. The other ends of the plurality of second switches 122 are connected to each other. The decoding array is configured to respectively decode the second data signal and the third data signal to control at least one first switch 1211 and one second switch 122 to conduct for decoding to output the gamma voltage to be output.

[0026] Among them, the first switch 1211 and the second switch 122 can be any type of switching device. For example, both the first switch 1211 and the second switch 122 are transistors. Optionally, the conduction logics of the first switch 1211 and the second switch 122 can be the same or different. For example, the first switch 1211 is a P-type transistor and the second switch 122 is an N-type transistor; or, both the first switch 1211 and the second switch 122 are P-type transistors, or both are N-type transistors. The present disclosure does not limit this.

[0027] In the decoding circuit of the present disclosure, first, a pre-decoder is used to pre-decode the first data signal to determine the gamma voltage to be output, and a second data signal and a third data signal corresponding to the gamma voltage to be output are output. Then, at least the first switches in the decoding array can be turned on under the control of the second data signal, and a second switch is turned on under the control of the third data signal, so as to output the gamma voltage to be output.

[0028] From Figure 1 it can be seen that all the decoding arrays in this decoding circuit adopt a non-full-type decoding method. The output of each gamma voltage only requires two switching devices, and multiple gamma voltages can also share the same second switch, greatly reducing the number of switching devices used in the decoding circuit, not only reducing the size of the decoding circuit, but also reducing the power consumption of the circuit.

[0029] In some possible implementation forms, if the number of bits n of the first data signal is an even number, for example, n is 4, 6, 8, 10 or 12, etc., at this time, the number of gamma voltages that the decoding array needs to output 2 n is a perfect square number, then the number of the first switch groups in the decoding array can be pieces, and the number of the second switches is also pieces, and each first switch group includes first switches.

[0030] For example, when n = 4, the decoding array 12 of the decoding circuit includes 4 first switch groups 121 and 4 second switches 122, and each first switch group 121 includes 4 first switches 1211. Or, if n = 10, then the decoding array 12 of the decoding circuit includes first switch groups 121 and 32 second switches 122, and each first switch group 121 includes 32 first switches 1211.

[0031] Next, taking n = 4 and the first switch and the second switch being the same type of transistor as an example, for example, both are P-type transistors, the structure of the decoding circuit provided by the present disclosure will be further described. Figure 2 It is a schematic structural diagram of another decoding circuit provided by an embodiment of the present disclosure.

[0032] As shown Figure 2 in FIG. 2, the decoding array 12 includes four first switch transistor groups 121 and four second switches 122. One ends of the 16 first switches 1211 in the four first switch transistor groups 121 are respectively connected to 16 gamma voltages (V0-V15), the other ends of the four first switches 1211 in each first switch transistor group 121 are connected to one end of a second switch 122, and the other ends of the four second switches 122 are connected to each other as the output terminal (out) of the decoding array.

[0033] Since the second data signals (such as Figure 2 B1-B4 in FIG. 2) and the third data signals (such as Figure 2 A1-A4 in FIG. 2) respectively only include n bits, in order to implement selecting one gamma voltage from 2 n gamma voltages for output each time, each of the first switches 1211 in each first switch transistor group 121 can be respectively controlled by one bit of the second data signal, and each second switch 122 can be respectively controlled by one bit of the third data signal.

[0034] Furthermore, the pre-decoder 11 can be composed of gate circuits. For example, the pre-decoder 11 can include NOT gates and NAND gates to perform logical processing on the n-bit first data signal to obtain an n-bit second data signal and an n-bit third data signal.

[0035] As shown Figure 2 in FIG. 3, the pre-decoder 11 includes a first gate circuit 111, a second gate circuit 112 and a third gate circuit 113.

[0036] Among them, the first gate circuit 111 is used to invert the first data signal (D0-D3) to obtain a fourth data signal (DB0-DB1);

[0037] The second gate circuit 112 is used to output an n-bit second data signal (B1-B4) according to n / 2 high-order signals (D2-D3) in the first data signal and n / 2 high-order signals (DB2-DB3) in the fourth data signal;

[0038] The third gate circuit 113 is used to output an n-bit third data signal (A1-A4) according to n / 2 low-order signals (D0-D1) in the first data signal and n / 2 low-order signals (DB0-DB1) in the fourth data signal.

[0039] Among them, the first gate circuit 111 can be composed of multiple NOT gates. The second gate circuit 112 and the third gate circuit 113 can be composed of multiple NAND gates.

[0040] Figure 3 FIG. 3 is a schematic structural diagram of a 4-bit pre-decoder provided by an embodiment of the present disclosure.

[0041] As shown Figure 3 in the figure, the pre - decoder includes 4 NOT gates and 8 NAND gates.

[0042] Among them, the 4 NOT gates are respectively used to invert the input 4 - bit first data signals (D0~D3) to obtain 4 - bit fourth data signals (DB0~DB3).

[0043] Each of the 4 NAND gates is respectively used to process two signals among D2, D3, DB2 and DB3 to obtain one - bit second signals. According to the circuit diagram as Figure 3 shown,

[0044] Each of the other 4 NAND gates is respectively used to process two signals among D1, D0, DB1 and DB0 to obtain one - bit third signals. According to the circuit diagram as Figure 3 shown,

[0045] It should be noted that Figure 3 the correspondence between each bit of the second and third signals shown and the first signal is only for illustrative purposes. In actual use, it can be adjusted according to the connection relationship between the first switch and the gamma voltage. For example, the correspondence between each bit of the second data signal and each bit of the first data signal can be as follows: Or, it can also be as shown below: And so on, the present disclosure does not limit this. In addition, the correspondence between the third data signal and each bit of the first data signal can also be adjusted as needed, which will not be elaborated here. From Figure 2 and Figure 3 it can be seen that the control terminals of the respective first switches 1211 in the first switch group 121 are respectively connected to different output terminals of the second gate circuit 112, where each output terminal of the second gate circuit 112 outputs one bit of the second data signal;

[0046] The control terminal of each second switch 122 is connected to a different output terminal of the third gate circuit 113, where each output terminal of the third gate circuit 113 outputs one bit of the third data signal.

[0047] For example, when the first data signal is 0000, then Figure 2 and Figure 3For the decoding circuit shown, in the second data signal, B4 = 0, and for the remaining bits of the second data signal: B1, B2, and B3 are all 1. In the third data signal, A4 = 0, and for the remaining bits of the third data signal, A1, A2, and A3 are all 1. At this time, since both the first switching transistor and the second switching transistor are P-type transistors, the first switching transistor connected to the gamma voltage V0 conducts, and one of the second switching transistors connected thereto conducts, so that the decoding circuit outputs the gamma voltage V0.

[0048] When the first data signal is 0001, the Figure 2 and Figure 3 shown decoding circuit is used. In the second data signal, B4 = 0, and for the remaining bits of the second data signal: B1, B2, and B3 are all 1. In the third data signal, A3 = 0, and for the remaining bits of the third data signal, A1, A2, and A4 are all 1. At this time, the first switching transistor connected to the gamma voltage V1 conducts, and one of the second switching transistors connected thereto conducts, so that the decoding circuit outputs the gamma voltage V1.

[0049] When the first data signal is 0010, the Figure 2 and Figure 3 shown decoding circuit is used. In the second data signal, B4 = 0, and for the remaining bits of the second data signal: B1, B2, and B3 are all 1. In the third data signal, A2 = 0, and for the remaining bits of the third data signal, A1, A3, and A4 are all 1. At this time, the first switching transistor connected to the gamma voltage V1 conducts, and one of the second switching transistors connected thereto conducts, so that the decoding circuit outputs the gamma voltage V2.

[0050] And so on, the decoding circuit can sequentially decode and output a gamma voltage corresponding to the input first data signal. As can be seen from the above figure, the number of logic gates included in the first gate circuit 111, the second gate circuit 112, and the third gate circuit 113 in the pre-decoder 11 is related to the number of bits of the first data signal. If n = 6, then the first gate circuit includes 6 NOT gates, the second gate circuit includes 2 3 = 8 NAND gates, and the third gate circuit also includes 8 NAND gates. The first switching group includes 8 first switching groups and 8 second switches, and each first switching group includes 8 first switches. That is to say, the second data signal output by the second gate circuit includes a total of 8 bits (B1~B8), and the third data signal output by the third gate circuit includes a total of 8 bits (A1~A8). Thus, the second data signal can drive one of the 8 first switching groups to conduct at each moment, and the third data signal can drive one second switch to conduct at each moment, that is, only the gamma voltage corresponding to the first switch connected to the conducting second switch will be output, thereby realizing the selection of one gamma voltage for output each time from 2 6 = 64 gamma voltages.

[0051] In some possible implementation forms, if the number of bits n of the first data signal is odd, for example, n is 5, 7, 9, 11, etc., at this time, the number of gamma voltages that the decoding array needs to output is 2 n a non-perfect square number, while 2 n-1 is a perfect square number, then the number of the first switch groups that the decoding array needs to include is pieces, and the number of the second switches is also pieces, and each first switch group includes first switches.

[0052] At this time, the structure of the decoding circuit is as Figure 4 shown. Figure 4 This is a schematic structural diagram of another decoding circuit provided by the present disclosure. As Figure 4 shown, the decoding array 12 in this decoding circuit further includes two third switches 123.

[0053] Among them, n - 1 low bits of the first data signal are connected to the input end of the pre-decoder 11, and one end of each third switch 123 is respectively connected to the other ends of the second switches 122, and the other ends of the two third switches 123 are connected to each other, and are used to output the gamma voltage to be output under the control of the highest bit of the first data signal.

[0054] From Figure 4 it can be known that at this time, the decoding array 12 includes first switch groups 121 and second switches 122, where each first switch group 121 includes first switches 1211. And the first switch group 121 can be divided into two parts 121a and 121b, where each part contains first switch groups, that is, the other ends of the multiple second switches 122 connected to the first switch group 121 in each part are connected to each other and are connected to one end of a third switch 123.

[0055] Next, taking n = 5 and the first switch and the second switch being the same type of transistor as an example, the structure of the decoding circuit provided by the present disclosure will be further described. Figure 5 This is a schematic structural diagram of another decoding circuit provided by the present disclosure.

[0056] As Figure 5 shown, when n = 5, the structure of the pre-decoder 11 in the decoding circuit is the same as the structure of the pre-decoder 11 in the decoding circuit when n = 4.

[0057] Since n = 5, the decoding circuit needs to obtain 2 from 5Select the gamma voltage to be output from 32 gamma voltages. At this time, 32 first switching transistors 1211 need to be included in the decoding array 12. These 32 first switching transistors 1211 can be divided into 8 first switching groups 121, and each switching group 121 includes 4 first switching transistors 1211. In addition, 8 second switches 122 are further included in the decoding array 12, and one end of each second switch is connected to the other ends of 4 first switches in a first switching group 121.

[0058] In addition, as Figure 5 shown, the other ends of every 4 second switches 122 are connected to one end of a third switch 123, and the other ends of two third switches 123 are connected to each other as the output end of the decoding array for outputting the gamma voltage.

[0059] Figure 5 In , the two third switches 123 are of the same type, so they can be controlled respectively based on the highest bit D4 in the first data signal and the anti-phase DB4 corresponding to the highest bit. If the two third switches 123 are of different types, then the two third switches 123 can also be both controlled by DB4, and the present disclosure does not limit this.

[0060] According to Figure 5 and Figure 3 it can be known that by using the decoding circuit provided by the present disclosure, when the number of bits of the first data signal increases, there is no need to change the pre-decoder and there is no need to change the control logic of the decoding switch array. Only according to the number of bits of the new first data, appropriately increase the number of first switching groups and second switches in the decoding array, and use the highest bit data signal to control the on-off state of the third switch, then accurate decoding of a higher-bit data signal can be achieved.

[0061] Through the above analysis, it can be known that if the number of bits of the first data signal is even, then the decoding circuit can adopt the form as Figure 2 shown. If the number of bits of the first data signal is odd, then the decoding circuit can adopt the form as Figure 4 or 5 shown.

[0062] The decoding circuit provided by the present disclosure first performs pre-decoding processing on the first data signal through a pre-decoder to obtain a second data signal and a third data signal with the same number of bits as the pre-decoded data signal, and then decodes the second data signal and the third data signal based on the decoding array, and then the accurate gamma voltage can be output. For each gamma voltage, at most three switching transistors are required, and a second switching transistor and a third switching transistor are shared by multiple gamma voltages, thus greatly reducing the number of switching transistors used in the decoding circuit and reducing the size of the decoding circuit.

[0063] Based on the decoding circuit provided by the above embodiment, the present disclosure embodiment can also provide a source driver circuit. AsFigure 6 The following is a schematic structural diagram of a source driver circuit provided by an embodiment of the present disclosure. As Figure 6 shown, the source driver circuit includes a gamma voltage generation circuit 61, a decoding circuit 62, and an amplifier 63 that are connected in sequence.

[0064] Among them, the gamma voltage generation circuit 61 is used to generate a gamma voltage, and the amplifier 63 is used to amplify the gamma voltage output by the decoding circuit 62.

[0065] In addition, for the structure and implementation principle of the decoding circuit 62, reference can be made to the detailed description of any embodiment of the present disclosure, and details are not described herein again.

[0066] Based on the source driver circuit provided in the above embodiment, an embodiment of the present disclosure can also provide a display driver integrated circuit (DDIC). The above explanation of the source driver circuit also applies to the DDIC in this embodiment, so details are not described herein again.

[0067] Based on the source driver circuit provided in the above embodiment, an embodiment of the present disclosure can also provide a device. Figure 7 The following is a schematic structural diagram of the device provided by an embodiment of the present disclosure. As Figure 7 described, the device includes a source driver circuit 71 and a display panel 72.

[0068] The above explanation of the source driver circuit also applies to the device in this embodiment, so details are not described herein again.

[0069] The decoding circuit in the source driver circuit, DDIC, and device provided by the present disclosure includes a pre-decoder and a decoding array. By first pre-decoding the first data signal using the pre-decoder, and then using a very small number of switches, a gamma voltage corresponding to the input first data signal can be output. Thereby, the number of switches used in the source driver circuit is greatly reduced, and the volume and loss of the source driver circuit are reduced.

[0070] In the description of this specification, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present disclosure, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0071] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A decoding circuit, characterized in that, Comprising: A pre-decoder and a decoding array connected in sequence; Wherein, the pre-decoder is used to pre-decode an n-bit first data signal to be decoded to determine a gamma voltage to be output, and output an n-bit second data signal and an n-bit third data signal corresponding to the gamma voltage, where n is an integer greater than 1; The pre-decoder includes a first gate circuit, a second gate circuit and a third gate circuit; When n is an even number, the decoding array includes first switch groups and second switches. Each first switch group includes first switches. The first gate circuit is configured to invert the first data signal to obtain a fourth data signal. The second gate circuit is configured to output the n-bit second data signal according to n / 2 high-order signals in the first data signal and n / 2 high-order signals in the fourth data signal. The third gate circuit is configured to output the n-bit third data signal according to n / 2 low-order signals in the first data signal and n / 2 low-order signals in the fourth data signal. When n is odd, the decoding array includes first switch groups and second switches, where each first switch group includes first switches; the first gate circuit is configured to invert n - 1 low-order signals in the first data signal to obtain a fourth data signal; the second gate circuit is configured to output n - 1 bits of the second data signal according to (n - 1) / 2 high-order signals in the first data signal and (n - 1) / 2 high-order signals in the fourth data signal; the third gate circuit is configured to output n - 1 bits of the third data signal according to (n - 1) / 2 low-order signals in the first data signal and (n - 1) / 2 low-order signals in the fourth data signal; The decoding array includes a plurality of first switch groups and a plurality of second switches respectively connected to a plurality of gamma voltages. Each first switch group includes a plurality of first switches. One end of each first switch is connected to a gamma voltage, and the other ends of the plurality of first switches in each first switch group are respectively connected to one end of a second switch. The other ends of the plurality of second switches are connected to each other. The decoding array is used to respectively decode the second data signal and the third data signal to control at least one first switch and one second switch to conduct, and output the gamma voltage to be output.

2. The circuit according to claim 1, wherein The control terminals of the respective first switches in each first switch group are respectively connected to different output terminals of the second gate circuit, wherein each output terminal of the second gate circuit outputs one bit of the second data signal; The control terminal of each second switch is connected to a different output terminal of the third gate circuit, wherein each output terminal of the third gate circuit outputs one bit of the third data signal.

3. The circuit according to claim 1, wherein The decoding array further includes: two third switches; The n-1 low-order bits of the first data signal are connected to the input end of the pre-decoder, and one end of each of the third switches is respectively connected to the other ends of two second switches, and the other ends of the two third switches are connected to each other for outputting the gamma voltage to be output under the control of the highest-order bit of the first data signal.

4. The circuit according to claim 3, wherein The first set of the multiple first switch groups is used to select and output one gamma voltage from the input two n-1 gamma voltages when the second data signal is within a first range; The second set of the plurality of first switch groups is used to select a gamma voltage from the other two input gamma voltages when the second data signal is within a second range. Each set of first switch groups includes n-1 a number of first switch groups. ​ 5. The circuit according to claim 4, wherein The control terminals of the respective first switches in each first switch group are respectively connected to different output terminals of the second gate circuit, wherein each output terminal of the second gate circuit outputs one bit of the second data signal; The control terminals of every two second switches are connected to an output terminal of the third gate circuit, wherein each output terminal of the third gate circuit outputs one bit of the third data signal.

6. A source driver circuit, characterized in that, Comprising: A gamma voltage generation circuit, a decoding circuit according to any one of claims 1-5, and an amplifier connected in sequence; Wherein, the gamma voltage generation circuit is used to generate a gamma voltage, and the amplifier is used to amplify the gamma voltage output by the decoding circuit.

7. A display driving integrated circuit DDIC, characterized in that, Comprising the source driver circuit according to claim 6.

8. A device, characterized in that, Comprising the source driver circuit according to claim 6 and a display panel.

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