Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method for fabricating the same are disclosed. The method for fabricating the semiconductor device includes forming a gate structure on a substrate, forming a source / drain region on both sides of the gate structure, forming an epitaxial layer on the source / drain region, forming an interlayer dielectric layer on the gate structure, forming a contact hole in the interlayer dielectric layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and performing an annealing process to form a first metal silicide layer and a second metal silicide layer.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming two layers of metal silicide within the contact holes after forming contact holes on both sides of a gate structure. Background Technology

[0002] In recent years, with the continuous shrinking of field-effect transistor (FET) device dimensions, the development of existing planar FET devices has reached the limits of fabrication technology. To overcome these limitations, replacing planar FET devices with non-planar FET devices, such as fin field-effect transistors (Fin FETs), has become the mainstream development trend. Because the three-dimensional structure of Fin FETs increases the contact area between the gate and the fin structure, it further enhances the gate's control over the carrier channel region, thereby reducing the drain-induced barrier lowering (DIBL) effect faced by small-sized devices and suppressing the short-channel effect (SCE). Furthermore, since Fin FETs have a wider channel width for the same gate length, they can achieve double the drain drive current. Moreover, the threshold voltage of the transistor device can be controlled by adjusting the work function of the gate.

[0003] However, in current fin field-effect transistor (FET) fabrication processes, particularly during the contact plug fabrication stage, excessively high contact resistance frequently occurs, affecting the overall device operation and electrical performance. Therefore, improving existing FET fabrication processes to address this issue is a crucial current research topic. Summary of the Invention

[0004] An embodiment of the present invention discloses a method for fabricating a semiconductor device, which mainly involves first forming a gate structure on a substrate, then forming a source / drain region on both sides of the gate structure, forming an epitaxial layer on the source / drain region, forming an interlayer dielectric layer on the gate structure, forming a contact hole in the interlayer dielectric layer and exposing the epitaxial layer, forming a low-stress metal layer in the contact hole, forming a barrier layer on the low-stress metal layer, and then performing an annealing process to form a first silicide metal layer and a second silicide metal layer.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a gate structure disposed on a substrate, a source / drain region disposed on both sides of the gate structure, and a contact plug disposed on the source / drain region next to the gate structure, wherein the contact plug includes a first metal silicide layer disposed on the source / drain region and a second metal silicide layer disposed on the first metal silicide layer. Attached Figure Description

[0006] Figures 1 to 6 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0007] Explanation of main component symbols

[0008] 12: Base

[0009] 14: Gate Structure

[0010] 16: Gate Structure

[0011] 18: Gate dielectric layer

[0012] 20: Gate material layer

[0013] 22: Hard Mask

[0014] 24: Spacer wall

[0015] 26: Source / Drain Region

[0016] 28: Epitaxial layer

[0017] 36: Contact hole etching stop layer

[0018] 38: Interlayer dielectric layer

[0019] 40: High dielectric constant dielectric layer

[0020] 42: Work function metal layer

[0021] 44: Low-resistivity metal layer

[0022] 46: Hard Mask

[0023] 48:Contact hole

[0024] 50: Low-stress metal layer

[0025] 52: Barrier Layer

[0026] 54: Annealing process

[0027] 56: Interface Layer

[0028] 58: Siliconized metal layer

[0029] 60: Siliconized metal layer

[0030] 62: Conductive layer

[0031] 64: Contact plug Detailed Implementation

[0032] Please refer to Figures 1 to 6 , Figures 1 to 6 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, and then at least one gate structure 14, 16 is formed on the substrate 12. In this embodiment, the gate structures 14, 16 are preferably formed by sequentially forming a gate dielectric layer, a gate material layer, and a hard mask on the substrate 12, and using a patterned photoresist (not shown) as a mask to perform a pattern transfer fabrication process, removing part of the hard mask, part of the gate material layer, and part of the gate dielectric layer in a single etch or successive etch step, and then stripping the patterned photoresist to form at least one gate structure 14, 16 on the substrate 12, which is composed of a patterned gate dielectric layer 18, a patterned gate material layer 20, and a patterned hard mask 22. In this embodiment, the number of gate structures 14 and 16 is two, but it is not limited to this. In order to highlight the contact plug formed between the two gate structures 14 and 16, this embodiment only shows part of the gate structures 14 and 16, for example, only the right half of the gate structure 14 and the left half of the gate structure 16.

[0033] In this embodiment, the substrate 12 is, for example, a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The gate dielectric layer 18 may comprise silicon dioxide (SiO2), silicon nitride (SiN), or a high dielectric constant (high-k) material; the gate material layer 20 may comprise conductive materials such as metal, polysilicon, or metal silicide; the hard mask 22 may be selected from the group consisting of silicon oxide, silicon nitride, silicon carbide (SiC), and silicon oxynitride (SiON), but is not limited thereto.

[0034] Furthermore, in one embodiment, it is also possible to pre-form multiple doped wells (not shown) or multiple shallow trench isolations (STIs) for electrical isolation in the substrate 12. Also, although this embodiment uses a planar transistor as an example, in other variations, the semiconductor fabrication process of the present invention can also be applied to non-planar transistors, such as fin-FETs. Figure 1 The indicated base 12 corresponds to a fin-like structure formed on a base 12.

[0035] Then, at least one spacer wall 24 is formed on the sidewalls of each gate structure 14, 16, and a source / drain region 26 and / or epitaxial layer 28 are formed in the substrate 12 on both sides of the spacer wall 24. In this embodiment, the spacer wall 24 can be a single spacer wall or a composite spacer wall, for example, it can include a bias spacer wall (not shown) and a main spacer wall (not shown). In this embodiment, the spacer wall 24 is preferably made of silicon nitride, but the spacer wall 24 can also be selected from the group consisting of silicon oxide, silicon oxynitride, and silicon carbide. The source / drain region 26 and the epitaxial layer 28 can contain different dopants or different materials depending on the conductivity type of the transistor being disposed. For example, the source / drain region 26 can contain P-type dopants or N-type dopants, while the epitaxial layer 28 can contain silicon germanide, silicon carbide, or silicon phosphide.

[0036] Then as Figure 2 As shown, a contact etch stop layer (CESL) 36 made of silicon nitride can be selectively formed on the substrate 12 and cover the gate structures 14 and 16. Then, an interlayer dielectric layer 38 is formed on the contact etch stop layer 36. Next, a planarization process is performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 38 and part of the contact etch stop layer 36, and to make the upper surface of the hard mask 22 flush with the upper surface of the interlayer dielectric layer 38.

[0037] Subsequently, a metal gate replacement fabrication process is performed to convert the gate structures 14 and 16 into metal gates. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonia hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the hard mask 22 and the gate material layer 20 in the gate structures 14 and 16, so as to form a groove (not shown) in the interlayer dielectric layer 38. Then, a high dielectric constant dielectric layer 40 and a conductive layer including at least a work function metal layer 42 and a low impedance metal layer 44 are sequentially formed in the groove, and a planarization process is then performed to make the surfaces of the U-shaped high dielectric constant dielectric layer 40, the U-shaped work function metal layer 42 and the low impedance metal layer 44 flush with the surface of the interlayer dielectric layer 38.

[0038] In this embodiment, the high dielectric constant dielectric layer 40 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. lead zirconate titanate (SrBi₂Ta₂O₉, SBT) and lead zirconate titanate (PbZr) x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x The group consisting of TiO3, BST, or combinations thereof.

[0039] The work function metal layer 42 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 42 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto; if the transistor is a P-type transistor, the work function metal layer 42 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 42 and the low impedance metal layer 44. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low impedance metal layer 44 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof. Since the conversion of a dummy gate into a metal gate according to the metal gate replacement fabrication process is a well-known technique in this field, it will not be described in detail here. Next, a portion of the high dielectric constant dielectric layer 40, a portion of the work function metal layer 42, and a portion of the low impedance metal layer 44 may be removed to form a groove (not shown). Then, a hard mask 46 is filled into the groove and made flush with the surface of the interlayer dielectric layer 38. The hard mask 46 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0040] like Figure 3 As shown, an etching process can then be performed using a patterned mask to remove part of the interlayer dielectric layer 38 and part of the contact hole etch stop layer 36 next to the gate structures 14 and 16 to form contact holes 48 to expose the surface of the epitaxial layer 28. Then, a low-stress metal layer 50 and a barrier layer 52 are sequentially formed in the contact holes 48, but not completely filling the contact holes 48.

[0041] In this embodiment, the low-stress metal layer 50 is preferably formed using a physical vapor deposition (PVD) process, while the barrier layer 52 is preferably formed using a chemical vapor deposition (CVD) process. The PVD process for forming the low-stress metal layer 50 preferably has a DC power of approximately 1000 watts, an RF power of approximately 4500 watts, and an automatic capacitance tuner position of approximately 75%. Generally, the automatic capacitance tuner position is a capacitance parameter used to control the intensity of plasma bombardment in an electrostatic discharge protection circuit. Compared to the prior art where controlling the automatic capacitance tuner position at approximately 10% results in a high-stress metal layer with approximately -712 MPa, this embodiment preferably adjusts the automatic capacitance tuner position to 70%–80%, or more preferably approximately 75%, thus producing a low-stress metal layer with a stress between approximately -330 MPa and -270 MPa, or more preferably approximately -299 MPa. In this embodiment, the low-stress metal layer 50 preferably comprises titanium, but according to other embodiments of the present invention, it may also be selected from the group consisting of titanium, cobalt, nickel and platinum, etc. The barrier layer 52 may comprise metal compounds such as titanium nitride and tantalum nitride, and preferably comprises titanium nitride.

[0042] like Figure 4 As shown, an annealing process 54 is then performed to form multiple metal silicide layers. In this embodiment, the annealing process 54 performed in this stage after the continuous deposition of the low-stress metal layer 50 and the barrier layer 52 may include a first heat treatment process and a second heat treatment process sequentially to form multiple metal silicide layers on the epitaxial layer 28. In this embodiment, the first heat treatment process includes a room temperature annealing process, the temperature of which is preferably between 500°C and 600°C, and most preferably 550°C, and the processing time is preferably between 10 seconds and 60 seconds, and most preferably 30 seconds. The second heat treatment process includes a spike annealing process, the temperature of which is preferably between 600°C and 950°C, and most preferably 600°C, and the processing time is preferably between 100 milliseconds and 5 seconds, and most preferably 5 seconds.

[0043] It is worth noting that, in this stage, after the aforementioned annealing process, the epitaxial layer 28 preferably reacts with the low-stress metal layer 50 sequentially from bottom to top between the surface of the epitaxial layer 28 and the unreacted barrier layer 52 to form an interface layer 56, a silicide metal layer 58, and another silicide metal layer 60. The interface layer 56 preferably comprises silicon germanide, the silicide metal layer 58 comprises metal germanosilicide or more specifically titanium germanosilicide (TiSiGe), and the silicide metal layer 60 comprises metal silicide or more specifically titanium silicide (TiSi).

[0044] like Figure 5 As shown, a conductive layer 62 is then formed within the contact hole 48 and fills the contact hole 48. In this embodiment, the conductive layer 62 preferably contains tungsten, but is not limited to this. Finally, a planarization process is performed, for example, by using a CMP process to remove part of the conductive layer 62, part of the barrier layer 52, and part of the low-stress metal layer 50. Depending on the fabrication process requirements, a portion of the interlayer dielectric layer 38 may also be removed to form the contact plug 64 electrically connecting to the epitaxial layer 28. This completes the fabrication of the semiconductor device according to the preferred embodiment of the present invention.

[0045] Please continue to refer to Figure 6 , Figure 6 This diagram discloses the distribution ratio of elements, including titanium atoms, silicon atoms, and germanium atoms, in the material layer of a contact plug 64 according to an embodiment of the present invention. In the diagram, the X-axis represents the relative depth distance of each material layer in the contact plug 64, and the Y-axis represents the concentration of each element in the contact plug 64. Figure 6 As shown, the germanium atom concentration in the contact plug 64 preferably decreases from the epitaxial layer 28 to the interface layer 56, then slightly increases in the silicide metal layer 58 composed of titanium silicon germanide, and then decreases again in the barrier layer 52 composed of titanium nitride. In this embodiment, the germanium concentration of the epitaxial layer 28 is preferably between 25% and 45%, or more preferably between 48% and 58%, the germanium concentration of the interface layer 56 is preferably between 17% and 23%, and the germanium concentration of the silicide metal layer 58 is preferably between 24% and 29%. In terms of thickness, the thickness of the interface layer 56 is preferably about 10-20 angstroms, the thickness of the silicide metal layer 58 is about 50 angstroms, and the thickness of the silicide metal layer 60 may be less than, equal to, or greater than the thickness of the silicide metal layer 58.

[0046] It should be noted that although in this embodiment a silicide metal layer 60 composed of titanium silicide (TiSi) is provided between the silicide metal layer 58 composed of titanium silicon germanide (TiSiGe) and the barrier layer 52 composed of titanium nitride, that is, two silicide metal layers 58 and 60 are provided between the interface layer 56 and the barrier layer 52, this is not the limitation. According to other embodiments of the present invention, the parameters in the fabrication process between the deposition of the low-stress metal layer 50 and the annealing process 54 can be slightly adjusted to avoid forming an additional silicide metal layer composed of titanium silicide (TiSi), so that the silicide metal layer 58 composed of titanium silicon germanide (TiSiGe) directly contacts the barrier layer 52 composed of titanium nitride above. This variation is also within the scope of the present invention. To correspond to this embodiment and to more clearly indicate the germanium concentration change between the interface layer 56 and the silicide metal layer 58 composed of titanium silicon germanide. Figure 6 Only the silicide metal layer 58 and the barrier layer 52 are shown, but the other silicide metal layer 60, which is composed of titanium silicide, between them is omitted.

[0047] In summary, the present invention first forms contact holes on both sides of a metal gate, then sequentially forms a low-stress metal layer and a barrier layer within the contact holes. An annealing process is then used to react the low-stress metal layer with the epitaxial layer to form an interface layer 56, a silicide metal layer 58 composed of titanium silicon germanide, and a silicide metal layer 60 composed of titanium silicide. According to a preferred embodiment of the present invention, by adjusting some parameters in the physical vapor deposition process, the present invention can form a low-stress metal layer mainly composed of titanium metal. This low-stress metal layer can promote the diffusion of germanium atoms into the silicide metal layer 58 composed of titanium silicon germanide and reduce the overall contact resistance of the contact plug.

[0048] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: A gate structure is formed on the substrate; Source / drain regions are formed on both sides of the gate structure; An epitaxial layer is formed on the source / drain region; An interlayer dielectric layer is formed on the gate structure; A contact hole is formed within the interlayer dielectric layer, exposing the epitaxial layer; A low-stress metal layer is formed inside the contact hole; A barrier layer is formed on the low-stress metal layer; as well as An annealing process is performed to form an interface layer containing silicon germanide, a first silicide metal layer containing silicon germanide, and a second silicide metal layer between the epitaxial layer surface and the unreacted barrier layer, from bottom to top, by reacting the epitaxial layer and the low-stress metal layer in sequence. The germanium concentration of the interface layer is lower than that of the first silicide metal layer.

2. The method of claim 1, wherein the barrier layer comprises titanium nitride.

3. The method of claim 1, wherein the germanium concentration of the interface layer is less than the germanium concentration of the epitaxial layer.

4. The method of claim 1, wherein the second silicide metal layer comprises a metal silicide.

5. A semiconductor device manufactured by the method according to any one of claims 1 to 4, characterized in that, Include: The gate structure is disposed on the substrate; The source / drain regions are located on both sides of the gate structure; A contact plug is disposed on the source / drain region adjacent to the gate structure, the contact plug comprising: A first silicide metal layer is disposed on the source / drain region; and A second metal silicide layer is disposed on the first metal silicide layer. An epitaxial layer is disposed on the source / drain region; An interface layer, disposed on the epitaxial layer, comprises silicon germanide; The first silicide metal layer is disposed on the interface layer and contains metal silicon germanide, wherein the germanium concentration of the interface layer is less than the germanium concentration of the first silicide metal layer; The second silicide metal layer is disposed on the first silicide metal layer; A barrier layer is disposed on the second silicide metal layer; as well as A conductive layer is disposed on the barrier layer.

6. The semiconductor device of claim 5, wherein the germanium concentration of the interface layer is less than the germanium concentration of the epitaxial layer.

7. The semiconductor device of claim 5, wherein the barrier layer comprises titanium nitride.

8. The semiconductor device of claim 5, wherein the conductive layer comprises tungsten.

9. The semiconductor device of claim 5, wherein the second silicide layer comprises a metal silicide.

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