Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a base, a fin on a part of a surface of the base, and a hard mask layer on a top surface of the fin; removing the hard mask layer; after removing the hard mask layer, forming a first protective layer on the surface of the fin by an epitaxial growth process; and after forming the first protective layer, forming an isolation structure layer on the surface of the substrate, the isolation structure layer being on a part of a sidewall of the fin, and a top surface of the isolation structure layer being lower than the top surface of the fin. Before forming the first protective layer, the hard mask layer is removed, so that the surface of the fin has a uniform epitaxial growth point of the first protective layer material, which improves the uniformity of the formed first protective layer, and avoids etching damage to the fin caused by an etching process in the epitaxial growth process, thereby improving a process window.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] In the existing semiconductor field, the FinFET is an emerging multi-gate device. Compared with the planar metal-oxide-semiconductor field-effect transistor (MOSFET), the FinFET has stronger short-channel rejection capability and higher operating current, and is now widely used in various semiconductor devices.

[0003] With the continuous development of semiconductor technology, the gate size of fin field-effect transistors is also constantly decreasing. At this time, the distribution width of boron and phosphorus doped ions has become an important factor affecting the short channel effect (SCE) of fin field-effect transistors.

[0004] The performance of semiconductor structures formed using existing fin field-effect transistors urgently needs improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a base, a fin located on a portion of the surface of the base, and a hard mask layer located on the top surface of the fin; removing the hard mask layer; after removing the hard mask layer, forming a first protective layer on the surface of the fin using an epitaxial growth process; after forming the first protective layer, forming an isolation structure layer on the surface of the substrate, the isolation structure layer being located on a portion of the sidewall of the fin, and the top surface of the isolation structure layer being lower than the top surface of the fin.

[0007] Optionally, the method for removing the hard mask layer includes: forming a cover layer on the surface of the substrate, the cover layer exposing the top of the hard mask layer; removing the hard mask layer using the cover layer as a mask; and removing the cover layer after removing the hard mask layer.

[0008] Optionally, before forming the cover layer, a second protective layer may be formed on the substrate surface.

[0009] Optionally, the material of the second protective layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0010] Optionally, the material of the second protective layer includes a carbon-containing material, wherein the percentage concentration of carbon atoms ranges from 15% to 80%.

[0011] Optionally, the process for forming the second protective layer includes atomic layer deposition or chemical vapor deposition.

[0012] Optionally, the overlay layer further exposes a portion of the second protective layer on the surface of the hard mask layer. After the overlay layer is formed and before the hard mask layer is removed, the process further includes: removing the exposed second protective layer to expose a portion of the surface of the hard mask layer.

[0013] Optionally, the process for removing the second protective layer exposed by the capping layer includes one or a combination of dry etching and wet etching processes.

[0014] Optionally, the process for removing the second protective layer exposed by the cover layer includes a plasma etching process. The process parameters of the plasma etching process include: etching gas including carbon fluoride, oxygen, and hydrofluoric acid; no bias voltage or low-frequency bias voltage; and the power range of the low-frequency bias voltage being less than or equal to 100 watts.

[0015] Optionally, after removing the cover layer and before forming the first protective layer, the method further includes: removing the second protective layer from the substrate surface to expose the fin surface.

[0016] Optionally, the process for removing the second protective layer from the substrate surface includes one or a combination of dry etching and wet etching processes.

[0017] Optionally, the process for removing the second protective layer from the substrate surface includes a plasma etching process, wherein the process parameters of the plasma etching process include: the etching gas includes a first etching gas, which includes a fluorine-containing, chlorine-containing, or bromine-containing gas.

[0018] Optionally, the etching gas may also include a second etching gas, which may include one or more of sulfur oxides, oxygen, argon, helium, and carbon dioxide.

[0019] Optionally, the material of the overlay layer is different from the material of the hard mask layer, and the material of the overlay layer includes spin-coated carbon and bottom anti-reflective material.

[0020] Optionally, the material of the cover layer is different from the material of the hard mask layer, and the material of the cover layer includes a dielectric material; the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0021] Optionally, the method for forming the cover layer includes: forming a dielectric material layer on the surface of the substrate, wherein the top surface of the dielectric material layer is higher than the top surface of the hard mask layer; planarizing the dielectric material layer until the top surface of the hard mask layer is exposed; and after the planarization process, etching back the dielectric material layer.

[0022] Optionally, the process for removing the hard mask layer includes one or a combination of dry etching and wet etching.

[0023] Optionally, the etching selectivity ratio of the hard mask layer and the fin in the process of removing the hard mask layer is greater than 10:1.

[0024] Optionally, the process for removing the hard mask layer includes a remote plasma process.

[0025] Optionally, the formation process of the first protective layer includes a selective epitaxial growth process, wherein the selective epitaxial growth process includes multiple film formation processes, and each film formation process includes: forming a material film, and an etching process after forming the material film.

[0026] Optionally, the material of the fin includes silicon, germanium-silicon, or a combination of both.

[0027] Optionally, the material of the first protective layer includes silicon.

[0028] Optionally, after forming the isolation structure layer, the method further includes: oxidizing the surface of the first protective layer to form a protective material layer and a gate oxide layer located on the protective material layer; the thickness of the protective material layer ranges from 1 angstrom to 15 angstroms.

[0029] Optionally, the first protective layer includes a protective material layer and a sacrificial layer located on the protective material layer; the material of the protective material layer includes silicon; the material of the sacrificial layer includes a dielectric material, the dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0030] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0031] In the semiconductor structure formation method provided by the present invention, before forming the first protective layer, a hard mask layer is removed. Since removing the hard mask layer exposes the top surface of the fin, during the process of forming the first protective layer on the surface of the fin using an epitaxial growth process, the surface of the fin has uniform epitaxial growth points of the first protective layer material, which is beneficial to improving the uniformity of the formed first protective layer and avoiding etching damage to the fin caused by the etching process that may be introduced in the epitaxial growth process, thereby improving the process window.

[0032] Furthermore, before forming the cover layer, a second protective layer is also formed on the surface of the substrate. The second protective layer is used to protect the surface of the fin and reduce etching damage to the fin when the cover layer is removed.

[0033] Furthermore, the process of the hard mask layer includes remote plasma processing, which helps to reduce etching damage to the surface of the fin.

[0034] Furthermore, the process for removing the second protective layer exposed by the cover layer includes a plasma etching process, which uses a no-bias voltage or a low-frequency bias voltage, which helps to reduce etching damage to the surface of the fin. Attached Figure Description

[0035] Figure 1 This is a schematic cross-sectional view of the semiconductor structure formation process;

[0036] Figure 2 This is a cross-sectional schematic diagram of another semiconductor structure formation process;

[0037] Figures 3 to 9 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0038] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0039] As described in the background section, the performance of semiconductor structures formed using existing FinFET technology urgently needs improvement. This paper will now illustrate and analyze one such semiconductor structure.

[0040] Figure 1 This is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0041] Please refer to Figure 1 A substrate is provided, the substrate including a base 100, a fin located on a portion of the surface of the base 100, and a hard mask layer 103 located on the top surface of the fin, the fin including a bottom structure 101 and a channel layer 102 located on the bottom structure 101; a protective layer 104 is formed on the surface of the fin using a non-selective epitaxial process.

[0042] In the above method, the bottom structure 101 of the fin is made of silicon, the channel layer 102 is made of germanium-silicon or silicon, and the protective layer 104 is made of monocrystalline silicon. In the non-selective epitaxial process, because silicon has a high lattice matching rate with the fin but a lattice mismatch with the hard mask layer 103, a monocrystalline silicon thin film layer is formed on the surface of the fin, while a large number of amorphous silicon thin films are formed on the surface of the hard mask layer 103. The formation rate of the amorphous silicon thin film layer is greater than the formation rate of the monocrystalline silicon thin film layer. Furthermore, the amorphous silicon thin film layer on the sidewalls of the hard mask layer 103 is difficult to remove by subsequent etching, thus residual amorphous silicon material is formed on the sidewalls of the hard mask layer 103, resulting in... Figure 1 The defect A shown will affect the performance of the formed device, such as causing leakage current.

[0043] To reduce the occurrence of defect A, in another embodiment, the protective layer is formed using a non-selective epitaxial process. Please refer to [reference needed]. Figure 2 .

[0044] Figure 2 This is a cross-sectional schematic diagram of another semiconductor structure formation process.

[0045] Please refer to Figure 2 A substrate is provided, the substrate including a base 200, a fin located on a portion of the surface of the base 200, and a hard mask layer 203 located on the top surface of the fin, the fin including a bottom structure 201 and a channel layer 202 located on the bottom structure 201; a protective layer 204 is formed on the surface of the fin using a selective epitaxial process.

[0046] The difference between this embodiment and the previous embodiment is that the protective layer 204 is formed using a selective epitaxial process. The selective epitaxial process includes multiple film-forming processes, each of which includes: forming a material film, and an etching process following the formation of the material film.

[0047] In the selective epitaxial process, the etching process after forming the material film can remove the amorphous silicon thin film layer on the surface of the hard mask layer 203. However, the etching process can also easily etch the fin, causing a rounded corner B at the fin's apex (e.g., Figure 2 This phenomenon (as shown in the figure) results in a high degree of roughness on the sidewall surface of the fin.

[0048] To address the aforementioned problems, this invention provides a semiconductor structure formation method. Before forming the first protective layer, a hard mask layer is removed. Since removing the hard mask layer exposes the top surface of the fin, during the epitaxial growth process of forming the first protective layer on the fin surface, the fin surface has uniform epitaxial growth points of the first protective layer material. This improves the uniformity of the formed first protective layer and avoids etching damage to the fin caused by the etching process that may be introduced during the epitaxial growth process, thereby improving the process window.

[0049] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0050] Figures 3 to 9 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0051] Please refer to Figure 3 A substrate is provided, the substrate including a base 200, a fin 201 located on a portion of the surface of the base 200, and a hard mask layer 202 located on the top surface of the fin 201.

[0052] In this embodiment, the substrate 200 is made of silicon.

[0053] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0054] The method for forming the fin 201 includes: providing an initial substrate (not shown in the figure); forming a channel epitaxial material layer (not shown in the figure) on the initial substrate; forming the hard mask layer 202 on the surface of the channel epitaxial material layer, the hard mask layer 202 exposing a portion of the surface of the channel epitaxial material layer; etching the channel epitaxial material layer and the initial substrate using the hard mask layer 202 as a mask to form a substrate 200 and the fin 201 located on the surface of the substrate, the fin 201 including a bottom structure I and an epitaxial layer II on the bottom structure I, the epitaxial layer II being formed using the epitaxial material layer, and the substrate 200 and the bottom structure I being formed using the initial substrate.

[0055] The fin 201 is made of silicon, germanium-silicon, or a combination of both. The fin 201 is used to form the channel of the device. Specifically, in this embodiment, the epitaxial layer II is made of germanium-silicon, and the bottom structure I is made of silicon.

[0056] The hard mask layer 202 is made of a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the hard mask layer 202 is made of silicon nitride.

[0057] Subsequently, the hard mask layer 202 is removed. For the method of removing the hard mask layer 202 in this embodiment, please refer to [reference needed]. Figures 4 to 7 .

[0058] Please refer to Figure 4 A cover layer 203 is formed on the surface of the substrate, the cover layer 203 exposing the top of the hard mask layer 202.

[0059] The material of the capping layer 203 is different from that of the hard mask layer 202. The capping layer 203 is used to protect the substrate and reduce etching damage to the substrate during the etching process of removing the hard mask layer 202.

[0060] In this embodiment, the material of the cover layer 203 includes spin-coated carbon and bottom anti-reflective material.

[0061] In this embodiment, the material of the cover layer 203 is spin-coated carbon, and the cover layer 203 has good fluidity and can cover the surface of the substrate well.

[0062] In other embodiments, the material of the cover layer is different from the material of the hard mask layer, and the material of the cover layer includes a dielectric material; the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0063] In other embodiments, the method for forming the cover layer includes: forming a first dielectric material layer on the surface of the substrate, wherein the top surface of the first dielectric material layer is higher than the top surface of the hard mask layer; planarizing the first dielectric material layer until the top surface of the hard mask layer is exposed; and after the planarization process, etching back the first dielectric material layer.

[0064] In this embodiment, before forming the cover layer 203, a second protective layer 204 is also formed on the surface of the substrate. The material of the second protective layer 204 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride.

[0065] The second protective layer 204 is used to protect the surface of the fin 201 and reduce the etching damage to the fin 201 when the covering layer 203 is removed later.

[0066] The material of the second protective layer 204 includes a carbon-containing material, wherein the percentage concentration of carbon atoms ranges from 15% to 80%.

[0067] The formation process of the second protective layer 204 includes atomic layer deposition (ALD) or chemical vapor deposition (CVD). ALD or CVD processes offer good shape retention, facilitating the formation of a uniform material film.

[0068] In this embodiment, the cover layer 203 also exposes a portion of the second protective layer 204 on the surface of the hard mask layer 202.

[0069] In this embodiment, before removing the hard mask layer 202, please refer to... Figure 5 .

[0070] Please refer to Figure 5 After the cover layer 203 is formed, and before the hard mask layer 202 is removed, the exposed second protective layer 204 is also removed, exposing part of the surface of the hard mask layer 202.

[0071] The process of removing the second protective layer 204 exposed by the cover layer 203 includes one or a combination of dry etching and wet etching processes.

[0072] In this embodiment, the process of removing the second protective layer 204 exposed by the cover layer 203 includes a plasma etching process. The process parameters of the plasma etching process include: etching gases including carbon fluoride, oxygen, and hydrofluoric acid; no bias voltage or low-frequency bias voltage; and the power range of the low-frequency bias voltage being less than or equal to 100 watts. The use of no bias voltage or low-frequency bias voltage in the plasma etching process helps to reduce etching damage to the surface of the fin.

[0073] Please refer to Figure 6 Using the cover layer 203 as a mask, the hard mask layer 202 is removed.

[0074] The process for removing the hard mask layer 202 includes one or a combination of dry etching and wet etching. In this embodiment, the process for removing the hard mask layer 202 is a wet etching process. In the wet etching process, the etching solution includes phosphoric acid.

[0075] The etching selectivity range for the hard mask layer 202 and the fin 201 in the process of removing the hard mask layer 202 is greater than 10:1. The purpose of selecting this etching selectivity range is to reduce etching damage to the fin 201 during the process of removing the hard mask layer 202.

[0076] In another embodiment, the process for removing the hard mask layer includes a remote plasma process. The remote plasma process helps reduce etching damage to the fin surface.

[0077] Please refer to Figure 7 After removing the hard mask layer 202, remove the cover layer 203.

[0078] In this embodiment, the process for removing the capping layer 203 is a gray-hair etching process. In other embodiments, the process for removing the capping layer 203 includes one or a combination of dry etching and wet etching processes.

[0079] Subsequently, after removing the covering layer 203, a first protective layer is formed on the surface of the fin 201.

[0080] In this embodiment, after removing the cover layer 203 and before forming the first protective layer, the second protective layer 204 on the substrate surface is also removed to expose the surface of the fin 201.

[0081] The process for removing the second protective layer 204 from the substrate surface includes one or a combination of dry etching and wet etching processes.

[0082] In this embodiment, the process of removing the second protective layer 204 on the substrate surface includes a plasma etching process. The process parameters of the plasma etching process include: the etching gas includes a first etching gas, which includes a fluorine-containing, chlorine-containing, and bromine-containing gas.

[0083] In other embodiments, the etching gas may also include a second etching gas, which may include one or more of sulfur oxides, oxygen, argon, helium, and carbon dioxide.

[0084] Please refer to Figure 8 After removing the hard mask layer 202, an epitaxial growth process is used to form a first protective layer 205 on the surface of the fin 201.

[0085] In this embodiment, specifically, after removing the second protective layer 204 from the substrate surface, an epitaxial growth process is used to form a first protective layer 205 on the surface of the fin 201.

[0086] Since the hard mask layer 202 has been removed before the formation of the first protective layer 205, the top surface of the fin 201 is exposed. During the formation of the first protective layer 205 on the surface of the fin 201 using the epitaxial growth process, the surface of the fin 201 has uniform epitaxial growth points of the first protective layer 205 material, which helps to improve the uniformity of the formed first protective layer 205 and avoids the etching damage to the fin 201 that may be introduced by the etching process in the epitaxial growth process, thereby improving the process window.

[0087] In this embodiment, the formation process of the first protective layer 205 includes a selective epitaxial growth process, which includes multiple film formation processes. Each film formation process includes: forming a material film and an etching process after forming the material film.

[0088] In another embodiment, the formation process of the first protective layer 205 includes a non-selective epitaxial growth process.

[0089] The material of the first protective layer 205 includes silicon.

[0090] In this embodiment, the first protective layer 205 is a single layer. The first protective layer 205 is used to reduce the surface state density of the fin 201 and improve the performance of the device. Simultaneously, the first protective layer 205 also provides material for the subsequent formation of the gate oxide layer. In other embodiments, the first protective layer can be multiple layers.

[0091] In another embodiment, the first protective layer includes a protective material layer and a sacrificial layer located on the protective material layer; the protective material layer is made of silicon; the sacrificial layer is made of a dielectric material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. The sacrificial layer serves to protect the protective material layer during the subsequent etching process to form the isolation structure layer. The protective material layer reduces the surface state density of the fins, thereby improving device performance.

[0092] Please refer to Figure 9 After the first protective layer 205 is formed, an isolation structure layer 206 is formed on the surface of the substrate. The isolation structure layer 206 is located on a portion of the sidewall of the fin 201, and the top surface of the isolation structure layer 206 is lower than the top surface of the fin 201.

[0093] The material of the isolation structure layer 206 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the material of the isolation structure layer 206 is silicon oxide.

[0094] The method for forming the isolation structure layer 206 includes: forming a second dielectric material layer on the surface of the substrate, the dielectric material layer being higher than the top surface of the fin 201; planarizing the second dielectric material layer until the top surface of the fin 201 is exposed; and after the planarization process, etching back the second dielectric material layer until the top surface of the second dielectric material layer is lower than the top surface of the fin 201. Specifically, in this embodiment, the top surface of the isolation structure layer 206 is higher than the top surface of the bottom structure I and lower than the top surface of the epitaxial layer II.

[0095] In this embodiment, after forming the isolation structure layer 206, the method further includes: oxidizing the surface of the first protective layer 205 to form a protective material layer (not shown in the figure) and a gate oxide layer (not shown in the figure) located on the protective material layer; the thickness of the protective material layer ranges from 1 angstrom to 15 angstroms. Specifically, the protective material layer is used to reduce the surface state density of the fin 201 to improve the performance of the device.

[0096] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a base, a fin located on a portion of the surface of the base, and a hard mask layer located on the top surface of the fin; Remove the hard mask layer; After removing the hard mask layer, an epitaxial growth process is used to form a first protective layer on the surface of the fin. After the first protective layer is formed, an isolation structure layer is formed on the surface of the substrate. The isolation structure layer is located on a portion of the sidewall of the fin, and the top surface of the isolation structure layer is lower than the top surface of the fin. After the isolation structure layer is formed, the surface of the first protective layer is oxidized to form a protective material layer and a gate oxide layer on the protective material layer.

2. The semiconductor structure formation method according to claim 1, characterized in that, The method for removing the hard mask layer includes: forming a cover layer on the surface of the substrate, the cover layer exposing the top of the hard mask layer; removing the hard mask layer using the cover layer as a mask; and removing the cover layer after removing the hard mask layer.

3. The semiconductor structure formation method as described in claim 2, characterized in that, Before forming the cover layer, the method further includes forming a second protective layer on the substrate surface.

4. The semiconductor structure formation method as described in claim 3, characterized in that, The material of the second protective layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

5. The semiconductor structure formation method as described in claim 4, characterized in that, The material of the second protective layer includes a carbon-containing material, wherein the percentage concentration of carbon atoms ranges from 15% to 80%.

6. The semiconductor structure formation method according to claim 3, characterized in that, The formation process of the second protective layer includes atomic layer deposition or chemical vapor deposition.

7. The semiconductor structure formation method according to claim 3, characterized in that, The overlay layer also exposes a portion of the second protective layer on the surface of the hard mask layer. After the overlay layer is formed and before the hard mask layer is removed, the process further includes: removing the exposed second protective layer to expose a portion of the surface of the hard mask layer.

8. The semiconductor structure formation method according to claim 7, characterized in that, The process of removing the second protective layer exposed by the capping layer includes one or a combination of dry etching and wet etching processes.

9. The semiconductor structure formation method as described in claim 8, characterized in that, The process for removing the second protective layer exposed by the capping layer includes a plasma etching process. The process parameters of the plasma etching process include: etching gas including carbon fluoride, oxygen, and hydrofluoric acid; no bias voltage or low-frequency bias voltage; and the power range of the low-frequency bias voltage being less than or equal to 100 watts.

10. The semiconductor structure formation method as described in claim 9, characterized in that, After removing the cover layer and before forming the first protective layer, the method further includes: removing the second protective layer from the substrate surface to expose the fin surface.

11. The semiconductor structure formation method according to claim 10, characterized in that, The process for removing the second protective layer from the substrate surface includes one or a combination of dry etching and wet etching processes.

12. The semiconductor structure formation method according to claim 10, characterized in that, The process for removing the second protective layer from the substrate surface includes a plasma etching process. The process parameters of the plasma etching process include: the etching gas includes a first etching gas, which includes gases containing fluorine, chlorine, and bromine.

13. The semiconductor structure formation method according to claim 12, characterized in that, The etching gas also includes a second etching gas, which comprises one or more of sulfur oxides, oxygen, argon, helium, and carbon dioxide.

14. The semiconductor structure formation method according to claim 2, characterized in that, The material of the cover layer is different from that of the hard mask layer. The material of the cover layer includes spin-coated carbon and bottom anti-reflective material.

15. The semiconductor structure formation method according to claim 2, characterized in that, The material of the cover layer is different from the material of the hard mask layer. The material of the cover layer includes a dielectric material. The dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

16. The semiconductor structure formation method as described in claim 15, characterized in that, The method for forming the cover layer includes: forming a dielectric material layer on the surface of the substrate, wherein the top surface of the dielectric material layer is higher than the top surface of the hard mask layer; planarizing the dielectric material layer until the top surface of the hard mask layer is exposed; and after planarizing the dielectric material layer, etching back the dielectric material layer.

17. The semiconductor structure formation method according to claim 1, characterized in that, The process for removing the hard mask layer includes one or a combination of dry etching and wet etching.

18. The semiconductor structure formation method as described in claim 17, characterized in that, The etching selectivity ratio for the hard mask layer and the fin is greater than 10:1 in the process of removing the hard mask layer.

19. The semiconductor structure formation method as described in claim 17, characterized in that, The process for removing the hard mask layer includes a remote plasma process.

20. The semiconductor structure formation method according to claim 1, characterized in that, The formation process of the first protective layer includes a selective epitaxial growth process, which includes multiple film formation processes. Each film formation process includes: forming a material film and an etching process after forming the material film.

21. The semiconductor structure formation method according to claim 1, characterized in that, The material of the fin includes silicon, germanium-silicon, or a combination of both.

22. The semiconductor structure formation method according to claim 1, characterized in that, The material of the first protective layer includes silicon.

23. The semiconductor structure formation method according to claim 22, characterized in that, The thickness of the protective material layer ranges from 1 angstrom to 15 angstroms.

24. The semiconductor structure formation method according to claim 1, characterized in that, The first protective layer includes a protective material layer and a sacrificial layer located on the protective material layer; the material of the protective material layer includes silicon; the material of the sacrificial layer includes a dielectric material, the dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

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