Display panel, display device and manufacturing method of display panel

Abstract

Embodiments of the present application provide a display panel, a display device and a manufacturing method of the display panel. The display panel comprises a first thin film transistor and a second thin film transistor. The first thin film transistor comprises a first substrate and a first active layer, a first gate insulating layer, a first gate layer and a first dielectric interlayer in sequence. The second thin film transistor comprises a second active layer, a second gate insulating layer, a second gate layer and a second dielectric interlayer in sequence on one side of the first dielectric interlayer. The first active layer is a polycrystalline silicon semiconductor, and the second active layer is an oxide semiconductor. The first dielectric interlayer is provided with a third via hole extending into the first gate insulating layer. The annealing process is performed through the third via hole before the second thin film transistor is formed, so that the hydrogen and high-temperature process of the annealing process do not affect the performance of the second thin film transistor device, and the stability of the second thin film transistor device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panels, in particular to a display panel, a display device and a manufacturing method of the display panel. BACKGROUND

[0002] Low Temperature Polycrystalline Silicon (LTPS) and oxide semiconductor (Oxide) are two kinds of semiconductors that are highly concerned in the display industry, and each has its own advantages. LTPS has the advantages of high mobility and fast charging, and is usually applied in small and medium-sized display devices. Oxide has the advantages of low leakage current, simple structure and low cost, and is usually applied in medium and large-sized display devices. If the advantages of the two materials can be combined together to form an LTPO (Low Temperature Polycrystalline Oxide) product, the display panel can have the characteristics of strong driving ability and low power consumption at the same time, and can be suitable for high-frequency display and low-frequency display, so that the user experience of the display product can be greatly improved.

[0003] In the related art, the device characteristics of LTPS are improved by a CNT Anneal (Contact Anneal) process. The CNT Anneal process improves the H (hydrogen) and high-temperature process in the LTPS process, which affects the H (hydrogen) process of the Oxide. The H (hydrogen) and Doping (doping) ions diffuse to the Oxide channel, so that the device stability of the Oxide is poor. Therefore, it is necessary to improve the device stability of the oxide semiconductor thin film transistor in the LTPO display panel. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a display panel, a display device and a manufacturing method of the display panel, so as to improve the device stability of the oxide semiconductor thin film transistor in the LTPO display panel. The specific technical solutions are as follows:

[0005] The first aspect of the present application provides a display panel, comprising a display area and a non-display area, wherein the display area comprises at least a plurality of first thin film transistors and second thin film transistors arranged at intervals along the length direction of the display panel.

[0006] The first thin film transistor comprises at least a first substrate and a first active layer, a first gate insulating layer, a first gate layer and a first dielectric layer interlayer arranged in sequence away from the first substrate.

[0007] The second thin film transistor at least comprises, in sequence from the side of the first interlayer dielectric layer away from the first substrate, a second active layer, a second gate insulating layer, a second gate layer, and a second interlayer dielectric layer;

[0008] The second interlayer dielectric layer is provided with a first via hole and a second via hole, the first thin film transistor further comprises a first source electrode and a first drain electrode electrically connected to the first active layer through the first via hole, the first via hole extends to the surface or the interior of the first active layer away from the first substrate, and the material of the first active layer comprises a polysilicon semiconductor;

[0009] The second thin film transistor further comprises a second source electrode and a second drain electrode electrically connected to the second active layer through the second via hole, the second via hole extends to the surface or the interior of the second active layer away from the first substrate, and the material of the second active layer comprises an oxide semiconductor;

[0010] The first interlayer dielectric layer of the display area is provided with a plurality of third via holes, the third via holes extend into the first gate insulating layer, and the second gate insulating layer and the second interlayer dielectric layer cover the third via holes.

[0011] In some embodiments of the present application, at least part of the third via hole is located on the surface of the first active layer away from the first substrate.

[0012] In some embodiments of the present application, the third via hole partially overlaps the first via hole, or the third via hole surrounds the first via hole.

[0013] In some embodiments of the present application, the non-display area of the display panel further comprises a peripheral area and a bending area, the peripheral area comprises a fourth via hole, and the bending area comprises a fifth via hole, in the direction close to the first substrate, the fourth via hole and the fifth via hole sequentially penetrate the second interlayer dielectric layer and the second gate insulating layer, and extend into the first substrate.

[0014] In some embodiments of the present application, the side of the first gate layer away from the first substrate is further provided with a storage capacitor electrode, a third gate insulating layer is arranged between the storage capacitor electrode and the first gate layer, and the storage capacitor electrode and the first gate layer constitute a storage capacitor.

[0015] In some embodiments of the present application, a first buffer layer is arranged between the first interlayer dielectric layer and the second active layer, a sixth via hole is arranged at a position opposite to the third via hole of the first buffer layer, and the sixth via hole is in communication with the third via hole.

[0016] In some embodiments of the present application, the first active layer and the first substrate further comprise a plurality of first shielding metals arranged along the length direction of the display panel, the first shielding metals are arranged opposite to the first gate layer, and the first shielding metals have a projection on the first substrate that is greater than or equal to the projection of the first gate layer on the first substrate.

[0017] In some embodiments of the present application, the first active layer and the first substrate further comprise a second shielding metal, and the second shielding metal has a projection on the first substrate that is greater than or equal to the projection of the fourth via on the first substrate.

[0018] The second aspect of the present application provides a display device, which comprises the display panel of any one of the embodiments of the first aspect.

[0019] The third aspect of the present application provides a manufacturing method of a display panel, which is used to manufacture the display panel of any one of the embodiments of the first aspect, and comprises the following steps:

[0020] forming a first substrate;

[0021] forming, in sequence, a first active layer, a first gate insulating layer, a first gate layer, and a first interlayer dielectric layer on a side away from the first substrate;

[0022] forming a plurality of third vias in the first interlayer dielectric layer of the display area by using a first mask, and the third vias extend into the first gate insulating layer;

[0023] forming, in sequence, a second active layer, a second gate insulating layer, and a second interlayer dielectric layer on the first interlayer dielectric layer;

[0024] forming a first via and a second via in the second interlayer dielectric layer of the display area by using a second mask, or forming the first via in the second interlayer dielectric layer of the display area by using the second mask and then forming the second via in the second interlayer dielectric layer of the display area by using a third mask;

[0025] the first source electrode and the first drain electrode are electrically connected to the first active layer through the first via, and the second source electrode and the second drain electrode are electrically connected to the second active layer through the second via.

[0026] In some embodiments of the present application, the non-display area comprises a peripheral area and a bending area, and the step of forming the third via further comprises the following steps:

[0027] Forming a first part of a fourth via in the first interlayer dielectric layer in the peripheral region and a first part of a fifth via in the first interlayer dielectric layer in the bending region through the first mask, the first part of the fourth via and the first part of the fifth via have the same extension depth as the third via.

[0028] In some embodiments of the present application, the step of forming the first via or the steps of forming the first via and the second via further comprise the following steps:

[0029] Forming a second part of the fourth via in the peripheral region of the non-display region and a second part of the fifth via in the bending region of the non-display region, the second part of the fourth via and the second part of the fifth via communicate with the first part of the fourth via and the first part of the fifth via and extend into the first substrate. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other embodiments can also be obtained by those skilled in the art based on these drawings.

[0031] Figure 1 A schematic diagram of a display panel in a first embodiment provided by the embodiments of the present application;

[0032] Figure 2 A schematic diagram of a display panel in a second embodiment provided by the embodiments of the present application;

[0033] Figure 3a A top view of a display panel in an embodiment of the present application;

[0034] Figure 3b A top view of another display panel in an embodiment of the present application;

[0035] Figure 4 A schematic diagram of a display panel in a third embodiment provided by the embodiments of the present application;

[0036] Figure 5 A schematic diagram of a display panel in a fourth embodiment provided by the embodiments of the present application;

[0037] Figure 6 A schematic diagram of a display panel in a fifth embodiment provided by the embodiments of the present application;

[0038] Figure 7 A schematic diagram of a display panel in a sixth embodiment provided by the embodiments of the present application;

[0039] Figure 8 A schematic diagram of the display panel provided by the embodiments of the present application in the seventh embodiment;

[0040] Figure 9 A schematic diagram of the display panel provided by the embodiments of the present application in the eighth embodiment;

[0041] Figure 10 A schematic diagram of the display panel provided by the embodiments of the present application in the ninth embodiment;

[0042] Figure 11 A schematic diagram of the display panel provided by the embodiments of the present application in the tenth embodiment;

[0043] Figure 12 A schematic diagram of the display panel provided by the embodiments of the present application in the eleventh embodiment;

[0044] Figure 13 A schematic diagram of the display panel provided by the embodiments of the present application in the twelfth embodiment;

[0045] Figure 14 A schematic diagram of the display panel provided by the embodiments of the present application in the thirteenth embodiment.

[0046] The reference signs are as follows:

[0047] First substrate 100, first PI substrate 110, first barrier layer 120, second PI substrate 130, third barrier layer 140, fourth barrier layer 150, second buffer layer 160;

[0048] First thin film transistor 200, first active layer 210, first gate insulating layer 220, first gate layer 230, first dielectric interlayer insulating layer 240, first via hole 250, first source 250a, first drain 250b, storage capacitor electrode 260, third gate insulating layer 270, first buffer layer 280, first shielding metal 290;

[0049] Second thin film transistor 300, second active layer 310, second gate insulating layer 320, second gate layer 330, second dielectric interlayer insulating layer 340, second via hole 350, second source 350a, second drain 350b;

[0050] Third via hole 400;

[0051] Peripheral region 500, fourth via hole 510, second shielding metal 520, source-drain metal line 530;

[0052] Bending region 600, fifth via hole 610;

[0053] Area a. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0055] like Figures 1-2 As shown, in a first aspect, the present application provides a display panel, comprising a display area and a non-display area. The display area comprises at least a plurality of first thin film transistors 200 and second thin film transistors 300 spaced apart along the length of the display panel. The first thin film transistors 200 comprise at least a first substrate 100 and a first active layer 210, a first gate insulating layer 220, a first gate layer 230, and a first dielectric interlayer insulating layer 240 sequentially disposed in a direction away from the first substrate 100. The second thin film transistors 300 comprise at least a second active layer 310, a second gate insulating layer 320, a second gate layer 330, and a second dielectric interlayer insulating layer 340 sequentially disposed on one side of the first dielectric interlayer insulating layer 240 in a direction away from the first substrate 100. The second dielectric interlayer insulating layer 340 is provided with a first via 250 and a second via 350. The first active layer 210 is electrically connected to the first source electrode 250a and the first drain electrode 250b through the first via 250. The first via 250 extends to the surface of the first active layer 210 away from the first substrate 100 or the interior thereof. The first active layer 210 is made of polycrystalline silicon semiconductor. The second active layer 310 is electrically connected to the second source electrode 350a and the second drain electrode 350b through the second via 350. The second via 350 extends to the surface of the second active layer 310 away from the first substrate 100 or the interior thereof. The second active layer 310 is made of an oxide semiconductor. The first dielectric interlayer insulating layer 240 in the display area is provided with a plurality of third vias 400. The third vias 400 extend into the first gate insulating layer 220 and are covered by the second gate insulating layer 320 and the second dielectric interlayer insulating layer 340.

[0056] In this embodiment, the first thin film transistor 200 includes a first active layer 210, and the material of the first active layer 210 includes a polysilicon (poly silicon) semiconductor, specifically a low-temperature polycrystalline silicon semiconductor (LTPS). The second thin film transistor 300 includes a second active layer 310, and the material of the second active layer 310 includes an oxide semiconductor (Oxide), specifically IGZO (Indium Gallium Zinc Oxide). The first thin film transistor (LTPS TFT) 200 and the second thin film transistor (Oxide TFT) 300 are combined to form an LTPO (Low Temperature Polycrystalline Oxide) product. The LTPO display panel has the characteristics of strong driving capability and low power consumption. CNTAnneal is used to improve the device characteristics of LTPS, but in this process, the high H (hydrogen) and high temperature process will affect the low H (hydrogen) process of Oxide, and the H (hydrogen) and Doping (doping) ions will diffuse into the Oxide channel, making the device stability of Oxide worse; therefore, before forming the second thin film transistor 300, a plurality of third vias 400 are opened on the first dielectric interlayer insulating layer 240 and extended into the first gate insulating layer 220, and a CNT Anneal process is performed through the third vias 400, so that the hydrogen at the interface between the first gate insulating layer 220 and the first active layer 210 escapes through the third vias 400, thereby increasing the subthreshold swing of the first thin film transistor 200 and improving the display effect of the LTPO display panel; it can be understood that the second thin film transistor 300 is not formed at this time, and the CNT Anneal process will not affect the oxide semiconductor. After the CNT annealing process is completed, the second active layer 310, the second gate insulating layer 320, the second gate layer 330, and the second dielectric interlayer insulating layer 340 are sequentially formed, followed by the first via 250 and the second via 350. Furthermore, the orthographic projection of the third via 400 in the first active layer 210 can be staggered with respect to the first active layer 210.

[0057] In the related art, a CNT Anneal process is performed after forming the second dielectric interlayer insulating layer 340, that is, after forming the second thin-film transistor (Oxide TFT) 300, a CNT Anneal process is performed through the first via 250, and then the second via 350 is opened. In this application, the CNT Anneal process is advanced. After the first via 250 is opened, there is no need to perform a CNT Anneal process to improve the characteristics of the LTPS TFT device. Instead, only a buffered oxide etchant (BOE, Buffered Oxide Etch) etching process is required to improve the contact resistance between the first active layer 210 and the first source 250a and the first drain 250b, thereby not affecting the device performance of the second thin-film transistor (Oxide TFT) 300. Specifically, CNT Anneal is mainly used to improve the characteristics of the driving transistor (Driving TFT). The first thin-film transistor 200 is described below using the driving transistor as an example.

[0058] In the related art, since the CNT Anneal process affects the performance of oxide TFT devices, to improve the performance of oxide TFT devices, on the one hand, it is necessary to appropriately increase the channel length of the oxide TFT, and on the other hand, it is necessary to use a dual-gate oxide TFT, that is, the oxide TFT includes a bottom gate and a top gate. The present application uses a third via 400 to pre-place the CNT Anneal process without affecting the performance of the oxide TFT device. It can reduce the channel size of the bottom gate and top gate of the dual-gate oxide TFT. Even while reducing the channel size of the top gate of the oxide TFT, it can remove the bottom gate of the oxide TFT and its corresponding bottom gate signal line, retaining only the top gate, that is, retaining only the second gate layer 330, effectively increasing the aperture ratio, reducing power consumption, and improving display quality and yield.

[0059] The first via 250 may extend to a surface of the first active layer 210 away from the first substrate 100, and the first source electrode 250a or the first drain electrode 250b may overlap the surface of the first active layer 210 through the first via 250 to form an electrical connection. Alternatively, the first via 250 may extend into the interior of the first active layer 210, and the first active layer 210 may have different doping concentrations at different depths in a direction perpendicular to the surface of the first substrate 100. The first source electrode 250a and the first drain electrode 250b may be electrically connected to the interior of the first active layer 210 through the first via 250. That is, the first source electrode 250a and the first drain electrode 250b may contact the first active layer 210 at various depths to form a sidewall overlap, effectively reducing contact resistance.

[0060] The second via hole 350 can extend to the surface of the second active layer 310 away from the first substrate 100, and the second source electrode 350a and the second drain electrode 350b are electrically connected to the surface of the second active layer 310 through the second via hole 350. Alternatively, the second via hole 350 extends to the inside of the second active layer 310, and the doping concentration of the second active layer 310 is different at different depths in the direction perpendicular to the surface of the first substrate 100. The second source electrode 350a and the second drain electrode 350b are electrically connected to the inside of the second active layer 310 through the second via hole 350, that is, the second source electrode 350a and the second drain electrode 350b are in contact with the sidewalls of the second active layer 310 at different depths to form a sidewall overlap, thereby effectively reducing the contact resistance.

[0061] As shown in Figures 11-12 , further, the second source electrode 350a and the second drain electrode 350b can be in surface overlap with the second active layer 310, that is, the second source electrode 350a and the second drain electrode 350b are connected to the surface of the second active layer 310. In this way, the overall structure of the second active layer 310 can be maintained, and the yield can be improved.

[0062] As shown in Figure 1 , Figure 2 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 11 , and Figure 12 In some embodiments, at least part of the third via hole 400 is located away from the surface of the first substrate 100.

[0063] In the present embodiment, considering the actual situation of pixel design, when the pixel PPI (Pixels Per Inch, pixel density unit) is high, the area of a single sub-pixel is small, and therefore the space available for the third via hole 400 is also small. For different pixel designs, the third via hole 400 can have different design forms. The third via hole 400 is partially located on the surface of the first active layer 210 or entirely located on the surface of the first active layer 210, that is, the orthographic projection of the third via hole 400 on the first active layer 210 falls on the first active layer 210, or the orthographic projection of the third via hole 400 on the first active layer 210 entirely falls on the first active layer 210.

[0064] It should be noted that when the third via hole 400 is partially located on the first active layer 210, the part of the third via hole 400 not located on the first active layer 210 can also extend below the first gate insulating layer 220.

[0065] Further, when the third via hole 400 does not overlap with the first active layer 210 at all, the third via hole 400 can also extend below the first gate insulating layer 220.

[0066] In order to ensure that the third via hole 400 and the first active layer 210 are overlapped or partially overlapped, the area of ​​the first active layer 210 corresponding to the third via hole 400 can be increased, such as Figure 3a As shown, the area of ​​the first active layer 210 at the square area a is increased to ensure that the third via hole 400 is overlapped or partially overlapped with the first active layer 210. Alternatively, as shown in FIG. Figure 3b As shown, the size of the third via hole 400 is reduced to ensure that the third via hole 400 overlaps with the first active layer 210 .

[0067] like Figures 6-9 As shown, in some embodiments, the third via hole 400 partially overlaps with the first via hole 250 , or the third via hole 400 surrounds the first via hole 250 .

[0068] In this embodiment, the third via 400 and the first via 250 partially overlap, which can reduce the actual etching area of ​​the first via 250 and increase the etching speed, thereby improving the manufacturing efficiency of the display panel. In addition, the third via 400 does not need to wrap around the first via 250, so the area of ​​the third via 400 is relatively small, but the area of ​​the overlapping portion may fluctuate due to process stability. Since the third via 400 surrounds the first via 250, the first via 250 only needs to etch two layers, the second dielectric interlayer insulating layer and the second gate insulating layer, to achieve connectivity between the first via 250 and the third via 400, reducing the etching depth of the first via 250, thereby improving the manufacturing efficiency of the display panel.

[0069] like Figures 1-2 and Figures 4-13 As shown, in some embodiments, the plurality of third vias 400 can be located in one, two, or more of the positions described in the above embodiments. The display panel includes a plurality of third vias 400, wherein the third vias 400 are at least partially located on a surface of the first active layer 210 away from the first substrate 100, or the third vias 400 do not contact the first active layer 210; the third vias 400 and the first vias 250 can partially overlap, or the third vias 400 surround the first vias 250.

[0070] In this embodiment, the position of the third via hole 400 is a combination of one or more of the above. The specific number and position in the pixel can be determined according to the effect of improving the characteristics of the first thin film transistor 200 and the pixel design margin.

[0071] like Figures 1-2 and Figures 4-13As shown, in some embodiments, the non-display area of ​​the display panel also includes a peripheral (BSM) area 500 and a bending (Bending) area 600, the peripheral area 500 includes a fourth via 510, and the bending area 600 includes a fifth via 610. Along the direction close to the first substrate 100, the fourth via 510 and the fifth via 610 sequentially penetrate the second dielectric interlayer insulating layer 340 and the second gate insulating layer 320, and extend into the first substrate 100.

[0072] In this embodiment, due to the high PPI requirement of the display area, some routing lines need to be set in the non-display area, and a fourth via 510 is set in the peripheral area 500 of the non-display area. The fourth via 510 is used to set the source-drain metal line 530, and the source-drain metal line 530 is used to provide a Vdd voltage signal.

[0073] In addition, in the flexible display panel, the display panel needs to be connected to the circuit in the bending area 600, and the fifth via 610 is used to electrically connect the peripheral metal wiring with the flexible circuit board; further, multiple fifth vias 610 are opened in the bending area 600 to reduce bending stress and improve bending performance.

[0074] like Figures 1-2 and Figures 4-13 As shown, in some embodiments, a storage capacitor electrode 260 is further provided on the side of the first gate layer 230 away from the first substrate 100, and a third gate insulating layer 270 is provided between the storage capacitor electrode 260 and the first gate layer 230, and the storage capacitor electrode 260 and the first gate layer 230 constitute a storage capacitor.

[0075] In this embodiment, the storage capacitor electrode 260 and the first gate layer 230 constitute a storage capacitor, which is used to store data signals. When the scanning signal pulse of the pixel unit ends, the storage capacitor can still maintain the voltage of the first gate layer 230 of the driving transistor, that is, the storage capacitor can still maintain the voltage of the first gate layer 230 of the first thin film transistor 200.

[0076] like Figure 13 As shown, in some embodiments, a first buffer layer 280 is provided between the first dielectric interlayer insulating layer 240 and the second active layer 310 , a sixth via is provided at a position opposite to the first buffer layer 280 and the third via 400 , and the sixth via is connected to the third via 400 .

[0077] In this embodiment, providing the first buffer layer 280 can reduce the diffusion of H in the LTPS DTFT to the second thin film transistor, thereby improving the performance of the second thin film transistor. In addition, providing the first buffer layer 280 can absorb stress by deforming when the display panel is subjected to an impact, especially enhancing the protection of the flexible display panel. CNT Anneal is performed after the formation of the first buffer layer 280, that is, after the formation of the first buffer layer 280, CNT Anneal is performed through the sixth via hole and the third via hole 400 opposite to the sixth via hole. Since the sixth via hole and the third via hole 400 are located at the same position, the sixth via hole and the third via hole 400 can be opened simultaneously in one process after the first buffer layer 280 is produced.

[0078] It can be understood that the present application can also advance the CNT Anneal process to after the first dielectric interlayer insulating layer 240 is formed, that is, during the display panel manufacturing process, the first buffer layer 280 set between the first dielectric interlayer insulating layer 240 and the second active layer 310 is only used to cover the third via 400, and CNT Anneal is performed through the third via 400 before the first buffer layer 280 is formed.

[0079] like Figures 1-2 and Figures 4-13 As shown, in some embodiments, a plurality of first blocking metals 290 are further arranged between the first active layer 210 and the first substrate 100 and are spaced apart along the length direction of the display panel. The first blocking metals 290 are arranged opposite to the first gate layer 230, and the orthographic projection of the first blocking metal 290 on the first substrate 100 is greater than or equal to the orthographic projection of the first gate on the first substrate 100.

[0080] In this embodiment, the first blocking metal 290 is arranged opposite to the first gate layer 230, and the positive projection of the first blocking metal 290 on the first substrate 100 is greater than or equal to the positive projection of the first gate on the first substrate 100, so that the first gate layer 230 is shielded by the first blocking metal 290 to avoid being affected by external light, thereby avoiding the increase of photogenerated carriers and further avoiding fluctuations in the threshold voltage of the driving transistor.

[0081] like Figures 1-2 and Figures 4-13 As shown, in some embodiments, a second blocking metal 520 is further included between the first active layer 210 and the first substrate 100 , and the orthographic projection of the second blocking metal 520 on the first substrate 100 is greater than or equal to the orthographic projection of the fourth via 510 on the first substrate 100 .

[0082] In the embodiment, the second shielding metal 520 is arranged between the first active layer 210 and the first substrate 100, and the second shielding metal 520 is electrically connected to the source-drain metal line 530 through the fourth via hole 510. The first shielding metal 290 and the second shielding metal 520 are the same layer of metal, and the first shielding metal 290 is located in the light-emitting area. By applying a certain voltage to the first shielding metal 290, the floating gate effect of the LTPS DTFT can be improved. Generally, the first shielding metal 290 needs to be opened, and then the Vdd signal is input through the source-drain metal line 530. However, since the area of a single pixel of a high-PPI display panel is small, it is not suitable to open the via hole of the first shielding metal 290 in the light-emitting area. Therefore, the first shielding metal 290 is connected to the second shielding metal 520, and the second metal layer 520 is connected to the source-drain metal line 530 through the fourth via hole 510. The second shielding metal 520 is used for shielding light and providing the VDD signal to the first shielding metal 290 through the source-drain metal line 530.

[0083] Figures 1-13 In the embodiment, the filling metal at the via hole of the peripheral area 500 and the bending area 600 is the source-drain metal line 530. The source-drain metal line 530 is made in the same layer as the first source 250a and the first drain 250b of the first thin film transistor 200 and the second source 350a and the second drain 350b of the second thin film transistor 300.

[0084] In order to reduce the resistance of the first source 250a and the first drain 250b of the first thin film transistor 200 and the resistance of the second source 350a and the second drain 350b of the second thin film transistor 300, and to improve the IR drop, in the existing OLED process, the source-drain metal line 530 is generally made in a layer different from the first source 250a and the first drain 250b and the second source 350a and the second drain 350b, that is, a layer of metal is formed on the basis of the original first source 250a and the first drain 250b and the second source 350a and the second drain 350b, that is, the source-drain metal line 530, as shown in FIG. 4. At this time, the filling metal at the via hole of the peripheral area 500 and the bending area 600 is the source-drain metal line 530. Figure 14 The second aspect of the present application provides a display device, which comprises the display panel in any one of the embodiments of the first aspect.

[0085] In the embodiment, the first thin film transistor 200 in the display panel of the display device includes a first active layer 210, the material of the first active layer 210 includes a polycrystalline silicon semiconductor, and specifically can be a low-temperature polycrystalline silicon semiconductor (LTPS). The second thin film transistor 300 includes a second active layer 310, the material of the second active layer 310 includes an oxide semiconductor (Oxide). The first thin film transistor 200 (LTPS TFT) and the second thin film transistor 300 (Oxide TFT) are combined to form an LTPO (Low Temperature Polycrystalline Oxide) product. The LTPO display panel has the characteristics of strong driving capability and low power consumption. CNT Anneal is used to improve the device characteristics of LTPS. However, the process of multi-H (hydrogen) and high-temperature process will affect the process of low-H (hydrogen) of Oxide. H (hydrogen) and Doping (doping) ions will diffuse to the Oxide channel, so that the device stability of Oxide becomes poor. Therefore, before the second thin film transistor 300 is formed, a plurality of third vias 400 are formed on the first dielectric interlayer insulation layer 240 and extend into the first gate insulation layer 220. The CNT Anneal process is performed through the third via 400, so that the hydrogen at the interface between the first gate insulation layer 220 and the first active layer 210 escapes through the third via 400, increases the subthreshold swing of the first thin film transistor 200, and improves the display effect of the LTPO display panel. It can be understood that at this time, the second thin film transistor 300 has not been formed, and the CNT Anneal process will not affect the oxide semiconductor. After the CNT Anneal process is completed, the second active layer 310, the second gate insulation layer 320, the second gate layer 330 and the second dielectric interlayer insulation layer 340 are sequentially formed, and then the first via 250 and the second via 350 are formed. In the related art, the CNT Anneal process is performed after the second dielectric interlayer insulation layer 340 is formed, that is, the CNT Anneal process is performed through the first via 250 after the second thin film transistor (Oxide TFT) 300 is formed. In the embodiment, the CNT Anneal process is placed in front. After the first via 250 is opened, the CNT Anneal process is not needed to improve the device characteristics of the LTPS TFT. Only the buffered oxide etch (BOE, Buffered Oxide Etch) etching process is needed to improve the contact resistance between the first active layer 210 and the first source 250a and the first drain 250b, so as not to affect the device performance of the second thin film transistor (Oxide TFT) 300.

[0086] The third aspect of the present application provides a manufacturing method of a display panel, which is used to manufacture the display panel in any one of the embodiments of the first aspect.

[0087] The first substrate 100 is formed.

[0088] The first active layer 210, the first gate insulating layer 220, the first gate layer 230, and the first interlayer dielectric layer 240 are sequentially formed on the side away from the first substrate 100.

[0089] The third via hole 400 is formed in the first interlayer dielectric layer 240 of the display area by the first mask, and the third via hole 400 extends to the first gate insulating layer 220.

[0090] The second active layer 310, the second gate insulating layer 320, and the second interlayer dielectric layer 340 are sequentially formed on the first interlayer dielectric layer 240.

[0091] The first via hole 250 and the second via hole 350 are formed in the second interlayer dielectric layer 340 of the display area by the second mask, or the first via hole 250 is formed in the second interlayer dielectric layer 340 of the display area by the second mask, and then the second via hole 350 is formed in the second interlayer dielectric layer 340 of the display area by the third mask.

[0092] The first source electrode 250a and the first drain electrode 250b are electrically connected to the first active layer 210 through the first via hole 250, and the second source electrode 350a and the second drain electrode 350b are electrically connected to the second active layer 310 through the second via hole 350.

[0093] In the embodiment, the first dielectric interlayer 240 in the display area is provided with a plurality of third via holes 400 by the first mask, the third via holes 400 extend into the first gate insulating layer 220, and the CNT Anneal process is performed through the third via holes 400. The CNT Anneal process in the prior art is performed after the second dielectric interlayer 340 is formed, that is, the CNT Anneal process is moved from after the second thin film transistor 300 is formed to before the second thin film transistor 300 is formed, so as to avoid the influence of the multi-H (hydrogen) and high-temperature process on the low-H (hydrogen) process of the oxide in this process, and the H (hydrogen) and Doping (doping) ions cannot diffuse to the oxide channel, which is beneficial to improve the device stability of the second thin film transistor (oxide TFT) 300. Further, in the prior art, the CNT Anneal process affects the performance of the oxide TFT device. In order to improve the performance of the oxide TFT device, on the one hand, the channel length of the oxide TFT needs to be appropriately increased, and on the other hand, a double-gate oxide TFT, that is, the oxide TFT includes a bottom gate and a top gate, needs to be used. The CNT Anneal process moved by the third via hole 400 does not affect the performance of the oxide TFT device, can reduce the channel size of the bottom gate and the top gate of the double-gate oxide TFT, and even while reducing the channel size of the top gate of the oxide TFT, the bottom gate of the oxide TFT and the corresponding bottom gate signal line can be removed, and only the top gate, that is, only the second gate layer 330, is reserved, so as to effectively improve the aperture ratio, reduce power consumption, and improve display effect and yield.

[0094] In some embodiments, the non-display area includes a peripheral area 500 and a bending area 600, and the step of forming the third via hole 400 further includes the following steps:

[0095] The first part of the fourth via hole 510 is formed in the first dielectric interlayer 240 of the peripheral area 500 by the first mask, and the first part of the fifth via hole 610 is formed in the first dielectric interlayer 240 of the bending area 600, and the extension depth of the first part of the fourth via hole 510 and the first part of the fifth via hole 610 is consistent with that of the third via hole 400.

[0096] In the embodiment, the third via hole 400, the first part of the fourth via hole 510 and the first part of the fifth via hole 610 are opened by the first mask, and the same mask is used to open the three via holes, so as to reduce the process and improve the production efficiency.

[0097] In some embodiments, the following steps are further included in the step of forming the first via hole 250 or in the step of forming the first via hole 250 and the second via hole 350:

[0098] The second part of the fourth via hole 510 is formed in the peripheral area 500 of the non-display area, and the second part of the fifth via hole 610 is formed in the bending area 600 of the non-display area. The second part of the fourth via hole 510 and the second part of the fifth via hole 610 are in communication with the first part of the fourth via hole 510 and the first part of the fifth via hole 610, and extend into the first substrate 100.

[0099] In the present embodiment, the first via hole 250, the second part of the fourth via hole 510 and the second part of the fifth via hole 610 are opened by the second mask plate; or the second via hole 350, the second part of the fourth via hole 510 and the second part of the fifth via hole 610 are opened by the third mask plate. The purpose is to form the first via hole 250, the second part of the fourth via hole 510 and the second part of the fifth via hole 610 by etching once through the same second mask plate; or to form the second via hole 350, the second part of the fourth via hole 510 and the second part of the fifth via hole 610 by etching once through the same third mask plate, so as to simplify the etching process and improve the production efficiency.

[0100] Further, the fourth via hole 510 and the fifth via hole 610 have a large depth in the direction perpendicular to the first substrate 100, so the fourth via hole 510 and the fifth via hole 610 are divided into two processes.

[0101] Further, in the related art, the first via hole 250 is first opened, then CNT anneal is performed, and then boe etch is performed to etch the oxide layer on the surface of the first active layer 210 at the first via hole 250, so as to improve the contact resistance between the first active layer 210 and the first source electrode 250a and the first drain electrode 250b at the first via hole 250. Finally, the second via hole 350 is opened, the first source electrode 250a and the first drain electrode 250b are connected through the first via hole 250, and the second source electrode 350a and the second drain electrode 350b are connected through the second via hole 350. In this process, the boe etch etching process is separated from the connection of the source electrode and the drain electrode by the process of opening the second via hole 350, which is easy to cause further oxidation of the first active layer 210 due to long-time exposure.

[0102] The application preposes CNT Anneal, the first via hole 400 and the first part of the fourth via hole 510 and the first part of the fifth via hole 610 are opened synchronously, the first via hole 250 and the second via hole 350 and the second part of the fourth via hole 510 and the second part of the fifth via hole 610 are opened synchronously, which can save the process and improve the production efficiency. After the first via hole 250 and the second via hole 350 are opened synchronously, the first active layer 210 is etched by boe etch, and then the first source 250a and the first drain 250b are directly connected with the first active layer 210 through the first via hole 250, so that the time of the boe etch etching process and the process of the first source 250a and the first drain 250b connecting with the first active layer 210 through the first via hole 250 is shortened, the first active layer 210 is avoided, and the contact resistance of the first active layer 210 and the first source 250a and the first drain 250b is reduced.

[0103] In some embodiments, the first substrate 100 includes a first PI (Polyimide) substrate 110, a first barrier layer 120, a second PI substrate 130, a third barrier layer 140, a fourth barrier layer 150 and a second buffer layer 160 arranged in sequence.

[0104] In the embodiment, the first shielding metal 290 and the second shielding metal 520 are located between the third barrier layer 140 and the fourth barrier layer 150. Polyimide (PI) has excellent thermal performance, chemical stability, dielectric ability and mechanical properties, and is suitable as a substrate material of a display panel.

[0105] The above are only preferred embodiments of the present application, and are not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area, and the display area includes at least a plurality of first thin film transistors and second thin film transistors spaced apart along a length direction of the display panel; The first thin film transistor at least includes a first substrate and a first active layer, a first gate insulating layer, a first gate layer, and a first dielectric interlayer insulating layer sequentially arranged in a direction away from the first substrate; The second thin film transistor at least includes a second active layer, a second gate insulating layer, a second gate layer, and a second dielectric interlayer insulating layer sequentially arranged on one side of the first dielectric interlayer insulating layer in a direction away from the first substrate; The second dielectric interlayer insulating layer is provided with a first via hole and a second via hole, the first thin film transistor further includes a first source electrode and a first drain electrode electrically connected to the first active layer through the first via hole, the first via hole extends to a surface or an interior of the first active layer away from the first substrate, and the material of the first active layer includes a polycrystalline silicon semiconductor; The second thin film transistor further includes a second source electrode and a second drain electrode electrically connected to the second active layer through the second via hole; the second via hole extends to the surface or interior of the second active layer away from the first substrate, and the material of the second active layer includes an oxide semiconductor; The first dielectric interlayer insulating layer of the display area is provided with a plurality of third via holes, the third via holes extending into the first gate insulating layer, and the second gate insulating layer and the second dielectric interlayer insulating layer covering the third via holes.

2. The display panel according to claim 1, wherein: At least a portion of the third via hole is located on a surface of the first active layer away from the first substrate.

3. The display panel according to claim 2, wherein: The third via hole partially overlaps with the first via hole, or the third via hole surrounds the first via hole.

4. The display panel according to claim 1, wherein: The non-display area of ​​the display panel also includes a peripheral area and a bending area, the peripheral area includes a fourth via hole, and the bending area includes a fifth via hole. Along the direction close to the first substrate, the fourth via hole and the fifth via hole successively penetrate the second dielectric interlayer insulating layer and the second gate insulating layer, and extend into the first substrate.

5. The display panel according to any one of claims 1 to 4, characterized in that: A storage capacitor electrode is further provided on a side of the first gate layer away from the first substrate. A third gate insulating layer is provided between the storage capacitor electrode and the first gate layer. The storage capacitor electrode and the first gate layer form a storage capacitor.

6. The display panel according to any one of claims 1 to 4, characterized in that: A first buffer layer is provided between the first dielectric interlayer insulating layer and the second active layer. A sixth via hole is provided at a position of the first buffer layer opposite to the third via hole. The sixth via hole is connected to the third via hole.

7. The display panel according to any one of claims 1 to 4, characterized in that: Between the first active layer and the first substrate, there are also multiple first blocking metals arranged at intervals along the length direction of the display panel. The first blocking metals are arranged opposite to the first gate layer, and the orthographic projection of the first blocking metal on the first substrate is greater than or equal to the orthographic projection of the first gate layer on the first substrate.

8. The display panel according to claim 7, wherein: A second blocking metal is further provided between the first active layer and the first substrate, and an orthographic projection of the second blocking metal on the first substrate is greater than or equal to an orthographic projection of the fourth via hole on the first substrate.

9. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 8.

10. A method for manufacturing a display panel, for manufacturing the display panel according to any one of claims 1 to 8, characterized in that: The following steps are involved: forming a first substrate; On a side away from the first substrate, a first active layer, a first gate insulating layer, a first gate layer, and a first dielectric interlayer insulating layer are sequentially formed; A plurality of third via holes are provided in the first dielectric interlayer insulating layer of the display area through a first mask, wherein the third via holes extend into the first gate insulating layer; forming a second active layer, a second gate insulating layer, and a second dielectric interlayer insulating layer in sequence on the first dielectric interlayer insulating layer; forming a first via hole and a second via hole in the second dielectric interlayer insulating layer in the display area through a second mask, or forming a first via hole in the second dielectric interlayer insulating layer in the display area through a second mask and then forming a second via hole in the second dielectric interlayer insulating layer in the display area through a third mask; The first source electrode and the first drain electrode are electrically connected to the first active layer through the first via hole, and the second source electrode and the second drain electrode are electrically connected to the second active layer through the second via hole.

11. The method for manufacturing a display panel according to claim 10, wherein: The non-display area includes a peripheral area and a bending area, and the step of forming the third via hole further includes the following steps: The first mask is used to form the first part of the fourth via in the first dielectric interlayer insulating layer in the peripheral area, and the first part of the fifth via is formed in the first dielectric interlayer insulating layer in the bending area. The extension depth of the first part of the fourth via and the first part of the fifth via is consistent with that of the third via.

12. The method for manufacturing a display panel according to claim 11, wherein: The step of forming the first via hole or the step of forming the first via hole and the second via hole further includes the following steps: The second portion of the fourth via is formed in the peripheral area of ​​the non-display area, and the second portion of the fifth via is formed in the bending area of ​​the non-display area. The second portion of the fourth via and the second portion of the fifth via are connected to the first portion of the fourth via and the first portion of the fifth via, and extend into the first substrate.

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