Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same, the method comprising: forming a dummy gate on a substrate, the dummy gate extending along a first direction, the dummy gate including an isolation region extending through the dummy gate along a second direction perpendicular to the first direction, and both the first and second directions being parallel to the substrate surface; forming a sacrificial sidewall on the sidewall of the dummy gate; forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer also located on the sidewall of the sacrificial sidewall and exposing the top surface of the dummy gate; etching back the sacrificial sidewall to form a first groove between the interlayer dielectric layer and the dummy gate; after forming the first groove, removing the isolation region to form an isolation opening in the dummy gate and the interlayer dielectric layer, the isolation opening communicating with the first groove; and forming a gate blocking structure in the isolation opening, which facilitates the formation of a gate structure with a better morphology.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the existing semiconductor field, the FinFET is an emerging multi-gate device. Compared with the planar metal-oxide-semiconductor field-effect transistor (MOSFET), the FinFET has stronger short-channel rejection capability and higher operating current, and is now widely used in various semiconductor devices.

[0003] With the continuous development of semiconductor technology, integrated circuits are constantly being "scaled down." When the size of semiconductor devices shrinks to the nanometer level, especially for FinFETs, their gate control capability is closely related to their physical size. The small geometric size and three-dimensional structure of FinFETs make the impact of process changes on the device increasingly severe, urgently requiring new methods for optimization. Existing methods for forming FinFET structures need improvement. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0005] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate; a gate opening and a gate blocking structure located within an interlayer dielectric layer on the substrate, wherein the gate opening extends along a first direction, and the gate blocking structure penetrates the gate opening along a second direction, the second direction being perpendicular to the first direction, and both the first and second directions being parallel to the substrate surface; a first groove located within the interlayer dielectric layer and on the sidewall of the gate opening, the first groove communicating with the gate opening, and the bottom of the first groove exposing the substrate, and the sidewall of the first groove exposing the interlayer dielectric layer; and a gate structure located within the gate opening and the first groove.

[0006] Optionally, the substrate includes: a base and a plurality of fins located on the base, the fins extending along a second direction; a gate structure spanning the fins and located on the sidewalls and top surface of a portion of the fins; and a gate blocking structure located between adjacent fins.

[0007] Optionally, the substrate further includes an isolation structure located on the substrate, the isolation structure being located on the sidewall surface of the fin portion, and the top surface of the isolation structure being lower than the top surface of the fin; the gate structure is also located on a portion of the isolation structure surface; and the gate blocking structure is located on the isolation structure surface.

[0008] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a dummy gate on the substrate, the dummy gate extending along a first direction, the dummy gate including an isolation region, the isolation region penetrating the dummy gate along a second direction, the second direction being perpendicular to the first direction, and both the first direction and the second direction being parallel to the substrate surface; forming a sacrificial sidewall on the sidewall of the dummy gate; forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer also being located on the sidewall of the sacrificial sidewall and exposing the top surface of the dummy gate; etching back the sacrificial sidewall to form a first groove between the interlayer dielectric layer and the dummy gate; after forming the first groove, removing the isolation region to form an isolation opening in the dummy gate and the interlayer dielectric layer, the isolation opening communicating with the first groove; and forming a gate blocking structure in the isolation opening.

[0009] Optionally, it further includes: after forming the gate blocking structure, removing the dummy gate and forming a gate opening in the interlayer dielectric layer; forming a gate structure in the gate opening.

[0010] Optionally, the first groove exposes the substrate surface; the gate structure is also located within the first groove.

[0011] Optionally, the first groove does not expose the substrate surface, with the retained sacrificial sidewall serving as the second sidewall; the gate blocking structure is also located in the first groove of the isolation opening sidewall, and the method further includes: after forming the gate blocking structure, removing the second sidewall of the gate opening sidewall to form a second groove within the interlayer dielectric layer and located in the gate opening sidewall; the gate structure is also located in the second groove.

[0012] Optionally, the substrate includes: a base and a plurality of fins located on the base, the fins extending along a second direction; the dummy gate spans the fins and is located on the sidewalls and top surface of a portion of the fins; the isolation region is located between adjacent fins.

[0013] Optionally, it includes: forming a first sidewall on the surface of the sacrificial sidewall before forming the interlayer dielectric layer; the first groove is located between the first sidewall and the dummy gate.

[0014] Optionally, the method of forming the first sidewall includes: forming a sidewall material layer on the substrate surface, the dummy gate sidewall, and the top surface; and etching back the sidewall material layer until the substrate surface and the top surface of the dummy gate are exposed.

[0015] Optionally, the material of the sacrificial sidewall is different from the material of the first sidewall; the material of the sacrificial sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride; the material of the first sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride.

[0016] Optionally, the material of the sacrificial sidewall includes silicon carbide, and the material of the first sidewall includes silicon nitride.

[0017] Optionally, it also includes: after forming the first sidewall and before forming the interlayer dielectric layer, forming a source / drain layer in the fins on both sides of the dummy gate.

[0018] Optionally, the top surface of the dummy gate also has a hard mask layer.

[0019] Optionally, the hard mask layer includes a first hard mask layer and a second hard mask layer located on the surface of the first hard mask layer; the material of the first hard mask layer includes silicon nitride; and the material of the second hard mask layer includes silicon oxide.

[0020] Optionally, the method for forming the gate blocking structure includes: forming a dielectric material layer within the isolation opening and on the surface of the interlayer dielectric layer; planarizing the dielectric material layer until the dummy gate surface is exposed, thereby forming the gate blocking structure.

[0021] Optionally, the substrate further includes an isolation structure located on the substrate, the isolation structure being located on the sidewall surface of the fin portion, and the top surface of the isolation structure being lower than the top surface of the fin; the gate structure is also located on a portion of the isolation structure surface; and the gate blocking structure is located on the isolation structure surface.

[0022] Optionally, the process for forming the first groove includes one or a combination of dry etching and wet etching.

[0023] Optionally, the process for forming the isolation opening includes one or a combination of dry etching and wet etching processes.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0025] In the semiconductor structure formation method provided by the present invention, the sacrificial sidewall is etched back to form a first groove between the interlayer dielectric layer and the dummy gate. The first groove creates a certain distance between the isolation region of the dummy gate and the interlayer dielectric layer, providing space for removing the isolation region, reducing the residue of the dummy gate material in the isolation region, facilitating the formation of a better isolation opening, reducing the occurrence of feet in the subsequently formed gate structure, and facilitating the formation of a gate structure with a better morphology, thereby improving the performance of the formed device.

[0026] Furthermore, before forming the interlayer dielectric layer, a first sidewall is formed on the surface of the sacrificial sidewall; the first groove is located between the first sidewall and the dummy gate, and the first sidewall is used to protect the interlayer dielectric layer from etching damage during the etching process of forming the first groove. Attached Figure Description

[0027] Figures 1 to 5 This is a schematic diagram of a semiconductor structure formation process;

[0028] Figures 6 to 21 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0029] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0030] As described in the background section, the performance of semiconductor structures formed using existing FinFET technology urgently needs improvement. This paper will now illustrate and analyze one such semiconductor structure.

[0031] Figures 1 to 5 This is a schematic diagram of the semiconductor structure formation process.

[0032] Please refer to Figure 1 A substrate is provided, the substrate including a base 100 and a fin 101 located on a portion of the base 100, an isolation structure 102 located on the base 100, the isolation structure 102 also located on a portion of the sidewall of the fin 101, and the top surface of the isolation structure 102 being lower than the top surface of the fin 101; a dummy gate oxide layer 103 is formed on the surface of the fin 101; a dummy gate structure is formed across the fin 101, the dummy gate structure including a dummy gate 104 and a sidewall 105 of the sidewall of the dummy gate 104, the dummy gate structure being located on a portion of the top surface and a portion of the sidewall surface of the fin 101, and on a portion of the top surface of the isolation structure 102.

[0033] Please refer to Figure 2 and Figure 3 , Figure 2 yes Figure 3 A top-view structural diagram. Figure 3 yes Figure 2 A cross-sectional view along the DD1 direction is shown. An interlayer dielectric layer 106 is formed on the substrate surface, exposing the top surface of the dummy gate 104. The dummy gate 104 is etched to form an opening 107 in the interlayer dielectric layer 106. The opening 107 extends through the dummy gate 104 along the extension direction of the fin 101. The opening 107 is located between adjacent fins 101, and the bottom of the opening 107 exposes the surface of the isolation structure 102. One opening 107 causes one dummy gate 104 to form two transition dummy gates 108.

[0034] Please refer to Figure 4 and Figure 5 , Figure 4 yes Figure 5 A top-view structural diagram. Figure 5 yes Figure 4 A cross-sectional view along the DD1 direction shows that a gate blocking structure 109 is formed within the opening 107; after the gate blocking structure 109 is formed, it replaces the transition dummy gate 108 to form a gate 110.

[0035] The above method is used to form gates for different devices. However, as semiconductor feature sizes continue to shrink, the size of the formed opening 107 is smaller along the direction parallel to the substrate and larger along the direction normal to the substrate, i.e., the depth-to-width ratio is large. Due to limitations in the etching process, when forming the opening 107, the material of the dummy gate 104 at the opening 107 cannot be completely etched away. Some residue A (such as...) will appear at the bottom of the opening 107, i.e., at the corner formed by the interface of the transition dummy gate 108, the fin 101, and the interlayer dielectric layer 106. Figure 3 As shown), the residue A will be filled with the material of the gate 110 in the subsequent metal gate replacement process to form the foot B of the gate 110 (as shown). Figure 5 As shown, the presence of foot B reduces the gate control capability of the device and may even cause abnormalities such as short circuits, seriously affecting the performance of the device.

[0036] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure in which a groove is formed between the interlayer dielectric layer and the dummy gate. The groove creates a certain distance between the isolation region of the dummy gate and the interlayer dielectric layer, providing space for removing the isolation region, reducing the residue of dummy gate material in the isolation region, facilitating the formation of a better isolation opening, reducing the occurrence of feet in the subsequently formed gate structure, and facilitating the formation of a gate structure with a better morphology, thereby improving the performance of the formed device.

[0037] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 6 to 21 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 6 and Figure 7 , Figure 6 for Figure 7 A top-view structural diagram. Figure 7 yes Figure 6 A schematic diagram of the cross-sectional structure along the MM1 direction, providing the substrate.

[0040] In this embodiment, the substrate includes a base 200 and a plurality of fins 201 located on the base 200, the fins 201 extending along a second direction Y.

[0041] In this embodiment, the substrate further includes an isolation structure 202 located on the substrate 200. The isolation structure 202 is located on a portion of the sidewall surface of the fin 201, and the top surface of the isolation structure 202 is lower than the top surface of the fin 201.

[0042] Please continue to refer to this. Figure 6 and Figure 7 A dummy gate 203 is formed on the substrate. The dummy gate 203 extends along a first direction X. The dummy gate 203 includes an isolation region I. The isolation region I penetrates the dummy gate 203 along a second direction Y. The second direction Y is perpendicular to the first direction X, and both the first direction X and the second direction Y are parallel to the substrate surface.

[0043] The dummy gate 203 is made of silicon. In this embodiment, the dummy gate 203 is made of polycrystalline silicon. In other embodiments, the dummy gate 203 can be made of amorphous silicon, silicon carbide, etc.

[0044] The dummy gate 203 is used to occupy space for the subsequent formation of the gate blocking structure and the gate structure.

[0045] In this embodiment, the dummy gate 203 is also located on a portion of the surface of the isolation structure 202.

[0046] The isolation region I is located between adjacent fins 201. The isolation region I will subsequently be removed to cut off the dummy gate 203, thereby further forming the gate structure of the device in different regions.

[0047] In this embodiment, the dummy gate 203 spans the fin 201 and is located on part of the sidewall and top surface of the fin 201.

[0048] In this embodiment, the top surface of the dummy gate 203 also has a hard mask layer.

[0049] The method for forming the dummy gate 203 includes: forming a dummy gate material layer (not shown in the figure) on the surface of the substrate; forming a hard mask layer on the surface of the dummy gate 203, wherein the hard mask layer exposes a portion of the dummy gate material layer; and etching the dummy gate material layer using the hard mask layer as a mask until the substrate is exposed.

[0050] In this embodiment, the hard mask layer includes a first hard mask layer 204 and a second hard mask layer 205 located on the surface of the first hard mask layer; the material of the first hard mask layer 204 includes silicon nitride; and the material of the second hard mask layer 205 includes silicon oxide.

[0051] Please refer to Figure 8 and Figure 9 , Figure 8 for Figure 9 A top-view structural diagram. Figure 9 yes Figure 8 A cross-sectional view along the NN1 direction shows that a sacrificial sidewall 206 is formed on the sidewall of the dummy gate 203.

[0052] In this embodiment, specifically, the sacrificial sidewall 206 is also formed on the sidewall of the first hard mask layer 204.

[0053] The method for forming the sacrificial sidewall 206 includes: forming a sacrificial material layer (not shown in the figure) on the substrate surface and the sidewall and top surface of the dummy gate 203; and etching back the sacrificial material layer until the substrate surface and the top surface of the dummy gate 203 are exposed. Specifically, the sacrificial material layer is etched back until the substrate surface and the top surface of the second hard mask layer 205 are exposed.

[0054] Subsequently, an interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer also being located on the sidewall of the sacrificial sidewall and exposing the top surface of the dummy gate.

[0055] In this embodiment, before forming the interlayer medium layer, a first sidewall 207 is formed on the surface of the sacrificial sidewall 206.

[0056] In this embodiment, the method for forming the first sidewall 207 includes: forming a sidewall material layer on the substrate surface, the sidewall of the dummy gate 203, and the top surface; and etching back the sidewall material layer until the substrate surface and the top surface of the dummy gate 203 are exposed. Specifically, a sidewall material layer is formed on the substrate surface, the sacrificial sidewall surface, and the surface of the second hard mask layer 205; and the sidewall material layer is etched back until the substrate surface and the surface of the second hard mask layer 205 are exposed.

[0057] In another embodiment, the method of forming the first sidewall 207 includes: forming a sidewall material layer on the substrate surface, the sidewall of the dummy gate 203 and the top surface, and forming the first sidewall 207 with the sidewall material layer of the sidewall of the dummy gate 203.

[0058] In this embodiment, the material of the sacrificial sidewall 206 is different from the material of the first sidewall 207. The material of the sacrificial sidewall 206 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, and silicon carbonitride; the material of the first sidewall 207 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, and silicon carbonitride. The material of the sacrificial sidewall 206 is different from the material of the first sidewall 207 so that when the sacrificial sidewall 206 is subsequently etched, the first sidewall 207 serves to protect the interlayer dielectric layer from etching damage.

[0059] In this embodiment, the material of the sacrificial sidewall 206 includes silicon carbide, and the material of the first sidewall 207 includes silicon nitride.

[0060] In this embodiment, after the first sidewall 207 is formed and before the interlayer dielectric layer is formed, a source / drain layer (not shown in the figure) is also formed in the fins 201 on both sides of the dummy gate 203.

[0061] Please refer to Figure 10 and Figure 11 , Figure 10 for Figure 11 A top-view structural diagram. Figure 11 yes Figure 10 A cross-sectional view along the NN1 direction shows an interlayer dielectric layer 208 formed on the substrate. The interlayer dielectric layer 208 is also located on the sidewall of the sacrificial sidewall 206 and exposes the top surface of the dummy gate 203.

[0062] The method for forming the interlayer dielectric layer 208 includes: forming an interlayer dielectric material layer on the substrate, the interlayer dielectric material layer also being located on the sidewalls and top surface of the dummy gate 203; planarizing the interlayer dielectric material layer until the top surface of the dummy gate 203 is exposed. Specifically, in this embodiment, the interlayer dielectric material layer is also located on the sidewalls and top surface of the hard mask layer, and the interlayer dielectric material layer is planarized until the first hard mask layer 204 is exposed. In this embodiment, the second hard mask layer 205 is retained for subsequent etching processes (such as the formation process of the first groove 209) to protect the dummy gate 203 from etching damage.

[0063] Please refer to Figure 12 , Figure 12 The view direction is the same Figure 11 The sacrificial sidewall 206 is etched back, and a first groove 209 is formed between the interlayer dielectric layer 208 and the dummy gate 203.

[0064] In this embodiment, specifically, the first groove 209 is located between the first sidewall 207 and the dummy gate 203.

[0065] The formation process of the first groove 209 includes one or a combination of dry etching and wet etching processes.

[0066] In this embodiment, the first groove 209 does not expose the substrate surface, with the retained sacrificial sidewall 206 serving as the second sidewall 210. In another embodiment, the first groove 209 exposes the substrate surface. When etching the sacrificial sidewall 206, the etching process required to etch the substrate surface without exposing it is relatively easier to implement than when exposing the substrate surface.

[0067] Please refer to Figure 13 and Figure 14 , Figure 13 for Figure 14 A top-view structural diagram. Figure 14 yes Figure 13 A cross-sectional view along the NN1 direction shows that after the first groove 209 is formed, the isolation region I is removed, and an isolation opening 211 is formed in the dummy gate 203 and the interlayer dielectric layer 208. The isolation opening 211 communicates with the first groove 209.

[0068] The formation process of the isolation opening 211 includes one or a combination of dry etching and wet etching. In this embodiment, the formation process of the isolation opening 211 is a dry etching process.

[0069] The first groove 209 creates a certain distance between the isolation region I of the dummy gate 203 and the interlayer dielectric layer 208, providing space for removing the isolation region I, reducing the residue of the dummy gate material in the isolation region I, facilitating the formation of a better isolation opening 211, reducing the occurrence of feet in the subsequently formed gate structure, and facilitating the formation of a gate structure with a better morphology, thereby improving the performance of the formed device.

[0070] Please refer to Figures 15 to 17 , Figure 15 for Figure 16 and Figure 17 A top-view structural diagram. Figure 16 yes Figure 15 A schematic diagram of the cross-sectional structure along the NN1 direction. Figure 17 yes Figure 15 A cross-sectional view along the EE1 direction shows that a gate blocking structure 212 is formed within the isolation opening 211.

[0071] In this embodiment, the gate blocking structure 212 is located on the surface of the isolation structure 202.

[0072] In this embodiment, before forming the gate blocking structure, the second sidewall 210 of the isolation opening 211 sidewall is removed, and the first groove 209 of the isolation opening 211 sidewall is used to form a third groove (not shown in the figure); the gate blocking structure 212 is also located in the third groove. In another embodiment, the first groove exposes the substrate surface, and the gate blocking structure is also located in the first groove of the isolation opening sidewall.

[0073] In this embodiment, the second sidewall 210 of the isolation opening 211 has more exposed surface area than the second sidewall 210 of the dummy gate 203, and therefore is easily removed.

[0074] The method for forming the gate blocking structure 212 includes: forming a dielectric material layer (not shown in the figure) within the isolation opening 212 and on the surface of the interlayer dielectric layer 208; planarizing the dielectric material layer until the surface of the dummy gate 203 is exposed, thereby forming the gate blocking structure 212. In this embodiment, during the planarization process, the first hard mask layer 204 serves to protect the dummy gate 203, and the first hard mask layer 204 is removed during the planarization process.

[0075] In this embodiment, the dielectric material layer is also formed within the first groove 209. Because the first groove 209 has a high aspect ratio, its top can be easily sealed beforehand. During the planarization process, the dielectric material layer at the top of the first groove 209 can be easily removed.

[0076] Please refer to Figure 18 and Figure 19 , Figure 18 for Figure 19 A top-view structural diagram. Figure 19 yes Figure 18 A cross-sectional view along the EE1 direction shows that after forming the gate blocking structure 212, the dummy gate 203 is removed, and a gate opening 213 is formed in the interlayer dielectric layer 208.

[0077] In this embodiment, after forming the gate blocking structure 212, the second sidewall 210 of the sidewall of the gate opening 213 is removed to form a second groove (not shown in the figure) inside the interlayer dielectric layer 208 and located on the sidewall of the gate opening 213.

[0078] Please refer to Figure 20 and Figure 21 , Figure 20 for Figure 21 A top-view structural diagram. Figure 21 yes Figure 20 A cross-sectional view along the EE1 direction shows that a gate structure 214 is formed within the gate opening 213.

[0079] In this embodiment, the gate structure 214 is also located within the second groove. In another embodiment, the first groove exposes the substrate surface, and the gate structure is also located within the first groove.

[0080] In this embodiment, the gate structure 214 is also located on a portion of the surface of the isolation structure 202.

[0081] The gate structure 214 includes a gate dielectric layer (not shown in the figure) located within the gate opening 213 and a gate layer (not shown in the figure) located on the surface of the gate dielectric layer.

[0082] Accordingly, this invention also provides a semiconductor structure, please refer to [the relevant documentation]. Figure 20 and Figure 21The system includes: a substrate; a gate opening 213 and a gate blocking structure 212 located within an interlayer dielectric layer 208 on the substrate, wherein the gate opening 213 extends along a first direction X, and the gate blocking structure 212 penetrates the gate opening 213 along a second direction Y, wherein the second direction Y is perpendicular to the first direction X, and both the first direction X and the second direction Y are parallel to the substrate surface; a first groove (not shown in the figure) located within the interlayer dielectric layer 208 and on the sidewall of the gate opening 213, wherein the first groove communicates with the gate opening 213, and the bottom of the first groove exposes the substrate, and the sidewall of the first groove exposes the interlayer dielectric layer 208; and a gate structure 214 located within the gate opening 213 and the first groove.

[0083] In this embodiment, the substrate includes a base 200 and a plurality of fins 201 located on the base 200. The fins 201 extend along a second direction Y. The gate structure 214 spans the fins 201 and is located on a portion of the sidewalls and top surface of the fins 201. The gate blocking structure 212 is located between adjacent fins 201.

[0084] In this embodiment, the substrate further includes an isolation structure 202 located on the substrate 200. The isolation structure 202 is located on a portion of the sidewall surface of the fin 201, and the top surface of the isolation structure 202 is lower than the top surface of the fin 201. The gate structure 214 is also located on a portion of the surface of the isolation structure 202. The gate blocking structure 212 is located on the surface of the isolation structure 202.

[0085] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, include: Provide substrate; A dummy gate is formed on the substrate, the dummy gate extending along a first direction, the dummy gate including an isolation region, the isolation region penetrating the dummy gate along a second direction, the second direction being perpendicular to the first direction, and both the first direction and the second direction being parallel to the substrate surface; A sacrificial sidewall is formed on the dummy gate sidewall; An interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer is also located on the sacrificial sidewall sidewall, and exposes the top surface of the dummy gate; The sacrificial sidewall is etched back to form a first groove between the interlayer dielectric layer and the dummy gate; After the first groove is formed, the isolation region is removed, and an isolation opening is formed in the dummy gate and the interlayer dielectric layer, the isolation opening communicating with the first groove; A gate blocking structure is formed within the isolation opening.

2. The method of forming a semiconductor structure of claim 1, wherein Also includes: After forming the gate blocking structure, the dummy gate is removed, and a gate opening is formed in the interlayer dielectric layer. A gate structure is formed within the gate opening.

3. The method of forming a semiconductor structure of claim 2, wherein, The first groove exposes the substrate surface; the gate structure is also located within the first groove.

4. The method of forming a semiconductor structure of claim 2, wherein The first groove does not expose the substrate surface, so that the retained sacrificial sidewall serves as the second sidewall; The gate blocking structure is also located in the first groove of the isolation opening sidewall. The method further includes: after forming the gate blocking structure, removing the second sidewall of the gate opening sidewall to form a second groove in the interlayer dielectric layer and located in the gate opening sidewall. The gate structure is also located within the second groove.

5. The method of forming a semiconductor structure of claim 1, wherein include: The substrate includes a base and a plurality of fins located on the base, the fins extending along a second direction; The dummy gate spans the fin and is located on the sidewall and top surface of the fin portion; the isolation region is located between adjacent fins.

6. The method of forming a semiconductor structure of claim 5, wherein include: Before forming the interlayer medium layer, a first sidewall is formed on the surface of the sacrificial sidewall; The first groove is located between the first sidewall and the dummy gate.

7. The method of forming a semiconductor structure of claim 6, wherein, The method of forming the first sidewall includes: forming a sidewall material layer on the substrate surface, the dummy gate sidewall, and the top surface; and etching back the sidewall material layer until the substrate surface and the top surface of the dummy gate are exposed.

8. The method of forming a semiconductor structure of claim 6, wherein, The material of the sacrificial sidewall is different from that of the first sidewall; the material of the sacrificial sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride; the material of the first sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

9. The method of forming a semiconductor structure of claim 8, wherein, The material of the sacrificial sidewall includes silicon carbide, and the material of the first sidewall includes silicon nitride.

10. The method of forming a semiconductor structure of claim 6, wherein Also includes: After the first sidewall is formed and before the interlayer dielectric layer is formed, a source / drain layer is also formed in the fins on both sides of the dummy gate.

11. The method of forming a semiconductor structure of claim 1, wherein, The top surface of the dummy gate also has a hard mask layer.

12. The method of forming a semiconductor structure of claim 11, wherein, The hard mask layer includes a first hard mask layer and a second hard mask layer located on the surface of the first hard mask layer; the material of the first hard mask layer includes silicon nitride; the material of the second hard mask layer includes silicon oxide.

13. The method of forming a semiconductor structure of claim 11, wherein, The method for forming the gate blocking structure includes: forming a dielectric material layer inside the isolation opening and on the surface of the interlayer dielectric layer; planarizing the dielectric material layer until the dummy gate surface is exposed, thereby forming the gate blocking structure.

14. The method of forming a semiconductor structure of claim 5, wherein, The substrate further includes an isolation structure located on the substrate, the isolation structure being located on the sidewall surface of the fin portion, and the top surface of the isolation structure being lower than the top surface of the fin; The gate structure is also located on a portion of the surface of the isolation structure; The gate blocking structure is located on the surface of the isolation structure.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the first groove includes one or a combination of dry etching and wet etching.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the isolation opening includes one or a combination of dry etching and wet etching processes.

17. A semiconductor structure, characterized in that, The semiconductor structure is formed using the method for forming a semiconductor structure as described in any one of claims 1 to 16, comprising: Substrate; A gate opening and a gate blocking structure are located in an interlayer dielectric layer on a substrate. The gate opening extends along a first direction, and the gate blocking structure penetrates the gate opening along a second direction. The second direction is perpendicular to the first direction, and both the first direction and the second direction are parallel to the substrate surface. A first groove located within the interlayer dielectric layer and on the sidewall of the gate opening, the first groove communicating with the gate opening, the bottom of the first groove exposing the substrate, and the sidewall of the first groove exposing the interlayer dielectric layer; A gate structure located within the gate opening and the first groove.

18. The semiconductor structure as claimed in claim 17, characterized in that, include: The substrate includes a base and a plurality of fins located on the base, the fins extending along a second direction; The gate structure spans the fin and is located on the sidewall and top surface of the fin portion; the gate blocking structure is located between adjacent fins.

19. The semiconductor structure as claimed in claim 18, characterized in that, The substrate further includes an isolation structure located on the substrate, the isolation structure being located on the sidewall surface of the fin portion, and the top surface of the isolation structure being lower than the top surface of the fin; The gate structure is also located on a portion of the surface of the isolation structure; The gate blocking structure is located on the surface of the isolation structure.

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