Power grid topology identification method and device based on power-on sequence

Abstract

The present invention provides a method and device for identifying power grid topology based on power-on sequence. The method includes: when a low-voltage switch is powered on, counting the number of times the voltage crosses zero, closing the switch after a delay according to delay information, and recording the number of times the voltage crosses zero at the closing time as the closing count value; when the number of low-voltage switches that establish communication connections with a fusion terminal meets a preset condition, sending a freeze signal to the low-voltage switch to stop counting the voltage zero crossings and determine the accumulated number as the power-on count value. The fusion terminal determines the power-on time and closing time of each low-voltage switch based on the power-on count value and the closing count value, and determines the power-on time and closing time of each low-voltage switch by matching the power-on time and closing time of the upper and lower levels. According to the technical solution of this embodiment, the power-on time and closing time are represented by the voltage zero crossing count value, which improves the accuracy of clock synchronization, does not require the addition of additional equipment, and is conducive to cost control.

Description

Technical Field

[0001] The present invention belongs to the technical field of power grid data processing, and in particular relates to a power grid topology identification method based on power-on sequence and a device thereof. Background Art

[0002] With the development of the new energy industry, the number of devices in low-voltage substations is increasing. To ensure that the power supply from the substation to the user's meter is identifiable, it is necessary to determine the grid topology corresponding to each low-voltage substation. The fusion terminal has information collection, IoT proxy, and edge computing functions. By connecting the fusion terminal to the low-voltage switches of each meter, it can collect information about the low-voltage switches. Before the substation is put into operation, each low-voltage switch in the substation is set to the open state and then energized and closed step by step. The fusion terminal accurately records the energization time and automatic closing time of each low-voltage switch in the substation to generate the grid topology of the low-voltage substation. Therefore, the clock synchronization accuracy of each low-voltage switch has a significant impact on the accuracy of the grid topology.

[0003] In related technologies, in order to improve the accuracy of clock synchronization, we can rely on Ethernet's millisecond-level accuracy of Network Time Protocol (NTP), Simple Network Time Protocol (SNTP), nanosecond-level accuracy of Precision Time Protocol (PTP) and other technologies, but the Ethernet communication lines and clock source servers that these technologies rely on are difficult to deploy in low-voltage areas. There are also some related technologies that use microsecond-level satellite positioning systems for time synchronization, which also require additional dedicated modules, and if the low-voltage switch is located in a sheltered place, the clock accuracy will also be seriously affected. Therefore, for low-voltage areas with a large number of low-voltage switches, a wide distribution, and high cost control requirements, the clock synchronization accuracy cannot be guaranteed. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiment of the present invention provides a power grid topology identification method based on power-on sequence and a device thereof, which can improve clock synchronization accuracy and improve the accuracy of the generated power grid topology.

[0006] In a first aspect, an embodiment of the present invention provides a power grid topology identification method based on power-on sequence, which is applied to a low-voltage distribution network system, wherein the low-voltage distribution network system includes a fusion terminal and multiple low-voltage switches, and the switching state of the low-voltage switches is an open state. The method includes:

[0007] When the low-voltage switch is powered, the delay information is determined and the number of times the voltage crosses zero is counted;

[0008] The low-voltage switch adjusts the switch state to the closed state after delaying according to the delay information, and records the number of voltage zero crossings at the closing moment as the closing count value;

[0009] Establishing a communication connection with the energized low-voltage switch through the fusion terminal; when the number of the low-voltage switches that have established a communication connection with the fusion terminal meets a preset condition, sending a freeze signal to each of the low-voltage switches through the fusion terminal at the same time; the low-voltage switch stops counting the voltage zero crossing in response to the freeze signal, determines the accumulated number of times after being energized as the energization count value, and reports the corresponding energization count value and the closing count value to the fusion terminal;

[0010] Based on the power-on count value and the closing count value, determining the power-on time and closing time of each low-voltage switch through the fusion terminal;

[0011] Based on the power-on time and the closing time of each low-voltage switch, the grid topology composed of all the low-voltage switches is determined, wherein, in the grid topology, the power-on time of the low-voltage switch located at the next level matches the closing time of the low-voltage switch located at the previous level.

[0012] In some embodiments, the low-voltage switch includes a zero-crossing detection and counting module, which is used to detect and count the voltage zero crossings of the alternating current input to the low-voltage switch. The counting of the number of voltage zero crossings includes:

[0013] When the zero-crossing detection and counting module obtains the input current, low-pass filtering is performed on the electrical signal generated by the input current to obtain an input electrical signal, wherein the input electrical signal is used to indicate the voltage value of the input current;

[0014] The zero-crossing detection and counting module detects and counts the number of times the voltage of the input electrical signal crosses zero.

[0015] In some embodiments, the fusion terminal includes a first carrier communication module, the low-voltage switch includes a second carrier communication module, the first carrier communication module is communicatively connected to the second carrier communication module, and the freezing signal is simultaneously sent to each of the low-voltage switches through the fusion terminal, and the low-voltage switch stops counting the voltage zero crossing in response to the freezing signal, including:

[0016] The converged terminal broadcasts the freeze signal through the first carrier communication module;

[0017] When the second carrier communication module of the low-voltage switch receives the freeze signal, it sends a trigger signal to the zero-crossing detection and counting module to enable the zero-crossing detection and counting module to stop voltage zero-crossing detection and counting.

[0018] In some embodiments, determining the energization time and the closing time of each low-voltage switch through the fusion terminal based on the energization count value and the closing count value includes:

[0019] determining the current frequency of the input electrical signal through the fusion terminal;

[0020] Based on the current frequency, the fusion terminal converts the power-on count value into the power-on duration, and converts the closing count value into the closing duration;

[0021] Based on the power-on time and the closing time, the power-on time and the closing time of each low-voltage switch are determined through the fusion terminal.

[0022] In some embodiments, determining the energization time and the closing time of each low-voltage switch through the fusion terminal based on the energization time and the closing time includes:

[0023] The fusion terminal determines a reference duration from the plurality of power-on durations, wherein the reference duration is the power-on duration of the low-voltage switch at the first stage;

[0024] Based on the reference duration and the power-on duration of each low-voltage switch, determining the power-on time of each low-voltage switch through the fusion terminal, wherein the power-on time is used to represent the time duration relative to the starting time when the low-voltage switch is switched to the closed state, and the starting time is the power-on time of the low-voltage switch at the first level;

[0025] The sum of the power-on time and the closing time is determined as the closing time of the low-voltage switch.

[0026] In some embodiments, determining the grid topology composed of all the low-voltage switches according to the energizing time and the closing time of each low-voltage switch includes:

[0027] The fusion terminal determines a reference interval of a lower-level power-on time of each low-voltage switch according to a preset time error and the closing time of each low-voltage switch;

[0028] Determining a superior-subordinate relationship among the plurality of low-voltage switches based on the lower-level power-on time reference interval and the power-on time of each low-voltage switch, wherein the power-on time of the low-voltage switch at the lower level is within the lower-level power-on time reference interval of the low-voltage switch at the upper level;

[0029] The power grid topology is generated according to the hierarchical relationship between the plurality of low-voltage switches.

[0030] In some embodiments, determining the delay information includes:

[0031] Generate a random number within a preset value range according to the preset unit duration;

[0032] The generated random number is determined as the value of the delay duration, and the delay duration is determined as the delay information.

[0033] In a second aspect, an embodiment of the present invention provides a power grid topology identification device based on power-on sequence, comprising:

[0034] A power-on control unit, configured to determine delay information and start counting the number of voltage zero crossings when the low-voltage switch is powered on;

[0035] A closing control unit, configured to adjust the switch state of the low-voltage switch to a closed state after a delay according to the delay information, and record the number of voltage zero crossings at the closing moment as a closing count value;

[0036] a freezing control unit, configured to establish a communication connection with the energized low-voltage switch through the fusion terminal, and when the number of the low-voltage switches that have established a communication connection with the fusion terminal meets a preset condition, simultaneously send a freezing signal to each of the low-voltage switches through the fusion terminal, and the low-voltage switch stops counting the voltage zero crossing in response to the freezing signal, determines the accumulated number of times after being energized as the energization count value, and reports the corresponding energization count value and the closing count value to the fusion terminal;

[0037] a time calculation unit, configured to determine, through the fusion terminal, a power-on time and a closing time of each of the low-voltage switches based on the power-on count value and the closing count value;

[0038] A topology generation unit is used to determine the power grid topology composed of all the low-voltage switches based on the power-on time and the closing time of each low-voltage switch, wherein in the power grid topology, the power-on time of the low-voltage switch at the next level matches the closing time of the low-voltage switch at the previous level.

[0039] In a third aspect, an embodiment of the present invention provides an electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the power grid topology identification method based on power-on sequence as described in the first aspect is implemented.

[0040] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium storing a computer program, wherein the computer program is used to execute the power grid topology identification method based on power-on sequence as described in the first aspect.

[0041] An embodiment of the present invention includes: when the low-voltage switch is powered on, determining delay information, and starting to count the number of times the voltage crosses zero; the low-voltage switch adjusts the switch state to the closed state after delaying according to the delay information, and records the number of times the voltage crosses zero at the closing moment as the closing count value; establishing a communication connection with the powered low-voltage switch through the fusion terminal, and when the number of the low-voltage switches that have established communication connections with the fusion terminal meets a preset condition, sending a freeze signal to each of the low-voltage switches through the fusion terminal at the same time, and the low-voltage switch stops the voltage from crossing zero in response to the freeze signal. The power-on time and the closing time of each low-voltage switch are determined by counting the number of times after power-on as the power-on count value, and the corresponding power-on count value and the closing count value are reported to the fusion terminal; based on the power-on count value and the closing count value, the power-on time and the closing time of each low-voltage switch are determined through the fusion terminal; according to the power-on time and the closing time of each low-voltage switch, the grid topology composed of all the low-voltage switches is determined, wherein, in the grid topology, the power-on time of the low-voltage switch at the next level matches the closing time of the low-voltage switch at the previous level. According to the technical solution of this embodiment, the voltage zero-crossing count can be used as the reference for clock synchronization, and the power-on time and the closing time can be represented by the voltage zero-crossing count value, which effectively improves the accuracy of clock synchronization, and does not require the addition of additional equipment, which is conducive to cost control.

[0042] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the technical solution of the present invention and do not constitute a limitation to the technical solution of the present invention.

[0044] Figure 1 is an example diagram of an implementation environment of the present invention;

[0045] Figure 2 This is a flow chart of a method for identifying power grid topology based on power-on sequence provided by one embodiment of the present invention;

[0046] Figure 3 yes Figure 2Specific flow chart of step 210;

[0047] Figure 4 yes Figure 2 Specific flow chart of step 230;

[0048] Figure 5 yes Figure 2 Specific flow chart of step 240;

[0049] Figure 6 yes Figure 2 Specific flow chart of step 230;

[0050] Figure 7 yes Figure 2 Specific flow chart of step 250;

[0051] Figure 8 yes Figure 2 Specific flow chart of step 210;

[0052] Figure 9 is a structural diagram of a power grid topology identification device based on power-on sequence provided by another embodiment of the present invention;

[0053] Figure 10 is a device diagram of an electronic device provided in another embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0055] It should be noted that although the device schematics illustrate functional module divisions and the flowcharts illustrate logical sequences, in certain circumstances, the steps shown or described may be performed in a sequence that differs from the module divisions in the device or the sequence in the flowcharts. The terms "first," "objective," and the like in the specification, claims, or accompanying drawings are used to distinguish similar objects and are not necessarily intended to describe a specific sequence or precedence.

[0056] The present invention provides a method and device for identifying power grid topology based on power-on sequence, the method comprising: when the low-voltage switch is powered on, determining delay information, and starting to count the number of times the voltage crosses zero; the low-voltage switch adjusts the switch state to the closed state after delaying according to the delay information, and records the number of times the voltage crosses zero at the closing moment as the closing count value; establishing a communication connection with the powered low-voltage switch through the fusion terminal, and when the number of the low-voltage switches that have established communication connections with the fusion terminal meets a preset condition, sending a freeze signal to each of the low-voltage switches through the fusion terminal at the same time, and the low-voltage switch responds. In response to the freezing signal, the counting of voltage zero crossings is stopped, the accumulated number of times after power-on is determined as the power-on count value, and the corresponding power-on count value and the closing count value are reported to the fusion terminal; based on the power-on count value and the closing count value, the power-on time and closing time of each low-voltage switch are determined through the fusion terminal; according to the power-on time and the closing time of each low-voltage switch, the grid topology composed of all the low-voltage switches is determined, wherein, in the grid topology, the power-on time of the low-voltage switch at the next level matches the closing time of the low-voltage switch at the previous level. According to the technical solution of this embodiment, the voltage zero crossing count can be used as the reference for clock synchronization, and the power-on time and closing time can be represented by the voltage zero crossing count value, which effectively improves the accuracy of clock synchronization, and does not require the addition of additional equipment, which is conducive to cost control.

[0057] Reference Figure 1 , Figure 1 A schematic diagram of an implementation environment provided by an embodiment of the present application is provided, wherein the implementation environment is a low-voltage distribution network system 100, the low-voltage distribution network system 100 includes a fusion terminal 110 and a low-voltage switch 120, and both the fusion terminal 110 and the low-voltage switch 120 are powered by three-phase four-wire, for example Figure 1 In the ABCN diagram, the voltage amplitudes of lines A, B, and C are equal and the angles are 120 degrees apart. Line N is the neutral line. Of course, other types of power supplies can also be used, as long as they can meet the power requirements of the equipment.

[0058] It should be noted that the converged terminal 110 is an edge device within the "cloud-pipe-edge-device" architecture of the intelligent IoT system. It features information collection, IoT proxy, and edge computing capabilities, supporting marketing, power distribution, and emerging businesses. It utilizes a hardware platform, software-based functions, modularized structure, hardware and software decoupling, and adaptive communication protocol design to meet the requirements of high-performance concurrency, large-capacity storage, and multiple collection objects. This intelligent converged terminal integrates functions such as power supply and consumption information collection in distribution stations, data collection from various collection terminals or energy meters, equipment status monitoring and communication networking, localized analysis and decision-making, and collaborative computing.

[0059] It should be noted that the converged terminal 110 includes a carrier communication head-end module 111, and the low-voltage switch 120 includes an MCU 121, a zero-crossing detection and metering chip 122, and a carrier communication tail-end module 123 with clock-synchronized IO shifting. Specifically, the MCU 121 and the zero-crossing detection and metering chip 122 can be connected via a serial peripheral interface (SPI), and the MCU 121 and the carrier communication tail-end module 123 with clock-synchronized IO shifting can be connected via an RS232 interface. Of course, they can also be connected via other available interfaces, and this embodiment does not limit this.

[0060] It should be noted that after the low-voltage switch 120 is energized, the MCU 121 can control the zero-crossing detection and metering chip 122 to perform voltage zero-crossing detection and counting. The carrier communication head-end module 111 of the fusion terminal 110 and the carrier communication tail-end module 123 with clock-synchronized IO shift can establish a communication connection. After the carrier communication tail-end module 123 with clock-synchronized IO shift obtains the freeze signal sent by the fusion terminal 110 through the carrier communication head-end module 111, it directly sends a clock-synchronized IO signal to the zero-crossing detection and metering chip 122, causing the zero-crossing detection and metering chip 122 to stop counting and send the count value to the MCU 121 for processing, and then reports information to the fusion terminal 110 through the carrier communication tail-end module 123 with clock-synchronized IO shift, such as reporting the power-on count value and the closing count value in the method of this application.

[0061] based on Figure 1 The implementation environment shown is described below in detail. The principle of the power grid topology identification method based on the power sequence provided by the embodiment of the present application is described in detail. Figure 2 , Figure 2 This is a flowchart of a power grid topology identification method based on power-on sequence provided in an embodiment of the present application. The terminal positioning method includes but is not limited to the following steps 210 to 250.

[0062] Step 210, when the low voltage switch is powered, determine the delay information and start counting the number of times the voltage crosses zero;

[0063] Step 220: the low-voltage switch adjusts the switch state to the closed state after delaying according to the delay information, and records the number of voltage zero crossings at the closing moment as the closing count value;

[0064] Step 230: Establish a communication connection with the energized low-voltage switches through the fusion terminal. When the number of low-voltage switches that have established communication connections with the fusion terminal meets a preset condition, send a freeze signal to each low-voltage switch through the fusion terminal. The low-voltage switch stops counting voltage zero crossings in response to the freeze signal, determines the accumulated number of times after energization as the energization count value, and reports the corresponding energization count value and closing count value to the fusion terminal.

[0065] Step 240, based on the power-on count value and the closing count value, determine the power-on time and closing time of each low-voltage switch through the fusion terminal;

[0066] Step 250, based on the power-on time and closing time of each low-voltage switch, determine the grid topology composed of all low-voltage switches, wherein in the grid topology, the power-on time of the low-voltage switch at the next level matches the closing time of the low-voltage switch at the previous level.

[0067] It should be noted that in order to determine the grid topology in the low-voltage distribution network system, it is necessary to ensure that the initial state of each low-voltage switch is the open state. After the low-voltage grid is energized, the grid topology is determined according to the power-on sequence of each low-voltage switch, that is, the first-level low-voltage switch is energized when the substation is energized, and the power-on time of each subsequent low-voltage switch is equal to the closing time of the low-voltage switch of the previous level.

[0068] It is understandable that although the closing operation can be performed after the low-voltage switch is energized, it takes a certain amount of time for the MCU to start and generate control signals. Therefore, there will inevitably be a certain time difference between the power-on moment and the closing moment. If this time difference is not taken into account, a large error will occur when the number of topological levels is large. Based on this, this embodiment generates a delay information when the low-voltage switch is energized, and delays closing according to the delay information. The sum of the power-on moment of the upper-level low-voltage switch and the delay information is determined as the power-on moment of the lower-level low-voltage switch. This is used as a basis for upper and lower level matching, which can effectively improve the accuracy of power grid topology matching.

[0069] It is worth noting that due to the large number of branches in the power grid topology, the delay information generated by multiple low-voltage switches at the same level can be different, so that the power-on time of the next-level low-voltage switch of each branch is different. The difference in the value of the power-on time is used to achieve the matching of the power grid topology, avoiding the same power-on time of the lower-level low-voltage switches in different branches, which affects the matching of the power grid topology. Those skilled in the art are motivated to determine the generation rules of the delay information according to actual needs, such as generating random numbers, or the delay information between each level meets a certain difference distribution, etc., which is not limited here. It is understandable that the delay information can be the delay time, such as 5 milliseconds, or it can be converted into the number of times the voltage crosses zero, such as 20 times the voltage crosses zero. The MCU of the low-voltage switch can recognize the delay information and thus control the closing operation. The specific form of the delay information is not limited here.

[0070] It should be noted that after the low-voltage switch is powered on, if the zero-crossing detection is started after a period of time, it will result in missing the number of voltage zero crossings, affecting the accuracy of clock synchronization based on the number of voltage zero crossings. In order to improve the accuracy of clock synchronization, the voltage zero detection and counting can be started immediately when the low-voltage switch is powered on, so that the electrical signals of the voltage zero-crossing detection of the multi-stage low-voltage switches of multiple branches are continuous in the time domain, for example Figure 1 In the illustrated implementation environment, the zero-crossing detection and metering chip 122 of the low-voltage switch 120 is connected to the three-phase four-wire circuit. When the three-phase four-wire circuit is energized, the zero-crossing detection and metering chip 122 can be powered simultaneously. After being powered, it can directly start voltage zero-crossing detection and counting without waiting for instructions from the MCU 121. This allows the power-on and closing times subsequently calculated based on the number of voltage zero crossings to have higher clock synchronization accuracy.

[0071] It should be noted that for low-voltage power grids, the frequency of alternating current is fixed and known. For example, when the cycle of alternating current is 50 Hz, the voltage will cross zero every 10 milliseconds. The zero-crossing detection and metering chip counts by 1 every 10 milliseconds, which is used as the benchmark for clock synchronization. The calculated power-on and closing times are accurate to 10 milliseconds, which is significantly improved compared to the hundreds of milliseconds in related technologies. There is no need to add expensive dedicated modules, and a simple voltage zero-crossing detection and counting can be used, effectively reducing the cost of low-voltage switches.

[0072] It should be noted that after the low-voltage switch is powered on, it starts to detect and count the voltage zero crossings. When the switch is closed, it does not stop the voltage zero crossing detection and obtain the closing count value, but maintains the voltage zero crossing detection and counting. At the closing moment, the current count value is obtained from the zero-crossing detection metering chip and recorded as the closing count value to ensure that the number of voltage zero crossings that the low-voltage switch stops counting in response to the freeze signal can represent the power-on time of the low-voltage switch, which is beneficial to improving the accuracy of topology calculation and clock synchronization accuracy.

[0073] It should be noted that after the low voltage switch is powered, a communication connection can be established with the fusion terminal through the carrier communication module, for example Figure 1 In the implementation environment shown, the carrier communication head-end module 111 establishes a communication connection with the carrier communication tail-end module 123 with clock synchronization IO shifting. The specific method of establishing the carrier communication connection is a technology well known to those skilled in the art and will not be elaborated here.

[0074] It is worth noting that after the fusion terminal sends a freeze signal to the low-voltage switch, the low-voltage switch will execute data freezing and reporting. Therefore, in order to ensure the integrity of the power grid topology, the freeze signal needs to be sent after all low-voltage switches have established communication connections with the fusion terminal. For example, when the total number of low-voltage switches is known, the preset condition of this embodiment can be that the number of low-voltage switches with established communication connections is equal to the total number of low-voltage switches; for example, when the total number of low-voltage switches is unknown, the preset condition of this embodiment can be that the freeze signal is sent after there are no new low-voltage switches connected for a period of time. For example, if there are no new low-voltage switches connected for 3 consecutive minutes, it can be considered that all low-voltage switches have established communication connections, and the freeze signal can be sent to perform subsequent operations.

[0075] It should be noted that after determining the power-on time and closing time of each low-voltage switch, the upper and lower levels of each low-voltage switch can be determined. For example, the low-voltage power grid includes low-voltage switch 1, low-voltage switch 2, low-voltage switch 3, low-voltage switch 4 and low-voltage switch 5, where low-voltage switch 1 and low-voltage switch 2 are located at the first level. When the power-on time of low-voltage switch 3 matches the closing time of low-voltage switch 1, it can be determined that low-voltage switch 3 is the next level of low-voltage switch 1. When the power-on time of low-voltage switch 4 matches the closing time of low-voltage switch 2, it can be determined that low-voltage switch 4 is the next level of low-voltage switch 2. When the power-on time of low-voltage switch 5 matches the closing time of low-voltage switch 3, it can be determined that low-voltage switch 5 is the next level of low-voltage switch 3. The resulting power grid topology includes two branches, where branch 1 is low-voltage switch 1, low-voltage switch 3 and low-voltage switch 5 in sequence, and branch 2 is low-voltage switch 2 and low-voltage switch 4 in sequence. It can be understood that the matching in this embodiment can be that the power-on moment of the next stage is equal to the closing moment of the previous stage, or that the matching is within the allowable error range, which is not limited here.

[0076] In addition, in one embodiment, the low voltage switch includes a zero crossing detection and counting module, which is used to detect and count the voltage zero crossing of the AC power input to the low voltage switch. Figure 3 , Figure 2 Step 210 shown specifically includes but is not limited to the following steps:

[0077] Step 310: When the zero-crossing detection and counting module obtains the input current, a low-pass filter is performed on the electrical signal generated by the input current to obtain an input electrical signal, wherein the input electrical signal is used to indicate the voltage value of the input current;

[0078] Step 320: Detect and count the number of times the voltage of the input electrical signal crosses zero using a zero-crossing detection and counting module.

[0079] It should be noted that the zero-crossing detection counting module can be Figure 1The zero-crossing detection and counting chip 122 in the illustrated implementation environment is, for example, a common metering chip RN2026. This embodiment does not impose too many restrictions on the specific selection of hardware modules.

[0080] It should be noted that if the voltage zero-crossing detection is performed directly on the electrical signal generated by the input current, there will be interference from noise and harmonics, which will increase the number of voltage zero-crossing detections and affect the accuracy of clock synchronization. Based on this, a filtering module can be set in the zero-crossing detection counting module to perform low-pass filtering after obtaining the input current to filter out noise and harmonics to ensure the accuracy of voltage zero-crossing detection.

[0081] In addition, in one embodiment, the fusion terminal includes a first carrier communication module, the low voltage switch includes a second carrier communication module, the first carrier communication module is communicatively connected to the second carrier communication module, and the Figure 4 , Figure 2 Step 230 shown specifically includes but is not limited to the following steps:

[0082] Step 410: The converged terminal broadcasts a freeze signal via the first carrier communication module;

[0083] Step 420: When the second carrier communication module of the low voltage switch receives the freeze signal, it sends a trigger signal to the zero crossing detection and counting module to cause the zero crossing detection and counting module to stop voltage zero crossing detection and counting.

[0084] It should be noted that the first carrier communication module can be Figure 1 The carrier communication head-end module 111 in the illustrated implementation environment, the second carrier communication module may be a carrier communication tail-end module 123 with clock synchronization IO shifting, which will not be repeated later.

[0085] It is understandable that, due to the large number of low-voltage switches, the fusion terminal can send the freeze signal by broadcasting to reduce the time difference of each low-voltage switch receiving the freeze signal and improve the accuracy of clock synchronization.

[0086] It should be noted that after the fusion terminal sends the freeze signal, each low-voltage switch freezes the current voltage zero-crossing count. Since the low-voltage switch starts counting after it is powered on, the accumulated count value can represent the power-on time of the low-voltage switch. The accumulated count value is determined as the power-on count value and reported to the fusion terminal at the same time as the closing count value. The power-on count value and closing count value of each low-voltage switch obtained by the fusion terminal are obtained through voltage zero-crossing detection. The clock synchronization accuracy is high, and the grid topology calculated based on this is more accurate. It can be understood that if Figure 1In the illustrated implementation, after the carrier communication headend module 111 sends a freeze signal to the carrier communication tailend module 123 with clock-synchronized IO shifting, to enhance freezing synchronization, the carrier communication tailend module 123 with clock-synchronized IO shifting can directly send a clock-synchronized IO signal to the zero-crossing detection and metering chip 122. In response to the clock-synchronized IO signal, the zero-crossing detection and metering chip 122 stops counting, ensuring that each low-voltage switch can freeze data synchronously and improving the clock synchronization accuracy of the power-on count. After the freeze is completed, the power-on count and the closing count have a high degree of clock synchronization accuracy. The MCU 121 then retrieves the above data from the zero-crossing detection and metering chip 122 and reports it, allowing the fusion terminal to process the data.

[0087] In addition, in one embodiment, referring to Figure 5 , Figure 2 Step 240 shown specifically includes but is not limited to the following steps:

[0088] Step 510, determining the current frequency of the input electrical signal through the fusion terminal;

[0089] Step 520: Based on the current frequency, the fusion terminal converts the power-on count value into the power-on duration and converts the closing count value into the closing duration;

[0090] Step 530: Based on the power-on duration and the closing duration, determine the power-on time and the closing time of each low-voltage switch through the fusion terminal.

[0091] It should be noted that since the current frequency of the low-voltage power grid is known, the power-on count value and the closing count value can be converted into time length. For example, if the current frequency is 50 Hz, the time length between two voltage zero-crossing counts is 10 milliseconds. If the power-on count value is 20, it is converted into a time length of 200 milliseconds. The same is true for the closing count value, which will not be repeated here.

[0092] It should be noted that since each low-voltage switch uses voltage zero-crossing detection as a representation of the time, the clock synchronization accuracy is relatively high, so that the error in the power-on and closing times of each low-voltage switch at the clock synchronization level is relatively small, which can effectively improve the calculation of the grid topology.

[0093] In addition, in one embodiment, referring to Figure 6 , Figure 2 Step 230 shown specifically includes but is not limited to the following steps:

[0094] Step 610: The fusion terminal determines a reference duration from a plurality of power-on durations, where the reference duration is the power-on duration of the low-voltage switch at the first stage.

[0095] Step 620: Based on the reference duration and the energization duration of each low-voltage switch, determine the energization time of each low-voltage switch through the fusion terminal. The energization time represents the duration of time the low-voltage switch is switched to the closed state relative to the start time, where the start time is the energization time of the first-stage low-voltage switch.

[0096] Step 630: Determine the sum of the power-on time and the closing time as the closing time of the low-voltage switch.

[0097] It should be noted that after determining the power-on time, since the low-voltage switch starts counting after power is supplied, the power-on time of the first-level low-voltage switch is the largest in value. The power-on time with the largest value can be used as a reference time, and the power-on time of each low-voltage switch can be subtracted to obtain the power-on time of each low-voltage switch. By using the time relative to the first-level low-voltage switch as the power-on time, the calculation process can be simplified and the efficiency and accuracy of data processing can be improved.

[0098] It should be noted that the closing count value is the value recorded during the counting process of the low-voltage switch. Therefore, the closing count value is the number of voltage zero crossings increased relative to the power-on time. Based on this, after determining the power-on time, the sum of the power-on time and the closing count value can be determined as the closing time, so that the closing time can also represent the duration relative to the starting time.

[0099] For example, low-voltage switch 1 is a first-level low-voltage switch, whose power-on time is 30ms and closing time is 10ms. The power-on time of low-voltage switch 2 is 20ms, the closing time of low-voltage switch 2 is 10ms, the power-on time of low-voltage switch 3 is 10ms, and the closing time of low-voltage switch 3 is 10ms. The reference time is 30ms. Subtract the power-on time of each low-voltage switch from 30ms, and the power-on time of low-voltage switch 1 is 0ms, the power-on time of low-voltage switch 2 is 10ms, the power-on time of low-voltage switch 3 is 20ms, the closing time of low-voltage switch 1 is 10ms, the closing time of low-voltage switch 2 is 20ms, and the closing time of low-voltage switch 3 is 30ms. From this, it can be matched that low-voltage switch 2 is the next level of low-voltage switch 1, and low-voltage switch 3 is the next level of low-voltage switch 2.

[0100] In addition, in one embodiment, referring to Figure 7 , Figure 2 Step 250 shown specifically includes but is not limited to the following steps:

[0101] Step 710: The fusion terminal determines a reference interval of the lower power-on time of each low-voltage switch based on a preset time error and the closing time of each low-voltage switch;

[0102] Step 720: Determine the hierarchical relationship among the plurality of low-voltage switches based on the lower-level power-on time reference interval and the power-on time of each low-voltage switch, wherein the power-on time of the low-voltage switch at the lower level is within the lower-level power-on time reference interval of the low-voltage switch at the upper level.

[0103] Step 730: Generate a power grid topology based on the hierarchical relationship among the multiple low-voltage switches.

[0104] It should be noted that although the embodiment of the present application realizes clock synchronization through voltage zero-crossing counting, there will still be certain errors. For example, there will be a certain time error in the transmission and reception of the broadcast message of the freeze signal. Therefore, the closing time of the upper level and the power-on time of the lower level are not necessarily equal in value. Based on this, the embodiment pre-sets the time error in the fusion terminal, and determines the sum of the time error and the closing time as the reference value of the power-on time of the lower level low-voltage switch. For example, if the time error is 50ms and the closing time of the upper level is 10ms, then the reference interval of the power-on time of the lower level is [10,60]. The low-voltage switch whose power-on time is in the reference interval of the power-on time of the lower level is determined as the low-voltage switch of the next level, and so on.

[0105] In addition, in one embodiment, referring to Figure 8 , Figure 2 Step 210 shown specifically includes but is not limited to the following steps:

[0106] Step 810, generating a random number within a preset value range according to a preset unit time length;

[0107] Step 820: Determine the generated random number as the value of the delay duration, and determine the delay duration as the delay information.

[0108] It should be noted that in order to avoid the same closing time or power-on time of multiple low-voltage switches, which will lead to inaccurate matching of the power grid topology, it is necessary to distinguish the delay information of each low-voltage switch to reduce the probability of overlapping power-on time and closing time between low-voltage switches in different branches. For example, the unit time length can be preset and a random number can be generated within a preset numerical range. Since the probability of random number overlap is small, multiple low-voltage switches at the same level are delayed with different random numbers, so that the probability of repeated power-on time of the low-voltage switches at the lower level is reduced, thereby improving the accuracy of the power grid topology.

[0109] Exemplarily, the unit time length can be 1ms, and the preset value range is [1,20]. After the low-voltage switch is energized, a random number is generated in [1,20], for example, 5, and the delay time is 5ms. After the delay of 5ms, the closing operation is performed.

[0110] In addition, refer to Figure 9The embodiment of the present invention provides a power grid topology identification device based on power-on sequence, and the power grid topology identification device 900 based on power-on sequence includes

[0111] The power-on control unit 910 is used to determine the delay information and start counting the number of voltage zero crossings when the low-voltage switch is powered;

[0112] The closing control unit 920 is used to adjust the low-voltage switch state to the closed state after delaying according to the delay information, and record the number of voltage zero crossings at the closing moment as the closing count value;

[0113] A freeze control unit 930 is configured to establish a communication connection with the energized low-voltage switches through the fusion terminal. When the number of low-voltage switches that have established communication connections with the fusion terminal meets a preset condition, a freeze signal is simultaneously sent to each low-voltage switch through the fusion terminal. The low-voltage switch responds to the freeze signal and stops counting voltage zero crossings. The accumulated number of times after energization is performed is determined as a power-on count value, and the corresponding power-on count value and closing count value are reported to the fusion terminal.

[0114] A time calculation unit 940 is used to determine the energization time and closing time of each low-voltage switch through the fusion terminal based on the energization count value and the closing count value;

[0115] The topology generation unit 950 is used to determine the grid topology composed of all low-voltage switches based on the power-on time and closing time of each low-voltage switch, wherein in the grid topology, the power-on time of the low-voltage switch at the next level matches the closing time of the low-voltage switch at the previous level.

[0116] In addition, refer to Figure 10 An embodiment of the present invention further provides a hardware structure of an electronic device, the electronic device comprising:

[0117] The processor 1001 may be implemented as a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is configured to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0118] The memory 1002 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1002 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1002 and is called by the processor 1001 to execute the power grid topology identification method based on the power-on sequence of the embodiments of this application.

[0119] Input / output interface 1003, used to implement information input and output;

[0120] Communication interface 1004, used to implement communication interaction between this device and other devices, which can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WiFi, Bluetooth, etc.);

[0121] Bus 1005 , which transmits information between various components of the device (e.g., processor 1001 , memory 1002 , input / output interface 1003 , and communication interface 1004 );

[0122] The processor 1001, memory 1002, input / output interface 1003, and communication interface 1004 are interconnected within the device via a bus 1005. The apparatus embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of these modules may be selected to achieve the objectives of this embodiment as needed.

[0123] An embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the above-mentioned power grid topology identification method based on power-on sequence is implemented.

[0124] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0125] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above and the functional modules / units in the system electronic devices may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0126] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0127] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0128] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0129] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0130] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes various media that can store programs, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0131] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. In some cases, the names of these units do not constitute limitations on the units themselves.

[0132] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing electronic device (which can be a personal computer, a server, a touch terminal, or a network electronic device, etc.) to execute the method according to the embodiments of the present application.

[0133] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art that are not disclosed herein.

[0134] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

[0135] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above implementation. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A method for identifying power grid topology based on power-on sequence, characterized in that: Applied to a low-voltage distribution network system, the low-voltage distribution network system includes a fusion terminal and multiple low-voltage switches, the switch state of the low-voltage switch is an open state, and the method includes: When the low-voltage switch is powered, the delay information is determined and the number of times the voltage crosses zero is counted; The low-voltage switch adjusts the switch state to the closed state after delaying according to the delay information, and records the number of voltage zero crossings at the closing moment as the closing count value; Establishing a communication connection with the energized low-voltage switch through the fusion terminal; when the number of the low-voltage switches that have established a communication connection with the fusion terminal meets a preset condition, sending a freeze signal to each of the low-voltage switches through the fusion terminal at the same time; the low-voltage switch stops counting the voltage zero crossing in response to the freeze signal, determines the accumulated number of times after being energized as the energization count value, and reports the corresponding energization count value and the closing count value to the fusion terminal; Based on the power-on count value and the closing count value, determining the power-on time and closing time of each low-voltage switch through the fusion terminal; Determining a power grid topology composed of all the low-voltage switches based on the energization time and the closing time of each low-voltage switch, wherein in the power grid topology, the energization time of the low-voltage switch at the next level matches the closing time of the low-voltage switch at the previous level; The determining, based on the energizing time and the closing time of each low-voltage switch, a topology of a power grid formed by all the low-voltage switches, includes: The fusion terminal determines a reference interval of a lower-level power-on time of each low-voltage switch according to a preset time error and the closing time of each low-voltage switch; Determining a superior-subordinate relationship among the plurality of low-voltage switches based on the lower-level power-on time reference interval and the power-on time of each low-voltage switch, wherein the power-on time of the low-voltage switch at the lower level is within the lower-level power-on time reference interval of the low-voltage switch at the upper level; The power grid topology is generated according to the hierarchical relationship between the plurality of low-voltage switches.

2. The method for identifying power grid topology based on power-on sequence according to claim 1, characterized in that: The low-voltage switch includes a zero-crossing detection and counting module, which is used to detect and count the voltage zero crossings of the alternating current input to the low-voltage switch. The counting of the number of voltage zero crossings includes: When the zero-crossing detection and counting module obtains the input current, low-pass filtering is performed on the electrical signal generated by the input current to obtain an input electrical signal, wherein the input electrical signal is used to indicate the voltage value of the input current; The zero-crossing detection and counting module detects and counts the number of times the voltage of the input electrical signal crosses zero.

3. The method for identifying power grid topology based on power-on sequence according to claim 2, characterized in that: The fusion terminal includes a first carrier communication module, the low-voltage switch includes a second carrier communication module, the first carrier communication module is communicatively connected to the second carrier communication module, and the freezing signal is simultaneously sent to each of the low-voltage switches through the fusion terminal, and the low-voltage switch stops counting voltage zero crossings in response to the freezing signal, including: The converged terminal broadcasts the freeze signal through the first carrier communication module; When the second carrier communication module of the low-voltage switch receives the freeze signal, it sends a trigger signal to the zero-crossing detection and counting module to enable the zero-crossing detection and counting module to stop voltage zero-crossing detection and counting.

4. The method for identifying power grid topology based on power-on sequence according to claim 2, characterized in that: The determining, by the fusion terminal, the energizing time and the closing time of each low-voltage switch based on the energizing count value and the closing count value includes: determining the current frequency of the input electrical signal through the fusion terminal; Based on the current frequency, the fusion terminal converts the power-on count value into the power-on duration, and converts the closing count value into the closing duration; Based on the power-on time and the closing time, the power-on time and the closing time of each low-voltage switch are determined through the fusion terminal.

5. The method for identifying power grid topology based on power-on sequence according to claim 4, characterized in that: The determining, by the fusion terminal, the energizing time and the closing time of each low-voltage switch based on the energizing time and the closing time, includes: The fusion terminal determines a reference duration from the plurality of power-on durations, wherein the reference duration is the power-on duration of the low-voltage switch at the first stage; Based on the reference duration and the power-on duration of each low-voltage switch, determining the power-on time of each low-voltage switch through the fusion terminal, wherein the power-on time is used to represent the time duration relative to the starting time when the low-voltage switch is switched to the closed state, and the starting time is the power-on time of the low-voltage switch at the first level; The sum of the power-on time and the closing time is determined as the closing time of the low-voltage switch.

6. The method for identifying power grid topology based on power-on sequence according to any one of claims 1 to 5, characterized in that: The determining of the delay information includes: Generate a random number within a preset value range according to the preset unit duration; The generated random number is determined as the value of the delay duration, and the delay duration is determined as the delay information.

7. A power grid topology identification device based on power-on sequence, characterized in that: Applied to a low-voltage distribution network system, the low-voltage distribution network system includes a fusion terminal and multiple low-voltage switches, the switch state of the low-voltage switch is an open state, and the power-on sequence-based grid topology identification device includes: A power-on control unit, configured to determine delay information and start counting the number of voltage zero crossings when the low-voltage switch is powered on; A closing control unit, configured to adjust the switch state of the low-voltage switch to a closed state after a delay according to the delay information, and record the number of voltage zero crossings at the closing moment as a closing count value; a freezing control unit, configured to establish a communication connection with the energized low-voltage switch through the fusion terminal, and when the number of the low-voltage switches that have established a communication connection with the fusion terminal meets a preset condition, simultaneously send a freezing signal to each of the low-voltage switches through the fusion terminal, and the low-voltage switch stops counting the voltage zero crossing in response to the freezing signal, determines the accumulated number of times after being energized as the energization count value, and reports the corresponding energization count value and the closing count value to the fusion terminal; a time calculation unit, configured to determine, through the fusion terminal, a power-on time and a closing time of each of the low-voltage switches based on the power-on count value and the closing count value; a topology generating unit, configured to determine a power grid topology composed of all the low-voltage switches based on the energization time and the closing time of each of the low-voltage switches, wherein in the power grid topology, the energization time of the low-voltage switch at the next level matches the closing time of the low-voltage switch at the previous level; The determining, based on the energizing time and the closing time of each low-voltage switch, a topology of a power grid formed by all the low-voltage switches, includes: The fusion terminal determines a reference interval of a lower-level power-on time of each low-voltage switch according to a preset time error and the closing time of each low-voltage switch; Determining a superior-subordinate relationship among the plurality of low-voltage switches based on the lower-level power-on time reference interval and the power-on time of each low-voltage switch, wherein the power-on time of the low-voltage switch at the lower level is within the lower-level power-on time reference interval of the low-voltage switch at the upper level; The power grid topology is generated according to the hierarchical relationship between the plurality of low-voltage switches.

8. An electronic device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method for identifying power grid topology based on power-on sequence as described in any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium storing a computer program, characterized in that: The computer program is used to execute the power grid topology identification method based on power-on sequence according to any one of claims 1 to 6.

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