Eye opening monitoring device and its operation method

Abstract

The present invention provides an eye opening monitoring device and an operation method thereof. The eye opening monitoring device includes a phase interpolator, a first sampling circuit, a second sampling circuit, and a clock calibration circuit. The first sampling circuit samples a data signal according to a data clock to generate first sampled data. The second sampling circuit samples the data signal according to a phase interpolation clock of the phase interpolator to generate second sampled data. The phase interpolator changes the phase of the phase interpolation clock according to a phase interpolation code. The clock calibration circuit counts multiple comparison results of the first sampled data and the second sampled data in multiple clock cycles for any one of different phase interpolation codes to obtain an error count value. The clock calibration circuit determines the phase interpolation code provided to the phase interpolator based on these error count values corresponding to different phase interpolation codes.

Description

Technical Field

[0001] The present invention relates to a signal transmission device, and particularly to an eye opening monitoring device and an operation method thereof. Background Art

[0002] An eye pattern is a tool for evaluating signal quality between different devices. The larger the "eye opening" of the eye pattern, the better the signal quality. If the signal is distorted due to noise or interference, the "eye opening" of the eye pattern will become smaller. An eye opening monitor (EOM) is widely used in a serializer / deserializer (SerDes) and / or other electronic circuits to monitor the eye opening of a signal. In order to monitor the eye opening in the X-axis direction of the eye pattern, a phase interpolator is configured in the clock path of the electronic circuit to change the clock phase (i.e., the position of the clock on the X-axis of the eye pattern).

[0003] For data sampling operations, an electronic circuit (such as a SerDes) uses a data clock to sample a data signal to generate sampled data. For eye opening monitoring operations, the electronic circuit uses a phase interpolator to interpolate the phase in the clock signal to generate a phase interpolated clock. Generally, the phase interpolator will cause a delay difference between the data clock and the phase interpolated clock. If there is a duty cycle error in the data clock or an incorrect clock that causes two tones, the problem will become worse.

[0004] It should be noted that the content of the "Background Art" section is used to help understand the present invention. Some (or all) of the content disclosed in the "Background Art" section may not be known prior art to those skilled in the art of the present invention. The content disclosed in the "Background Art" section does not mean that the content was known to those skilled in the art before the filing of the present invention application. Summary of the Invention

[0005] The present invention provides an eye opening monitoring device and an operation method thereof to make the phase of the phase interpolated clock match the phase of the data clock.

[0006] According to an embodiment of the present invention, the above-mentioned eye opening monitoring device includes a phase interpolator, a first sampling circuit, a second sampling circuit, and a clock calibration circuit. The first sampling circuit is configured to sample a data signal according to a data clock to generate first sampled data. The phase interpolator is configured to receive the data clock. The phase interpolator generates a phase interpolated clock by changing the phase of the data clock based on a phase interpolation code change amount. The second sampling circuit is coupled to the phase interpolator to receive the phase interpolated clock. The second sampling circuit is configured to sample the data signal according to the phase interpolated clock to generate second sampled data. The clock calibration circuit is coupled to the first sampling circuit and the second sampling circuit to receive the first sampled data and the second sampled data. The clock calibration circuit can change the phase interpolation code to change the phase of the phase interpolated clock. The clock calibration circuit counts multiple comparison results of the first sampled data and the second sampled data in multiple clock cycles for any one of different phase interpolation codes to obtain an error count value. The clock calibration circuit determines a calibration code as the phase interpolation code provided to the phase interpolator based on these error count values corresponding to different phase interpolation codes.

[0007] According to an embodiment of the present invention, the above-mentioned operation method includes: generating first sampled data by the first sampling circuit sampling a data signal according to a data clock; generating a phase interpolated clock by the phase interpolator changing the phase of the data clock based on a phase interpolation code change amount; generating second sampled data by the second sampling circuit sampling the data signal according to the phase interpolated clock; changing the phase interpolation code by the clock calibration circuit to change the phase of the phase interpolated clock; for any one of different phase interpolation codes, counting multiple comparison results of the first sampled data and the second sampled data in multiple clock cycles by the clock calibration circuit to obtain an error count value; and determining a calibration code by the clock calibration circuit based on these error count values corresponding to different phase interpolation codes as the phase interpolation code provided to the phase interpolator.

[0008] Based on the above, the eye opening monitoring device according to embodiments of the present invention can change the phase of the phase interpolated clock generated by the phase interpolator by changing the phase interpolation code, and then compare the first sampled data and the second sampled data to obtain a comparison result. For any one of different phase interpolation codes, the clock calibration circuit can count multiple comparison results (such as counting the number of times of errors occurring in these clock cycles) in multiple clock cycles to obtain an error count value. The clock calibration circuit can determine / lock the phase interpolation code (calibration code) provided to the phase interpolator based on these error count values corresponding to different phase interpolation codes so that the phase of the phase interpolated clock matches the phase of the data clock. Description of the Drawings

[0009] Figure 1It is a schematic diagram of a circuit block of an eye opening monitor device according to an embodiment of the present invention.

[0010] Figure 2 It is a schematic diagram of a circuit block of an eye opening monitor device applied to a serializer / deserializer according to an embodiment of the present invention.

[0011] Figure 3 It is a schematic flowchart of an operation method of an eye opening monitor device according to an embodiment of the present invention.

[0012] Figure 4 As illustrated in an embodiment of the present invention, Figure 3 It is a schematic flowchart of the shown step S320.

[0013] Figure 5 As illustrated in an embodiment of the present invention, Figure 4 It is a schematic diagram of a specific operation example of the shown process.

[0014] Figure 6 As illustrated in another embodiment of the present invention, Figure 4 It is a schematic diagram of a specific operation example of the shown process.

[0015] Figure 7 As illustrated in an embodiment of the present invention, Figure 3 It is a schematic flowchart of the shown step S330.

[0016] Figure 8 As illustrated in another embodiment of the present invention, Figure 3 It is a schematic flowchart of the shown step S330.

[0017] Figure 9 As illustrated in yet another embodiment of the present invention, Figure 3 It is a schematic flowchart of the shown step S330.

[0018] Figure 10 As illustrated in an embodiment of the present invention, Figure 9 It is a schematic flowchart of the shown step S910.

[0019] Figure 11 As illustrated in still another embodiment of the present invention, Figure 3 It is a schematic flowchart of the shown step S330.

[0020] Figure 12 As illustrated in an embodiment of the present invention, Figure 11 It is a schematic flowchart of the shown step S1130.

[0021] Description of Reference Numerals

[0022] 100, 200: Eye opening monitoring device

[0023] 110: Phase interpolator

[0024] 120: Sampling circuit

[0025] 121, 131, 270: Buffer

[0026] 122, 132, 280: Sense amplifier

[0027] 123, 133: Deserializer

[0028] 130: Sampling circuit

[0029] 140: Clock calibration circuit

[0030] 250: Clock Data Recovery (CDR) circuit

[0031] 260: Data switching circuit

[0032] 261: Divider

[0033] 262: Multiplexer

[0034] 263: Equalizer

[0035] D_CLK: Data clock

[0036] D_D, PI_D: Sampled data

[0037] E_CLK: Edge clock

[0038] ERR_CNT: Error count value

[0039] MAX_CODE: Rated interpolation code

[0040] NONERR5, NONERR61, NONERR62, NONERR63: Continuous region

[0041] PI_CLK: Phase interpolation clock

[0042] PI_CODE: Phase interpolation code

[0043] RXD: Received data

[0044] S310~S330, S410~S460, S705~S765, S810~S820, S910~S920, S1130, S1210~S1260: Steps

[0045] SD: Data signal

[0046] SD_EYE1, SD_EYE2: Eye diagram

[0047] TD: Test data

[0048] X51, X52, X61, X62, X63, X64: Reference phase interpolation code Detailed implementation manners

[0049] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used in the drawings and the description to refer to the same or like parts.

[0050] As used throughout the specification of this application (including the claims), the term "coupled (or connected)" can refer to any direct or indirect means of connection. For example, if it is described in the text that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some means of connection. The terms "first", "second", etc. mentioned throughout the specification of this application (including the claims) are used to name elements or to distinguish different embodiments or scopes, rather than to limit the upper or lower limits of the number of elements, nor to limit the order of the elements. Additionally, wherever possible, components / elements / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / elements / steps using the same reference numerals or the same terms in different embodiments can be referred to each other's relevant descriptions.

[0051] Figure 1 FIG. is a schematic diagram of a circuit block of an eye opening monitor device 100 according to an embodiment of the present invention. Figure 1 The illustrated eye opening monitor device 100 includes a phase interpolator 110, a sampling circuit 120, a sampling circuit 130, and a clock calibration circuit 140. The phase interpolator 110 can receive a data clock D_CLK and generate a phase interpolation clock PI_CLK. The sampling circuit 120 is coupled to the phase interpolator 110 to receive the phase interpolation clock PI_CLK. The clock calibration circuit 140 is coupled to the sampling circuit 120 and the sampling circuit 130 to receive a second sampled data (sampled data PI_D) and a first sampled data (sampled data D_D).

[0052] Figure 1The eye-opening monitoring device 100 shown can be applied to any electronic circuit according to the actual design. For example, the eye-opening monitoring device 100 can be applied to a serializer / deserializer (SerDes) and / or other electronic circuits. For example, Figure 2 FIG. Figure 2 is a schematic circuit block diagram of an eye-opening monitoring device 200 applied to a serializer / deserializer according to an embodiment of the present invention. Figure 2 The eye-opening monitoring device 200 shown includes a phase interpolator 110, a sampling circuit 120, a sampling circuit 130, a clock calibration circuit 140, a clock data recovery (CDR) circuit 250, and a data switching circuit 260. Figure 2 The eye-opening monitoring device 200, the phase interpolator 110, the sampling circuit 120, the sampling circuit 130, and the clock calibration circuit 140 shown can refer to Figure 1 the related descriptions of the eye-opening monitoring device 100, the phase interpolator 110, the sampling circuit 120, the sampling circuit 130, and the clock calibration circuit 140 shown, and / or Figure 1 the eye-opening monitoring device 100, the phase interpolator 110, the sampling circuit 120, the sampling circuit 130, and the clock calibration circuit 140 shown can refer to Figure 2 the related descriptions of the eye-opening monitoring device 200, the phase interpolator 110, the sampling circuit 120, the sampling circuit 130, and the clock calibration circuit 140 shown.

[0053] The CDR circuit 250 can provide a received data RXD, a data clock D_CLK, and an edge clock E_CLK. The specific implementation manner of the CDR circuit 250 is not limited in this embodiment. According to the actual design, in some embodiments, the CDR circuit 250 can include a known CDR circuit or other CDR circuits. The data switching circuit 260 is coupled to the CDR circuit 250 to receive the data clock D_CLK and the received data RXD. The data switching circuit 260 is coupled to the sampling circuit 120, the sampling circuit 130, and a sense amplifier 280 to provide a data signal SD. The data switching circuit 260 can selectively output a test data TD as the data signal SD during calibration. The data switching circuit 260 can selectively output the received data RXD as the data signal SD during normal operation.

[0054] The specific implementation manner of the data switching circuit 260 is not limited in this embodiment. According to the actual design, in Figure 2In the illustrated embodiment, the data switching circuit 260 may include a frequency divider 261, a multiplexer 262, and an equalizer 263. The input terminal of the frequency divider 261 is coupled to the CDR circuit 250 to receive the data clock D_CLK. The clock calibration circuit 140 may control / determine the frequency division ratio of the frequency divider 261. Based on the frequency division ratio, the frequency divider 261 may divide the data clock D_CLK to generate test data TD (i.e., the divided clock). The first input terminal of the multiplexer 262 is coupled to the output terminal of the frequency divider 261 to receive the test data TD. The second input terminal of the multiplexer 262 is coupled to the CDR circuit 250 to receive the received data RXD. The output terminal of the multiplexer 262 is coupled to the input terminal of the equalizer 263. Based on the control of the clock calibration circuit 140, the multiplexer 262 may select to output the test data TD to the equalizer 263 during calibration, and select to output the received data RXD to the equalizer 263 during normal operation. The output terminal of the equalizer 263 is coupled to the sampling circuits 120, 130, and the sense amplifier 280 to provide a data signal SD.

[0055] In Figure 2 In the illustrated embodiment, the sampling circuit 120 includes a buffer 121, a sense amplifier 122, and a deserializer 123. The input terminal of the buffer 121 is coupled to the phase interpolator 110 to receive the phase interpolated clock PI_CLK. The clock terminal of the sense amplifier 122 is coupled to the output terminal of the buffer 121 to receive the buffered phase interpolated clock. The input terminal of the sense amplifier 122 is coupled to the output terminal of the equalizer 263 to receive the data signal SD. The output terminal of the sense amplifier 122 outputs a sampled data string to the deserializer 123. The input terminal of the deserializer 123 is coupled to the output terminal of the sense amplifier 122 to receive the sampled data string. The output terminal of the deserializer outputs the sampled data PI_D to the clock calibration circuit 140.

[0056] In Figure 2 In the illustrated embodiment, the sampling circuit 130 includes a buffer 131, a sense amplifier 132, and a deserializer 133. The input terminal of the buffer 131 is coupled to the CDR circuit 250 to receive the data clock D_CLK. The clock terminal of the sense amplifier 132 is coupled to the output terminal of the buffer 131 to receive the buffered data clock. The input terminal of the sense amplifier 132 is coupled to the output terminal of the equalizer 263 to receive the data signal SD. The output terminal of the sense amplifier 132 outputs a sampled data string to the deserializer 133. The input terminal of the deserializer 133 is coupled to the output terminal of the sense amplifier 132 to receive the sampled data string. The output terminal of the deserializer 133 outputs the sampled data D_D to the clock calibration circuit 140.

[0057] The input terminal of buffer 270 is coupled to the CDR circuit 250 to receive the edge clock E_CLK. The clock terminal of sense amplifier 280 is coupled to the output terminal of buffer 270 to receive the buffered edge clock. The input terminal of sense amplifier 280 is coupled to the output terminal of equalizer 263 to receive the data signal SD.

[0058] According to different design requirements, the above-mentioned clock calibration circuit 140 can be implemented in the form of hardware, firmware, software (i.e., programs), or a combination of multiple of the foregoing three. In terms of hardware, the above-mentioned clock calibration circuit 140 can be implemented as a logic circuit on an integrated circuit. The related functions of the above-mentioned clock calibration circuit 140 can be implemented as hardware using a hardware description language (such as Verilog HDL or VHDL) or other suitable programming languages. For example, the related functions of the above-mentioned clock calibration circuit 140 can be implemented in various logic blocks, modules, and circuits of one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), and / or other processing units. In terms of software form and / or firmware form, the related functions of the above-mentioned clock calibration circuit 140 can be implemented as programming codes. For example, the above-mentioned clock calibration circuit 140 is implemented using general programming languages (such as C, C ++, or assembly language) or other suitable programming languages. The programming codes can be recorded / stored in a "non-transitory computer readable medium". In some embodiments, the non-transitory computer readable medium includes, for example, tapes, disks, cards, semiconductor memories, programmable logic circuits, and / or storage devices. The storage device includes a hard disk drive (HDD), a solid-state drive (SSD), or other storage devices. A computer, a central processing unit (CPU), a controller, a microcontroller, or a microprocessor can read and execute the programming codes from the non-transitory computer readable medium to implement the above-mentioned clock calibration circuit 140.

[0059] Figure 3 is a schematic flowchart of an operation method of an eye opening monitoring device according to an embodiment of the present invention. Please refer to Figure 2 (or Figure 1 ) and Figure 3. In step S310, the phase interpolator 110 can generate a phase interpolated clock PI_CLK by changing the phase of the data clock D_CLK based on the phase interpolation code PI_CODE. The sampling circuit 120 can sample the data signal SD according to the timing of the phase interpolated clock PI_CLK to generate sampled data PI_D, and the sampling circuit 130 can sample the data signal SD according to the data clock D_CLK to generate sampled data D_D.

[0060] In step S320, the clock calibration circuit 140 can change the phase interpolation code PI_CODE to change the phase of the phase interpolated clock PI_CLK generated by the phase interpolator 110, and then compare the sampled data PI_D with the sampled data D_D to obtain a comparison result. For example, the clock calibration circuit 140 can check whether the sampled data PI_D is the same as the sampled data D_D. The clock calibration circuit 140 can also count multiple comparison results in multiple clock cycles for any one of different phase interpolation codes PI_CODE in step S320 to obtain an error count value. For example, the clock calibration circuit 140 can count the number of times an error occurs in the sampled data PI_D compared to the sampled data D_D in multiple clock cycles for one phase interpolation code PI_CODE to obtain an error count value, and count the number of times an error occurs in the sampled data PI_D in multiple clock cycles for another phase interpolation code PI_CODE to obtain another error count value. In step S330, the clock calibration circuit 140 can determine / lock a calibration code as the phase interpolation code PI_CODE provided to the phase interpolator 110 based on these error count values corresponding to different phase interpolation codes PI_CODE.

[0061] Figure 3 The specific implementation details of the shown step S320 can be determined according to the actual design. For example, Figure 4 is shown according to an embodiment of the present invention, Figure 3 the flow diagram of the shown step S320. In Figure 4In the illustrated embodiment, step S320 includes steps S410, S420, S430, S440, S450, and S460. In step S410, test data TD is applied (or selected) as data signal SD. For example, the frequency divider 261 may perform a frequency division operation of doubling the data clock D_CLK to generate test data TD in step S410. That is, the data clock D_CLK may be used as test data TD in step S410. Next, the clock calibration circuit 140 may scan different phase interpolation codes PI_CODE to count the error count values corresponding to each phase interpolation code PI_CODE. Before entering step S420, the clock calibration circuit 140 may reset the current phase interpolation code PI_CODE to an initial value (e.g., reset to 0).

[0062] In step S420, the clock calibration circuit 140 may check whether the current phase interpolation code PI_CODE exceeds the rated interpolation code MAX_CODE. The rated interpolation code MAX_CODE may be determined according to actual design requirements. For example, in some embodiments, the value range of the phase interpolation code PI_CODE is 0 to 63, so the rated interpolation code MAX_CODE may be "63". When the current phase interpolation code PI_CODE does not exceed the rated interpolation code MAX_CODE (the judgment result of step S420 is "yes"), the clock calibration circuit 140 may proceed to step S430.

[0063] In step S430, the clock calibration circuit 140 may apply the current phase interpolation code PI_CODE, that is, provide the current phase interpolation code PI_CODE to the phase interpolator 110. Based on the phase interpolation code PI_CODE provided by the clock calibration circuit 140, the phase interpolator 110 may adjust the phase of the phase interpolation clock PI_CLK to the phase corresponding to the current phase interpolation code PI_CODE. That is, the rising edge (or falling edge) of the phase interpolation clock PI_CLK is at the X-axis position of the eye diagram corresponding to the current phase interpolation code PI_CODE.

[0064] In step S440, the clock calibration circuit 140 can compare the sampled data PI_D with the sampled data D_D over multiple clock cycles to obtain multiple comparison results. For example, the clock calibration circuit 140 can check whether the sampled data PI_D is the same as the sampled data D_D in the first clock cycle to obtain a first comparison result. The operations of the clock calibration circuit 140 in other clock cycles can be inferred by analogy. The number of clock cycles for running step S440 can be determined according to the actual design (or actual application). For example, in some embodiments, the clock calibration circuit 140 can compare the sampled data PI_D with the sampled data D_D over 10,000 clock cycles to obtain 10,000 comparison results. In other embodiments, the clock calibration circuit 140 can compare the sampled data PI_D with the sampled data D_D over 100,000 clock cycles to obtain 100,000 comparison results.

[0065] The clock calibration circuit 140 can also obtain an error count value ERR_CNT by counting the multiple comparison results over multiple clock cycles for the current phase interpolation code PI_CODE in step S440. For example, the clock calibration circuit 140 can count the number of times an error occurs (i.e., the sampled data PI_D is not equal to the sampled data D_D) for the sampled data PI_D compared to the sampled data D_D over multiple clock cycles to obtain an error count value ERR_CNT corresponding to the current phase interpolation code PI_CODE.

[0066] After step S440 is completed, the clock calibration circuit 140 can proceed to step S450. In step S450, the clock calibration circuit 140 can store / hold this error count value ERR_CNT corresponding to the current phase interpolation code PI_CODE, and then proceed to step S460. In step S460, the clock calibration circuit 140 can increment the current phase interpolation code PI_CODE. For example, the clock calibration circuit 140 can increase the phase interpolation code PI_CODE by one step. After incrementing the phase interpolation code PI_CODE, the clock calibration circuit 140 can perform step S420 again to check whether the current phase interpolation code PI_CODE exceeds the rated interpolation code MAX_CODE. When the current phase interpolation code PI_CODE exceeds the rated interpolation code MAX_CODE (the judgment result of step S420 is "no"), the clock calibration circuit 140 can proceed to step S330.

[0067] Figure 5 is shown according to an embodiment of the present invention, Figure 4 a schematic diagram of a specific operation example of the shown process. Figure 5The upper part shows a curve graph of the error count value ERR_CNT, where the vertical axis represents the error count value ERR_CNT (i.e., the number of times the sampled data PI_D is not equal to the sampled data D_D), and the horizontal axis represents the phase interpolation code PI_CODE. The value range of the phase interpolation code PI_CODE is 0 to MAX_CODE, where the rated interpolation code MAX_CODE can be determined according to actual design requirements. Figure 5 The eye diagram SD_EYE1 of the data signal SD, the data clock D_CLK, and the phase interpolation clock PI_CLK are also shown. The clock calibration circuit 140 can change the phase interpolation code PI_CODE to change the phase of the phase interpolation clock PI_CLK generated by the phase interpolator 110, and then check and compare whether the sampled data PI_D is the same as the sampled data D_D to obtain a comparison result. For any one of different phase interpolation codes PI_CODE, the clock calibration circuit 140 can count multiple comparison results in multiple clock cycles to obtain the error count value ERR_CNT. For example, the clock calibration circuit 140 can count the number of times the sampled data PI_D has an error (i.e., PI_D is different from D_D) in 10,000 clock cycles for a phase interpolation code PI_CODE to obtain an error count value ERR_CNT, and count the number of times the sampled data PI_D has an error in the next 10,000 clock cycles for another phase interpolation code PI_CODE to obtain another error count value ERR_CNT. After completing the scan of the phase interpolation code PI_CODE, the clock calibration circuit 140 can obtain Figure 5 The curve graph of the error count value ERR_CNT shown in the upper part.

[0068] Figure 6 It is shown according to another embodiment of the present invention. Figure 4 A schematic diagram of a specific operation example of the shown process. Figure 6 The eye diagram SD_EYE2 of the shown data signal SD indicates that the data signal SD is affected by noise interference, resulting in false eyes in the eye diagram SD_EYE2. Figure 6 The data clock D_CLK and the phase interpolation clock PI_CLK are also shown. The clock calibration circuit 140 can change the phase interpolation code PI_CODE to change the phase of the phase interpolation clock PI_CLK generated by the phase interpolator 110, and then check and compare whether the sampled data PI_D is the same as the sampled data D_D to obtain a comparison result.

[0069] Figure 6The upper part shows a curve graph of the error count value ERR_CNT, where the vertical axis represents the error count value ERR_CNT (i.e., the number of times the sampled data PI_D is not equal to the sampled data D_D), and the horizontal axis represents the phase interpolation code PI_CODE. The numerical range of the phase interpolation code PI_CODE is 0 to MAX_CODE. For any one of the different phase interpolation codes PI_CODE, the clock calibration circuit 140 can count multiple comparison results in multiple clock cycles to obtain the error count value ERR_CNT. After completing the scan of the phase interpolation code PI_CODE, the clock calibration circuit 140 can obtain Figure 6 The curve graph of the error count value ERR_CNT shown in the upper part.

[0070] Figure 3 The specific implementation details of the shown step S330 can be determined according to the actual design. For example, in some embodiments, the clock calibration circuit 140 can scan different phase interpolation codes PI_CODE to find one or more continuous regions in these error count values ERR_CNT of different phase interpolation codes PI_CODE (such as Figure 5 or Figure 6 the curve of the error count value ERR_CNT shown) that represent error-free count values, and select one from the different phase interpolation codes in this continuous region (or the largest continuous region among these continuous regions) as the calibration code. The definition of the "count value representing no error" can be determined according to the actual design. For example, in some embodiments, the "count value representing no error" can be "0". In other embodiments, the "count value representing no error" can be "a count value less than a certain threshold", where the threshold can be an integer determined according to the actual design.

[0071] If taking the Figure 5 curve of the error count value ERR_CNT shown as an example, the "continuous region of count values representing no error" can be Figure 5 the continuous region NONERR5 shown. The clock calibration circuit 140 can select one from the different phase interpolation codes in the continuous region NONERR5 as the calibration code.

[0072] If taking the Figure 6 curve of the error count value ERR_CNT shown as an example, the "continuous region of count values representing no error" can be Figure 6The continuous regions NONERR61, NONERR62, and NONERR63 are shown. The clock calibration circuit 140 may select / keep the largest continuous region NONERR62 from these continuous regions NONERR61, NONERR62, and NONERR63, while ignoring / discarding the small continuous regions NONERR61 and NONERR63. The clock calibration circuit 140 may select one of the different phase interpolation codes in the largest continuous region NONERR62 as the calibration code.

[0073] Figure 7 is shown according to an embodiment of the present invention. Figure 3 The schematic flowchart of the step S330 is shown. In Figure 7 the embodiment shown, the step S330 includes steps S705, S710, S715, S720, S725, S730, S735, S740, S745, S750, S755, S760, and S765. In step S705, the current phase interpolation code PI_CODE is reset to 0, and the previous length prev_length is also reset to 0. In step S710, the current length cur_length is reset to 0.

[0074] The clock calibration circuit 140 may check in step S715 whether the error count value ERR_CNT corresponding to the current phase interpolation code PI_CODE is a "count value indicating no error". In Figure 7 the embodiment shown, the "count value indicating no error" may be "0". When the error count value ERR_CNT corresponding to the current phase interpolation code PI_CODE is 0 (the judgment result of step S715 is "yes"), the clock calibration circuit 140 may execute step S720. The clock calibration circuit 140 may check in step S720 whether the current length cur_length is 0. When the current length cur_length is 0 (the judgment result of step S720 is "yes"), the clock calibration circuit 140 may execute step S725 to set the current start position cur_start to the current phase interpolation code PI_CODE. When the current length cur_length is not 0 (the judgment result of step S720 is "no"), the clock calibration circuit 140 may execute step S730.

[0075] In step S730, the clock calibration circuit 140 can increment the current length cur_length by one step. In step S735, the clock calibration circuit 140 can check whether the previous length prev_length is less than the current length cur_length. When the previous length prev_length is less than the current length cur_length (the judgment result in step S735 is "yes"), the clock calibration circuit 140 can execute step S740 to set the previous length prev_length to the current length cur_length and set the previous start position prev_start to the current start position cur_start. When the previous length prev_length is not less than the current length cur_length (the judgment result in step S735 is "no"), the clock calibration circuit 140 can execute step S745.

[0076] In step S745, the clock calibration circuit 140 can increment the current phase interpolation code PI_CODE by one step. In step S750, the clock calibration circuit 140 can check whether the current phase interpolation code PI_CODE exceeds the rated interpolation code MAX_CODE. When the current phase interpolation code PI_CODE exceeds the rated interpolation code MAX_CODE (the judgment result in step S750 is "no"), the clock calibration circuit 140 can execute step S755. When the current phase interpolation code PI_CODE has not exceeded the rated interpolation code MAX_CODE (the judgment result in step S750 is "yes"), the clock calibration circuit 140 can return to step S715.

[0077] When the error count value ERR_CNT corresponding to the current phase interpolation code PI_CODE is not 0 (the judgment result in step S715 is "no"), the clock calibration circuit 140 can execute step S760. In step S760, the clock calibration circuit 140 can increment the current phase interpolation code PI_CODE by one step. In step S765, the clock calibration circuit 140 can check whether the current phase interpolation code PI_CODE exceeds the rated interpolation code MAX_CODE. When the current phase interpolation code PI_CODE has not exceeded the rated interpolation code MAX_CODE (the judgment result in step S765 is "yes"), the clock calibration circuit 140 can return to step S710.

[0078] When the current phase interpolation code PI_CODE exceeds the rated interpolation code MAX_CODE (the judgment result in step S765 is "No"), the clock calibration circuit 140 can execute step S755. In step S755, the clock calibration circuit 140 can select a phase interpolation code as the calibration code in a continuous region defined by the previous start position prev_start and the previous length prev_length. According to the actual design, in some embodiments, the clock calibration circuit 140 can calculate the phase interpolation code = prev_start + (prev_length) / 2 as the calibration code.

[0079] Figure 3 The specific implementation details of the illustrated step S330 are not limited to Figure 7 the related description. For example, in some other embodiments, the clock calibration circuit 140 can scan different phase interpolation codes PI_CODE to find multiple reference phase interpolation codes with error count peaks among these different phase interpolation codes PI_CODE. Then, the clock calibration circuit 140 can use these reference phase interpolation codes to calculate the calibration code.

[0080] Figure 8 is shown according to another embodiment of the present invention, Figure 3 the flowchart of the illustrated step S330. In Figure 7 the illustrated embodiment, step S330 includes steps S810 and S820. In step S810, the clock calibration circuit 140 can scan different phase interpolation codes PI_CODE to find multiple reference phase interpolation codes with error count peaks from these phase interpolation codes PI_CODE. In step S820, the clock calibration circuit 140 can use these reference phase interpolation codes to calculate the calibration code.

[0081] If taking Figure 5 the curve of the illustrated error count value ERR_CNT as an example, the clock calibration circuit 140 can find two reference phase interpolation codes X51 and X52 with error count peaks from these phase interpolation codes PI_CODE (step S810). The clock calibration circuit 140 can use these two reference phase interpolation codes X51 and X52 to calculate the calibration code in step S820. For example, in some embodiments, the clock calibration circuit 140 can calculate (X51 + X52) / 2 as the calibration code in step S820.

[0082] If taking Figure 6Taking the curve of the error count value ERR_CNT shown as an example, the clock calibration circuit 140 can find four reference phase interpolation codes X61, X62, X63, and X64 with error count peaks from these phase interpolation codes PI_CODE (step S810). The clock calibration circuit 140 can use these four reference phase interpolation codes X61, X62, X63, and X64 to calculate the calibration code in step S820. For example, in some embodiments, the clock calibration circuit 140 can calculate Y61 = (X61 + X62) / 2 and calculate Y62 = (X63 + X64) / 2 in step S820. Next, the clock calibration circuit 140 can calculate (Y61 + Y62) / 2 as the calibration code.

[0083] Figure 3 The specific implementation details of the shown step S330 are not limited to Figure 7 and Figure 8 the related descriptions. For example, Figure 9 is illustrated according to another embodiment of the present invention, Figure 3 the flow schematic diagram of the shown step S330. In Figure 9 the shown embodiment, step S330 includes steps S910 and S920. In step S910, the clock calibration circuit 140 can scan the different phase interpolation codes PI_CODE to find at least one continuous region of the count values representing no error among the multiple error count values ERR_CNT, and then retain the largest continuous region from the at least one continuous region. According to the actual design, in some embodiments, Figure 9 the implementation details of the shown step S910 can refer to Figure 10 the related details.

[0084] Figure 10 is illustrated according to an embodiment of the present invention, Figure 9 the flow schematic diagram of the shown step S910. In Figure 10 the shown embodiment, step S330 includes steps S705, S710, S715, S720, S725, S730, S735, S740, S745, S750, S760, and S765. Figure 10 The shown steps S705, S710, S715, S720, S725, S730, S735, S740, S745, S750, S760, and S765 can be analogized with reference to Figure 7 the related descriptions of the shown steps S705, S710, S715, S720, S725, S730, S735, S740, S745, S750, S760, and S765, so details are not repeated here. Different from the embodiment shown in Figure 7 is that in Figure 10In the illustrated embodiment, when the judgment result of step S750 (or step S765) is "No", the clock calibration circuit 140 executes step S920.

[0085] In Figure 9 In the illustrated step S920, the clock calibration circuit 140 may find multiple reference phase interpolation codes having error count peaks in different phase interpolation codes PI_CODE. Then, the clock calibration circuit 140 may use these reference phase interpolation codes to calculate the calibration code. Figure 9 The illustrated step S920 may be analogized with reference to Figure 8 the relevant description of the illustrated process, and thus will not be elaborated herein.

[0086] Figure 3 The specific implementation details of the illustrated step S330 are not limited to Figure 7 , Figure 8 or Figure 9 the relevant description. For example, Figure 11 is illustrated according to a further embodiment of the present invention, Figure 3 the flow diagram of the illustrated step S330. In Figure 11 the illustrated embodiment, step S330 includes steps S910, S920 and S1130. Figure 11 The illustrated steps S910 and S920 may be analogized with reference to Figure 9 the relevant description of the illustrated steps S910 and S920, and thus will not be elaborated herein.

[0087] Figure 3 The data signal SD (first test data) used in the illustrated step S320 is different from Figure 11 the data signal SD (second test data) used in the illustrated step S1130. For example, the first test data is a first clock signal, and the second test data is a second clock signal, where the period of the first clock signal is less than the period of the second clock signal.

[0088] After determining the calibration code (i.e., after step S920), the clock calibration circuit 140 may control the frequency divider 261 to perform a frequency division operation of doubling the frequency of the data clock D_CLK to generate the test data TD. That is, assuming the period of the data clock D_CLK is T, the data signal SD (second test data) at this time may be a clock signal with a period of 2T. The second test data may be used to fine-tune the calibration code. In Figure 11In the illustrated step S1130, the sampling circuit 130 samples the second test data (data signal SD) in accordance with the data clock D_CLK to generate third sampled data (sampled data D_D), and the sampling circuit 120 samples the second test data (data signal SD) in accordance with the phase interpolation clock PI_CLK to generate fourth sampled data (sampled data PI_D). The clock calibration circuit 140 can check the third sampled data and the fourth sampled data to determine whether to fine-tune the calibration code. The clock calibration circuit 140 can use the fine-tuned calibration code as the phase interpolation code PI_CODE provided to the phase interpolator 110.

[0089] Figure 12 is illustrated according to an embodiment of the present invention, Figure 11 a schematic flow diagram of the illustrated step S1130. In Figure 12 the illustrated embodiment, step S1130 includes steps S1210, S1220, S1230, S240, S1250, and S1260. In step S1210, test data TD (second test data) with a period of 2T is applied as the data signal SD, and the calibration code calculated in step S920 is applied as the phase interpolation code PI_CODE provided to the phase interpolator 110. In step S1220, the sampling circuit 130 samples the second test data (data signal SD) in accordance with the data clock D_CLK to generate third sampled data (sampled data D_D), and the sampling circuit 120 samples the second test data (data signal SD) in accordance with the phase interpolation clock PI_CLK to generate fourth sampled data (sampled data PI_D). In step S1230, the clock calibration circuit 140 can check the third sampled data and the fourth sampled data to determine whether to fine-tune the calibration code. When the third sampled data is different from the fourth sampled data (i.e., the judgment result of step S1230 is "no"), the clock calibration circuit 140 can perform step S1240.

[0090] In step S1240, the clock calibration circuit 140 can finely adjust the calibration code, that is, finely adjust the current phase interpolation code PI_CODE. For example, in some embodiments, the clock calibration circuit 140 can increase the current phase interpolation code PI_CODE by one step in step S1240. In other embodiments, the clock calibration circuit 140 can decrease the current phase interpolation code PI_CODE by one step in step S1240. In step S1250, the clock calibration circuit 140 can reset the frequency divider 261. After resetting the frequency divider 261, the clock calibration circuit 140 can return to step S1220 to generate the third sampled data (sampled data D_D) and the fourth sampled data (sampled data PI_D) again. When the third sampled data is the same as the fourth sampled data (that is, the judgment result in step S1230 is "yes"), the clock calibration circuit 140 can perform step S1260. In step S1260, the clock calibration circuit 140 can use the finely adjusted calibration code as the phase interpolation code PI_CODE provided to the phase interpolator 110.

[0091] In summary, the eye opening monitoring device described in the above embodiments can change the phase of the phase interpolation clock PI_CLK generated by the phase interpolator 110 by changing the phase interpolation code PI_CODE, and then compare the sampled data PI_D and the sampled data D_D to obtain a comparison result. For any one of different phase interpolation codes PI_CODE, the clock calibration circuit 140 can count / statistical multiple comparison results in multiple clock cycles (for example, count the number of errors occurring in these clock cycles), and obtain an error count value ERR_CNT corresponding to a certain phase interpolation code PI_CODE. The clock calibration circuit 140 can determine / lock the phase interpolation code PI_CODE (calibration code) provided to the phase interpolator 110 based on these error count values ERR_CNT corresponding to different phase interpolation codes PI_CODE, so that the phase of the phase interpolation clock PI_CLK matches the phase of the data clock D_CLK.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An eye-opening monitoring device, characterized in that, The eye opening monitoring device includes: A first sampling circuit configured to sample a data signal according to a data clock to generate first sampled data; A phase interpolator configured to receive the data clock, wherein the phase interpolator changes the phase of the data clock based on a phase interpolation code to generate a phase interpolated clock; A second sampling circuit coupled to the phase interpolator to receive the phase interpolated clock, configured to sample the data signal according to the phase interpolated clock to generate second sampled data; and A clock calibration circuit coupled to the first sampling circuit and the second sampling circuit to receive the first sampled data and the second sampled data, wherein the clock calibration circuit changes the phase interpolation code to change the phase of the phase interpolated clock, the clock calibration circuit counts comparison results of the first sampled data and the second sampled data in a plurality of clock cycles for any one of different phase interpolation codes to obtain an error count value, and the clock calibration circuit determines a calibration code as the phase interpolation code provided to the phase interpolator based on the plurality of error count values corresponding to different phase interpolation codes.

2. The eye-opening monitoring device according to claim 1, wherein The first sampling circuit includes: A buffer having an input terminal for receiving the data clock; A sense amplifier having a clock terminal coupled to an output terminal of the buffer to receive a buffered data clock, wherein an input terminal of the sense amplifier receives the data signal, and an output terminal of the sense amplifier outputs a sampled data string; and A deserializer having an input terminal coupled to the output terminal of the sense amplifier to receive the sampled data string, wherein an output terminal of the deserializer outputs the first sampled data to the clock calibration circuit.

3. The eye-opening monitoring device according to claim 1, wherein The second sampling circuit includes: A buffer having an input terminal coupled to the phase interpolator to receive the phase interpolated clock; A sense amplifier having a clock terminal coupled to an output terminal of the buffer to receive a buffered phase interpolated clock, wherein an input terminal of the sense amplifier receives the data signal, and an output terminal of the sense amplifier outputs a sampled data string; and A deserializer having an input terminal coupled to the output terminal of the sense amplifier to receive the sampled data string, wherein an output terminal of the deserializer outputs the second sampled data to the clock calibration circuit.

4. The eye-opening monitoring device according to claim 1, characterized in that, The eye opening monitoring device further includes: A clock data recovery circuit for providing the data clock and receiving data.

5. The eye-opening monitoring device according to claim 1, wherein The eye opening monitoring device further includes: A data switching circuit coupled to the first sampling circuit and the second sampling circuit to provide the data signal, wherein the data switching circuit selectively outputs test data as the data signal during calibration, and the data switching circuit selectively outputs received data as the data signal during normal operation.

6. The eye-opening monitoring device according to claim 5, characterized in that, The data switching circuit includes: A frequency divider having an input terminal for receiving the data clock, wherein an output terminal of the frequency divider outputs the test data; A multiplexer having a first input terminal coupled to the output terminal of the frequency divider to receive the test data, wherein a second input terminal of the multiplexer is for receiving the received data; and An equalizer, having an input terminal coupled to an output terminal of the multiplexer, wherein an output terminal of the equalizer is coupled to the first sampling circuit and the second sampling circuit to provide the data signal.

7. The eye-opening monitoring device according to claim 1, wherein The clock calibration circuit scans the different phase interpolation codes to find at least one continuous region of the count values representing no error among the multiple error count values, and selects one of the different phase interpolation codes in the largest continuous region of the at least one continuous region as the calibration code.

8. The eye-opening monitoring device according to claim 1, characterized in that, The clock calibration circuit scans the different phase interpolation codes to find multiple reference phase interpolation codes having error count peaks among the different phase interpolation codes, and uses the multiple reference phase interpolation codes to calculate the calibration code.

9. The eye-opening monitoring device according to claim 1, wherein The clock calibration circuit scans the different phase interpolation codes to find at least one continuous region of the count values representing no error among the multiple error count values, retains the largest continuous region from the at least one continuous region, finds multiple reference phase interpolation codes having error count peaks among the different phase interpolation codes, and uses the multiple reference phase interpolation codes to calculate the calibration code.

10. The eye-opening monitoring device according to claim 1, characterized in that, The first test data is used as the data signal to determine the calibration code, and second test data different from the first test data after determining the calibration code is used as the data signal to fine-tune the calibration code.

11. The eye-opening monitoring device according to claim 10, characterized in that, The first test data is a first clock signal, the second test data is a second clock signal, and a period of the first clock signal is less than a period of the second clock signal.

12. The eye-opening monitoring device according to claim 10, wherein The first sampling circuit samples the second test data according to the data clock to generate third sampling data, the second sampling circuit samples the second test data according to the phase interpolation clock to generate fourth sampling data, and the clock calibration circuit checks the third sampling data and the fourth sampling data to determine whether to fine-tune the calibration code.

13. A method for operating an eye-opening monitoring device, characterized in that, The operation method includes: generating first sampling data by a first sampling circuit sampling a data signal according to a data clock; generating a phase interpolation clock by a phase interpolator changing a phase of the data clock based on a phase interpolation code; generating second sampling data by a second sampling circuit sampling the data signal according to the phase interpolation clock; changing the phase interpolation code by a clock calibration circuit to change a phase of the phase interpolation clock; obtaining an error count value by the clock calibration circuit counting multiple comparison results of the first sampling data and the second sampling data in multiple clock cycles for any one of the different phase interpolation codes; and determining a calibration code by the clock calibration circuit based on the multiple error count values corresponding to the different phase interpolation codes as the phase interpolation code provided to the phase interpolator.

14. The operating method according to claim 13, characterized in that, The operation method further includes: scanning, by the clock calibration circuit, the different phase interpolation codes to find at least one continuous region of the count values representing no error among the multiple error count values; and selecting one of the different phase interpolation codes in the largest continuous region of the at least one continuous region as the calibration code.

15. The operating method according to claim 13, characterized in that, The operation method further includes: The clock calibration circuit scans the different phase interpolation codes to find multiple reference phase interpolation codes having error count peaks in the different phase interpolation codes: and uses the multiple reference phase interpolation codes to calculate the calibration code.

16. The operation method according to claim 13, wherein The operation method further includes:[[]] The clock calibration circuit scans the different phase interpolation codes to find at least one continuous region of the count values representing error-free count values among the multiple error count values; retains the largest continuous region from the at least one continuous region; finds multiple reference phase interpolation codes having error count peaks in the different phase interpolation codes; and uses the multiple reference phase interpolation codes to calculate the calibration code.

17. The operating method according to claim 13, characterized in that, The operation method further includes:[[]] uses first test data as the data signal to determine the calibration code; and after determining the calibration code, uses second test data different from the first test data as the data signal to fine-tune the calibration code.

18. The operating method according to claim 17, characterized in that, The first test data is a first clock signal, the second test data is a second clock signal, and the period of the first clock signal is less than the period of the second clock signal.

19. The operating method according to claim 17, wherein, The operation method further includes:[[]] the first sampling circuit samples the second test data according to the data clock to generate third sampling data; the second sampling circuit samples the second test data according to the phase interpolation clock to generate fourth sampling data; and the clock calibration circuit checks the third sampling data and the fourth sampling data to determine whether to fine-tune the calibration code.

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