A decoding method and device

Abstract

The present application discloses a coding device, including: a staircase error decorrelation interleaver (SEDI), a staircase code encoder, a staircase error decorrelation deinterleaver (SEDD) and an output unit; SEDI is used to receive a first information sequence, and the first information sequence is processed by SEDI to obtain a second information sequence; the staircase code encoder is used to perform staircase coding on the second information sequence to obtain a first check sequence; SEDD is used to perform SEDD processing on the first check sequence to obtain a second check sequence; the output unit is used to receive the first information sequence, and combine the second check sequence and the first information sequence for output; or receive the first information sequence at the next moment, and combine the second check sequence and the first information sequence at the next moment for output. The coding device disclosed in the present application can play a role in reducing noise correlation, and SEDD does not need to interleave the information sequence, and the coding complexity is low.

Description

[0001] This application is a divisional application. The application number of the original application is 201810032298.2, and the original application date is January 12, 2018. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of coding, and in particular to a coding method and device for solving noise correlation. Background Art

[0003] At present, high-speed optical transmission networks are developing towards large capacity, packetization, and intelligence. High-speed optical transmission networks need to use efficient forward error correction (FEC) codes to combat optical damage during optical transmission (such as uncompensated dispersion, polarization mode dispersion, and nonlinear effects) and maintain a sufficiently low bit error rate during long-distance transmission. Among them, most FEC codes are designed under additive white Gaussian noise (AWGN).

[0004] However, in an actual communication system, noise is correlated, and the correlation of noise can lead to performance degradation of FEC codes. The coding method and device provided in the present application can reduce the impact of noise correlation on the coding system, and the coding complexity is low. Summary of the invention

[0005] The purpose of the present application is to provide a coding method and device to solve the problem of coding system performance degradation caused by noise correlation.

[0006] In a first aspect, a coding device is provided, comprising: a staircase error decorrelation interleaver (SEDI), a staircase code encoder, a staircase error decorrelation deinterleaver (SEDD) and an output unit; the SEDI is used to perform SEDI processing on a received first information sequence to obtain a second information sequence; the staircase code encoder is used to perform staircase encoding on the second information sequence to obtain a first check sequence; the SEDD is used to perform SEDD processing on the first check sequence to obtain a second check sequence; the output unit is used to receive the first information sequence, combine the second check sequence with the first information sequence and output it; or combine the second check sequence with the first information sequence at the next moment and output it.

[0007] The information sequence and the check sequence contained in the sequence finally output by the encoding device provided in the embodiment of the present application are disrupted in position (that is, interleaved) relative to the information sequence and the check sequence generated by the staircase code encoder. Therefore, it can reduce the noise correlation. Moreover, SEDD does not need to interleave the information sequence, and the encoding complexity and power consumption are not high.

[0008] In a possible implementation, the operations of the SEDI and the SEDD are mutually inverse, and the SEDI and the SEDD interleave the received data in units of bits. This embodiment can ensure the systematicness of the output sequence and improve the code performance.

[0009] In one possible implementation, the ladder code encoder includes a first cache and a second cache, wherein the first cache stores a second information sequence at a current moment, and the second cache stores data stored in the first cache at a previous moment; the ladder code encoder is used to encode the mth row data in the first cache and the nth column data in the second cache to obtain the mth verification data, and write the mth verification data into the mth row of the first cache, wherein m and n are both integers, and the value of m corresponds to a unique value of n; the ladder code encoder reads the verification data in the first cache to obtain the first verification sequence.

[0010] In a possible implementation, when the number of rows M of data in the first cache is greater than the number of columns N of data in the second cache, the data in the second cache includes additional MN columns of all-0 data, where M and N are both positive integers.

[0011] In a possible implementation manner, the lengths of the first information sequence and the second information sequence are 512×478 bits, and the lengths of the first check sequence and the second check sequence are 512×32 bits.

[0012] In a second aspect, a coding method is provided, characterized in that it includes: receiving a first information sequence, performing step error decorrelation interleaving (SEDI) processing on the first information sequence to obtain a second information sequence; performing step coding on the second information sequence to obtain a first check sequence; performing step error decorrelation deinterleaving (SEDD) processing on the first check sequence to obtain a second check sequence; merging the second check sequence and the first information sequence and outputting them, or merging the second check sequence and the first information sequence at the next moment and outputting them.

[0013] In a possible implementation, the interleaving operation performed on the first information sequence and the interleaving operation performed on the first check sequence are inverse to each other, and both are interleaved in units of bits. This embodiment can ensure the systematicness of the output sequence and improve the code performance.

[0014] In a possible implementation, the second information sequence is step-coded to obtain a first check sequence, specifically including: encoding the m-th row data in the first cache and the n-th column data in the second cache to obtain the m-th check data, and writing the m-th check data into the m-th row of the first cache, wherein the first cache stores the second information sequence at the current moment, and the second cache stores the data stored in the first cache at the previous moment; m and n are both integers, and the value of m corresponds to a unique value of n; and the check data in the first cache is read out to obtain the first check sequence.

[0015] In a possible implementation, when the number of rows M of data in the first cache is greater than the number of columns N of data in the second cache, the data in the second cache includes additional MN columns of all-0 data, where M and N are both positive integers.

[0016] In a possible implementation manner, the lengths of the first information sequence and the second information sequence are 512×478 bits, and the lengths of the first check sequence and the second check sequence are 512×32 bits.

[0017] According to a third aspect, a coding device is provided, comprising: an input interface, a processor and an output interface, wherein the processor is used to receive a first information sequence through the input interface and send a merged sequence through the output interface; and is also used to perform step error decorrelation interleaving (SEDI) processing on the first information sequence to obtain a second information sequence; perform step coding on the second information sequence to obtain a first check sequence; perform step error decorrelation deinterleaving (SEDD) processing on the first check sequence to obtain a second check sequence; and merge the second check sequence with the first information sequence, or merge the second check sequence with the first information sequence at the next moment.

[0018] In a possible implementation, the interleaving operation performed on the first information sequence and the interleaving operation performed on the first check sequence are inverse to each other, and both are interleaved in units of bits. This embodiment can ensure the systematicness of the output sequence and improve the code performance.

[0019] In a possible implementation, the processor performs step encoding on the second information sequence to obtain a first check sequence, specifically including: the processor encodes the m-th row data in the first cache and the n-th column data in the second cache to obtain the m-th check data, and writes the m-th check data into the m-th row of the first cache, wherein the first cache stores the second information sequence at a current moment, and the second cache stores the data stored in the first cache at a previous moment; m and n are both integers, and the value of m corresponds to a unique value of n; the check data in the first cache is read out to obtain the first check sequence.

[0020] In a possible implementation, when the number of rows M of data in the first cache is greater than the number of columns N of data in the second cache, the data in the second cache includes additional MN columns of all-0 data, where M and N are both positive integers.

[0021] In a possible implementation manner, the lengths of the first information sequence and the second information sequence are 512×478 bits, and the lengths of the first check sequence and the second check sequence are 512×32 bits.

[0022] The information sequence and the check sequence contained in the sequence finally output by the encoding device provided in the embodiment of the present application are disrupted in position (that is, interleaved) relative to the information sequence and the check sequence generated by the staircase code encoder. Therefore, it can reduce the noise correlation. Moreover, SEDD does not need to interleave the information sequence, and the encoding complexity and power consumption are not high. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural block diagram of the communication system;

[0024] Figure 2 A structural block diagram of a coding device provided in an embodiment of the present application;

[0025] Figure 3 A structural block diagram of a SEDD provided in another embodiment of the present application;

[0026] Figure 4 An interleaving table in a SEDD provided in another embodiment of the present application;

[0027] FIG5( a ) is a structural block diagram of a coding device provided in another embodiment of the present application;

[0028] FIG5( b ) is a structural block diagram of a coding device provided in another embodiment of the present application;

[0029] FIG6( a) is a structural block diagram of a coding device provided in another embodiment of the present application;

[0030] FIG6( b ) is a structural block diagram of a coding device provided in another embodiment of the present application;

[0031] Figure 7 A flow chart of an encoding method provided in another embodiment of the present application;

[0032] Figure 8 This is a structural block diagram of the encoding device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0034] Figure 1 The structural block diagram of the communication system is shown. At the transmitting end, the source provides a data stream to be sent; the encoder receives the data stream, encodes it, and sends the encoded data stream to the transmitter, which sends the encoded data stream out through the channel. At the receiving end, the receiver receives the encoded data stream, decodes it through the decoder, recovers the original data, and sends it to the destination. Among them, the encoding method provided by the present application is used for Figure 1 The encoder shown is a very important part of the communication system.

[0035] The present application embodiment provides a coding device, such as Figure 2 As shown, it includes: a staircase error de-correlator interleaver (SEDI) staircase error decorrelation deinterleaver 210, a staircase code encoder 220, a staircase error de-correlator DE-Interleaver (SEDD) staircase error decorrelation deinterleaver 230 and an output unit 240,

[0036] SEDI 210, used to receive a first information sequence, and perform SEDI processing on the first information sequence to obtain a second information sequence;

[0037] The ladder code encoder 220 is used to perform ladder coding on the second information sequence to obtain a first check sequence.

[0038] Specifically, the ladder code encoder 220 includes a first cache and a second cache, wherein the first cache stores a second information sequence at a current moment, and the second cache stores data stored in the first cache at a previous moment; the ladder code encoder encodes the mth row data in the first cache and the nth column data in the second cache to obtain the mth check data, and writes the mth check data into the mth row of the first cache, wherein m and n are both integers, and the value of m corresponds to a unique value of n; the check data in the first cache is read out to obtain a first check sequence.

[0039] Assuming that the second information sequence is 512 rows×478 columns, and m=3, n=1, the third row of data in the first cache and the first column of data in the second cache together constitute 478+512=990 ​​bits of data, and the 990 bits of data are encoded (Bose-Chaudhuri-Hocquenghem, BCH) to obtain a BCH codeword with a length of 1022 bits, wherein the extra 32 bits of information are the third check data, and the third check data is stored in the third row of the first cache; and so on, 512 32-bit check data are obtained, which are respectively stored in 512 rows of the first cache, where the value of m corresponds to a unique value of n, and the corresponding relationship is pre-written.

[0040] It is worth noting that the second cache stores all the data stored in the first cache at the previous moment, that is, the second cache includes the information data and check data stored in the first cache at the previous moment, that is, the data in the second cache is 512 rows × 510 columns. At this time, the number of rows of data in the first cache, 512, is greater than the number of columns of data in the second cache, 510, and the number of columns of data in the second cache is two columns less, so an additional 2 columns of all-0 data are added to the data in the second cache to make up the number of columns in the second cache. In this way, at the current moment, 512 32-bit check data can be obtained.

[0041] SEDD 230 is used to perform SEDD processing on the first check sequence to obtain a second check sequence. Specifically, SEDD 230 performs SEDD processing on the first check sequence in units of bits; wherein SEDD 230 includes a first 12-level interleaver 301, a group interleaver 302, a second 12-level interleaver 303 and a controller 304, such as Figure 3 The first 12-stage interleaver 301 includes 12 interleavers connected in series, which together constitute Figure 4 The interleaving table shown in the figure shows that every 64-bit first check sequence is interleaved. Figure 3 After the interleaving table shown, a 64-bit first information sequence with disrupted position order is obtained; it is worth noting that Figure 4 1-64 represents the 64 bits in the first check sequence, and 0-63 represents the position of the bit after interleaving. The controller 304 can generate 12-bit binary control data p1_cnt (value range is 1 to 4095) to control which one or more interleavers among the 12 serial interleavers included in the first 12-stage interleaver work; for example, when p1_cnt = 1 (00000000 0001), the first 11 interleavers do not work, and only the 12th interleaver works, which is reflected in Figure 4In the interleaving table shown, columns 1-11 do not work, and only the 12th column can be focused on. At this time, after the first bit of the first check sequence is interleaved, the value of the 12th column of the 1st row is 4, indicating that it has switched to the position of the 5th bit; after the second bit of the first check sequence is interleaved, the value of the 12th column of the 2nd row is 11, indicating that it has switched to the position of the 12th bit; and so on, every 64 bits of the first check sequence are interleaved to obtain a first check sequence in a shuffled order. When p1_cnt=3(0000 0000 0011), the first 10 interleavers do not work, and only the 11th and 12th interleavers work. At this time, you can only look at Figure 4 In the 11-12 columns, the first bit of the first check sequence is first interleaved by the 11th interleaver, and the value of the 11th column of the 1st row is 14, indicating that it is switched to the position of the 15th bit. Then the 15th bit passes through the 12th interleaver, and the value of the 12th column of the 15th row is 47, indicating that it is switched to the position of the 48th bit. That is, after the first bit of the first check sequence passes through the first 12-level interleaver, it will be switched to the position of the 48th bit. And so on, every 64-bit first check sequence is interleaved to obtain a first check sequence in a shuffled order.

[0042] It is worth noting that the first 12-stage interleaver 301 is time-varying with a time-varying period of 5, that is, Figure 4 The interleaving table shown is only one of the five interleaving tables included in the first 12-stage interleaver 301. After a group of 64-bit first check sequences are interleaved, the next interleaving table will be switched to in a cycle.

[0043] The group interleaver 302 is used to perform a "row-by-row" interleaving operation on the first check sequence after passing through the first 12-stage interleaver 301; still taking the first information sequence of 512 rows × 478 columns as an example, after passing through the step code encoder 220, the length of the first check sequence should be 512 rows × 32 columns, that is, 16384 bits. The first check sequence can be divided into 256 groups of sequences with a length of 64 bits, each group of 64-bit sequences is interleaved by the first 12-stage interleaver 301, and the interleaved data is sent to the group interleaver 302; the group interleaver 302 divides the interleaved data into 8 groups, each group has 2048 bits, and performs row-column interleaving on the 8 groups of data in turn, and sends the row-column interleaved data to the second 12-stage interleaver 303, wherein the row-column interleaving method of each group of data is as follows: first write into the group interleaver 302 by row, each row has 64 bits, and a total of 32 rows; when reading, it is read by column, the first 32 bits of the output sequence come from the first column, the 33rd to 64th bits come from the second column, and so on.

[0044] The second 12-level interleaver 303 is used to interleave the sequence output by the group interleaver 302 again to obtain a second check sequence. The second 12-level interleaver 303 has the same structure as the first 12-level interleaver 301, except that the interleaving table in the second 12-level interleaver 303 is different from the interleaving table in the first 12-level interleaver 301. Further, when controlling the operation of the second 12-level interleaver 303, the value range of the twelve-bit binary control signal p2_cnt generated by the controller 304 is: 1 to (4095-41).

[0045] It is worth noting that the interleaving function of SEDI is reversible with the interleaving function of SEDD. The data entering SEDI enters the third 12-level interleaver, the group interleaver and the fourth 12-level interleaver in turn for interleaving and output. Among them, the third 12-level interleaver performs the inverse operation of the second 12-level interleaver, the fourth 12-level interleaver performs the inverse operation of the first 12-level interleaver, and the group interleaver of SEDI performs the inverse operation of the group interleaver of SEDD.

[0046] Specifically, the execution process of the group interleaver in SEDI is described below. Since the data length entering the group interleaver in SEDI is 512×478=244736 bits, the 244736 bits are divided into 8 groups, each with 30592 bits, and the following operations are performed on the 30592-bit data: the 30592-bit data is divided into 12 groups, the first 11 groups include 40×64 bits, which are written into the group interleaver by column, 40 bits per column, and 64 columns in total; the 12th group includes 38×64 bits, which are also written into the group interleaver by column, 38 bits per column, and 64 columns in total; when reading, it is read out by row, first read out the 64 bits of the first row, then read the second row, and so on. After the group interleaver of SEDI performs "column-out" interleaving on the 8 groups of 30592-bit data in sequence, the interleaved data is sent to the fourth 12-level interleaver.

[0047] The output unit 240 is configured to receive the first information sequence, combine the second check sequence and the first information sequence for output; or receive the first information sequence at the next moment, combine the second check sequence and the first information sequence at the next moment for output.

[0048] Specifically, in the case where the output unit 240 combines and outputs the second check sequence and the first information sequence, the output unit 240 includes a cache unit 541 and a merging unit 542, as shown in FIG5(a), the cache unit is used to store the first information sequence, and after the SEDD 230 outputs the second check sequence, the second check sequence and the first information sequence are combined and output by the merging unit, or the output unit 240 includes a delay unit 543 and a merging unit 542, as shown in FIG5(b), the delay unit 543 delays the first information sequence, and then the second check sequence and the first information sequence are combined and output by the merging unit 542, and the specific delay time is: the difference between the time when the first information sequence enters the encoding device and the time when the second check sequence is generated, minus the time required for the first information sequence to be output. In this case, after the first information sequence is output, the second check sequence is output next, and no additional cache is required.

[0049] Further, in the case where the output unit 240 combines and outputs the second check sequence with the first information sequence at the next moment, the output unit 240 may include a cache unit 641 and a merging unit 642, as shown in FIG6(a), the cache unit 641 is used to store the second check sequence, and after the output unit 240 receives the first information sequence at the next moment, the second check sequence and the first information sequence at the next moment are combined and output through the merging unit 642, or the output unit 240 includes a delay unit 643 and a merging unit 642, as shown in FIG6(b), the delay unit 643 delays the second check sequence, and then combines and outputs the second check sequence and the first information sequence at the next moment through the merging unit 642, and the specific delay time is: the difference between the generation time of the second check sequence and the time when the first information sequence at the next moment is output from the encoding device. At this time, after the first information sequence at the next moment is output, the second check sequence at the current moment is output next, and no additional cache is required.

[0050] The information sequence and the check sequence contained in the sequence finally output by the encoding device provided in this embodiment are disrupted in position (that is, interleaved) relative to the information sequence and the check sequence generated by the staircase code encoder. Therefore, it can play a role in reducing noise correlation. Moreover, SEDD does not need to interleave the information sequence, and the encoding complexity and power consumption are not high.

[0051] Another embodiment of the present application provides an encoding method, such as Figure 7 As shown, including:

[0052] 701. Receive a first information sequence, and perform SEDI processing on the first information sequence to obtain a second information sequence.

[0053] 702. Perform ladder coding on the second information sequence to obtain a first check sequence.

[0054] 703. Perform SEDD processing on the first check sequence to obtain a second check sequence.

[0055] 704. Combine the second check sequence and the first information sequence and output them; or receive the first information sequence at the next moment, combine the second check sequence and the first information sequence at the next moment and output them.

[0056] The interleaving method of SEDI and SEDD has been described in detail in the previous device embodiment, and will not be repeated here in this embodiment.

[0057] Optionally, the first information sequence at the current moment is stored in the first cache, and the data stored in the first cache at the previous moment is stored in the second cache; step 702 specifically includes: encoding the m-th row data in the first cache and the n-th column data in the second cache to obtain the m-th verification data, and writing the m-th verification data into the m-th row of the first cache, wherein m and n are both integers, and the value of m corresponds to a unique value of n; and then reading the verification data in the first cache to obtain the first verification sequence.

[0058] Further, when the number of rows M of data in the first cache is greater than the number of columns N of data in the second cache, the data in the second cache includes additional MN columns of all-0 data, where M and N are both positive integers.

[0059] Optionally, merging the second check sequence and the first information sequence for output specifically includes: storing the first information sequence, and merging the second check sequence and the first information sequence for output after the second check sequence is obtained, or delaying the first information sequence, and then merging the second check sequence and the first information sequence for output, wherein the specific delay time is: the difference between the time when the first information sequence enters the encoding device and the time when the second check sequence is generated, minus the time required for the first information sequence to be output. In this case, after the first information sequence is output, the second check sequence is output next, and no additional cache is required.

[0060] Optionally, merging the second check sequence with the first information sequence at the next moment and outputting it specifically includes: storing the second check sequence, and after receiving the first information sequence at the next moment, merging the second check sequence with the first information sequence at the next moment and outputting it, or delaying the second check sequence, and then merging the second check sequence with the first information sequence at the next moment and outputting it, and the specific delay time is: the difference between the generation time of the second check sequence and the time when the first information sequence at the next moment is output from the encoding device. In this case, after the first information sequence at the next moment is output, the second check sequence at the current moment is outputted next, and no additional cache is required.

[0061] In the encoding method provided in this embodiment, the information sequence and the check sequence contained in the final output sequence are disrupted relative to the information sequence and the check sequence generated by the encoding (that is, interleaved), so it can play a role in reducing noise correlation, and there is no need to interleave the information sequence in step 703, so the encoding complexity and power consumption are not high.

[0062] Another embodiment of the present application provides a coding device 800, such as Figure 8 As shown, it includes: an input interface 801, a processor 802 and an output interface 803; the processor 802 is used to receive the first information sequence through the input interface 801, send the combined sequence through the output interface 803, and implement the steps and functions implemented by the cascade coding device 800 in the above-mentioned implementation manner, which will not be repeated here.

[0063] The present application provides an embodiment of a computer-readable storage medium or a computer program product for storing a computer program, which is used to execute the encoding method involved in the above method embodiment.

[0064] Understandably, Figure 8 Only a simplified design of the encoding device is shown. In practical applications, the encoding device may include any number of interfaces and processors, etc., and all terminals that can implement the embodiments of the present application are within the protection scope of the embodiments of the present application.

[0065] It is further understood that the processor involved in the embodiments of the present application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0066] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present invention. Therefore, "in one embodiment" or "in an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. In various embodiments of the present invention, the serial numbers of the above-mentioned processes do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0067] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or it can be an electrical, mechanical or other form of connection.

[0068] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0069] In short, the above is only a preferred embodiment of the technical solution of the present invention, and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A processing device, characterized in that: Includes a receiver and a decoder; The receiver is used to receive a first sequence, wherein the first sequence includes a second check sequence and a first information sequence at a next moment, the second check sequence is obtained by performing a step code error decorrelation deinterleaving process on the first check sequence, the first check sequence is obtained by performing a step code encoding on the second information sequence, and the second information sequence is obtained by performing a step code error decorrelation interleaving process on the first information sequence; The decoder is used to decode the first sequence.

2. The processing device according to claim 1, characterized in that The operations of the staircase code error decorrelation interleaving and the staircase code error decorrelation deinterleaving are inverse to each other, and the staircase code error decorrelation interleaving and the staircase code error decorrelation deinterleaving interleave the received data in units of bits.

3. The processing device according to claim 1 or 2, characterized in that: The length of the first information sequence and the second information sequence is 512×478 bits, and the length of the first check sequence and the second check sequence is 512×32 bits.

4. A processing method, characterized in that: The method comprises: Receive a first sequence, wherein the first sequence includes a second check sequence and a first information sequence at a next moment, the second check sequence is obtained by performing step code error decorrelation deinterleaving processing on the first check sequence, the first check sequence is obtained by performing step code encoding on the second information sequence, and the second information sequence is obtained by performing step code error decorrelation interleaving processing on the first information sequence; The first sequence is decoded.

5. The processing method according to claim 4, characterized in that: The interleaving operation performed on the first information sequence and the interleaving operation performed on the first check sequence are inverse to each other, and both are interleaved in units of bits.

6. The processing method according to claim 4 or 5, characterized in that: The length of the first information sequence and the second information sequence is 512×478 bits, and the length of the first check sequence and the second check sequence is 512×32 bits.

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