Semiconductor structure and method of forming the same

Abstract

Semiconductor structures and methods of forming the same are provided. A method of forming a semiconductor structure includes forming a floating gate layer on a substrate. A trench is formed in the floating gate layer and the substrate. A first dielectric layer is formed in the trench. A second dielectric layer is formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. A first sacrificial layer is formed on the third dielectric layer. A dielectric stack is formed on the first sacrificial layer. A control gate layer is formed on the dielectric stack. The first sacrificial layer is removed to form an air gap between the third dielectric layer and the dielectric stack.

Description

Technical Field

[0001] This application relates to semiconductor structures and methods for forming them, and in particular to semiconductor structures with air gaps and methods for forming them. Background Technology

[0002] Non-volatile memory typically includes a floating gate and a control gate. The floating gate traps and stores electrons, while the control gate controls the potential and is connected to the word line. As demands increase, semiconductor structures are expected to have smaller dimensions to improve integration density. However, shrinking the size of semiconductor structures can introduce coupling interference between adjacent floating gates, i.e., interference between active regions. Alternatively, leakage current problems may arise, leading to a decrease in the reliability and yield of the semiconductor structure.

[0003] Therefore, existing semiconductor structures and their fabrication methods do not yet fully meet the requirements in all aspects. Consequently, there are still some problems to be overcome regarding semiconductor structures and their fabrication methods that can be further processed into non-volatile memory. Summary of the Invention

[0004] In view of the aforementioned problems, this application, by sequentially forming a first dielectric layer, a second dielectric layer, a third dielectric layer, and a dielectric stack in a trench, can form an air gap between the third dielectric layer and the dielectric stack, thereby avoiding coupling interference and leakage problems through the air gap. In particular, since this application uses a multi-layer dielectric layer combined with a dielectric stack structure, the reliability of the semiconductor structure can be maintained when using wet etching to form the air gap, thereby improving the reliability and performance of the subsequently formed memory devices.

[0005] This application provides a method for forming a semiconductor structure, comprising: forming a floating gate layer on a substrate; forming a trench in the floating gate layer and the substrate; forming a first dielectric layer in the trench; forming a second dielectric layer on the first dielectric layer; forming a third dielectric layer on the second dielectric layer; forming a first sacrificial layer on the third dielectric layer; forming a dielectric stack on the first sacrificial layer; forming a control gate layer on the dielectric stack; and removing the first sacrificial layer to form an air gap between the third dielectric layer and the dielectric stack.

[0006] This application provides a semiconductor structure comprising: a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a dielectric stack. The substrate has trenches between multiple active regions. The first dielectric layer is disposed in the trenches. The second dielectric layer is disposed on the first dielectric layer. The third dielectric layer is disposed on the second dielectric layer. The dielectric stack is disposed on the third dielectric layer. An air gap is provided between the third dielectric layer and the dielectric stack.

[0007] The semiconductor structure of this application can be applied to various types of memory devices. To make the components and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0008] Figures 1 to 11 These are cross-sectional schematic diagrams illustrating the formation of semiconductor structures at various stages, based on some embodiments of this application.

[0009] Figure 12 This is a three-dimensional schematic diagram of a semiconductor structure based on some embodiments of this application.

[0010] Figure 13 This is a cross-sectional schematic diagram of a semiconductor structure according to some embodiments of this application.

[0011] Figure 14 This is a three-dimensional schematic diagram of a semiconductor structure based on some embodiments of this application.

[0012] Figure 15 This is a top view schematic diagram of a semiconductor structure according to some embodiments of this application. Detailed Implementation

[0013] Figures 1 to 11 and Figure 13 This is a cross-sectional schematic diagram illustrating the formation of semiconductor structure 1 at various stages according to some embodiments of this application. Figure 12 for Figure 11 A three-dimensional schematic diagram, and Figure 14 Then it is Figure 13 A three-dimensional diagram. Furthermore, Figure 15 This is a top-down view, and Figures 1 to 11 and Figure 13 It is along Figure 15 A cross-sectional diagram of line segment XX'.

[0014] Reference Figure 1 In some embodiments, a substrate 100 is provided, on which a tunneling dielectric layer 110, a floating gate layer 200, a first hard mask 210, and a second hard mask 220 are sequentially formed. That is, the tunneling dielectric layer 110 is formed on the substrate 100; the floating gate layer 200 is formed on the tunneling dielectric layer 110; the first hard mask 210 is formed on the floating gate layer 200; and the second hard mask 220 is formed on the first hard mask 210.

[0015] The substrate 100 may be, for example, a silicon wafer; it may be a bulk semiconductor or a semiconductor-on-insulation (SOI) substrate. Generally, an SOI substrate comprises a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or a similar material, providing the insulating layer on a silicon or glass substrate. Other types of substrate 100 include, for example, multilayer or gradient substrates. In some embodiments, the substrate 100 may be an elemental semiconductor, including silicon and germanium; the substrate 100 may also be a compound semiconductor, including, for example, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, but not limited thereto; the substrate 100 may also be an alloy semiconductor, including, for example, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or any combination thereof, but this application is not limited thereto. In some embodiments, the substrate 100 may be a doped or undoped semiconductor substrate.

[0016] The tunneling dielectric layer 110 may be or may include oxides, nitrides, oxynitrides, combinations thereof, or any other suitable dielectric material, but this application is not limited thereto. The tunneling dielectric layer 110 may be, for example, silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials, any other suitable dielectric materials, or combinations thereof. High-k dielectric materials may be metal oxides, metal nitrides, metal silicides, transition metal oxides, transition metal nitrides, transition metal silicides, metal oxynitrides, metal aluminates, zirconium silicates, or zirconium aluminates.

[0017] The tunneling dielectric layer 110 can be formed by a deposition process or a thermal oxidation process. The aforementioned deposition process may include or may be a chemical vapor deposition (CVD) process, and the aforementioned CVD process may be low-pressure chemical vapor deposition (LPCVD), low-temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) of atomic layer chemical vapor deposition, atmospheric pressure chemical vapor deposition (APCVD), or other suitable processes.

[0018] The floating gate layer 200 may include polycrystalline silicon, amorphous silicon, metal, metal nitride, conductive metal oxide, combinations thereof, or other suitable materials, but this application is not limited thereto. In some embodiments, the floating gate layer 200 may be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process.

[0019] In some embodiments, a first hard mask 210 and a second hard mask 220 are formed on the floating gate layer 200. The first hard mask 210 and / or the second hard mask 220 may include oxides, nitrides, oxynitrides, carbides, or combinations thereof. It is understood that suitable materials can be selected to form the first hard mask 210 and the second hard mask 220 depending on the subsequent etching process conditions, and therefore the embodiments of this application are not limited thereto. The first hard mask 210 may include oxides, and the second hard mask 220 may include nitrides. The first hard mask 210 and / or the second hard mask 220 may be obtained by CVD deposition or other suitable processes. In some embodiments, the second hard mask 220 may be omitted or other hard masks may be used.

[0020] After forming the first hard mask 210 and the second hard mask 220, the first hard mask 210 and the second hard mask 220 can be patterned according to the required shape of the trench 300. The first hard mask 210 and the second hard mask 220 can be used as etching masks to remove a portion of the floating gate layer 200, the tunneling dielectric layer 110, and the substrate 100 through an etching process to form the trench 300 in the floating gate layer 200, the tunneling dielectric layer 110, and the substrate 100. The aforementioned etching process can include dry etching, wet etching, or other suitable etching methods. Dry etching can include, but is not limited to, plasma etching, plasma-free gas etching, sputter etching, ion milling, and reactive ion etching (RIE). Wet etching can include, but is not limited to, using acidic solutions, alkaline solutions, or solvents to remove at least a portion of the structure to be removed. In addition, the etching process can be purely chemical etching, purely physical etching, or any combination thereof.

[0021] Trench 300 is used to define, for example, subsequent... Figure 15 The active area is shown. In other words, multiple active areas can be separated from each other by trench 300. A floating gate layer 200 and a subsequently formed control gate layer may be disposed in the active area. Trench 300 may be a shallow trench isolation structure. Trench 300 may penetrate the second hard mask 220, the first hard mask 210, the floating gate layer 200 and the tunneling dielectric layer 110, but does not penetrate the substrate 100.

[0022] like Figure 1 As shown, after forming trench 300, a liner 310 and a first dielectric layer 320 are formed. The liner 310 is conformally disposed in trench 300, and the first dielectric layer 320 is conformally disposed on the liner 310. The materials and formation processes of the liner 310 and / or the first dielectric layer 320 may be the same as or different from those of the tunneling dielectric layer 110. The liner 310 may include oxides, such as high-temperature oxide (HTO) or silicon oxide. The first dielectric layer 310 may include nitrides, such as silicon nitride. In some embodiments, the liner 310 and / or the first dielectric layer 320 may be formed by a deposition process.

[0023] Reference Figure 2A second dielectric layer 330 is formed on the first dielectric layer 320. The second dielectric layer 330 is formed on the first dielectric layer 320 in a blanket-like manner. The material and formation process of the second dielectric layer 330 may be the same as or different from the material and formation process of the tunneling dielectric layer 110. The second dielectric layer 330 can be formed by high-density plasma chemical vapor deposition (HDP-CVD). After forming the second dielectric layer 330, a planarization process can be further performed to make the top surface of the second dielectric layer 330 substantially flush with the top surface of the first dielectric layer 320. The aforementioned planarization process can be a chemical mechanical planarization (CMP) process.

[0024] The second dielectric layer 330 may include an oxide, such as an oxide or silicon oxide formed using tetraethoxysilane (TEOS) as a precursor. In some embodiments, the second dielectric layer 330 may be a porous oxide.

[0025] Reference Figure 3 A portion of the second dielectric layer 330 is removed by dry etching to expose the first dielectric layer 320 in the trench 300, while the second dielectric layer 330A remains on the first dielectric layer 320. In some embodiments, the upper portion of the second dielectric layer 330 is removed by dry etching. The aforementioned dry etching process can be a reactive ion etching process. Therefore, by using a dry etching process, the size and shape of the second dielectric layer 330A remaining on the first dielectric layer 320 can be precisely controlled, thereby controlling the size and shape of the subsequently formed air gap.

[0026] After the dry etching process, the second dielectric layer 330A is exposed above the first dielectric layer 320 near the upper part of the trench 300. The second dielectric layer 330A covers the first dielectric layer 320 near the lower part of the trench 300. The top surface of the second dielectric layer 330A may be lower than, flush with, or higher than the tunneling dielectric layer 110. Depending on the application requirements, the height of the top surface of the second dielectric layer 330A can affect the size and shape of the air gap subsequently formed.

[0027] The second dielectric layer 330A may include an extension that extends upward. The extension of the second dielectric layer 330A is located at the upper part of the trench 300. The extension of the second dielectric layer 330A extends toward the subsequently formed dielectric stack. The width of the extension of the second dielectric layer 330A gradually decreases upward.

[0028] After performing a dry etching process, the second dielectric layer 330A has a concave top surface, such as a U-shaped top surface, a V-shaped top surface, a concave top surface, or other similar top surface. The second dielectric layer 330A has a convex bottom surface, such as a convex bottom surface. In some embodiments, the second dielectric layer 330A has a tip portion located between the first dielectric layer 320 and the subsequently formed third dielectric layer 340. In some embodiments, the upper portion of the second dielectric layer 330A is smaller than the lower portion of the second dielectric layer 330A.

[0029] The etching rate of the second dielectric layer 330 can be greater than that of the substrate 310, thus making it easier to etch the second dielectric layer 330 through an etching process to control the size of the second dielectric layer 330A. The etching rate of the second dielectric layer 330 can also be greater than that of the first dielectric layer 320, so that when a portion of the second dielectric layer 330 is removed by dry etching, the first dielectric layer 320 located in the trench 300 can be preserved. In other words, the first dielectric layer 320 can serve as an etching stop layer when etching the second dielectric layer 330. In some embodiments, the substrate 310 and the first dielectric layer 320 located on the top surface of the second hard mask 220 can be further removed to expose the top surface of the second hard mask 220, the substrate 310, and the first dielectric layer 320.

[0030] Reference Figure 4 A third dielectric layer 340 is formed on the second dielectric layer 330. In some embodiments, the third dielectric layer 340 is compliantly formed on the second hard mask 220, the substrate 310, the first dielectric layer 320, and the second dielectric layer 330A. In some embodiments, the first dielectric layer 320, the second dielectric layer 330, and the third dielectric layer 340 are in contact with each other. In some embodiments, the first dielectric layer 320 and the third dielectric layer 340 surround the second dielectric layer 330A. In some embodiments, the first dielectric layer 320 directly covers the bottom surface of the second dielectric layer 330A, and the third dielectric layer 340 directly covers the top surface of the second dielectric layer 330A. Because the third dielectric layer 340 is compliantly formed on the second dielectric layer 330A, the third dielectric layer 340 may have a shape corresponding to the second dielectric layer 330A.

[0031] The material and formation process of the third dielectric layer 340 may be the same as or different from those of the tunneling dielectric layer 110. The third dielectric layer 340 may include a nitride, such as silicon nitride. In some embodiments, since both the first dielectric layer 320 and the third dielectric layer 340 are silicon nitride, the first dielectric layer 320 and the third dielectric layer 340 may substantially lack an interface. In some embodiments, the third dielectric layer 340 may be formed by atomic layer deposition.

[0032] In some embodiments, the liner 310 and the second dielectric layer 330 may comprise oxides, and the first dielectric layer 320 and the third dielectric layer 340 may comprise nitrides. Therefore, in... Figure 1 In the trench 300 shown, layers with different etching rates can be alternately disposed within the trench 300. Specifically, the etching rates of the layers in the trench 300 can be alternating between high and low. In some embodiments, the etching rate of the substrate 310 is greater than the etching rate of the first dielectric layer 320, the etching rate of the first dielectric layer 320 is less than the etching rate of the second dielectric layer 330, and the etching rate of the second dielectric layer 330 is greater than the etching rate of the third dielectric layer 340. Therefore, this application can control the shape of the subsequently formed air gap by using layers with high etching rates, and can use layers with low etching rates as etching stop layers to provide support in the subsequently formed semiconductor structure.

[0033] Reference Figure 5 A first sacrificial layer 400 is formed on the third dielectric layer 340. In some embodiments, the first sacrificial layer 400 is formed on the third dielectric layer 340 in a blanket manner. The material and formation process of the first sacrificial layer 400 may be the same as or different from the material and formation process of the second dielectric layer 330. After forming the first sacrificial layer 400, a planarization process may be further performed to make the top surface of the first sacrificial layer 400 substantially flush with the top surface of the third dielectric layer 340. The first sacrificial layer 400 may be an oxide formed from tetraethoxysilane as a precursor, or it may be a spin-on glass (SOG) oxide. In some embodiments, the first sacrificial layer 400 may be a porous oxide formed from tetraethoxysilane as a precursor.

[0034] Reference Figure 6 A portion of the first sacrificial layer 400 is removed by dry etching to expose the third dielectric layer 340 in the trench 300, while the first sacrificial layer 400A remains on the third dielectric layer 340. The aforementioned dry etching process can be a SiCoNi etching process, specifically a remotely plasma-assisted dry etching process. Therefore, the size and shape of the first sacrificial layer 400A retained on the third dielectric layer 340 can be precisely controlled by using a dry etching process. In some embodiments, the shape of the first sacrificial layer 400A corresponds to the shape of the second dielectric layer 330A. In some embodiments, the first sacrificial layer 400A has a concave top surface. In some embodiments, the top surface of the first sacrificial layer 400A is lower than the floating gate layer 200.

[0035] Reference Figure 7Using the first sacrificial layer 400A as an etching mask, a portion of the third dielectric layer 340 and the first dielectric layer 320 is removed to expose the upper portion of the liner 310 in the trench 300 through the first dielectric layer 320A and the third dielectric layer 340A. In some embodiments, the first dielectric layer 320A, the third dielectric layer 340A, and the first sacrificial layer 400A are substantially coplanar. In some embodiments, the top surfaces of the first dielectric layer 320A, the third dielectric layer 340A, and the first sacrificial layer 400A are below the liner 310. In some embodiments, the third dielectric layer 340 and the second hard mask 220 located on the top surface of the floating gate layer 200 may be further removed.

[0036] Reference Figure 8 A second sacrificial layer 500 is formed on the first sacrificial layer 400A. In some embodiments, the second sacrificial layer 500 is formed on the first dielectric layer 320A, the third dielectric layer 340A, and the first sacrificial layer 400A in a blanket manner. The material and formation process of the second sacrificial layer 500 may be the same as or different from the material and formation process of the first sacrificial layer 400. After forming the second sacrificial layer 500, a planarization process may be further performed to make the top surface of the second sacrificial layer 500 substantially flush with the top surfaces of the substrate 310 and the first hard mask 210. The second sacrificial layer 500 may be a porous oxide formed from tetraethoxysilane as a precursor. In some embodiments, the second sacrificial layer 500 may be a spin-on glass (SOG) oxide. In some embodiments, since both the first sacrificial layer 400A and the second sacrificial layer 500 are porous oxides, the first sacrificial layer 400A and the second sacrificial layer 500 may substantially lack an interface. In this embodiment, the second dielectric layer 330A may also be a porous oxide.

[0037] Reference Figure 9 The second sacrificial layer 500 and the first hard mask 210 located on the floating gate layer 200 are removed to expose the floating gate layer 200. In some embodiments, the upper portion of the substrate 310 is removed, leaving the substrate 310A intact. The second sacrificial layer 500 and the first hard mask 210 can be removed by radio frequency plasma etching and SICONI technology. In some embodiments, the second sacrificial layer 500 can be completely removed, leaving the first sacrificial layer 400A intact. In other embodiments, a portion of the second sacrificial layer 500 can be removed, leaving another portion of the second sacrificial layer 500 on the first sacrificial layer 400A. Understandably, the extent of removal of the first sacrificial layer 400A can be adjusted according to subsequent electrical requirements.

[0038] like Figure 9As shown, in some embodiments, a portion of the floating gate layer 200 may be further removed to form an opening 510 in the floating gate layer 200. In some embodiments, the opening 510 may be formed by dry etching. In some embodiments, the width of the opening 510 is greater than... Figure 1 The width of the trench 300 shown. In some embodiments, the opening 510 may be used to define the dimensions of a subsequently formed control gate.

[0039] Reference Figure 10 A dielectric stack 600 is formed on the first sacrificial layer 400A. In some embodiments, the dielectric stack 600 is compliantly formed on the opening 510. The dielectric stack 600 is compliantly formed on the floating gate layer 200, the substrate 310A, the first dielectric layer 320A, the third dielectric layer 340A, and the first sacrificial layer 400A. The dielectric stack 600 on the floating gate layer 200 is further away from the substrate 100 than the dielectric stack 600 located on the first sacrificial layer 400A. The dielectric stack 600 can serve as a control dielectric layer in a subsequently formed memory device.

[0040] The dielectric stack 600 may include a first sublayer, a second sublayer, and a third sublayer. The first sublayer is disposed on a first sacrificial layer 400A. The second sublayer is disposed on the first sublayer. The third sublayer is disposed on the second sublayer. The first and third sublayers may include oxides, and the second sublayer may include nitrides. Therefore, the dielectric stack 600 may be an oxide-nitride-oxide (ONO) structure.

[0041] In another embodiment, the dielectric stack 600 may further include a bottom layer and a top layer. The bottom layer may be disposed between the first sacrificial layer 400A and the first sublayer. The top layer may be disposed between the third sublayer and the subsequently formed control gate layer. The bottom and top layers of the dielectric stack 600 may include nitrides. Therefore, the dielectric stack 600 may be a nitride-oxide-nitride-oxide-nitride (NONON) structure. In yet another embodiment, the dielectric stack 600 may consist only of silicon nitride or silicon oxide.

[0042] Reference Figure 11 A control gate layer 700 is formed on the dielectric stack 600. In some embodiments, the control gate layer 700 is formed on the dielectric stack 600 in a blanket manner. The material and formation process of the control gate layer 700 may be the same as or different from the material and formation process of the floating gate layer 200. The control gate layer 700 may include polysilicon.

[0043] like Figure 12As shown, a double patterning process can be further performed on the control gate layer 700. In some embodiments, a patterned hard mask can be formed on the control gate layer 700 to pattern the control gate layer 700 to form the shape as shown later. Figure 15 The word line WL is shown. Depending on requirements, the word line WL may further include other layers or components. A patterned control gate layer 700 extends along a first direction D1 and is spaced apart from each other in a second direction D2. In some embodiments, spacers may be further formed on the sidewalls of the control gate layer 700 to reduce leakage current generation.

[0044] Reference Figure 13 After forming the control gate layer 700 on the dielectric stack 600, a first sacrificial layer 400A between the third dielectric layer 340A and the dielectric stack 600 is removed by a wet etching process to obtain a semiconductor structure 1 with an air gap 800. In some embodiments, a wet etching process is used to substantially completely remove the first sacrificial layer 400A, and the third dielectric layer 340A and the dielectric stack 600 are used as etching stop layers, and an air gap 800 is formed at the location corresponding to the first sacrificial layer 400A to obtain the semiconductor structure 1.

[0045] In some embodiments, the air gap 800 has the same shape as the first sacrificial layer 400A. In some embodiments, the air gap 800 has a concave top surface and a convex bottom surface. In some embodiments, the air gap 800 has a pointed portion. In some embodiments, the pointed portion of the air gap 800 is more gently sloping than the pointed portion of the second dielectric layer 330A. In some embodiments, the air gap 800 has an upwardly extending extension, and the width of the extension of the air gap 800 gradually decreases upward.

[0046] An air gap 800 is formed on the third dielectric layer 340A and between the third dielectric layer 340A and the dielectric stack 600. In some embodiments, the air gap 800 is in direct contact with the third dielectric layer 340A and the dielectric stack 600. In some embodiments, the air gap 800 is surrounded by the third dielectric layer 340A and the dielectric stack 600. In other words, the air gap 800 is formed in the space formed by the third dielectric layer 340A and the dielectric stack 600. In some embodiments, the air gap 800 may be filled with air, a vacuum, or other suitable gas.

[0047] The air gap 800 is supported by the second dielectric layer 330A below the air gap 800, therefore the air gap 800 can be adjusted to be set as follows: Figure 1 The depth of the trench 300 shown. As the thickness of the second dielectric layer 330A decreases, the air gap 800... Figure 1The deeper the groove 300 shown.

[0048] In some embodiments, the etching rate of the first sacrificial layer 400A is greater than that of the third dielectric layer 340A and the dielectric stack 600, thus maintaining the reliability of the third dielectric layer 340A and the dielectric stack 600 while removing the first sacrificial layer 400A. That is, the etching rate of the first sacrificial layer 400A is greater than that of the third dielectric layer 340A, and the etching rate of the first sacrificial layer 400A is greater than the etching rate of the layer in the dielectric stack 600 that is in direct contact with the first sacrificial layer 400A.

[0049] In the case where the dielectric stack 600 is an ONO structure, the first sublayer of the dielectric stack 600 is in direct contact with the first sacrificial layer 400A. Therefore, the etching rate of the first sacrificial layer 400A is greater than the etching rate of the first sublayer of the dielectric stack 600, and also greater than the etching rate of the third dielectric layer 340A, to ensure the reliability of the dielectric stack 600 and the third dielectric layer 340A.

[0050] In the case where the dielectric stack 600 is a NONON structure, the bottom layer of the dielectric stack 600 is in direct contact with the first sacrificial layer 400A. Therefore, the etching rate of the first sacrificial layer 400A is greater than the etching rate of the bottom layer of the dielectric stack 600, and also greater than the etching rate of the third dielectric layer 340A, to ensure the reliability of the dielectric stack 600 and the third dielectric layer 340A.

[0051] It should be noted that, such as Figure 13 As shown, the first dielectric layer 320A and the third dielectric layer 340A are disposed adjacent to the air gap 800. Therefore, even if the first sacrificial layer 400A located under the dielectric stack 600 has been removed to form the air gap 800, the first dielectric layer 320A and the third dielectric layer 340A can still provide effective support for the dielectric stack 600.

[0052] It should also be noted that the shape and size of the air gap 800 are based on the shape and size of the first sacrificial layer 400A, which in turn are based on the shape and size of the second dielectric layer 330A. Therefore, when the second dielectric layer 330A is formed using a precise dry etching process, this application can precisely form the first sacrificial layer 400A, that is, precisely form the air gap 800. Furthermore, since this application forms the air gap 800 using a dry etching process, the air gap 800 can be easily adjusted by modifying the parameters of the dry etching process. Therefore, this application can provide various shapes and sizes of the air gap 800, thereby improving the adjustability of the process used to form the air gap 800.

[0053] Can be used as Figure 13The semiconductor structure 1 shown undergoes further processing to form a memory device. As... Figure 14 As shown, in some embodiments, between such Figure 1 The area between the trenches 300 shown is the active region AA, and the etchant of the aforementioned wet etching process can remove the first sacrificial layer 400A along a direction parallel to the extension direction of the active region AA, thereby forming an air gap 800. In some embodiments, the air gap 800 is disposed between adjacent active regions AA, but not within the active region AA. In some embodiments, the air gap 800 extends along the second direction D2 and is spaced apart from each other in the first direction D1. In some embodiments, the air gap 800 can be directly disposed under the dielectric stack 600 to avoid coupling interference between the active regions AA and to avoid leakage current.

[0054] Reference Figure 15 In some embodiments, such as Figure 14 The air gap 800 shown can be set as follows: Figure 15 In the region R1 shown, the extension direction of the air gap 800 is perpendicular to the extension direction of the word line WL. In some embodiments, the extension direction of the air gap 800 is parallel to the extension direction of the active region AA.

[0055] In some embodiments, a capping layer may be further formed on the word line WL. The capping layer may include an oxide. The capping layer may be formed by chemical vapor deposition. The capping layer may include a material with high step coverage to completely cover, such as... Figure 15 The area R1 shown is an overlay layer. This layer prevents components located beneath the overlay layer from being exposed and provides support for the semiconductor structure.

[0056] In summary, because the semiconductor structure of this application includes an air gap, it can effectively reduce coupling interference between active regions and avoid leakage current generation. Furthermore, this application sequentially comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, an air gap, and a dielectric stack, thereby forming a semiconductor structure with multiple dielectric layers and dielectric stacks.

[0057] Because the air gap is directly located between the third dielectric layer and the dielectric stack, and the etching rate of the first sacrificial layer is greater than that of the third dielectric layer and the dielectric stack, the integrity and reliability of the third dielectric layer and the dielectric stack can be maintained when wet etching is performed to form the air gap. Furthermore, since the first sacrificial layer is completely surrounded by the third dielectric layer and the dielectric stack, the etching time can be shortened or the etchant concentration reduced during the wet etching process, without being limited by the third dielectric layer and the dielectric stack. Therefore, the process margin for performing wet etching can be improved.

[0058] Furthermore, the formation method of this application avoids the problem of easily damaging the integrity of the air gap and the control gate layer when forming the air gap first and then forming the control gate layer on the air gap. For example, since this application first sets a component such as the first sacrificial layer at a predetermined position in the air gap, it can help form a high-quality control gate layer on the first sacrificial layer, thereby ensuring the reliability of the control gate layer.

[0059] Furthermore, since the shape and size of the air gap in this application correspond to the shape and size of the second dielectric layer, which is precisely formed using a dry etching process, the shape and size of the air gap can be easily controlled by adjusting the parameters of the dry etching process. In addition, since this application has a substrate, a first dielectric layer, and a third dielectric layer adjacent to the air gap at the top of the trench, the support strength of the dielectric stack can be improved, thereby maintaining the reliability of the semiconductor structure.

[0060] For example, even when an air gap exists beneath the dielectric stack, the substrate, first dielectric layer, and third dielectric layer adjacent to the air gap provide support for the dielectric stack, thereby preventing the dielectric stack from cracking. Furthermore, the formation method provided in this application is applicable to existing semiconductor manufacturing equipment, thus reducing process costs. In summary, this application provides a semiconductor structure with high reliability and excellent performance, as well as a method for forming the same.

[0061] Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of this application to achieve the same purpose and / or advantages as the embodiments described herein, and they can make various changes, substitutions and replacements without departing from the spirit and scope of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A floating gate layer is formed on a substrate; A trench is formed in the floating gate layer and the substrate; A first dielectric layer is formed in the trench; A second dielectric layer is formed on the first dielectric layer; A third dielectric layer is formed on the second dielectric layer; A first sacrificial layer is formed on the third dielectric layer; A dielectric stack is formed on the first sacrificial layer; A control gate layer is formed on the dielectric stack; as well as The first sacrificial layer is removed to form an air gap between the third dielectric layer and the dielectric stack. The first dielectric layer, the second dielectric layer, and the third dielectric layer are in contact with each other. The air gap has a concave top surface and a convex bottom surface, and a pointed portion of the air gap is more gentle than a pointed portion of the second dielectric layer.

2. The forming method as described in claim 1, characterized in that, Forming the second dielectric layer on the first dielectric layer further includes: The second dielectric layer is formed on the first dielectric layer in a blanket-like manner; and A portion of the second dielectric layer is removed to expose the first dielectric layer in the trench.

3. The forming method as described in claim 2, characterized in that, The third dielectric layer is compliantly formed on the floating gate layer, the first dielectric layer, and the second dielectric layer.

4. The forming method as described in claim 1, characterized in that, A liner is formed in the trench, the liner being located between the substrate and the first dielectric layer, and a first sacrificial layer is formed on the third dielectric layer, further comprising: The first sacrificial layer is formed on the third dielectric layer by a blanket-like process; Remove a portion of the first sacrificial layer to expose the third dielectric layer in the trench; and Remove the third dielectric layer, the first dielectric layer, and the substrate to expose the floating gate layer.

5. The forming method as described in claim 4, characterized in that, Removing the third dielectric layer, the first dielectric layer, and the substrate further includes: The third dielectric layer and the first dielectric layer are removed by using the remaining portion of the first sacrificial layer as a mask to expose the substrate; A second sacrificial layer is formed on the remaining portion of the first sacrificial layer; Remove the second sacrificial layer and the liner to expose the floating gate layer.

6. The forming method as described in claim 1, characterized in that, After the dielectric stack is formed on the first sacrificial layer, the first sacrificial layer is removed by wet etching.

7. A semiconductor structure, characterized in that, include: A substrate having a trench between multiple active regions; A first dielectric layer is disposed in the trench; A second dielectric layer is disposed on the first dielectric layer; A third dielectric layer is disposed on the second dielectric layer; and A dielectric stack is disposed on the third dielectric layer, and an air gap is provided between the third dielectric layer and the dielectric stack. The first dielectric layer, the second dielectric layer, and the third dielectric layer are in contact with each other. The air gap has a concave top surface and a convex bottom surface, and a pointed portion of the air gap is more gentle than a pointed portion of the second dielectric layer.

8. The semiconductor structure as described in claim 7, characterized in that, The air gap is in direct contact with the third dielectric layer and the dielectric stack.

9. The semiconductor structure as described in claim 7, characterized in that, The air gap is surrounded by the third dielectric layer and the dielectric stack.

10. The semiconductor structure as claimed in claim 7, characterized in that, The second dielectric layer comprises an oxide, and the first dielectric layer and the third dielectric layer comprise nitrides.

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