Method for optimizing virtual graphics before OPC and mask manufacturing method

Abstract

The present application provides a method for optimizing a virtual pattern before OPC, comprising the following steps: providing an original design pattern of a polysilicon layer comprising a first, a second and a third polysilicon pattern which are parallel to each other and arranged in sequence and at intervals along a predetermined direction; identifying the original design pattern and obtaining size information of the first, the second and the third polysilicon pattern; adjusting the size of the second polysilicon pattern and the positions of the first and the third polysilicon pattern based on the obtained size information of the first, the second and the third polysilicon pattern to obtain a corrected pattern. The present application also provides a manufacturing method of a mask based on the above optimization method. The present application avoids repairing the pattern after finding the undesirable pattern after performing OPC by optimizing the virtual pattern before OPC to obtain an optimized pattern, improves the flexibility of operation, reduces the risk caused by OPCV missing the pattern, improves the product yield and performance stability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing and relates to a method for optimizing virtual graphics before OPC and a method for fabricating a mask. Background Technology

[0002] Photolithography is a crucial technology in semiconductor manufacturing. It transfers patterns from a photomask to the surface of a silicon wafer, forming semiconductor products that meet design requirements. As the feature size of integrated circuits continues to shrink, the design dimensions of semiconductor devices become increasingly precise, approaching the limits of photolithography imaging systems. This leads to more pronounced light diffraction effects, resulting in optical image degradation of the final design pattern. The actual photolithographic pattern is severely distorted relative to the pattern on the photomask, causing increasingly serious deviations between the photolithographic pattern on the silicon wafer and the pattern on the photomask. This can be corrected through optical proximity effects, such as by adding sub-resolution auxiliary patterns to improve linewidth uniformity and increase the photolithography process window. This ensures the consistency between the final pattern on the silicon wafer and the design pattern, achieving a photolithographic pattern that closely approximates the user's desired target pattern.

[0003] However, at nodes of 40nm and below, as the gate size decreases, gate line shrinkage becomes more severe. Increased correction of the pattern on the photomask leads to overlap between adjacent gate patterns, causing Optical Proximity Correction (OPC) to fail. Furthermore, as the complexity of the layout increases, limitations in lithography resolution and the predictive limitations of the OPC model mean that OPC cannot cover all hotspot issues, making it difficult to comprehensively address the ever-changing layouts.

[0004] Because polysilicon layers have the smallest linewidth, they are the most challenging to fabricate. The conventional approach is to regulate the orientation of the layout in the design rules and improve process conditions by increasing resolution through the selection of dipole light sources during photolithography. (See also...) Figure 1 The image shows a polysilicon layer pattern 11 obtained after OPC in the prior art. However, in actual production, it was found that while selecting a dipole light source can increase resolution, it can also result in unsatisfactory patterns when performing OPC correction for certain special patterns. Please refer to [link to relevant documentation]. Figure 2 Displayed as Figure 1 The magnified view of the area shown in the dashed box shows that the traditional approach is to highlight the hotspot areas using Optical Proximity Correct Verification (OPCV). Figure 1 The area shown in the dashed box needs to be repaired again, i.e., by... Figure 2The repair is performed in the direction indicated by the middle arrow, but this process is a measure taken after the actual graphic is found to be unsatisfactory after OPC is executed. It is a post-processing method and can only detect fixed adjustment values. It is not flexible enough in practical applications, and there is a possibility of missing hot spots when using OPCV to capture hot areas, which poses a certain risk.

[0005] Therefore, how to provide a method for optimizing virtual graphics before OPC and a method for making a mask, so as to optimize the virtual graphics of the polysilicon layer before OPC, obtain the optimized graphics, and then perform appropriate correction through OPC, avoids the need to repair the graphics after discovering unsatisfactory graphics after OPC, improves the flexibility of operation, and reduces the risk caused by missed captures due to OPCV, has become an important technical problem that urgently needs to be solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for optimizing virtual graphics before OPC and a method for making a mask, so as to solve the problem that some special patterns in the prior art are not ideal when OPC is performed. The method of highlighting hot spots and repairing them is a post-processing measure that is taken after the actual graphics are found to be unsatisfactory after OPC is executed. Moreover, it can only find fixed dimensional defects, which is not flexible enough in practical applications. Furthermore, there is a possibility of missing hot spots when using OPCV, which poses a certain risk.

[0008] To achieve the above and other related objectives, this invention provides a method for optimizing virtual graphics before OPC, comprising the following steps:

[0009] A primary design pattern for a polysilicon layer is provided, the primary design pattern comprising three parallel polysilicon patterns, a first polysilicon pattern, and a third polysilicon pattern arranged sequentially and at intervals along a predetermined direction;

[0010] Identify the original design pattern and obtain the size information of the first polysilicon pattern, the second polysilicon pattern, and the third polysilicon pattern;

[0011] Based on the obtained size information of the first polysilicon pattern, the second polysilicon pattern, and the third polysilicon pattern, adjust the size of the second polysilicon pattern, the position of the first polysilicon pattern, and the position of the third polysilicon pattern to obtain a corrected pattern.

[0012] Optionally, the size information includes the width of the polysilicon pattern.

[0013] Optionally, the method for obtaining the corrected pattern includes the following steps: if the width of the obtained second polysilicon pattern is greater than the width of the first polysilicon pattern and the width of the third polysilicon pattern, then it is not necessary to adjust the size of the second polysilicon pattern, the position of the first polysilicon pattern and the position of the third polysilicon pattern, and the original design pattern is the corrected pattern.

[0014] Optionally, the method for obtaining the corrected pattern includes the following steps: if the width of the obtained second polysilicon pattern is equal to the width of the first polysilicon pattern and the width of the third polysilicon pattern, then the edges of the second polysilicon pattern are adjusted by a fixed value in the direction closer to the first polysilicon pattern and in the direction closer to the third polysilicon pattern, respectively, and the first polysilicon pattern is moved by a corresponding value in the direction away from the second polysilicon pattern, and the third polysilicon pattern is moved by a corresponding value in the direction away from the second polysilicon pattern, thereby obtaining the corrected pattern.

[0015] Optionally, the method for obtaining the corrected pattern includes the following steps: If the width of the obtained second polysilicon pattern is less than the width of the first polysilicon pattern and the width of the third polysilicon pattern, then the edges of the second polysilicon pattern are adjusted by a fixed value in the direction closer to the first polysilicon pattern and in the direction closer to the third polysilicon pattern, respectively, and the first polysilicon pattern is moved by a corresponding value in the direction away from the second polysilicon pattern, and the third polysilicon pattern is moved by a corresponding value in the direction away from the second polysilicon pattern, thereby obtaining the corrected pattern.

[0016] Optionally, the value of the fixed value is determined based on the width of the second polysilicon pattern.

[0017] Optionally, the fixed value is determined based on the difference between the width of the second polysilicon pattern and the width of the first polysilicon pattern.

[0018] Optionally, the size information of the first polysilicon pattern, the size information of the second polysilicon pattern, and the size information of the third polysilicon pattern can be obtained using EDA tools.

[0019] This invention also provides a method for manufacturing a photomask, comprising the following steps:

[0020] The modified graphic obtained by optimizing the virtual graphic before OPC is then subjected to OPC to obtain the OPC corrected graphic.

[0021] The mask pattern is obtained based on the OPC correction pattern;

[0022] A mask is created based on the mask pattern.

[0023] Optionally, the mask is used to fabricate a polysilicon layer gate structure.

[0024] As described above, the method for optimizing the virtual pattern of the polysilicon layer of the present invention optimizes the virtual pattern of the polysilicon layer before OPC, and then performs appropriate correction through OPC after obtaining the optimized pattern. This avoids the need to repair the pattern after discovering an unsatisfactory pattern after executing OPC, thereby improving operational flexibility and reducing the risk caused by missed captures due to OPCV, and improving product yield and performance stability. Attached Figure Description

[0025] Figure 1 The diagram shows a schematic representation of a polycrystalline silicon layer in the prior art.

[0026] Figure 2 Displayed as Figure 1 A magnified view of the area indicated by the dashed box.

[0027] Figure 3 This is a schematic diagram of the original design of a polycrystalline silicon layer.

[0028] Figure 4 The image shown is a schematic diagram of a polysilicon layer pattern after OPC in the prior art.

[0029] Figure 5 The flowchart shows the steps of the method for optimizing virtual graphics before OPC according to the present invention.

[0030] Figure 6 This is a data diagram showing the adjustment table of the method for optimizing virtual graphics before OPC according to the present invention.

[0031] Figure 7 The diagram shows a polysilicon layer pattern obtained after adjusting the size of the second polysilicon pattern using the method of optimizing the virtual pattern before OPC according to the present invention.

[0032] Figure 8 The diagram shows a corrected graphic obtained by adjusting the positions of the first and third polysilicon graphics using the method for optimizing virtual graphics before OPC according to the present invention.

[0033] Figure 9 The image shown is an actual graphic representation of a polysilicon layer obtained without the OPC optimization method of this invention.

[0034] Figure 10 The image shown is an actual graphic representation of a polysilicon layer obtained by optimizing the virtual graphics before OPC according to the present invention.

[0035] Component designation explanation

[0036] 11 Polycrystalline silicon patterns

[0037] 1. Original design graphics

[0038] 2 First polysilicon pattern

[0039] 3 Second polysilicon pattern

[0040] 4 Second polysilicon pattern

[0041] 5. Original Graphics

[0042] 6. Actual Graphics

[0043] 7 Original Graphics

[0044] 8. Correct the graphics

[0045] 9. Actual Graphics

[0046] Steps S1 to S3 Detailed Implementation

[0047] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] Please see Figures 3 to 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0049] Regarding the unsatisfactory polysilicon layer pattern obtained after OPC (Optical Processing) as mentioned in the background art, the inventors analyzed that the cause of this problem may be as follows: Typically, a pattern contains both densely distributed patterns (such as 1:1 equally spaced lines) and sparse patterns (such as independent lines). The photolithography process windows for densely distributed patterns are different from those for sparse patterns, resulting in a smaller common process window. The lighting conditions suitable for exposing dense patterns are not suitable for exposing sparse patterns. Please refer to [link to relevant documentation]. Figure 3 The diagram shows a schematic of the original polysilicon layer design pattern 1. Three polysilicon patterns are arranged side-by-side with intervals. The middle polysilicon pattern 3 is in a densely distributed state, while the adjacent polysilicon patterns 2 and 4 are in a semi-densely distributed state. Please refer to [link / reference needed]. Figure 4 This is displayed as the polysilicon pattern after OPC in the prior art. This causes the polysilicon patterns 2 and 4 on either side of the central polysilicon pattern 3 to form according to the maximum values ​​in the standard size table after illumination, while the central polysilicon pattern 3 is formed according to the standard value, thus producing... Figure 4 The phenomenon of "large sandwiching small" is shown in the diagram. To reduce process variations caused by different pattern densities in integrated circuit layouts, the current common practice is to insert sub-resolution patterns into the surrounding areas of the sparsely patterned mask pattern to improve depth of focus and process window uniformity. The inserted patterns are smaller than the imaging resolution of the lithography system and consist of thin, elongated rectangular lines parallel to the mask pattern. These lines themselves do not form lithographic patterns during exposure, but they do affect the light intensity distribution of the nearby mask pattern during lithographic imaging.

[0050] Example 1

[0051] This embodiment provides a method for optimizing virtual graphics before OPC. Please refer to [link to relevant documentation]. Figure 5 The flowchart of this method is shown, including the following steps:

[0052] S1: Provide an original design pattern of a polysilicon layer, the original design pattern including three parallel polysilicon patterns, a first polysilicon pattern, and a third polysilicon pattern arranged sequentially and at intervals along a predetermined direction;

[0053] S2: Identify the original design pattern and obtain the size information of the first polysilicon pattern, the size information of the second polysilicon pattern, and the size information of the third polysilicon pattern;

[0054] S3: Based on the obtained size information of the first polysilicon pattern, the second polysilicon pattern, and the third polysilicon pattern, adjust the size of the second polysilicon pattern, the position of the first polysilicon pattern, and the position of the third polysilicon pattern to obtain a corrected pattern.

[0055] First, please refer to Figure 3 Step S1 is executed to provide an original design pattern 1 of a polysilicon layer. The original design pattern 1 includes three parallel polysilicon patterns 2, 3 and 4 arranged sequentially and at intervals along a predetermined direction.

[0056] Next, step S2 is executed to identify the original design pattern 1 and obtain the size information of the first polysilicon pattern 2, the second polysilicon pattern 3, and the third polysilicon pattern 4. The identification of the original design pattern 1 is specifically implemented using Electronic Design Automation (EDA) tools. That is, the size information of the first polysilicon pattern 2, the second polysilicon pattern 3, and the third polysilicon pattern 4 is obtained through EDA tools.

[0057] As an example, the size information includes the width of the polysilicon pattern. In other embodiments, the size information may also be the length of the polysilicon pattern and the distance between adjacent polysilicon cells, selected appropriately according to the actual technical problem to be solved.

[0058] Step S3 is executed, and the size of the second polysilicon pattern 3, the position of the first polysilicon pattern 2, and the position of the third polysilicon pattern 4 are adjusted based on the obtained size information of the first polysilicon pattern 2, the second polysilicon pattern 3, and the third polysilicon pattern 4 to obtain the corrected pattern 5.

[0059] As an example, the method for obtaining the corrected pattern 5 includes the following steps: if the width of the obtained second polysilicon pattern 3 is greater than the width of the first polysilicon pattern 2 and the width of the third polysilicon pattern 4, then it is not necessary to adjust the size of the second polysilicon pattern 3, the position of the first polysilicon pattern 2 and the position of the third polysilicon pattern 4, and the original design pattern 1 is the corrected pattern 5.

[0060] As an example, the method for obtaining the corrected pattern 5 includes the following steps: if the width of the obtained second polysilicon pattern 3 is equal to the width of the first polysilicon pattern 2 and the width of the third polysilicon pattern 4, then the edges of the second polysilicon pattern 3 are adjusted by a fixed value in the direction closer to the first polysilicon pattern 2 and the direction closer to the third polysilicon pattern 4, respectively, and the first polysilicon pattern 2 is moved by a corresponding value in the direction away from the second polysilicon pattern 3, and the third polysilicon pattern 4 is moved by a corresponding value in the direction away from the second polysilicon pattern 3, thereby obtaining the corrected pattern 5.

[0061] As an example, the value of the fixed value is determined based on the width of the second polysilicon pattern 3.

[0062] As an example, the method for obtaining the corrected pattern 5 includes the following steps: if the width of the obtained second polysilicon pattern 3 is smaller than the width of the first polysilicon pattern 2 and the width of the third polysilicon pattern 4, then the edges of the second polysilicon pattern 3 are adjusted by a fixed value in the direction closer to the first polysilicon pattern 2 and the direction closer to the third polysilicon pattern 4, respectively, and the first polysilicon pattern 2 is moved by a corresponding value in the direction away from the second polysilicon pattern 3, and the third polysilicon pattern 4 is moved by a corresponding value in the direction away from the second polysilicon pattern 3, thereby obtaining the corrected pattern 5.

[0063] As an example, the value of the fixed value is determined based on the difference between the width of the second polysilicon pattern 3 and the width of the first polysilicon pattern 2.

[0064] Specifically, the dimensions of the second polysilicon pattern 3, the position of the first polysilicon pattern 2, and the position of the third polysilicon pattern 4 can be adjusted according to an adjustment table based on design rules. Please refer to [link / reference needed]. Figure 6 The data is displayed as an adjustment table. The contents of the adjustment table include a first width (the width of the second polysilicon pattern 3), a second width (the width of the first polysilicon pattern 2 and the third polysilicon pattern 4), and a fixed value. The fixed value is selected based on the value of the first width or the difference between the first width and the second width. Figure 6 The adjustment table shown is just one example. In actual applications, an applicable adjustment table can be obtained by reasonably designing rules based on the relevant dimensional information of the original design drawing.

[0065] Furthermore, when the first width is greater than the second width, that is, when the width of the second polysilicon pattern 3 is greater than the width of the first polysilicon pattern 2 and the third polysilicon pattern 4, the fixed value adjusted in subsequent steps is zero. That is, it is not necessary to adjust the first polysilicon pattern 3, nor is it necessary to adjust the first polysilicon pattern 2 and the third polysilicon pattern 4. In this case, the original design pattern is the corrected pattern. For example, when the first width is 45nm and the second width is 35nm, the fixed value adjusted in subsequent steps is zero.

[0066] Furthermore, when the first width equals the second width, that is, when the width of the second polysilicon pattern 3 equals the widths of the first polysilicon pattern 2 and the third polysilicon pattern 4, please refer to [reference needed]. Figure 7First, the edges of the second polysilicon pattern 3 are adjusted by fixed values ​​towards the first polysilicon pattern 2 and towards the third polysilicon pattern 4, respectively. The difference between the width of the second polysilicon pattern 3 after adjustment and the width of the second polysilicon pattern 3 before adjustment is twice the fixed value. Please refer to... Figure 8 The process involves moving the first polysilicon pattern 2 away from the second polysilicon pattern 3 by a corresponding value, and moving the third polysilicon pattern 4 away from the second polysilicon pattern 3 by a corresponding value, thus obtaining the corrected pattern. In this case, the fixed value is determined based on the first width, and the range of the fixed value is 2% to 4% of the first width value. For example, when both the first width and the second width are 40nm, the fixed value is 1nm. The purpose of adjusting the positions of the first polysilicon pattern 2 and the third polysilicon pattern 4 is that the width of the second polysilicon pattern 3 was appropriately adjusted in the previous step, resulting in a decrease in the distance between the second polysilicon pattern 3 and the first and third polysilicon patterns 2 and 4. In the subsequent photolithography process, the reduced spacing between adjacent polysilicon patterns will cause a partial deviation between the original pattern on the mask and the actual pattern. Therefore, it is necessary to appropriately offset the first polysilicon pattern 2 and the third polysilicon pattern 4 along the adjustment direction of the second polysilicon pattern 3, and the offset value corresponds to the fixed value of the size adjustment of the first polysilicon pattern 3.

[0067] Furthermore, when the first width is less than the second width, that is, when the width of the second polysilicon pattern 3 is less than the width of the first polysilicon pattern 2 and the third polysilicon pattern 4, similar to the previous case, the edges of the second polysilicon pattern 3 are first adjusted by a fixed value towards the direction closer to the first polysilicon pattern 2 and towards the direction closer to the third polysilicon pattern 4, respectively. Then, the first polysilicon pattern 2 is moved by a corresponding value away from the second polysilicon pattern 3, and the third polysilicon pattern 4 is... Figure 4 The shape is moved away from the second polysilicon pattern 3 by a corresponding value to obtain a corrected pattern. In this case, the fixed value is determined based on the difference between the first width and the second width. As the difference between the first width and the second width increases, the fixed value adjusted in subsequent steps gradually increases. For example, when the first width is 40nm and the second width is 60nm, the fixed value adjusted in subsequent steps is 4nm.

[0068] The method for optimizing virtual graphics before OPC in this embodiment optimizes the virtual graphics of the polysilicon layer before OPC, avoiding the need to repair the graphics after discovering unsatisfactory graphics after OPC is executed. This improves operational flexibility, reduces the risk of missed captures due to OPCV, and improves product yield and performance stability.

[0069] Example 2

[0070] This embodiment provides a method for creating a mask, specifically a method for creating a mask based on the method of optimizing virtual graphics before OPC in Embodiment 1, including the following steps: obtaining an OPC-corrected graphic by performing OPC on the corrected graphic obtained by the method of optimizing virtual graphics before OPC in Embodiment 1; obtaining a mask graphic based on the OPC-corrected graphic; and creating a mask based on the mask graphic.

[0071] As an example, the mask is used to fabricate a polysilicon layer gate structure.

[0072] For details, please refer to Figure 9 The image displayed is the actual polysilicon pattern obtained without optimization. After optimizing the original image 5 ( Figure 9 The actual graphic obtained after OPC correction (as shown in the graphic with the middle stripe filling) is 6 ( Figure 9 In the dotted-fill pattern shown, the second polysilicon pattern 3 differs significantly in morphology from the first polysilicon pattern 2 and the third polysilicon pattern 4. The regions adjacent to the second polysilicon pattern 3 and the first and third polysilicon patterns 2 and 4 show a noticeable inward contraction, exhibiting a "large sandwiching a small" phenomenon. Please refer to... Figure 10 The image displayed is an actual polycrystalline silicon pattern obtained after optimization, based on the original pattern 7 ( Figure 10 After optimizing the area shown by the dashed line, we obtain the corrected image 8. Figure 10 The actual graphic 9 is obtained after performing OPC correction on the corrected graphic 8 (as shown in the striped filling pattern). Figure 10 In the dotted filling pattern shown, although the first polysilicon pattern in the final actual pattern is not perfect, it is similar to... Figure 9 Compared to the unoptimized graphics shown, Figure 10 The difference between the first polysilicon pattern and the second polysilicon pattern has been significantly reduced. Therefore, after optimization, OPC correction has a significant improvement effect on the case of unsatisfactory polysilicon patterns.

[0073] The mask fabrication method in this embodiment optimizes the virtual pattern of the polysilicon layer before traditional OPC correction to obtain a corrected pattern. Then, OPC correction is performed based on this to obtain a mask pattern for mask fabrication. The final actual pattern has significantly improved consistency and accuracy compared to the actual pattern without optimization.

[0074] In summary, the method for optimizing virtual graphics before OPC of the present invention optimizes the virtual graphics of the polysilicon layer before OPC, avoiding the need for repair after OPC is completed due to the discovery of unsatisfactory graphics. This improves operational flexibility and reduces the risk of missed captures due to OPCV, effectively improving the integrity and stability of the graphics, thereby increasing product yield and performance stability. The mask fabrication method of the present invention, based on the corrected graphics obtained by optimizing the virtual graphics before OPC, performs OPC correction to obtain a mask pattern for mask fabrication. The final actual graphics, compared to the unoptimized actual graphics, show significantly improved consistency and accuracy, thus effectively improving product yield and performance stability. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0075] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for optimizing virtual graphics before OPC, characterized in that, Includes the following steps: A primary design pattern for a polysilicon layer is provided, the primary design pattern comprising three parallel polysilicon patterns, a first polysilicon pattern, and a third polysilicon pattern arranged sequentially and at intervals along a predetermined direction; Identify the original design pattern and obtain the size information of the first polysilicon pattern, the second polysilicon pattern, and the third polysilicon pattern; If the width of the second polysilicon pattern in the acquired size information is less than or equal to the width of the first polysilicon pattern and the width of the third polysilicon pattern, the size of the second polysilicon pattern, the position of the first polysilicon pattern, and the position of the third polysilicon pattern are adjusted based on the acquired size information of the first polysilicon pattern, the size information of the second polysilicon pattern, and the size information of the third polysilicon pattern to obtain a corrected pattern.

2. The method for optimizing virtual graphics before OPC according to claim 1, characterized in that: The size information includes the width of the polysilicon pattern.

3. The method for optimizing virtual graphics before OPC according to claim 2, characterized in that, The method for obtaining the corrected pattern includes the following steps: if the width of the obtained second polysilicon pattern is greater than the width of the first polysilicon pattern and the width of the third polysilicon pattern, then it is not necessary to adjust the size of the second polysilicon pattern, the position of the first polysilicon pattern and the position of the third polysilicon pattern, and the original design pattern is the corrected pattern.

4. The method for optimizing virtual graphics before OPC according to claim 2, characterized in that, The method for obtaining the corrected pattern includes the following steps: if the width of the obtained second polysilicon pattern is equal to the width of the first polysilicon pattern and the width of the third polysilicon pattern, then the edges of the second polysilicon pattern are adjusted by a fixed value in the direction closer to the first polysilicon pattern and in the direction closer to the third polysilicon pattern, respectively, and the first polysilicon pattern is moved by a corresponding value in the direction away from the second polysilicon pattern, and the third polysilicon pattern is moved by a corresponding value in the direction away from the second polysilicon pattern, thereby obtaining the corrected pattern.

5. The method for optimizing virtual graphics before OPC according to claim 2, characterized in that, The method for obtaining the corrected pattern includes the following steps: if the width of the obtained second polysilicon pattern is smaller than the width of the first polysilicon pattern and the width of the third polysilicon pattern, then the edges of the second polysilicon pattern are adjusted by a fixed value in the direction closer to the first polysilicon pattern and the direction closer to the third polysilicon pattern, respectively, and the first polysilicon pattern is moved by a corresponding value in the direction away from the second polysilicon pattern, and the third polysilicon pattern is moved by a corresponding value in the direction away from the second polysilicon pattern, thereby obtaining the corrected pattern.

6. The method for optimizing virtual graphics before OPC according to claim 4, characterized in that, The value of the fixed value is determined based on the width of the second polysilicon pattern.

7. The method for optimizing virtual graphics before OPC according to claim 5, characterized in that, The value is determined based on the difference between the width of the second polysilicon pattern and the width of the first polysilicon pattern.

8. The method for optimizing virtual graphics before OPC according to claim 1, characterized in that: The size information of the first polysilicon pattern, the size information of the second polysilicon pattern, and the size information of the third polysilicon pattern are obtained using EDA tools.

9. A method for fabricating a photomask, characterized in that, Includes the following steps: The modified graphic obtained by the method of optimizing virtual graphics before OPC according to any one of claims 1 to 8 is then subjected to OPC to obtain the OPC correction graphic; The mask pattern is obtained based on the OPC correction pattern; A mask is created based on the mask pattern.

10. The method for manufacturing a photomask according to claim 9, characterized in that, The mask is used to fabricate a polysilicon layer gate structure.

Images