Memory systems, methods executed thereon, and non-transitory computer-readable media

Abstract

This application relates to cache block budgeting techniques. In some memory systems, a controller can configure a memory device with a cache. The cache may include a first subset of blocks configured to operate statically in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and operating in a second mode. Blocks operating in the second mode may be configured to store relatively more bits per memory cell than blocks operating in the first mode. The controller may track and store a corresponding ratio for each block in the second subset of blocks of the ratio of loops executed in the first mode to loops executed in the second mode. The controller may select blocks from the second subset of blocks to switch between modes in response to a trigger and based on the corresponding ratio of the blocks.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 397,799, filed August 9, 2021, entitled “Cache Block Budgeting Technologies,” which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] This technical field relates to cache block budgeting techniques. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to typically correspond to one of two supported states, logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically updated by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus includes a memory device; and a controller coupled to the memory device and configured to cause the apparatus to: configure the memory device with a cache, the cache including a first subset of blocks configured to operate statically in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and operating in a second mode, wherein the first block operating in the first mode is configured to store a first number of bits per memory cell, and the second block operating in the second mode is configured to store a second number of bits per memory cell greater than the first number of bits; for each block in the second subset of blocks, storing a corresponding ratio of loops executed in the first mode to loops executed in the second mode; and selecting a block from the second subset of blocks to switch from the first mode to the second mode or from the second mode to the first mode in response to a trigger and at least in part based on the corresponding ratio of the blocks.

[0007] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium includes instructions that, when executed by a processor of an electronic device, cause the electronic device to: configure the memory device with a cache, the cache including a first subset of blocks configured to operate statically in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and operating in a second mode, wherein the first block operating in the first mode is configured to store a first number of bits per memory cell, and the second block operating in the second mode is configured to store a second number of bits per memory cell greater than the first number of bits; for each block in the second subset of blocks, storing a corresponding ratio of loops executed in the first mode to loops executed in the second mode; and selecting a block from the second subset of blocks to switch from the first mode to the second mode or from the second mode to the first mode in response to a trigger and at least in part based on the corresponding ratio of the blocks.

[0008] A method executed by a memory system is described. The method includes: configuring the memory device with a cache, the cache including a first subset of blocks configured to operate statically in the first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and operating in the second mode, wherein the first block operating in the first mode is configured to store a first number of bits per memory cell, and the second block operating in the second mode is configured to store a second number of bits per memory cell greater than the first number of bits; for each block in the second subset of blocks, storing a corresponding ratio of loops executed in the first mode to loops executed in the second mode; and selecting a block from the second subset of blocks to switch from the first mode to the second mode or from the second mode to the first mode in response to a trigger and at least in part based on the corresponding ratio of the block. Attached Figure Description

[0009] Figure 1 Examples of systems that support cache block budgeting techniques based on the examples disclosed herein are shown.

[0010] Figure 2 Examples of systems that support cache block budgeting techniques based on the examples disclosed herein are shown.

[0011] Figure 3 Examples of memory systems that support cache block budgeting techniques according to the examples disclosed herein are shown.

[0012] Figure 4 An example of a flowchart supporting cache block budgeting techniques based on the examples disclosed herein is shown.

[0013] Figure 5 A block diagram of a memory system supporting cache block budget technology is shown based on the examples disclosed herein.

[0014] Figure 6 The flowchart illustrates one or more methods supporting cache block budgeting techniques based on the examples disclosed herein. Detailed Implementation

[0015] Some memory devices, such as NAND flash memory, may include a cache containing a subset of memory cells (e.g., in a memory array) for storing data or other information. In some instances, the cache may contain memory blocks that support fewer bits per cell compared to other blocks in the memory device. For example, the cache may contain one or more single-level cell (SLC) blocks that contain relatively fewer bits per cell compared to other blocks, such as blocks containing multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), five-level cell (PLC), or any combination of these or other multi-level memory cells. Since supporting blocks with fewer bits per cell provides improved performance (e.g., relatively higher reliability, relatively faster access operations, relatively greater durability) compared to other blocks used for data storage, such caches can improve the durability and performance of the memory device. However, in some cases, caching may be associated with reduced memory device capacity (e.g., due to fewer bits per cell compared to blocks outside the cache), which may lead to reduced memory device storage capacity and performance of certain operations such as wear leveling, garbage collection, etc. (e.g., operations that may benefit from an over-provisioned pool of blocks or resources to be used).

[0016] As described herein, a cache may contain a subset of dynamic blocks that can switch between a first mode (e.g., SLC, MLC, TLC) supporting relatively fewer bits per unit and a second mode (e.g., MLC, TLC, or QLC) supporting relatively more bits per unit. In some instances, program-and-erase (P / E) cycles performed on dynamic blocks in the second mode may be more block-intensive than P / E cycles in the first mode (e.g., due to the larger number of bits per unit corresponding to the second mode). The memory system controller may configure the cache to support a target total bytes written (TBW) based on a target capacity of the memory device. The memory system controller may configure a target ratio between cycles performed in the first mode and cycles performed in the second mode for at least some (if not every) dynamic blocks in the cache and based on the target TBW of the cache. In some instances, the target ratio may correspond to a first target cycle count for the first mode and a second target cycle count for the second mode. When the memory device is used (e.g., during product operation), the memory system controller may track the cycle count for each dynamic block in the cache. If the memory system controller recognizes a trigger that selects one or more dynamic blocks to switch from a first mode to a second mode (or from a second mode to a first mode), the memory system controller may select one or more dynamic blocks based on or in response to a cycle count, a target cycle ratio for the corresponding block, or both. For example, the trigger may be a memory device capacity that meets (e.g., exceeds or equals) or falls below a target memory device capacity, a cache write command, a cache erase command, or any combination thereof.

[0017] Alternatively, the memory system controller may be configured to modify the target cycle ratio of one or more dynamic blocks based on or in response to cache usage levels (e.g., by the host system). During runtime, the memory system controller may periodically compare the cache's TBW (Total Block Size) with the cache's target TBW. If the actual TBW differs from the target TBW (e.g., for a specific time period), the memory system controller may determine to adjust (e.g., increase or decrease) the target cycle ratio of one or more dynamic blocks. Therefore, the memory system controller can utilize one or more processes to improve block allocation within the cache, which can improve the performance and durability of the memory device while maintaining the memory device's capacity target.

[0018] First, refer to Figure 1 and 2 Features of this disclosure are described in the context of the systems and apparatus described. (Referencing...) Figure 3 and 4 The features of this disclosure are described in the context of memory systems and process flows. Further details are provided by reference. Figure 5 and 6Device diagrams and flowcharts related to cache block budgeting techniques are shown and described in the context of the device diagrams and flowcharts of this disclosure.

[0019] Figure 1 An example of a system 100 supporting cache block budgeting techniques according to the examples disclosed herein is shown. System 100 includes a host system 105 coupled to a memory system 110.

[0020] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0021] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or any other computing device containing memory and processing means.

[0022] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed via the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1A memory system 110 is shown, but the host system 105 can be coupled to any number of memory systems 110.

[0023] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0024] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or updating data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-coded) logic to perform the operations described herein that pertain to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory capable of storing operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory available for internal storage or computation by the memory system controller 115, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, it may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to memory device 130) according to a caching strategy.

[0029] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions belonging to memory system controller 115 herein. Generally, one or more functions belonging to memory system controller 115 herein may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135, which can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein. For example, as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as SLC. Alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each; if configured to store two bits, it may be referred to as MLC; if configured to store three bits, it may be referred to as TLC; if configured to store four bits, it may be referred to as QLC, or more generally, a multilevel memory cell. Compared to SLC memory, multilevel memory cells can provide greater storage density (e.g., increased capacity), but in some cases may involve narrower read or write tolerances or greater complexity for supporting circuitry. In some instances, SLC memory may offer higher reliability, faster access operations, improved durability, etc., compared to multilevel memory cells.

[0034] Some memory devices 130 may include static SLC memory cells that operate in SLC mode throughout the entire lifecycle of the memory device 130. Static SLC memory cells can support relatively high reliability and endurance of the memory device 130, but may have lower storage density compared to other memory cells. As the amount of data written to the memory device 130 increases (e.g., the usage level of the memory device 130), the capacity of the memory device 130 may decrease (e.g., the over-provisioning pool containing available memory cells within the memory device 130 may decrease). Therefore, a memory device 130 containing a relatively large number of static SLC memory cells can store a relatively small amount of data (e.g., low capacity). To maintain sufficient capacity within the memory device 130 while improving endurance and performance, the memory device 130 may include one or more dynamic memory cells. The one or more dynamic memory cells may be programmed as SLC memory cells or multi-level memory cells (e.g., MLC, TLC, QLC, PLC, etc.).

[0035] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may have one or more limitations, such as the same operation being performed on memory cells within different pages 175 with the same page address within the corresponding plane 165 (e.g., involving command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0036] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0037] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0038] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise represent data retained in the old block 170 as invalid or obsolete, and may update the logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 instead of the old invalid block 170. For example, in some cases, this copying and remapping may be performed due to latency or wear and tear considerations, rather than erasing and rewriting the entire old block 170. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or plane 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0039] In some cases, an L2P mapping table can be maintained, and data can be marked as valid or invalid at the page level. Page 175 may contain valid data, invalid data, or no data. Invalid data may be outdated data due to a newer or more recent version of the data being stored in a different page 175 of memory device 130. Invalid data may have previously been programmed into an invalid page 175 but may no longer be associated with a valid logical address (e.g., a logical address referenced by host system 105). Valid data may be the latest version of such data stored on memory device 130. Page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0040] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called “garbage collection” may be invoked to allow block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, allowing more blocks 170 to be used to store subsequent data (e.g., data subsequently received from the host system 105). In some instances, the performance of the memory device 130 during garbage collection and wear leveling operations may be referred to as dirty performance.

[0041] In some instances, the overprovisioning pool within memory device 130 may include free blocks 170 erased during such operations (e.g., blocks 170 that currently do not store data), which can improve the efficiency and reliability of media management operations of memory device 130. As the usage level of memory device 130 increases, the capacity of available blocks within memory device 130 (e.g., and the corresponding capacity of the overprovisioning pool) may decrease, potentially leading to performance degradation (e.g., dirty performance). In some instances, memory device 130 may include a cache containing blocks 170 supporting a first operating mode (e.g., SLC memory). Compared to a second mode (e.g., multi-level cell memory), the first mode can support fewer bits per memory cell and may have a reduced capacity. Therefore, if memory device 130 includes a cache of blocks operating in the first mode, the capacity of the device may be reduced, potentially leading to reduced overprovisioning and performance degradation of memory device 130.

[0042] As described herein, the cache within the memory device 130 may be configured to include a first subset of blocks configured to operate in a first mode and a second subset of blocks, which may be referred to as dynamic blocks, configured to dynamically switch between operating in the first mode and operating in a second mode. The memory system controller 115 may configure the cache to support a target TBW based on or in response to a target capacity of the memory device 130. The memory system controller 115 may configure a target cycle ratio for each dynamic block in the cache, associated with a first target cycle count in the first mode and a second target cycle count in the second mode, based on the target TBW of the cache (e.g., the total target TBW). In some instances, the P / E cycle performed on a block in the second mode may cause greater wear on the block than the P / E cycle performed on a block in the first mode, and the target cycle ratio may be calculated based on the ratio of wear in the first mode to wear in the second mode to maintain sufficient durability for each block 170.

[0043] When host system 105 uses memory device 130, memory system controller 115 can track the cycle count of each dynamic block in the cache. If memory system controller 115 identifies a trigger that selects one or more dynamic blocks to switch from a first mode to a second mode or from a second mode to a first mode, memory system controller 115 can select the appropriate dynamic block based on or in response to the cycle count of one or more dynamic blocks and a target cycle ratio. For example, the trigger could be a memory device 130 capacity exceeding or falling below a target capacity, a cache write command, a cache erase command, or any combination thereof. Alternatively, memory system controller 115 can modify the target cycle ratio of one or more dynamic blocks based on the cache usage level. Memory system controller 115 can periodically compare the actual TBW of the cache with the target TBW. If the actual TBW differs from the target TBW (e.g., at a specific time period, at a specific reference time), memory system controller 115 can determine to adjust (e.g., increase or decrease) the target cycle ratio of one or more dynamic blocks. Therefore, the memory system controller 115 can utilize one or more processes to improve the allocation of dynamic blocks within the cache, which can improve the performance and durability of the memory device 130 while maintaining the capacity target of the memory device 130.

[0044] System 100 may include any number of non-transitory computer-readable media that support cache block budgeting techniques. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions described herein that pertain to host system 105, memory system controller 115, or memory device 130. For example, such instructions, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions described herein.

[0045] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0046] Figure 2 An example of a system 200 supporting cache block budgeting techniques according to the examples disclosed herein is shown. System 200 may be a reference. Figure 1 An example of system 100 described in the description of the present invention. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 if requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may implement references to Figure 1 The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0047] As described herein, memory system 210 may include one or more memory devices 240 for storing, for example, data transferred between memory system 210 and host system 205 in response to receiving an access command from host system 205. The one or more memory devices 240 may be as described in the reference... Figure 1 Examples of memory devices described. For example, memory device 240 may include NAND memory, PCM, self-selected memory, 3D cross-connect, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0048] Memory system 210 may include a memory controller 230 for controlling the transfer of data directly to and from memory device 240, for example, for storing data, retrieving data, and determining the memory location of stored and retrieved data. The memory controller 230 may communicate directly with one or more memory devices 240, or via a bus (not shown), using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, for example, different memory controllers 230 for each type of memory device 240. In some cases, the memory controller 230 may implement a reference... Figure 1 Aspects of the local controller 135 described.

[0049] The memory system 210 may further include an interface 220 for communicating with the host system 205 and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 may be used to convert data between the host system 205 and the memory device 240, for example, as shown in data path 250, and may be collectively referred to as the data path components.

[0050] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling command bursts, and once the burst stops, the buffered data can be stored or transmitted (or both). Buffer 225 may contain relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM) or hardware accelerators or both to allow for fast storage and retrieval of data in and out of buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0051] The temporary storage of data in buffer 225 can refer to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten by data from an additional access command). Furthermore, buffer 225 can be a non-cached buffer. That is, the host system 205 may not read data directly from buffer 225. For example, a read command can be added to a queue without requiring an address to be matched against an address already in buffer 225 (e.g., no cached address matching or lookup operation is needed).

[0052] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be a reference... Figure 1 An example of a memory system controller 115 is described. Bus 235 can be used for communication between system components. In some instances, memory system controller 215 may be an instance of a processor associated with an ASIC. For example, system 200 may include multiple memory dies. A first memory die (e.g., an ASIC controller die) may include interface 220, buffer 225, memory controller 230, or a combination thereof, and may be controlled by memory system controller 215. In some cases, the first memory die may additionally include memory system controller 215. A second memory die may include one or more memory devices 240 and may include a local controller (not shown). Memory dies may communicate with each other using bus 235.

[0053] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) may be used to control the processing of access commands and the movement of corresponding data. For example, this may be advantageous if the memory system 210 processes more than one access command from the host system 205 in parallel. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, queues (if used) may be located anywhere within the memory system 210.

[0054] Data transferred between host system 205 and one or more memory devices 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path component instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory devices 240 (e.g., using a memory system 210-specific protocol) by communicating with data path component on bus 235.

[0055] If host system 205 transmits an access command to memory system 210, the command can be received by interface 220, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered as the front end of memory system 210. After receiving each access command, interface 220 can, for example, transmit the command to memory system controller 215 via bus 235. In some cases, interface 220 can add each command to command queue 260 to transmit the command to memory system controller 215.

[0056] The memory system controller 215 may determine whether an access command has been received based on or in response to communication from the interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving the command from the command queue 260. After, for example, the command has been retrieved from the command queue 260 by the memory system controller 215, the command may be removed from the command queue. In some cases, the memory system controller 215 may cause the interface 220 to remove the command from the command queue 260, for example, via the bus 235.

[0057] Once it is determined that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving data to the memory device 240.

[0058] In either case, the memory system controller 215 may use the buffer 225 to temporarily store data received from or sent to the host system 205, and for other purposes. The buffer 225 may be considered as an intermediate part of the memory system 210. In some cases, buffer address management (e.g., pointers to locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0059] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available to store the data associated with the write command, for example via firmware (e.g., controller firmware).

[0060] In some cases, buffer queue 265 can be used to control the flow of commands associated with data stored in buffer 225, including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating where the data associated with each command is stored in buffer 225 can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least some portions of the access commands can be processed in parallel.

[0061] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to transfer" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the stored data within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data transfer to buffer 225 has been completed.

[0062] Once written data has been stored in buffer 225 via interface 220, the data can be transferred outside buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data outside buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that data transfer to memory device 240 has been completed.

[0063] In some cases, memory queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can push write commands from buffer queue 265 (e.g., via bus 235) to memory queue 270 for processing. Memory queue 270 may contain entries for each access command. In some instances, memory queue 270 may additionally contain buffer pointers (e.g., addresses) indicating where the data associated with the command is stored in buffer 225, and memory pointers (e.g., addresses) indicating the location in one or more memory devices 240 associated with the data. In some cases, memory controller 230 can obtain the location of data to be retrieved from buffer 225 from buffer 225, buffer queue 265, or memory queue 270. Memory controller 230 can manage the location of stored data within memory devices 240 (e.g., for wear leveling, garbage collection, etc.). Entries can be added to memory queue 270, for example, via memory system controller 215. After the data transfer is complete, the entry can be removed from the storage queue 270, for example, via the storage controller 230 or the memory system controller 215.

[0064] In order to process a read command received from host system 205, memory system controller 215 may again first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the read command, for example via firmware (e.g., controller firmware).

[0065] In some cases, buffer queue 265 can be used to supplement buffer storage of data associated with read commands in a manner similar to that discussed above regarding write commands. For example, if buffer 225 has sufficient space to store read data, memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can, for example, use bus 235 to indicate to memory system controller 215 that a data transfer to buffer 225 has been completed.

[0066] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location of data retrieved from the memory device 240 from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 can obtain the location of data stored in the buffer 225 from the buffer queue 265. In some cases, the storage controller 230 can obtain the location of stored data in the buffer 225 from the storage queue 270. In some cases, the memory system controller 215 can move commands processed by the storage queue 270 back to the command queue 260.

[0067] Once data has been stored in buffer 225 by storage controller 230, it can be transferred out of buffer 225 and sent to host system 205. For example, storage system controller 215 can enable interface 220 to retrieve data from buffer 225 using data path 250 and transfer the data to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 can process commands from command queue 260 and can indicate to storage system controller 215, for example, via bus 235, that the data transfer to host system 205 has been completed.

[0068] The memory system controller 215 can execute received commands in a sequence (e.g., according to the first-in-first-out order of the command queue 260). For each command, the memory system controller 215 can cause the data corresponding to the command to move in and out of buffer 225, as discussed above. While the data is moved into buffer 225 and stored therein, the command can remain in buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been transferred out of buffer 225), the command can be removed from buffer queue 265, for example, via the memory system controller 215. If the command is removed from buffer queue 265, the address where the data previously associated with the command was stored can be used to store the data associated with the new command.

[0069] The memory system controller 215 may be additionally configured for operations associated with one or more memory devices 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0070] For reference Figure 1As described, memory device 240 may include cache 285 to improve the performance of memory device 240. Cache 285 may include blocks configurable to operate in one or more modes. As described herein, a block operating in a first mode may store fewer bits per memory cell than a block operating in a second mode. For example, a block operating in the first mode may store data in an SLC, and a block operating in the second mode may store data in a multi-level memory cell (e.g., MLC, TLC, or QLC). In some instances, a block operating in the first mode may store data in an MLC, and a block operating in the second mode may store data in a TLC or QLC. Alternatively or concurrently, a block operating in the first mode may store data in a TLC, and a block operating in the second mode may store data in a QLC.

[0071] In some cases, a memory device 240 containing a large number of blocks operating in the second mode (e.g., a NAND memory device 240) may perform operations more slowly than a memory device 240 containing fewer blocks operating in the second mode. Therefore, the memory device 240 can use a cache 285 containing blocks operating in the first mode to handle relatively low-latency programs. For example, the cache 285 may store frequently accessed or recently accessed data to support relatively low-latency read operations. Alternatively, the memory system 210 may first write data to the cache 285 to support relatively low-latency write operations before moving data from the cache 285 to other memory cells (e.g., higher-capacity memory cells of the memory device 240, such as TLC). Different numbers of bits per memory cell can support different durability and, correspondingly, different numbers of P / E cycles. In one instance, within the lifetime of each corresponding block, an SLC block can support 100,000 P / E cycles, an MLC block can support 30,000 P / E cycles, a TLC block can support 8,000 P / E cycles, and a QLC block can support 2,000 P / E cycles. Therefore, blocks operating according to the first mode (e.g., blocks storing fewer bits per memory cell) can support a higher TBW than other blocks.

[0072] To improve performance and durability, some memory devices 240 may use a cache 285 containing blocks configured to operate statically in a first mode, such as static SLC blocks 275. Static SLC blocks 275 can operate according to the first mode for their lifetime and can support more durability and reliability than other blocks in the memory device 240. Although a cache 285 containing static SLC blocks 275 may store less data than another cache containing other blocks, cache 285 can last longer and can support more data cycles (e.g., more write operations and more TBW). However, in some instances, the reduced data storage associated with cache 285 can reduce the capacity of the memory device 240. For example, each static SLC block 275 within cache 285 may store relatively less information than other blocks in the memory device 240 and may be removed from the over-provisioned pool (e.g., free block pool) of the memory device 240. Therefore, cache 285 can reduce overprovisioning, increase write amplification factor, and reduce the performance of memory device 240 (e.g., dirty performance).

[0073] To balance the endurance of memory device 240 with sufficient over-provisioning of memory device 240, at least a portion of cache 285 may contain dynamic blocks 280. Each dynamic block 280 may be programmed according to a first or second mode for each P / E cycle performed on the corresponding block. In some cases, P / E cycles performed according to the second mode may reduce the endurance of dynamic block 280 relatively more than P / E cycles performed according to the first mode. For example, if data is written to dynamic block 280 one or more times in the second mode, the total number of P / E cycles supported by dynamic block 280 (e.g., TBW) may be reduced to less than the total number of P / E cycles supported by blocks operating in the first mode (e.g., SLC blocks). Some systems can handle such dynamic blocks 280 (e.g., switching between storing data in an SLC and storing data in a multi-level cell) as if the block and the block that statically stores data in a multi-level cell supported the same total number of P / E cycles. However, such systems may not be able to effectively account for the durability gains provided by the dynamic block 280 periodically or irregularly storing data in the SLC. The durability reduction due to the P / E cycle in the second mode may be the product of wear leveling or other procedures performed to prevent data storage in the second mode (e.g., the wear on the block in the second mode may be greater than in the first mode).

[0074] As described herein, memory system controller 215 can calculate the ratio of cycles in a first mode to cycles in a second mode supported by each dynamic block 280 (e.g., the amount of block that a single cycle in the second mode can consume corresponds to the calculated ratio compared to a single cycle in the first mode). Memory system controller 215 can utilize the calculated ratio and a process (e.g., an algorithm) to configure cache 285 to contain a subset of dynamic blocks 280 and determine whether to program each dynamic block 280 in the first or second mode when using cache 285. This can provide a target number of P / E cycles performed on each dynamic block 280 while maintaining the target durability of each dynamic block 280. This document describes the process for efficiently configuring and dynamically allocating blocks in cache 285, and references... Figure 4 The process is described in further detail.

[0075] The memory system controller 215 can configure the cache 285 using one or more static SLC blocks 275, dynamic blocks 280, other blocks, or any combination thereof to achieve a balance between performance, durability, and capacity of the memory device 240. The memory system controller 215 can identify the number of blocks supporting a second mode (e.g., blocks containing multi-level cells) that can be allocated within the memory device 240 to achieve the target capacity of the memory device 240 (e.g., a threshold capacity that maintains sufficient over-provisioning and storage capacity). The memory system controller 215 can allocate the remaining blocks to the cache 285 to improve the performance of the memory device 240. The memory system controller 215 can configure the target TBW (e.g., the target amount of data that the cache 285 can support) of the cache 285 according to the target capacity and durability of the memory device 240. In some instances, the cache 285 can be allocated with a first number of static SLC blocks 275 and a second number of dynamic blocks 280 to support the target TBW of the cache 285.

[0076] The memory system controller 215 can configure a target ratio for each dynamic block 280 in cache 285, representing the number of cycles executed in a first mode versus the number of cycles executed in a second mode. This target ratio, which may be referred to as the target cycle ratio, corresponds to a corresponding first target count of P / E cycles in the first mode and a corresponding second target count of P / E cycles in the second mode. A target cycle ratio can be calculated for each dynamic block 280 in cache 285 to achieve a balance between the durability and performance (e.g., target TBW) of cache 285 and the capacity target of memory device 240. For example, each dynamic block 280 can be configured to operate in the first mode for a first percentage of cycles and in the second mode for a second percentage of cycles, wherein the first and second percentages can be calculated such that the dynamic block 280 can support the target TBW (e.g., target durability of cache 285, memory device 240, or both). In some cases, the memory system controller 215 can configure a target ratio for each block of cache 285, where a second mode with zero cycle counts is assigned to static SLC blocks 275. In some instances, cache 285, target TBW of cache 285, target cycle ratio, or any combination thereof can be configured (e.g., pre-configured) during the design of memory device 240.

[0077] In some instances, the configuration parameters of cache 285 may be determined by memory system controller 215 or some other component or controller based on a characterization operation (e.g., NAND characterization operation), a process (e.g., an algorithm), or both. Parameters may be calculated and determined to meet the target TBW of memory device 240 while reducing the allocation of static SLC blocks 275 within cache 285 (e.g., minimizing the allocation of static SLC blocks 275) (e.g., obtaining zero or near-zero static SLC blocks 275 within cache 285).

[0078] While the durability and performance of cache 285 can be improved by configuring the target TBW and target cycle count at design time (e.g., based on or in response to an estimated usage level of host system 205), some host systems 205 may write more data to memory device 240 than others, which may affect configuration parameters. For example, a first host system 205 may write data to memory device 240 frequently, store a relatively large amount of data on memory device 240, or both. A second host system 205 may write data to memory device 240 less frequently than the first host system 205, store less data on memory device 240, or both. The TBW (e.g., actual TBW) of the first host system 205 to memory device 240 may exceed the target TBW over a specific period or reference time (e.g., after one month of use), and the target cycle count of cache 285 may not support the relatively high usage level of the first host system 205 (e.g., the operating frequency of dynamic block 280 in the second mode may be significantly higher than in the first mode). Alternatively, the second host system 205 may have a lower TBW (Total Quantity) for the memory device 240 than the target TBW over a specific time period or reference time. The difference between the actual TBW and the target TBW may result in less endurance or less capacity, or both, compared to dynamically determining the target cycle count based on or in response to the usage level of the memory device 240.

[0079] As described herein, memory system controller 215 can dynamically switch modes of one or more dynamic blocks 280, adjust the configuration target cycle ratio of one or more dynamic blocks 280, or both, based on the usage level of memory device 240 (e.g., during product operation). Memory system controller 215 can track a first number of P / E cycles performed on each dynamic block 280 in cache 285 in a first mode and a second number of P / E cycles performed on each dynamic block 280 in a second mode. Alternatively, memory system controller 215 can track the total number of times (TBW) is executed on cache 285. In some instances, TBW may correspond to the total number of P / E cycles performed on blocks in cache 285. This document contains references. Figure 3 Further descriptions can be made of additional aspects of the components used to track data associated with cache usage.

[0080] The memory system controller 215 can determine, based on or in response to a target cycle ratio, whether to program each dynamic block 280 in cache 285 in a first mode or a second mode. In some instances, the memory system controller 215 can monitor the target cycle ratio of the P / E cycle for each dynamic block 280 to determine whether to switch the mode of the corresponding dynamic block 280. Alternatively, the memory system controller 215 can monitor one or more triggers to switch the dynamic block 280 from the first mode to the second mode or from the second mode to the first mode. The one or more triggers may include a memory device 240 capacity meeting a threshold capacity, a memory device 240 capacity not meeting a threshold capacity, a write command for memory device 240, an erase command for memory device 240, or any combination thereof.

[0081] In one instance, if the capacity of data stored in memory device 240 is less than a threshold capacity of memory device 240, memory device 240 or memory system controller 215 may trigger one or more dynamic blocks 280 in cache 285 to switch from a first mode to a second mode (e.g., increasing the capacity of memory device 240 to meet the threshold capacity). If the capacity of data stored in memory device 240 exceeds the threshold capacity, memory device 240 or memory system controller 215 may trigger one or more dynamic blocks 280 in cache 285 to switch from the second mode to the first mode (e.g., improving performance while meeting the threshold capacity). Alternatively, each write or erase command received for memory device 240 may trigger memory system controller 215 to select one or more dynamic blocks 280 to switch modes. For example, if a command instructs to write data to memory device 240, memory system controller 215 may select one or more dynamic blocks 280 to switch from the first mode to the second mode. If a command instructs to erase data from memory device 240, memory system controller 215 may select one or more dynamic blocks 280 to switch from the second mode to the first mode.

[0082] The memory system controller 215 can select one or more dynamic blocks 280 to switch from a first mode to a second mode or from a second mode to a first mode based on the tracking cycle ratio and the target cycle ratio of the dynamic blocks 280. The memory system controller 215 can identify a first group of one or more dynamic blocks 280 that lag behind in cycle ratio. For example, the ratio of cycles executed in the first mode to cycles executed in the second mode may be less than the target ratio for each block in the first group of dynamic blocks 280. The memory system controller 215 can identify a second group of one or more dynamic blocks 280 that lead in cycle ratio. For example, the ratio of cycles executed in the first mode to cycles executed in the second mode may be greater than the target ratio for each block in the second group of dynamic blocks 280. If the memory system controller 215 identifies a trigger that switches a dynamic block 280 from the second mode to the first mode, the memory system controller 215 can select one or more dynamic blocks 280 from the first group to program in the first mode. If the memory system controller 215 recognizes a trigger that switches dynamic block 280 from the first mode to the second mode, the memory system controller 215 can select one or more dynamic blocks 280 from the second group to program in the second mode. This selection procedure allows dynamic blocks 280 to tend toward a target cycle ratio, supporting more efficient use of dynamic blocks 280.

[0083] In some instances, the memory system controller 215 may periodically (or irregularly) determine whether to adjust the target cycle ratio of dynamic blocks 280 based on or in response to the TBW of cache 285 (e.g., the actual TBW of host system 205 for cache 285). The TBW of cache 285 may correspond to the data written to cells operating in a first mode (e.g., static SLC block 275 and dynamic blocks 280 operating as SLC blocks), which can support relatively low-latency operation of cache 285. If the actual TBW of cache 285 is greater than the target TBW of cache 285, then for one or more of dynamic blocks 280, the memory system controller 215 may increase the target ratio of cycles executed in the first mode to cycles executed in the second mode. Therefore, the memory system controller 215 may program relatively more dynamic blocks 280 in cache 285 in the first mode to handle the increased overhead of host system 205, which can provide a longer lifetime for cache 285 while supporting a relatively larger workload (e.g., compared to the unadjusted cycle target). If the actual TBW of cache 285 is less than the target TBW of cache 285, the memory system controller 215 can reduce the target ratio of the loops executed in the first mode to the loops executed in the second mode for one or more of the dynamic blocks 280. Therefore, the memory system controller 215 can program a relatively larger number of dynamic blocks 280 in the second mode in cache 285 to account for a relatively lower workload experienced by cache 285 than expected (e.g., lower workload than the target TBW of cache 285). This increase in the number of dynamic blocks 280 operating in the second mode can support an increase in the total capacity of memory device 240, as well as increased over-provisioning and improved performance of memory device 240 for operations such as wear leveling, garbage collection, etc. (e.g., dirty performance), while still meeting the actual workload of cache 285. By adjusting one or more cycle targets based on or in response to the actual TBW of cache 285, memory system controller 215 can improve the allocation of blocks in cache 285 according to the usage level of cache 285, memory device 240, or both, to balance the durability, performance, and capacity of memory device 240.

[0084] Alternatively, the memory system controller 215 may determine whether to adjust the target cycle ratio of the dynamic blocks 280 based on the wear leveling state of the dynamic blocks 280. For example, wear leveling may be tracked based on the number of erases performed on each dynamic block 280. In some instances, the adjusted wear leveling state may be calculated by applying the ratio between erases performed in a first mode and erases performed in a second mode to account for increased wear on the dynamic blocks 280 operating in the second mode. Therefore, the wear leveling process of one or more of the dynamic blocks 280 may indicate to the memory system controller 215 that the number of erases on one or more blocks exceeds or falls below a threshold number, where said number can be calculated to account for erases performed in both the first and second modes. The memory system controller 215 can thus adjust the target cycle ratio of one or more dynamic blocks 280 based on the indicated wear leveling state.

[0085] The memory device 240 described herein may be configured with a cache 285, a target TBW for the cache 285, and a target ratio (e.g., at design time) for the number of cycles executed in a first mode and the number of cycles executed in a second mode for each dynamic block 280 within the cache 285. The memory system controller 215 may monitor the usage levels of the cache 285, the memory device 240, or both (e.g., at runtime) to dynamically adjust the allocation of dynamic blocks 280, the target cycle ratio of dynamic blocks 280, or both, to improve the performance and overprovisioning of the memory device 240.

[0086] Figure 3 An example of a memory system 300 supporting cache block budget technology according to the examples disclosed herein is shown. In some instances, memory system 300 may implement aspects of systems 100 and 200. For example, memory system 300 may include a memory system controller 315 and a memory device 340, which may be a reference... Figure 1 and 2 Examples of or aspects thereof are described in the memory system controller 215 and memory device 240.

[0087] Although the various components of memory system 300 are shown individually for clarity, the components of memory system 300 can be combined in any way, or additional components can be added. Furthermore, the location of components may differ from that shown (e.g., a component may be contained in memory system controller 315, or in a storage controller, or in memory device 340, etc.). In some instances, operations described as being performed by one component may be performed additionally or alternatively by different components. In some instances, one or more parameters described as being stored in or configured by one component may be additionally or alternatively stored in or configured by different components (e.g., parameters may be stored within a component of memory system controller 315, within cache 355, within the hard disk drive of memory system 300, or at other locations within memory system 300).

[0088] Memory system 300 may include a memory system controller 315, a memory device 340, and a connection 305 for communicating commands between the memory system controller 315 and the memory device 340. The memory system controller 315 or its various components may be configured to support cache block budgeting techniques in the cache 355 within the memory device 340. For example, the memory system controller 315 may include a P / E cycle counting component 320, a P / E cycle target component 325, a cycle component 330, a TBW component 335, a logic component 345, or any combination thereof. Each of these components may communicate directly or indirectly with each other via one or more buses 310. The memory device 340 may include a cache 355, which may be as described in the reference... Figure 2 An example of cache 285 is described. Cache 355 may contain a first subset of blocks configured to operate statically according to a first mode (e.g., using SLC blocks), a second subset of blocks (e.g., dynamic block 350) configured to dynamically switch between operating in the first mode and operating in a second mode (e.g., using multi-level memory cell blocks), one or more other subsets of blocks, or any combination thereof. Memory system 300 may support the first mode, the second mode, one or more other programming modes, or combinations thereof, of dynamic block 350 in cache 355.

[0089] If this article contains references Figure 2As described, the memory system controller 315 can configure the memory device 340 using cache 355, a target TBW of cache 355, a target ratio of the number of cycles executed in a first mode to the number of cycles executed in a second mode for each dynamic block 350 in cache 355, or any combination thereof. In some instances, the target ratio may correspond to a first target cycle count in the first mode and a second target cycle count in the second mode for each dynamic block 350. The P / E cycle target component 325 can configure and store the target cycle ratio and target cycle count of the dynamic block 350 (e.g., associated with a specific dynamic block 350, such as a dynamic block identifier). In some cases, each of the dynamic blocks 350 may initially be configured with the same target cycle ratio. The target TBW of the memory device 340 may be configured and stored by the TBW component 335. Alternatively or additionally, the TBW component 335 may configure the target capacity and target TBW of the memory device 340 (e.g., based on or in response to an estimated usage level of the host system). The memory system controller 315 can instruct the memory device 340 to configure the cache 355, including configuration parameters, via connection 305 (e.g., command signaling sent using connection 305). In some instances, the memory device 340 can be configured (e.g., pre-configured) using the cache 355 and corresponding parameters.

[0090] When the host system (e.g., during product operation) accesses memory device 340, P / E cycle counting component 320 can track the ratio of cycles executed in a first mode to cycles executed in a second mode for each dynamic block 350 in cache 355. Memory system controller 315 (e.g., using P / E cycle counting component 320) can store the cycle ratio executed for each dynamic block 350 and update the stored ratio throughout the lifetime of memory device 340. Alternatively, during operation, TBW component 335 can track the TBW for cache 355. Memory system controller 315 (e.g., using TBW component 335) can store the TBW for cache 355 (e.g., the actual TBW) and the target TBW configured for cache 355. In some instances, TBW component 335 can determine the TBW for cache 355 based on or in response to the number of cycles executed for each dynamic block 350, which can be tracked by P / E cycle counting component 320.

[0091] The periodization component 330 can determine the period or other schedule (e.g., a non-periodic schedule) for monitoring and, in some instances, updating the target cycle ratio of dynamic blocks 350 in cache 355. The period can be determined based on or in response to an estimated usage level of the host system. If the period is relatively short, the memory system controller 315 may interpret irregular data (e.g., data that may not accurately represent typical usage of the host system). Therefore, the periodization component 330 can be selected to provide sufficient time for obtaining accurate host system data usage (e.g., the period can be days, weeks, months, or some other duration).

[0092] For reference Figure 2 As described, one or more triggers used to switch dynamic block 350 from a first mode to a second mode or from a second mode to a first mode can be identified by logic component 345. For example, the logic component can identify whether a write command has been received for memory device 340, whether an erase command has been received for memory device 340, whether the capacity of memory device 340 is higher or lower than a threshold capacity, whether the capacity of cache 355 is higher or lower than a threshold capacity, or any combination thereof.

[0093] Logic component 345 can select one or more of dynamic blocks 350 to switch from a first mode or from a second mode to a first mode in response to identifying one or more flip-flops and based on the cycle count of one or more dynamic blocks 350, as referenced. Figure 2 As described. Logic component 345 can receive signaling (e.g., current cycle count) from P / E cycle counting component 320 indicating a first cycle count for each dynamic block 350 in a first mode and a second cycle count in a second mode. Logic component 345 can receive signaling from P / E cycle targeting component 325 indicating a target cycle ratio for each dynamic block 350. Logic component 345 can compare the first and second cycle counts within a cycle interval with the target cycle ratio to identify a first group of dynamic blocks 350 associated with the smaller ratio of cycles in the first mode to cycles in the second mode compared to the target cycle ratio, and a second group of dynamic blocks 350 associated with the larger ratio of cycles in the first mode to cycles in the second mode compared to the target cycle ratio.

[0094] If logic component 345 determines that a relatively larger number of dynamic blocks 350 can be programmed in a first mode (e.g., in response to a trigger recognition), then logic component 345 selects one or more dynamic blocks 350 from the first group. If logic component 345 determines that a relatively larger number of dynamic blocks 350 can be programmed in a second mode (e.g., in response to a trigger recognition), then logic component 345 selects one or more dynamic blocks 350 from the second group. Logic component 345 can transmit an indication of the selected block and a corresponding mode for programming the selected block to memory device 340 via connection 305.

[0095] For reference Figure 2 As described, logic component 345 can adjust the cyclic targets of one or more dynamic blocks 350 based on the usage levels of memory device 340 and cache 355. Logic component 345 can compare the current TBW of cache 355 with the adjustment target TBW of cache 355 (e.g., a second threshold TBW) at one or more intervals, based on the period indicated by period component 330. Logic component 345 can receive signaling from TBW component 335 indicating the current TBW and the second threshold TBW of cache 355. In some instances, TBW component 335 can calculate the second threshold TBW based on or in response to the target TBW (e.g., a first threshold TBW) of cache 355 and the period. In one instance, if the lifetime of cache 355 is three years and the period is six months, the second threshold TBW for the first interval (e.g., the first six months of using cache 355) can be one-sixth of the target TBW of cache 355.

[0096] If the TBW of cache 355 is less than the second threshold TBW of cache 355 during the cycle interval, logic component 345 may indicate to P / E cycle target component 325 a decreased first target count for the first mode and an increased second target count for the second mode of one or more dynamic blocks 350. If the TBW of cache 355 is greater than the second threshold TBW of cache 355 during the cycle interval, logic component 345 may indicate to P / E cycle target component 325 an increased first target count for the first mode and a decreased second target count for the second mode of one or more dynamic blocks 350. P / E cycle target component 325 may store the updated target cycle count accordingly. Alternatively, logic component 345 may determine not to update the target cycle count based on or in response to the TBW of cache 355 being relatively close to the second threshold TBW of cache 355 during the cycle interval (e.g., within an error threshold).

[0097] Alternatively, logic component 345 may determine (e.g., track) the wear leveling state of dynamic block 350 based on or in response to the number of erases performed on dynamic block 350 in each cycle interval, as referenced. Figure 2 As described. Logic component 345 can select one or more dynamic blocks 350 to be programmed according to a first mode or a second mode in response to determining a loss balance state.

[0098] Therefore, the memory system controller 315 may include one or more components for configuring the memory device 340 with cache 355, a target TBW of cache 355, and a target cycle ratio for each dynamic block 350 within cache 355. The memory system controller 315 may include one or more components for dynamically switching the programming mode of dynamic blocks 350, adjusting the target cycle ratio of dynamic blocks 350, or both, to improve performance and reduce overprovisioning.

[0099] Figure 4 An example of a flowchart 400 supporting cache block budgeting techniques according to the examples disclosed herein is shown. Flowchart 400 may illustrate a process that can be implemented by system 100 (or one or more of its components), system 200 (or one or more of its components), or memory system 300 (or one or more of its components), as referenced. Figure 1-3 As described. Flowchart 400 can illustrate the process for managing blocks within the cache to improve the performance, durability, and capacity of the cache and corresponding memory devices, as described in the reference. Figure 1-3 As described.

[0100] Various aspects of flowchart 400 may be implemented by a controller (e.g., a memory system controller) and other components. Alternatively, various aspects of flowchart 400 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory device, a memory system controller, or both). For example, if the instructions are executed by a controller (e.g., a memory system controller or a storage controller), the controller may perform the operations of flowchart 400. Alternative instances of flowchart 400 may be implemented, some of which may be performed in a different order or not at all. In some cases, operations may include features not mentioned below, or additional operations may be added.

[0101] At 405, the memory device is configured with a cache. For example, the memory device may receive cache configuration from the memory system controller. Configuration may be received from the controller or other components of the memory device. The configuration may indicate a first subset of blocks in the cache configured to operate statically in a first mode, and a second subset of blocks in the cache configured to dynamically switch between operating in the first mode and operating in a second mode. See reference... Figure 1-3As described, a block operating in a first mode can be configured to store a first number of bits per memory cell, and a block operating in a second mode can be configured to store a second number of bits per memory cell, which is more than the first number of bits per memory cell.

[0102] At 410, a target ratio of the number of cycles executed in the first mode to the number of cycles executed in the second mode can be allocated to each block in the second subset of blocks (e.g., dynamic blocks) in the cache, based on the corresponding first target count of the first mode and the corresponding second target count of the second mode. The target cycle ratio for each block can be configured based on or in response to a cache threshold TBW.

[0103] In section 415, the ratio of loops executed in the first mode to loops executed in the second mode for each block in the second subset of the cache can be tracked, stored, or both. In some instances, when the host system uses memory devices, the memory system controller can track and store the corresponding ratio.

[0104] At 420, it can be determined whether a first trigger is set to switch a block in the second subset of blocks from the first mode to the second mode. The first trigger could be a memory device capacity failing to meet a threshold capacity, a command instructing data to be written to the memory device, or both. At 425, if the first trigger is set (e.g., the trigger bit is set to indicate that the memory system has detected the value of the first trigger), it can be determined (e.g., tracked at 415) whether the block ratio is greater than a corresponding target ratio for the block. For example, it can be determined whether the number of P / E cycles executed by the block in the first mode is greater than a target number of P / E cycles in the first mode.

[0105] At 430, if the corresponding ratio of a block is greater than a target ratio (e.g., the ratio of P / E cycles executed in the first mode to those executed in the second mode is greater than the target ratio), the block can be selected. For example, a block can be selected from a subset of blocks to switch from the first mode to the second mode in response to the identification of a first trigger. In some instances, the memory system controller can select a block and program it in the second mode in subsequent P / E cycles. At 435, if the corresponding ratio of a block is less than the target ratio (e.g., the ratio of P / E cycles executed in the first mode to those executed in the second mode is less than the target ratio), another block can be selected, and the block can remain in the first mode for one or more subsequent cycles.

[0106] At 440, if the first trigger is not set (e.g., if the first trigger is not recognized), it can be determined whether a second trigger is set to switch blocks in the second subset of blocks from the second mode to the first mode. The second trigger may be a memory device capacity meeting a threshold capacity, a command indicating that data is deleted from the memory device, or both.

[0107] At 445, if a second trigger is set (e.g., if the second trigger is identified), it can be determined (e.g., as tracked at 415) whether the block ratio is less than the corresponding target ratio for the block. For example, it can be determined whether the ratio of the P / E cycle executed in the first mode to the P / E cycle executed in the second mode is less than the target ratio.

[0108] At 450, if the corresponding ratio of a block is less than the target ratio, the block can be selected. For example, a block can be selected from a subset of blocks to switch from a second mode to a first mode in response to the identification of a first trigger. In some instances, the memory system controller can select a block and program it in the first mode in a subsequent P / E cycle. At 455, if the corresponding ratio of a block is greater than the target ratio, another block can be selected, and the block can remain in the second mode for one or more subsequent cycles.

[0109] At 460, you can determine if the period has expired. In some instances, the period can be a configured period. See reference... Figure 3 As described, cycles can be configured, stored, or both via the cycle component of the memory system controller. The process can be repeated if the cycle has not expired. For example, the memory system controller can continue to track the corresponding rate of rotation of dynamic blocks at 415.

[0110] At 465, if a cycle has expired, it can be determined whether the current TBW of the cache is less than the cache's second threshold TBW. The second threshold TBW can be calculated based on the threshold TBW configured for the cache and the timing associated with the cycle. For example, if a cycle expires six times over the entire lifetime of the memory system, the second threshold TBW at the time of the first expiration might be one-sixth of the cache's threshold TBW. The second threshold TBW at the time of the second expiration might be two-sixths of the cache's threshold TBW. In some instances, such as reference... Figure 3 As described, the memory system controller can configure, track, or store the cache's TBW, the cache's threshold TBW, the cache's second threshold TBW, or any combination thereof.

[0111] In 470, if the cache's TBW is less than the cache's second threshold TBW, the first target count of the first mode for at least one block in the second block subset can be reduced, and the second target count of the second mode for at least one block in the second block subset can be increased. Therefore, for at least one dynamic block, the target ratio of the loop executed in the first mode to the loop executed in the second mode can be reduced. In some instances, such as reference... Figure 3 As described, the P / E cycle target component of the memory system controller can adjust the target ratio of at least one block and can store the adjusted ratio.

[0112] In step 475, if the cache's TBW is greater than or equal to the cache's second threshold TBW, it can be determined whether the cache's current TBW is greater than the cache's third threshold TBW. In some instances, the third threshold TBW can be the same as the second threshold TBW. Alternatively, the third TBW can be different from (e.g., greater than) the second threshold TBW, such that if the cache's actual TBW is within the range between the cache's second and third threshold TBWs, no target adjustment is needed. The third threshold TBW can be calculated based on the cache's threshold TBW and the period.

[0113] At 480, if the cache's TBW is greater than the cache's third threshold TBW, the first target count of the first mode for at least one block in the second block subset can be increased, and the second target count of the second mode for at least one block in the second block subset can be decreased. Therefore, for at least one dynamic block, the target ratio of the loop executed in the first mode to the loop executed in the second mode can be increased.

[0114] If the actual TBW of the cache is less than or equal to the third threshold TBW of the cache, the target ratio for the cycle can be maintained. For example, the memory system controller can avoid adjusting one or more target ratios based on or in response to the actual TBW of the cache being within the threshold range of the target TBW of the cache. When adjusting or determining not to adjust the target ratio, the memory system controller can continue to track the corresponding ratio of the cycle of dynamic blocks at 415.

[0115] Figure 5 A block diagram 500 is shown of a memory system 520 supporting cache block budget technology according to an example disclosed herein. The memory system 520 may be as described in the reference... Figure 1-3Examples of aspects of the described memory systems 110, 210, or 300. Memory system 520 or its various components may be examples of constructs for performing the various aspects of the cache block budget techniques described herein. For example, memory system 520 may include cache configuration component 525, cycle ratio component 530, block selection component 535, target cycle ratio component 540, trigger component 545, TBW component 550, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0116] Cache configuration component 525 may be configured or otherwise support components for performing the following operations: configuring a memory device with a cache, the cache comprising a first subset of blocks configured to operate statically in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and operating in a second mode, wherein the first block operating in the first mode is configured to store a first number of bits per memory cell, and the second block operating in the second mode is configured to store a second number of bits per memory cell greater than the first number of bits. Cyclic ratio component 530 may be configured or otherwise support components for performing the following operations: storing, for each block in the second subset of blocks, a corresponding ratio of cycles executed in the first mode to cycles executed in the second mode. Block selection component 535 may be configured or otherwise support components for performing the following operations: selecting blocks from the second subset of blocks to switch from the first mode to the second mode or from the second mode to the first mode in response to a trigger and at least in part based on the corresponding ratio of the blocks.

[0117] In some instances, the target cycle ratio component 540 may be configured or otherwise support a component for performing the following operation: allocating a corresponding target ratio of the cycles executed in the first mode to the cycles executed in the second mode to each block in the second block subset based on (e.g., in response to) a cache threshold TBW, according to a corresponding first target count in the first mode and a corresponding second target count in the second mode.

[0118] In some instances, trigger component 545 may be configured or otherwise support components for performing the following operations: identifying a trigger that switches the block from a first mode to a second mode. In some instances, cycle ratio component 530 may be configured or otherwise support components for performing the following operations: determining, based on (e.g., in response to) identifying a trigger, that a corresponding ratio of the block is greater than a corresponding target ratio of the block, wherein the block is selected based on (e.g., in response to) said determination. In some instances, the trigger includes a current capacity of the memory device failing to meet a threshold capacity, a command instructing data to be written to the memory device, or both.

[0119] In some instances, trigger component 545 may be configured or otherwise support components for performing the following operations: identifying a trigger that switches the block from a second mode to a first mode. In some instances, cycle ratio component 530 may be configured or otherwise support components for performing the following operations: determining, based on (e.g., in response to) identifying a trigger, that a corresponding ratio of the block is less than a corresponding target ratio of the block, wherein the block is selected based on (e.g., in response to) the determination. In some instances, the trigger includes a current capacity of the memory device satisfying a threshold capacity, a command instructing the deletion of data from the memory device, or both.

[0120] In some instances, the TBW component 550 may be configured or otherwise support a component for performing the following operation: comparing the current TBW of the cached at a first time with a second threshold TBW of the cached at the first time, the second threshold TBW being based on the cached threshold TBW and the first time (e.g., calculated using the cached threshold TBW and the first time). In some instances, the target cycle ratio component 540 may be configured or otherwise support a component for performing the following operation: modifying the target ratio of at least one block in the second block subset based on (e.g., in response to) the comparison.

[0121] In some instances, the current TBW of the cache at a first time is less than a second threshold TBW of the cache, and the target cycle ratio component 540 may be configured or otherwise support components for performing the following operations: modifying the target cycle ratio by reducing a first target cycle count of a first mode of at least one block in the second block subset based on (e.g., in response to) the current TBW being less than the second threshold TBW, and by increasing a second target cycle count of a second mode of at least one block in the second block subset based on (e.g., in response to) the current TBW being less than the second threshold TBW.

[0122] In some instances, the current TBW of the cache at a first time is greater than a second threshold TBW of the cache, and the target cycle ratio component 540 may be configured or otherwise support components for performing the following operations: modifying the target cycle ratio by increasing a first target count of a first pattern of at least one block in the second block subset based on (e.g., in response to) the current TBW being greater than the second threshold TBW, and decreasing a second target count of a second pattern of at least one block in the second block subset based on (e.g., in response to) the current TBW being greater than the second threshold TBW. In some instances, the comparison is performed according to a configured period.

[0123] In some instances, cache configuration component 525 may be configured or otherwise support components for allocating a first subset of blocks and a second subset of blocks to the cache based on (e.g., in response to) a threshold capacity of the memory device. In some instances, cache configuration component 525 may be configured or otherwise support components for allocating blocks to either a first subset of blocks or a second subset of blocks based on (e.g., in response to) a cache threshold TBW.

[0124] In some instances, the first block operating in a first mode stores the first data in an SLC, and the second block operating in a second mode stores the second data in an MLC, TLC, or QLC. In some instances, the first block operating in a first mode stores the first data in an MLC, and the second block operating in a second mode stores the second data in a TLC or QLC. In some instances, the first block operating in a first mode stores the first data in a TLC, and the second block operating in a second mode stores the second data in a QLC. In some instances, the memory device includes a NAND memory device.

[0125] Figure 6 A flowchart is shown illustrating method 600 supporting cache block budget techniques according to examples disclosed herein. The operation of method 600 can be implemented by a memory system or its components as described herein. For example, the operation of method 600 can be implemented by, as referenced... Figure 1-5 The described memory system is used for execution. In some instances, the memory system can execute a set of instructions to control the functional elements of the device, thereby performing the described function. Alternatively, the memory system can use dedicated hardware to perform aspects of the described function.

[0126] At 605, the method may include configuring a memory device with a cache, the cache comprising a first subset of blocks configured to operate statically in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and operating in a second mode, wherein the first block operating in the first mode is configured to store a first number of bits per memory cell, and the second block operating in the second mode is configured to store a second number of bits per memory cell greater than the first number of bits. The operation of 605 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 605 may be as described in the references... Figure 5 The described cache configuration component 525 is used for execution.

[0127] In 610, the method may include, for each block in the second subset of blocks, storing a corresponding ratio of loops executed in the first mode to loops executed in the second mode. The operation of 610 can be performed according to the examples disclosed herein. In some instances, aspects of the operation of 610 may be derived from, as referenced... Figure 5 The described cycle ratio component 530 is used for execution.

[0128] In 615, the method may include selecting blocks from a second subset of blocks to switch from a first mode or from a second mode to a first mode in response to a trigger and at least in part based on a corresponding ratio of the blocks. The operation of 615 may be performed according to the examples disclosed herein. In some instances, aspects of the operation of 615 may be as described in references... Figure 5 The block selection component 535 is described for execution.

[0129] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing processor-executable instructions) for performing: configuring a memory device with a cache, the cache comprising a first subset of blocks configured to operate statically in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and operating in a second mode, wherein the first block operating in the first mode is configured to store a first number of bits per memory cell, and the second block operating in the second mode is configured to store a second number of bits per memory cell greater than the first number of bits; for each block in the second subset of blocks, storing a corresponding ratio of loops executed in the first mode to loops executed in the second mode; and selecting blocks from the second subset of blocks to switch from the first mode to the second mode or from the second mode to the first mode in response to a trigger and based on the corresponding ratio of the blocks.

[0130] Some instances of the method 600 and device described herein may further include operational features, circuits, logic, components, or instructions for performing the following: allocating each block in the second block subset to a corresponding target ratio of loops executed in the first mode to loops executed in the second mode, based on a cache threshold TBW, according to a corresponding first target count of the first mode and a corresponding second target count of the second mode.

[0131] Some examples of the method 600 and apparatus described herein may further include operational features, circuitry, logic, components, or instructions for performing the following operations: identifying a trigger that switches the block from a first mode to a second mode, and determining, based on the identified trigger, that a corresponding ratio of the block may be greater than a corresponding target ratio of the block, wherein the block may be selected based on said determination. In some examples of the method 600 and apparatus described herein, the trigger includes a current capacity of the memory device failing to meet a threshold capacity, a command indicating that data should be written to the memory device, or both.

[0132] Some examples of the method 600 and apparatus described herein may further include operational features, circuitry, logic, components, or instructions for performing the following operations: identifying a trigger that switches the block from a second mode to a first mode, and determining, based on the identified trigger, that a corresponding ratio of the block may be less than a corresponding target ratio of the block, wherein the block may be selected based on said determination. In some examples of the method 600 and apparatus described herein, the trigger includes a current capacity of the memory device satisfying a threshold capacity, a command instructing the deletion of data from the memory device, or both.

[0133] Some examples of the method 600 and device described herein may further include operational features, circuitry, logic, components, or instructions for performing the following operations: comparing a current TBW in a first-time cache with a second threshold TBW in a first-time cache, the second threshold TBW being based on the cached threshold TBW and the first time; and modifying a target ratio of at least one block in a second subset of blocks based on the comparison.

[0134] In some instances of the method 600 and device described herein, the current TBW of the first-time cache may be less than a second threshold TBW of the cache, and modifying the target cycle ratio may include: reducing the first target cycle count of a first mode of at least one block in the second block subset based on the current TBW being less than the second threshold TBW, and increasing the second target cycle count of a second mode of at least one block in the second block subset based on the current TBW being less than the second threshold TBW.

[0135] In some instances of the method 600 and device described herein, the current TBW of the cache in the first time period may be greater than a second threshold TBW of the cache, and modifying the target cycle ratio may include: increasing a first target count of a first pattern of at least one block in the second block subset based on the current TBW being greater than the second threshold TBW, and decreasing a second target count of a second pattern of at least one block in the second block subset based on the current TBW being greater than the second threshold TBW. In some instances of the method 600 and device described herein, the comparison may be performed according to a configured period.

[0136] Some instances of the method 600 and device described herein may further include operational features, circuits, logic, components, or instructions for allocating a first subset and a second subset of blocks to a cache based on a threshold capacity of the memory device. Some instances of the method 600 and device described herein may further include operational features, circuits, logic, components, or instructions for allocating blocks to either a first subset or a second subset of blocks based on a cache threshold TBW.

[0137] In some instances of the method 600 and apparatus described herein, a first block operating in a first mode stores first data in an SLC, and a second block operating in a second mode stores second data in an MLC, TLC, or QLC; or a first block operating in a first mode stores first data in an MLC, and a second block operating in a second mode stores second data in a TLC or QLC; or a first block operating in a first mode stores first data in a TLC, and a second block operating in a second mode stores second data in a QLC.

[0138] In some instances of the method 600 and apparatus described herein, the memory device includes a NAND memory device.

[0139] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0140] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, signals may represent buses of signals, which may have various bit widths.

[0141] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0142] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0143] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, it achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0144] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0145] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0146] Additionally, the terms "directly in response to" or "directly responding to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly responding to" such other condition or action.

[0147] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0148] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, such as degenerate, semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0149] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," not "preferred" or "superior to other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0150] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral distinguishing them from each other. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0151] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0152] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0153] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of"), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0154] Computer-readable media includes both non-transitory computer-readable storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then those coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically. Combinations of these are also included within the scope of computer-readable media.

[0155] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system comprising: Memory devices; as well as A controller, coupled to the memory device and configured to cause the memory system to perform the following operations: The memory device is configured with a cache, the cache including a first subset of blocks configured to operate statically in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and operating in a second mode, wherein the first subset of blocks operating in the first mode is configured to store a first number of bits per memory cell, and the second subset of blocks operating in the second mode is configured to store a second number of bits per memory cell that is greater than the first number of bits. For each block in the second subset, a corresponding ratio is stored between the loops executed in the first mode and the loops executed in the second mode; as well as A block is selected from the second subset of blocks to switch from the first mode to the second mode or from the second mode to the first mode in response to a trigger and at least in part based on the corresponding ratio of the selected blocks.

2. The memory system of claim 1, wherein the controller is further configured to cause the memory system to perform the following operations: Based on the corresponding first target count of the first mode and the corresponding second target count of the second mode, and at least in part based on the total threshold write bytes (TBW) of the cache, a corresponding target ratio of the loops executed in the first mode to the loops executed in the second mode is allocated to each block in the second block subset.

3. The memory system of claim 2, wherein the controller is further configured to cause the memory system to perform the following operations: Identify the trigger that switches the selected block from the first mode to the second mode; and The selection of the selected block is based at least in part on identifying the trigger and determining that the corresponding ratio of the selected block is greater than the corresponding target ratio of the selected block, wherein the selection of the selected block is based at least in part on the determination.

4. The memory system of claim 3, wherein the trigger comprises the memory device’s current capacity failing to meet a threshold capacity, a command instructing data to be written to the memory device, or both.

5. The memory system of claim 2, wherein the controller is further configured to cause the memory system to perform the following operations: Identify the trigger that switches the selected block from the second mode to the first mode; and The selection of the selected block is based at least in part on identifying the trigger and determining that the corresponding ratio of the selected block is less than the corresponding target ratio of the selected block, wherein the selection of the selected block is based at least in part on the determination.

6. The memory system of claim 5, wherein the trigger comprises a current capacity of the memory device satisfying a threshold capacity, a command instructing the deletion of data from the memory device, or both.

7. The memory system of claim 2, wherein the controller is further configured to cause the memory system to perform the following operations: The current TBW of the cache at a first time is compared with a second threshold TBW of the cache at the first time, the second threshold TBW being at least partially based on the cache's threshold TBW and the first time; and The target ratio of at least one block in the second block subset is modified, at least in part, based on the comparison.

8. The memory system according to claim 7, wherein: At the first time, the current TBW of the cache is less than the second threshold TBW of the cache; and The controller, configured to cause the memory system to modify the target ratio, is configured to cause the memory system to perform the following operations: At least in part based on the fact that the current TBW is less than the second threshold TBW, the first target count of the first pattern of the at least one block in the second block subset is reduced; as well as At least in part based on the fact that the current TBW is less than the second threshold TBW, the second target count of the second mode of the at least one block in the second block subset is increased.

9. The memory system according to claim 7, wherein: At the first time, the current TBW of the cache is greater than the second threshold TBW of the cache; and The controller, configured to cause the memory system to modify the target ratio, is configured to cause the memory system to perform the following operations: At least in part based on the fact that the current TBW is greater than the second threshold TBW, the first target count of the first pattern of the at least one block in the second block subset is increased; as well as The second target count of the second mode of at least one block in the second block subset is reduced, at least in part, based on the fact that the current TBW is greater than the second threshold TBW.

10. The memory system of claim 7, wherein the comparison is performed according to a configured period.

11. The memory system of claim 1, wherein the controller is further configured to cause the memory system to perform the following operations: The first and second block subsets are allocated to the cache, at least in part based on the threshold capacity of the memory device.

12. The memory system of claim 1, wherein the controller is further configured to cause the memory system to perform the following operations: One or more blocks in the memory device are allocated to the first block subset or the second block subset, based at least in part on the total total write bytes (TBW) of the cache.

13. The memory system according to claim 1, wherein: The first block operating in the first mode stores the first data in a single-level cell (SLC), and the second block operating in the second mode stores the second data in a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). The first block operating in the first mode stores the first data in the MLC, and the second block operating in the second mode stores the second data in the TLC or QLC; or The first block operating in the first mode stores the first data in the TLC, and the second block operating in the second mode stores the second data in the QLC.

14. The memory system of claim 1, wherein the memory device includes a NAND memory device.

15. A non-transitory computer-readable medium storing code, the non-transitory computer-readable medium comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to perform the following operations: The memory device is configured with a cache, the cache including a first subset of blocks configured to operate statically in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and operating in a second mode, wherein the first subset of blocks operating in the first mode is configured to store a first number of bits per memory cell, and the second subset of blocks operating in the second mode is configured to store a second number of bits per memory cell that is greater than the first number of bits. For each block in the second subset, a corresponding ratio is stored between the loops executed in the first mode and the loops executed in the second mode; and A block is selected from the second subset of blocks to switch from the first mode to the second mode or from the second mode to the first mode in response to a trigger and at least in part based on the corresponding ratio of the selected block.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: Based on the corresponding first target count of the first mode and the corresponding second target count of the second mode, and at least in part based on the total threshold write bytes (TBW) of the cache, a corresponding target ratio of the loops executed in the first mode to the loops executed in the second mode is allocated to each block in the second block subset.

17. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: Identify the trigger that switches the selected block from the first mode to the second mode; and The selection of the selected block is based at least in part on identifying the trigger and determining that the corresponding ratio of the selected block is greater than the corresponding target ratio of the selected block, wherein the selection of the selected block is based at least in part on the determination.

18. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: Identify the trigger that switches the selected block from the second mode to the first mode; and The selection of the selected block is based at least in part on identifying the trigger and determining that the corresponding ratio of the selected block is less than the corresponding target ratio of the selected block, wherein the selection of the selected block is based at least in part on the determination.

19. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: The current TBW of the cache at a first time is compared with a second threshold TBW of the cache at the first time, the second threshold TBW being at least partially based on the cache's threshold TBW and the first time; and The target ratio of at least one block in the second block subset is modified, at least in part, based on the comparison.

20. The non-transitory computer-readable medium of claim 19, wherein: At the first time, the current TBW of the cache is less than the second threshold TBW of the cache; and When the instruction that causes the electronic device to modify the target ratio is executed by the processor of the electronic device, the electronic device causes the electronic device to perform the following operations: At least in part based on the fact that the current TBW is less than the second threshold TBW, the first target count of the first pattern of the at least one block in the second block subset is reduced; as well as At least in part based on the fact that the current TBW is less than the second threshold TBW, the second target count of the second mode of the at least one block in the second block subset is increased.

21. The non-transitory computer-readable medium according to claim 19, wherein: At the first time, the current TBW of the cache is greater than the second threshold TBW of the cache; and When the instruction that causes the electronic device to modify the target ratio is executed by the processor of the electronic device, the electronic device causes the electronic device to perform the following operations: At least in part based on the fact that the current TBW is greater than the second threshold TBW, the first target count of the first pattern of the at least one block in the second block subset is increased; as well as The second target count of the second mode of at least one block in the second block subset is reduced, at least in part, based on the fact that the current TBW is greater than the second threshold TBW.

22. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: The first and second block subsets are allocated to the cache, at least in part based on the threshold capacity of the memory device.

23. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: Blocks are allocated to either the first subset of blocks or the second subset of blocks, at least in part based on the total total write bytes (TBW) of the cache.

24. A method executed by a memory system, comprising: The memory device is configured with a cache, the cache including a first subset of blocks configured to operate statically in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and operating in a second mode, wherein the first subset of blocks operating in the first mode is configured to store a first number of bits per memory cell, and the second subset of blocks operating in the second mode is configured to store a second number of bits per memory cell that is greater than the first number of bits. For each block in the second subset, a corresponding ratio is stored between the loops executed in the first mode and the loops executed in the second mode; as well as A block is selected from the second subset of blocks to switch from the first mode to the second mode or from the second mode to the first mode in response to a trigger and at least in part based on the corresponding ratio of the selected blocks.

25. The method of claim 24, further comprising: Based on the corresponding first target count of the first mode and the corresponding second target count of the second mode, and at least in part based on the total threshold write bytes (TBW) of the cache, a corresponding target ratio of the loops executed in the first mode to the loops executed in the second mode is allocated to each block in the second block subset.

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