Solid-state drives, devices, and operating methods of solid-state drives

Abstract

This disclosure provides a solid-state drive, a device, and a method for operating the solid-state drive. The solid-state drive includes a magnetoresistive random access memory (MRAM), a NAND flash memory, and a solid-state drive controller. The solid-state drive controller is configured to: receive first data from a host; store the first data in a solid-state drive data buffer; retrieve the first data from the solid-state drive data buffer and write the first data to the MRAM via the MRAM controller; determine, based on the characteristics of the first data, whether to store the first data in the MRAM or the NAND flash memory via a data allocation circuit; and, in response to determining that the first data should be stored in the NAND flash memory, read the first data from the MRAM, write the first data to the NAND flash memory, and erase the first data from the MRAM. This disclosure reduces the design complexity of power-down protection.

Description

Technical Field

[0001] This disclosure generally relates to solid-state drives (SSDs) and methods of operating solid-state drives, and more specifically, to solid-state drives having magnetoresistive random-access memory (MRAM) and methods of operating solid-state drives. Background Technology

[0002] Traditional solid-state drives (SSDs) use NAND flash memory as the primary data storage medium. NAND flash memory offers many desirable characteristics, such as high density, low cost, and non-volatility compared to static random-access memory (SRAM) and dynamic random-access memory (DRAM), and fast access and low latency compared to hard disk drives (HDDs). In recent years, emerging non-volatile memories have become increasingly popular. Researchers have developed and analyzed several non-volatile RAMs (NVRAMs) for application in memory / storage systems. In SSD systems, NVRAM can be added as a new layer between DRAM and NAND flash memory to provide greater flexibility. Magnetoresistive random-access memory (MRAM) is one of the most mature non-volatile RAMs currently available. Magnetoresistive random access memory (MRAM) has many advantages, such as byte addressability, fast read / write speeds, higher reliability (compared to NAND) and non-volatility (compared to dynamic random access memory). Summary of the Invention

[0003] This disclosure describes solid-state drive devices and methods of operation for hybrid media system architectures using magnetoresistive random access memory (MRAM) and NAND flash memory in solid-state drives. A major problem with multi-level cell (e.g., two or more) NAND flash memory is power loss protection. The technology disclosed herein provides solid-state drives with magnetoresistive MRAM and NAND flash memory, and methods of operation for solid-state drives.

[0004] In one aspect, a solid-state drive is provided. The solid-state drive includes a magnetoresistive random access memory (MRAM), a NAND flash memory, and a solid-state drive controller coupled to the MRAM and the NAND flash memory. The solid-state drive controller includes data allocation circuitry and a MRAM controller. The data allocation circuitry is configured to determine whether to store data in one of the MRAM or the NAND flash memory. The MRAM controller is coupled to the MRAM and configured to read data from or write data to the MRAM. The solid-state drive controller is configured to receive first data from a host, store the first data in a solid-state drive data buffer, retrieve the first data from the solid-state drive data buffer, and write the first data into a magnetoresistive random access memory (MRAM) via a magnetoresistive random access memory (MRAM) controller; determine, based on the characteristics of the first data, whether to store the first data in the MRAM or in a NAND flash memory via a data allocation circuit; and in response to determining that the first data should be stored in the NAND flash memory, read the first data from the MRAM, write the first data into the NAND flash memory, and erase the first data from the MRAM.

[0005] In some embodiments, the solid-state drive controller is configured to retain the first data in the magnetoresistive random access memory in response to determining that the first data will be stored in the magnetoresistive random access memory.

[0006] In some embodiments, the solid-state drive controller is also configured to record the physical address of the first data in the magnetoresistive random access memory or NAND memory in the addressing table.

[0007] In some embodiments, the solid-state drive controller is also configured to store an addressing table in a magnetoresistive random access memory, a NAND memory, or a dynamic random access memory coupled to the solid-state drive controller.

[0008] In some embodiments, the solid-state drive controller is further configured to: receive a read command from a host for reading second data; look up an address table via a data allocation circuit to determine whether the second data is stored in a magnetoresistive random access memory (MRAM) or a NAND flash memory; in response to determining that the second data is stored in the MRAM, retrieve the second data from the MRAM and store the second data in a solid-state drive data buffer; in response to determining that the second data is stored in the NAND flash memory, retrieve the second data from the NAND flash memory and store the second data in a solid-state drive data buffer; and retrieve the second data from the solid-state drive data buffer and send the second data to the host.

[0009] In some embodiments, the solid-state drive controller is further configured to: determine whether the number of times the host accesses the second data exceeds a threshold within a certain period of time; in response to the number of times the host accesses the second data exceeds the threshold within a certain period of time, and in response to determining that the second data is stored in NAND memory, migrate the second data from NAND memory to magnetoresistive random access memory, erase the second data from NAND memory, and update the physical address of the second data in the addressing table.

[0010] In some embodiments, the data allocation circuit is configured to: calculate the read access frequency of each logic block on the magnetoresistive random access memory and the NAND memory; select a threshold frequency based on the storage capacity of the magnetoresistive random access memory; determine whether the read access frequency of each logic block on the magnetoresistive random access memory and the NAND memory exceeds the threshold frequency; in response to determining that the read access frequency of the logic block on the magnetoresistive random access memory does not exceed the threshold frequency, migrate the data of the logic block stored on the magnetoresistive random access memory to the NAND memory; and in response to determining that the read access frequency of the logic block on the NAND memory exceeds the threshold frequency, migrate the data of the logic block stored on the NAND memory to the magnetoresistive random access memory.

[0011] In some embodiments, the data allocation circuitry includes a machine learning model. The machine learning model includes a data allocation engine and a data migration engine. The machine learning model is configured to, in response to receiving a read command from a host for reading second data stored on a solid-state drive: calculate the read access frequency of the second data; obtain the current state of the machine learning model; input the read access frequency of the second data and the current state of the machine learning model to the data allocation engine for determining whether the second data should be stored in magnetoresistive random access memory (MRAM) or NAND flash memory, and generate a determination result; input the determination result of the data allocation engine to the data migration engine for determining whether to migrate the second data between MRAM and NAND flash memory; calculate the read access latency for accessing the second data stored on the solid-state drive; and generate machine learning samples, the machine learning samples including the read access frequency of the second data, the current state of the machine learning model, the output of the data migration engine, and the read access latency.

[0012] In some embodiments, the solid-state drive controller is also configured to flush all data in the solid-state drive data buffer to the magnetoresistive random access memory in response to a power failure.

[0013] In another aspect, an apparatus is provided. The apparatus includes a host and a solid-state drive. The solid-state drive includes a magnetoresistive random access memory (MRAM), NAND flash memory, and a solid-state drive controller coupled to the MRAM and NAND flash memory. The solid-state drive controller includes data allocation circuitry and a MRAM controller. The data allocation circuitry is configured to determine whether to store data in one of the MRAM or the NAND flash memory. The MRAM controller is coupled to the MRAM and configured to read data from or write data to the MRAM. The solid-state drive controller is configured to receive first data from a host; store the first data to a solid-state drive data buffer; retrieve the first data from the solid-state drive data buffer and write the first data to a magnetoresistive random access memory (MRAM) via a magnetoresistive random access memory (MRAM) controller; determine, based on the characteristics of the first data, whether to store the first data in the MRAM or in a NAND flash memory via a data allocation circuit; and in response to determining that the first data should be stored in the NAND flash memory, read the first data from the MRAM, write the first data to the NAND flash memory, and erase the first data from the MRAM.

[0014] In another aspect, a method of operating a solid-state drive is provided. The solid-state drive includes a magnetoresistive random access memory (MRAM), a NAND flash memory, and a solid-state drive controller coupled to the MRAM and the NAND flash memory. The method of operating includes: receiving first data from a host via the solid-state drive controller; storing the first data in a solid-state drive data buffer via the solid-state drive controller; retrieving the first data from the solid-state drive data buffer and writing the first data to the MRAM via the solid-state drive controller; determining, based on characteristics of the first data, whether to store the first data in the MRAM or the NAND flash memory via the solid-state drive controller; and, in response to determining that the first data should be stored in the NAND flash memory, reading the first data from the MRAM, writing the first data to the NAND flash memory, and erasing the first data from the MRAM via the solid-state drive controller.

[0015] In some embodiments, the solid-state drive controller includes a machine learning model. The machine learning model includes a data allocation engine and a data migration engine, and is configured to, in response to receiving a read command from a host for reading second data stored on the solid-state drive: calculate the read access frequency of the second data; obtain the current state of the machine learning model; input the read access frequency of the second data and the current state of the machine learning model to the data allocation engine for determining whether the second data should be stored in magnetoresistive random access memory (MRAM) or NAND flash memory, and generate a determination result; input the determination result of the data allocation engine to the data migration engine for determining whether to migrate the second data between MRAM and NAND flash memory; calculate the read access latency for accessing the second data stored on the solid-state drive; and generate machine learning samples, the machine learning samples including the read access frequency of the second data, the current state of the machine learning model, the output of the data migration engine, and the read access latency. Attached Figure Description

[0016] Certain features of various embodiments of the present technology are particularly set forth in the appended claims. A better understanding of the features and advantages of the present technology will be obtained by referring to the following detailed description, which illustrates illustrative embodiments utilizing the principles of the present disclosure, with accompanying drawings of the illustrative embodiments:

[0017] Figure 1 A block diagram of a system according to an exemplary embodiment is shown.

[0018] Figure 2 A block diagram illustrating a data allocation circuit according to an exemplary embodiment and its interaction with a magnetoresistive random access memory and a NAND memory is shown.

[0019] Figure 3 A block diagram illustrating a data allocation circuit according to an exemplary embodiment and its interaction with a magnetoresistive random access memory and a NAND memory is shown.

[0020] Figure 4 A flowchart illustrating a method for processing write commands in a solid-state drive according to an exemplary embodiment is shown.

[0021] Figure 5 A flowchart illustrating a method for processing read commands in a solid-state drive according to an exemplary embodiment is shown.

[0022] Figure 6 A flowchart illustrating a method for migrating data in a solid-state drive based on data popularity according to an exemplary embodiment is shown.

[0023] Figure 7 A flowchart illustrating a method for migrating data to a solid-state drive based on data popularity according to an exemplary embodiment is shown.

[0024] Figure 8 A flowchart illustrating a method for migrating data to a solid-state drive based on data popularity according to an exemplary embodiment is shown.

[0025] Figure 9 A flowchart illustrating a method for managing storage in a solid-state drive according to an exemplary embodiment is shown. Detailed Implementation

[0026] To provide a full understanding of the various embodiments of this disclosure, certain specific details are set forth in the following description. However, those skilled in the art will understand that this disclosure can be practiced without these details. Furthermore, while various embodiments of this disclosure are disclosed herein, many adjustments and modifications can be made within the scope of this disclosure based on common general knowledge known to those skilled in the art. These modifications include substituting any aspect of this disclosure with known equivalents to achieve the same results in substantially the same manner.

[0027] Unless the context otherwise requires, the word “comprising” and its variations, such as “having” and “including,” shall be interpreted in an open, inclusive sense, that is, “including but not limited to.” Throughout the specification, the enumeration of numerical ranges is intended as a shorthand notation for an independent reference to each individual numerical value falling within that range, which includes the numerical value defining the range. Each individual numerical value is included in this specification as if it were enumerated independently herein. Furthermore, unless the context explicitly requires otherwise, the singular forms “a,” “this,” and “that,” etc., include plural referents.

[0028] References to "an embodiment" or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification do not necessarily refer to the same embodiment, but may do so in some cases. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0029] Various embodiments relate to the application of hybrid media system architectures using magnetoresistive random access memory and NAND memory in solid-state drives. Several types of NAND memory are currently used. For example, single-level cell (SLC) NAND memory includes one bit per cell and two possible voltage states. Multi-level cell (MLC) NAND memory includes two bits per cell, thus including four possible voltage states. Triple-level cell (TLC) NAND memory includes three bits per cell and eight possible voltage states. And quad-level cell (QLC) NAND memory includes four bits per cell and sixteen possible voltage states. NAND memory with more levels than quad-level cell NAND memory is considered in this disclosure, and the techniques of this disclosure are applicable to (and interchangeable with) those NAND memory devices.

[0030] A major problem with NAND memory devices having multiple levels of cells (two or more) is power loss protection. Due to the complex programming model of NAND memory devices with multiple levels of cells, they require large storage space to store data that has been received by the solid-state drive but has not yet been written to the NAND. In the event of a power loss, this data requires large capacitors to support it to ensure that it can be stored in the NAND. In this case, magnetoresistive random access memory (MRAM) can be used as a data buffer because data written to MRAM is power-loss safe. MRAM with high write / read speeds can also be used as a write buffer to improve system performance. The solid-state drive disclosed herein includes data allocation circuitry that uses machine learning algorithms to separate hot data / cold data for allocating data on the MRAM and NAND.

[0031] As traditional solid-state drives transitioned from three-cell NAND to four-cell NAND to reduce costs, NAND write times increased. Maintaining high bandwidth, especially under heavy write operations, became increasingly challenging. Furthermore, four-cell NAND has a unique programming model that requires caching more data before it can be safely stored. This makes power-loss protection more complex.

[0032] This document discloses a system with a hybrid architecture of magnetoresistive random access memory (MRAM) and NAND flash memory. MRAM is used as a write cache and for storing hot data (i.e., data accessed more frequently than a threshold) and / or system metadata. NAND flash memory is used to store host data. This disclosure provides a data allocation circuit that uses a machine learning algorithm to balance the data written to the MRAM and NAND flash memory.

[0033] In the system disclosed herein, a magnetoresistive random access memory (MRAM) is added together with NAND flash memory (and in some embodiments, also with dynamic random access memory) as a memory layer (separate memory). A MRAM controller is placed on a solid-state drive controller to control the MRAM. For example, the interface between the MRAM and the solid-state drive controller may be a non-volatile dual in-line memory module (NVDIMM). The solid-state drive controller sends commands (read, write, reset, etc.) to the MRAM via the MRAM controller. In some embodiments, the MRAM is used to store host data configured to be written to NAND flash memory. The host data is initially temporarily stored on the MRAM. In conventional techniques, host data is typically first written to dynamic random access memory (DRAM) and then moved from DRAM to NAND flash memory. However, due to the programming model of NAND flash memory, large amounts of data need to be buffered. Traditional systems have limited power backup, resulting in data loss during power outages. According to the technology disclosed herein, host data is written to non-volatile magnetoresistive random access memory, requiring less power backup in solid-state drive systems because host data is not lost even in the event of a sudden power failure.

[0034] In some embodiments, the magnetoresistive random access memory (MRAM) is configured to store system metadata, such as driver states, address tables, etc. During power outages, system data can be stored in the MRAM and does not need to be moved to NAND.

[0035] In some embodiments, magnetoresistive random access memory (MRAM) is configured to store hot host data that is frequently accessed by the host. Holding hot data on MRAM provides fast read access and reduces access latency. The techniques disclosed herein can allocate hot and cold data via data distribution circuitry on a solid-state drive controller.

[0036] First refer to Figure 1 . Figure 1A block diagram of a system 100 according to an exemplary embodiment is shown. For example, the system can be any computer system, such as a tower server, server platform, server, desktop computer, portable computer, notebook computer, tablet computer, smartphone, etc. System 100 includes a host 102 and a solid-state drive 104. The host includes one or more microprocessors and one or more host buffers / memories. Solid-state drive 104 includes a solid-state drive controller 106, a magnetoresistive random access memory 108, and a NAND memory 110. The magnetoresistive random access memory 108 is coupled to the solid-state drive controller 106 in parallel with the NAND memory 110. In some embodiments, solid-state drive 104 also includes dynamic random access memory 112. Solid-state drive controller 106 includes computing circuitry 120, a solid-state drive data buffer 122, data distribution circuitry 124, and a magnetoresistive random access memory controller 126.

[0037] Magnetoresistive random access memory 108 is configured to store / save data before the solid-state drive controller 106 determines whether to store data in magnetoresistive random access memory 108, NAND memory 110, or, in some cases, dynamic random access memory 112. For example, host 102 may send data to solid-state drive 104 for storage. After receiving data from host 102, the solid-state drive controller stores it in solid-state drive data buffer 122, then retrieves the data from solid-state drive data buffer 112 and writes the data to magnetoresistive random access memory 108 via magnetoresistive random access memory controller 126.

[0038] Solid-state drive controller 106 is configured to use data distribution circuitry 124 to determine where to store data. If data is to be stored in NAND memory 110, solid-state drive controller 106 reads data from magnetoresistive random access memory 108 and stores the data in NAND 110 via magnetoresistive random access memory controller 126. Solid-state drive controller 106 also erases data from magnetoresistive random access memory 106 via magnetoresistive random access memory controller 126. If it is determined that data is to be stored in magnetoresistive random access memory, solid-state drive controller 106 retains the data in magnetoresistive random access memory 108. In some embodiments, when data is to be stored in dynamic random access memory 112, solid-state drive controller 106 reads data from magnetoresistive random access memory 108 and stores the data in dynamic random access memory 112 via magnetoresistive random access memory controller 126. The solid-state drive controller 106 also erases data from the magnetoresistive random access memory 108 via the magnetoresistive random access memory controller 126.

[0039] After the solid-state drive controller 106 stores data from the host to the destination (i.e., magnetoresistive random access memory 108, NAND memory 110, or dynamic random access memory 112), the solid-state drive controller is also configured to record the physical address of the data in the magnetoresistive random access memory 108, NAND memory 110, or dynamic random access memory 112 in an addressing table. This can speed up data read operations after quickly identifying the physical address of the data. In some embodiments, the addressing table may be stored in the magnetoresistive random access memory 108 for quick lookup by the solid-state drive controller 106. The addressing table is continuously updated to include new addresses for new data and data migrated between the magnetoresistive random access memory 108 and the NAND memory 110. The size of the addressing table can increase and become quite large. In some embodiments, when the address table size increases, in order to leave sufficient space in the magnetoresistive random access memory 108 to store hot host data / system data, the solid-state drive controller 106 may migrate the address table to dynamic random access memory 112 or NAND memory 110. In some embodiments, changes to the address table may first be stored in the magnetoresistive random access memory 108 and migrated to dynamic random access memory 112 or NAND memory 110 at a specific frequency.

[0040] During a read operation, the solid-state drive controller 106 receives a read command from the host 102 to read certain data. The solid-state drive controller 106 then looks up the address table through data allocation circuitry to determine whether the data is stored in the magnetoresistive random access memory 108, the NAND flash memory 110, or the dynamic random access memory 112. When data is stored in the magnetoresistive random access memory 108, the solid-state drive controller 106 retrieves the data from the magnetoresistive random access memory 108 and stores it in the solid-state drive data buffer 122. When data is stored in the NAND flash memory 110, the solid-state drive controller 106 retrieves the data from the NAND flash memory 110 and stores it in the solid-state drive data buffer 122. Then, the solid-state drive controller 106 retrieves the data from the solid-state drive data buffer 122 and sends the requested data to the host 102.

[0041] After receiving a read command for reading data from host 102, solid-state drive controller 106 determines whether the number of times host 102 accesses the data within a certain period exceeds a threshold. If the number of times host 102 accesses the data within a certain period exceeds the threshold, solid-state drive controller 106 can determine that the data is "hot," meaning that host 102 frequently requests access to the data. To allow host 102 to access the data quickly, solid-state drive controller 106 may store the data in magnetoresistive random access memory 108, as its response time is typically faster than NAND memory. In some embodiments, after solid-state drive controller 106 determines that the data is "hot," it also determines whether the data is stored in magnetoresistive random access memory 108 by, for example, looking up the physical address of the data in an addressing table. If the data is stored in magnetoresistive random access memory 108, solid-state drive controller 106 takes no further action and retains the data in magnetoresistive random access memory 108. If data is stored in NAND memory 110 (or dynamic random access memory 112), the solid-state drive controller 106 migrates the data from NAND memory 110 to magnetoresistive random access memory 108, erases the data from NAND memory 110, and updates the physical address of the data in the addressing table. The solid-state drive controller 106 can be configured to perform the above actions whenever it receives a read access request from the host 102.

[0042] In some embodiments, to consider the data stored in the solid-state drive 104 as a whole, the solid-state drive controller 106 may examine all data stored in the magnetoresistive random access memory 108 and the NAND memory 110 (and / or dynamic random access memory 112, if the dynamic random access memory 112 stores any host data) to identify “hot” and “cold” data. In some embodiments, the solid-state drive controller 106 uses data allocation circuitry 124 to determine whether the data is “hot” or “cold.” For example, data allocation circuitry 124 calculates the read access frequency of each logic block in the magnetoresistive random access memory 108 and the NAND memory 110. Furthermore, data allocation circuitry 124 selects a threshold frequency based on the storage capacity of the magnetoresistive random access memory 108. For example, when the storage capacity of the magnetoresistive random access memory 108 is relatively large, data allocation circuitry 124 selects a relatively low threshold frequency to store more hot data in the magnetoresistive random access memory 108. Conversely, when the storage capacity of the magnetoresistive random access memory 108 is relatively small, the data allocation circuit 124 selects a relatively high threshold frequency to avoid storing too much hot data in the magnetoresistive random access memory 108, which could hinder the normal operation of the magnetoresistive random access memory 108 by the solid-state drive controller 106. Other methods for selecting the threshold frequency can be considered. For example, the data allocation circuit 124 uses the average access frequency of all logic blocks as the threshold frequency. In this embodiment, data with an access frequency not exceeding the average access frequency is considered cold data and is to be stored in the NAND memory 110, while data with an access frequency exceeding the average access frequency is considered hot data and is to be stored in the magnetoresistive random access memory 108.

[0043] After determining / selecting the threshold frequency, the data allocation circuit 124 determines whether the read access frequency of each logic block on the magnetoresistive random access memory 108 and the NAND memory 110 exceeds the threshold frequency. When the read access frequency of a logic block on the magnetoresistive random access memory 108 does not exceed the threshold frequency (i.e., cold data), the data allocation circuit 124 migrates the data of that logic block stored in the magnetoresistive random access memory 108 to the NAND memory 110. When the read access frequency of a logic block on the magnetoresistive random access memory 108 exceeds the threshold frequency (i.e., hot data), the data allocation circuit 124 takes no further action and retains the data in the magnetoresistive random access memory 108. When the read access frequency of a logic block on the NAND memory 110 does not exceed the threshold frequency (i.e., cold data), the data allocation circuit 124 takes no further action and retains the data in the NAND memory 110. When the read access frequency of a logic block on NAND memory 110 exceeds a threshold frequency (i.e., hot data), data allocation circuit 124 migrates the data of that logic block stored in NAND memory 110 to magnetoresistive random access memory 108. These operations allow host 102 to access host data quickly, reducing access latency and improving system efficiency.

[0044] In some embodiments, the data distribution circuitry 124 of the solid-state drive controller 106 includes a machine learning model for determining whether data is hot data and where to store the data. (Reference) Figure 2 . Figure 2 A block diagram illustrating a data allocation circuit 124 according to an exemplary embodiment and its interaction with a magnetoresistive random access memory 108 and a NAND memory 110 is shown. The data allocation circuit 124 includes a machine learning model 202 for determining whether data is hot data and whether to store the data in the magnetoresistive random access memory 108 or the NAND memory 110. The machine learning model 202 can be trained using initial training samples and training samples generated by the data allocation circuit 122 when processing prior read commands (read access requests) from the host 102. As training is performed with an increasing number of training samples, the accuracy of the machine learning model 202 in making data allocation decisions (e.g., where to store data) gradually improves.

[0045] Machine learning model 202 includes a data allocation engine 202a and a data migration engine 202b. Data allocation engine 202a is configured to determine whether to store data in magnetoresistive random access memory 108 or in NAND memory 110. Data migration engine 202b is configured to determine whether to migrate data from magnetoresistive random access memory 108 to NAND memory 110 or vice versa.

[0046] The data allocation circuit 124 includes other functional blocks, such as a current state observation block 204 configured to observe the current state of the machine learning model 202. Upon receiving a read command from the host 102, the current state observation block 204 obtains the current / latest model parameters of the machine learning model 202 and inputs them into the data allocation engine 202a of the machine learning model 202. The read command also triggers the machine learning model 202 to calculate the read access frequency of the data requested by the read command. The data read access frequency and the current state of the machine learning model 202 are input into the data allocation engine 202a to determine whether to store the data in magnetoresistive random access memory (MRAM) or NAND flash memory, in order to maximize data access speed or minimize data access latency. The determination result of the data allocation engine 202a is provided to the data migration engine 202b to determine whether to migrate data between MRAM and NAND flash memory. For example, the data allocation engine 202a determines that the data is hot data and should be stored in MRAM 108. This result is sent to the data migration engine 202b. The data migration engine 202b looks up the address table to determine where the data is currently stored. For example, if the data is currently stored in NAND memory 110, which is inconsistent with the determination from the data allocation engine 202a, the data migration engine 202b decides to migrate the data from NAND memory 110 to magnetoresistive random access memory 108, and erases the data from NAND memory 110 after the migration is complete. Alternatively, if the data is currently stored in magnetoresistive random access memory 108, which is consistent with the determination from the data allocation engine 202a, the data migration engine 202b may decide to retain the data in magnetoresistive random access memory 108 and take further action on that data.

[0047] In some embodiments, data allocation engine 202a determines that data is cold data and should be stored in NAND memory 110. This result is sent to data migration engine 202b. Data migration engine 202b can look up the address table to know where the data is currently stored. For example, if the data is currently stored in NAND memory 110, consistent with the determination from data allocation engine 202a, then data migration engine 202b decides to retain the data in NAND memory 110 and takes further action on the data. Alternatively, if the data is currently stored in magnetoresistive random access memory 108, inconsistent with the determination from data allocation engine 202a, then data migration engine 202b can decide to migrate the data from magnetoresistive random access memory 108 to NAND memory 110, and erase the data from magnetoresistive random access memory 110 after the migration is complete.

[0048] Data migration decisions from data migration engine 202b are provided to data migration decision block 206 to implement the data migration decisions as described above. Although not shown, it is... Figure 1 As shown, the data migration decision is transmitted to the magnetoresistive random access memory 108 and the NAND memory 110 via the magnetoresistive random access memory controller 126.

[0049] In some embodiments, the magnetoresistive random access memory 108 and the NAND memory 110 are configured to report data access latency to the data distribution circuitry 124. For example, each of the magnetoresistive random access memory 110 and the NAND memory 110 is configured to wait for the requested data to be fetched into the solid-state drive data buffer 122 (e.g., ...). Figure 1 A timestamp is recorded when the data allocation circuit 124 (as shown in the diagram) is accessed. The timestamp is reported to the read latency feedback block 208 of the data allocation circuit 124 to determine the time difference between the time delay between the moment a read command is received and the moment the requested data is retrieved. In another example, the moment the read command is received can be sent to the magnetoresistive random access memory 108 and the NAND memory 110 to allow the magnetoresistive random access memory 108 and the NAND memory 110 to locally determine the access latency. The magnetoresistive random access memory 108 and the NAND memory 110 can then report the access latency to the read latency feedback block 208 of the data allocation circuit 124. The methods for obtaining read latency feedback are not limited to these examples. Other currently known or later developed methods for calculating and reporting access latency are also within the scope of this disclosure.

[0050] In some embodiments, the machine learning model 202 is implemented using a neural network. For example, the neural network employs a reinforcement learning algorithm. Figure 3A block diagram illustrating a data allocation circuit 124 according to an exemplary embodiment and its interaction with a magnetoresistive random access memory 108 and a NAND memory 110 is shown. Figure 3 As shown, the data distribution circuit 124 includes a current state observation block 302, an actor net 304, a critic net 306, and a machine learning sample library 308. The current state observation block 302 is similar to... Figure 2 The current state observation block 204 is configured to observe the current states of the participant network 304 and the commentator network 306. When a read command is received from the host 102, the current state observation block 302 obtains the current parameters of the participant network 304 and the commentator network 306. The current state observation block 302 also shares its current state with the machine learning sample library 308 for use by the machine learning sample library 308 in generating machine learning / training samples.

[0051] Participant network 304 and commentator network 306 are trained using samples from machine learning sample library 308. Training samples can be imported from another library or generated locally in data allocation circuit 124 based on feedback from magnetoresistive random access memory 108 and NAND memory 110, as will be illustrated herein. Participant network 304 is configured to determine actions to store data into magnetoresistive random access memory 108 and NAND memory 110. Participant network 304 receives read commands, its current state (e.g., current parameters), and the output of commentator network 306 as inputs, and outputs actions to magnetoresistive random access memory 108 and NAND memory 110. For example, the action may involve reading data from magnetoresistive random access memory 108 or NAND memory 110 and migrating the data from magnetoresistive random access memory 108 to NAND memory 110, or migrating the data from NAND memory 110 to magnetoresistive random access memory 108, or retaining the data in magnetoresistive random access memory 108 or NAND memory 110. After the action is performed in magnetoresistive random access memory 108 and NAND memory 110, magnetoresistive random access memory 108 and NAND memory 110 are configured to report feedback indicating the access latency associated with the read access to the reviewer network 306 and the machine learning sample library 308. In some embodiments, during the generation of the action, participant network 304 is configured to calculate the read access frequency of the data requested by the read command and provide the read access frequency to the machine learning sample library 308.

[0052] Commenter network 306 takes as input the current state of commenter network 306 from current state observation block 302, the actions taken by participant network 304, and feedback from magnetoresistive random access memory 108 and NAND memory 110 to generate comments. Commenter network 306 shares the generated comments with participant network 304 and machine learning sample library 308. Based on the outputs from participant network 304 and commenter network 306 and the feedback from magnetoresistive random access memory 108 and NAND memory 110, machine learning sample library 308 generates machine learning samples. Machine learning samples include the data read access frequency, the current state of participant network 304 and commenter network 306 (e.g., machine learning models), the actions generated by participant network 304, and the read access latency of read commands. Machine learning sample library 308 can store one or more machine learning samples (e.g., machine learning sample 1, 2, ..., i).

[0053] Figure 4 A flowchart illustrating a method 400 for processing write commands in a solid-state drive according to an exemplary embodiment is shown. The solid-state drive includes magnetoresistive random access memory, NAND memory, and a solid-state drive controller. Method 400 may be generated by the solid-state drive controller (e.g., Figure 1 The solid-state drive controller executes the operation. In step 402, the solid-state drive controller receives a write command from the host, which includes data to be written to the solid-state drive. The data may be host data used by the host for various purposes. In some embodiments, data is retrieved from a host buffer and sent to the solid-state drive. In step 404, the solid-state drive controller stores the data in a solid-state drive data buffer (e.g., ...). Figure 1 (Solid-state drive data buffer 122). In step 406, the solid-state drive controller retrieves data from the solid-state drive data buffer and writes the data to the magnetoresistive random access memory. In the art of this disclosure, whenever the solid-state drive controller receives data to be stored in the solid-state drive, it stores the data in the magnetoresistive random access memory before deciding which storage device of the solid-state drive to store the data.

[0054] In step 408, the solid-state drive controller determines whether to store the data in magnetoresistive random access memory (MRAM) or NAND flash memory. If the solid-state drive controller determines that the data will be stored in MRAM, in step 410, the solid-state drive controller retains the data in MRAM and takes no further action on the data. If the solid-state drive controller determines that the data will be stored in NAND flash memory, in step 412, the solid-state drive controller retrieves / reads the data from MRAM. In step 414, the solid-state drive controller writes the data to NAND flash memory. In step 416, the solid-state drive controller erases the data from MRAM to free up storage space in MRAM. In step 418, the solid-state drive controller records the physical address of the first data in either MRAM or NAND flash memory in the address table. In step 420, the solid-state drive controller stores the address table in the solid-state drive's MRAM or DRAM.

[0055] Figure 5 A flowchart illustrating a method 500 for processing a read command in a solid-state drive according to an exemplary embodiment is shown. The solid-state drive includes magnetoresistive random access memory, NAND memory, and a solid-state drive controller. Method 500 may be generated by the solid-state drive controller (e.g., Figure 1 The solid-state drive controller (SSD) executes the following steps: In step 502, the SSD receives a read command from the host for reading data. In step 504, the SSD looks up the address table to find the physical address of the requested data. The address table is configured to store a mapping between multiple data items and their corresponding physical addresses in magnetoresistive random access memory (MRAM) or NAND flash memory. In step 506, the SSD determines whether the data is stored in MRAM or NAND flash memory based on the address table lookup. If the data is stored in NAND flash memory, the SSD retrieves the data from the NAND flash memory in step 508. If the data is stored in MRAM, the SSD retrieves the data from MRAM in step 510. In step 512, the SSD stores the data retrieved from MRAM or NAND flash memory into the SSD data buffer. In step 514, the SSD retrieves the data from the SSD data buffer and sends the data to the host.

[0056] Figure 6A flowchart illustrating a method 600 for migrating data to a solid-state drive based on data popularity, according to an exemplary embodiment, is shown. The solid-state drive includes magnetoresistive random access memory, NAND memory, and a solid-state drive controller. Method 600 can be performed by the solid-state drive controller (e.g., Figure 1 The solid-state drive controller (SSD) performs the following steps. The SSD maintains a counter for the data. In step 602, after a read access to the data, the SSD updates the counter by incrementing it. In step 604, the SSD determines whether the number of read accesses to the data by the host within a given time period exceeds a threshold. This operation determines the frequency at which the host requests to read the data. If the number of read accesses to the data by the host within a given time period does not exceed the threshold, the SSD determines the data is "cold," and in step 606, determines whether the data is stored in magnetoresistive random access memory (MRAM). If the cold data is not stored in MRAM, in step 608, the SSD retains the data in its current storage location (e.g., in NAND memory). If the cold data is stored in MRAM, in step 610, the SSD migrates the data from MRAM to NAND memory. To improve the efficiency of the SSD, less frequent data is removed from MRAM to free up space for more frequent data. In step 612, the solid-state drive controller erases the data from the magnetoresistive random access memory. In step 614, the solid-state drive controller updates the physical address of the data now stored in the NAND memory.

[0057] If it is determined that the number of read accesses to data by the host exceeds a threshold within a certain period of time, the solid-state drive controller determines that the data is "hot" and, in step 616, determines whether the data is stored in NAND memory. If the hot data is not stored in NAND memory, in step 608, the solid-state drive controller retains the data at its current storage location (e.g., in magnetoresistive random access memory). If the hot data is stored in NAND memory, in step 618, the solid-state drive controller migrates the data from NAND memory to magnetoresistive random access memory. Because the read latency of magnetoresistive random access memory is lower than that of NAND memory, this operation prepares the hot data for faster access next time. In step 620, the solid-state drive controller erases the data from NAND memory. In step 622, the solid-state drive controller updates the physical address of the data now stored in magnetoresistive random access memory. Method 600 can be executed each time the solid-state drive controller receives a read command from the host. Method 600 allows a solid-state drive controller to migrate data between magnetoresistive random access memory and NAND memory based on the frequency at which the data is accessed, in order to reduce access latency and improve the efficiency of a system with solid-state drives and a host.

[0058] Figure 7 A flowchart illustrating a method 700 for migrating data in a solid-state drive based on data popularity according to an exemplary embodiment is shown. The solid-state drive includes magnetoresistive random access memory, NAND memory, and a solid-state drive controller. Method 700 may be performed by the solid-state drive controller (e.g., Figure 1 The solid-state drive controller (e.g., via) executes the process. In step 702, the solid-state drive controller (e.g., via...) Figure 1 The computing circuit 120 calculates the read access frequency of each logic block in the magnetoresistive random access memory (MRAM). The solid-state drive controller can select a threshold frequency based on the storage capacity of the MRAM. In step 704, the solid-state drive controller determines whether the read access frequency of each logic block in the MRAM exceeds the threshold frequency. If the read access frequency of the logic block in the MRAM exceeds the threshold frequency, in step 706, the solid-state drive controller retains the data stored in that logic block in the MRAM. If the read access frequency of the logic block in the MRAM does not exceed the threshold frequency, in step 708, the solid-state drive controller migrates the data stored in that logic block in the MRAM to the NAND flash memory. These operations migrate data that was frequently accessed by the host but is now accessed less frequently from the MRAM to the NAND flash memory, freeing up space in the MRAM for other data.

[0059] Figure 8 A flowchart illustrating a method 800 for migrating data in a solid-state drive based on data popularity according to an exemplary embodiment is shown. The solid-state drive includes magnetoresistive random access memory, NAND memory, and a solid-state drive controller. Method 800 may be performed by the solid-state drive controller (e.g., Figure 1 The solid-state drive controller (e.g., via) executes. In step 802, the solid-state drive controller (e.g., via) Figure 1 The computing circuit 120 calculates the read access frequency of each logic block in the NAND memory. The solid-state drive controller can select a threshold frequency based on the storage capacity of the magnetoresistive random access memory. In step 804, the solid-state drive controller determines whether the read access frequency of each logic block on the NAND memory exceeds the threshold frequency. If the read access frequency of the logic block on the NAND memory does not exceed the threshold frequency, then in step 806, the solid-state drive controller retains the data stored in that logic block in the NAND memory. If the read access frequency of the logic block on the NAND memory exceeds the threshold frequency, then in step 808, the solid-state drive controller migrates the data stored in that logic block in the NAND memory to the magnetoresistive random access memory. These operations migrate data that was previously accessed less frequently by the host but has become more frequently accessed by the host from the NAND memory to the magnetoresistive random access memory to reduce future data access latency.

[0060] Figure 9 A flowchart illustrating a method 900 for managing storage in a solid-state drive according to an exemplary embodiment is shown. The solid-state drive includes magnetoresistive random access memory, NAND memory, and a solid-state drive controller. Method 900 may be performed by the solid-state drive controller (e.g., Figure 1 The solid-state drive controller (SSD) performs the operation. The SSD controller includes a machine learning model for managing the storage of the SSD. The machine learning model includes a data allocation engine and a data migration engine. In step 902, when a read command for reading data stored on the SSD is received from the host, the machine learning model calculates the data read access frequency. In step 904, the machine learning model obtains its current state. In step 906, the machine learning model inputs the data read access frequency and its current state to the data allocation engine to determine whether the data should be stored in magnetoresistive random access memory (MRAM) or NAND flash memory, and generates a determination result. The determination result indicates whether the data should be stored in MRAM or NAND flash memory based on the data read access frequency.

[0061] In step 908, the machine learning model inputs the determination result from the data allocation engine into the data migration engine, which then determines whether to migrate data between magnetoresistive random access memory (MRAM) and NAND flash memory. For example, if data is to be stored in MRAM but is currently stored in NAND flash memory, the data migration engine outputs a determination indicating that the data should be migrated from NAND flash memory to MRAM. If data is to be stored in MRAM and is currently stored in MRAM, the data migration engine outputs a determination indicating that the data should remain in MRAM. In step 910, the machine learning model calculates the read access latency for accessing data stored on the solid-state drive. In step 912, the machine learning model calculates machine learning samples, which include the data read access frequency, the current state of the machine learning model, the output of the data migration engine, and the read access latency. When the process returns to step 902 after step 912, the machine learning model can generate machine learning samples each time a read command is received from the host.

[0062] In the technology disclosed herein, magnetoresistive random access memory can provide high write / read bandwidth and is used as a write buffer to improve the overall performance of the solid-state drive. When using quad-cell NAND as data storage, the solid-state drive can achieve high capacity and high performance.

[0063] The techniques disclosed herein (e.g., a hybrid system of magnetoresistive random access memory and quad-cell NAND) can reduce the design complexity of power-loss protection. Since magnetoresistive random access memory is non-volatile, power-loss backup is no longer required.

[0064] In the technology disclosed herein, by including data distribution circuitry in the solid-state drive controller, data can be separated and stored in different memory sections, such as magnetoresistive random access memory (MRAM) or NAND flash memory, and the system can automatically adjust the data placement location, thereby improving the system's memory access latency. By migrating hot data from NAND flash memory to MRAM, system garbage collection time is reduced, the write amplification factor (WAF) of the solid-state drive is lowered, and overall performance is improved.

[0065] This technology provides a solid-state driver architecture for a hybrid memory / storage system with magnetoresistive random access memory and NAND, where the magnetoresistive random access memory is used as a write buffer and cache to store hot data and system metadata.

[0066] In some embodiments, this technology provides a data placement path in which host data is first written to magnetoresistive random access memory (MRAM) and then to NAND flash memory. This approach addresses the power loss issues of NAND flash memory and improves the access speed and capacity of solid-state drives.

[0067] In some embodiments, this technology provides a data distribution circuit that uses a machine learning model to make decisions about where data is placed. Hot data is held on magnetoresistive random access memory, while cold data is held on NAND flash memory.

[0068] In some embodiments, this technology provides a data allocation engine that uses data access frequency as input and read latency as feedback to output a decision about whether data is written to magnetoresistive random access memory or NAND flash memory.

[0069] The foregoing description of this disclosure is provided for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. The breadth and scope of this disclosure should not be limited to any of the exemplary embodiments described above. Many modifications and variations will be apparent to those skilled in the art. These modifications and variations include any related combinations of the disclosed features. The embodiments were chosen and described in order to best explain the principles of this disclosure and its practical application, thereby enabling others skilled in the art to understand the various embodiments of this disclosure and the various modifications suitable for the particular intended use. The scope of this disclosure is defined by the foregoing claims and their equivalents.

Claims

1. A solid-state drive, comprising: Magnetoresistive random access memory; NAND memory; as well as A solid-state drive controller coupled to the magnetoresistive random access memory and the NAND memory, wherein the solid-state drive controller includes: A data allocation circuit is configured to determine whether to store data into one of the magnetoresistive random access memory or the NAND memory; A magnetoresistive random access memory controller, coupled to the magnetoresistive random access memory, is configured to read data from the magnetoresistive random access memory or write data to the magnetoresistive random access memory. The solid-state drive controller is configured as follows: Receive the first data from the host; The first data is stored in the solid-state drive data buffer; The first data is extracted from the solid-state drive data buffer and written into the magnetoresistive random access memory through the magnetoresistive random access memory controller. Based on the characteristics of the first data, the data allocation circuit determines whether to store the first data in the magnetoresistive random access memory or in the NAND flash memory; and In response to determining that the first data is stored in the NAND memory, the first data is read from the magnetoresistive random access memory, the first data is written to the NAND memory, and the first data is erased from the magnetoresistive random access memory.

2. The solid-state driver according to claim 1, wherein, The solid-state drive controller is also configured to retain the first data in the magnetoresistive random access memory in response to determining that the first data will be stored in the magnetoresistive random access memory.

3. The solid-state driver according to claim 2, wherein, The solid-state drive controller is also configured to record the physical address of the first data in the magnetoresistive random access memory or the NAND memory in an addressing table.

4. The solid-state driver according to claim 3, wherein, The solid-state drive controller is also configured to store the addressing table in the magnetoresistive random access memory or dynamic random access memory coupled to the solid-state drive controller.

5. The solid-state driver according to claim 3, wherein, The solid-state driver controller is also configured to: Receive a read command from the host for reading the second data; The data allocation circuit uses the address table to determine whether the second data is stored in the magnetoresistive random access memory or in the NAND memory. In response to determining that the second data is stored in the magnetoresistive random access memory, the second data is retrieved from the magnetoresistive random access memory and the second data is stored in the solid-state drive data buffer; In response to determining that the second data is stored in the NAND memory, the second data is retrieved from the NAND memory and the second data is stored in the solid-state drive data buffer; as well as The second data is extracted from the solid-state drive data buffer and sent to the host.

6. The solid-state driver according to claim 5, wherein, The solid-state driver controller is also configured to: Determine whether the number of times the host accesses the second data within a certain period of time exceeds a threshold; In response to the host accessing the second data more than a threshold number of times within a certain period of time and in response to determining that the second data is stored in the NAND memory, the second data is migrated from the NAND memory to the magnetoresistive random access memory, the second data is erased from the NAND memory, and the physical address of the second data is updated in the addressing table.

7. The solid-state driver according to claim 1, wherein, The data distribution circuit is configured as follows: Calculate the read access frequency of each logic block in the magnetoresistive random access memory and the NAND memory; The threshold frequency is selected based on the storage capacity of the magnetoresistive random access memory. Determine whether the read access frequency of each logic block in the magnetoresistive random access memory and the NAND memory exceeds the threshold frequency; In response to determining that the read access frequency of the logic block in the magnetoresistive random access memory does not exceed the threshold frequency, the data of the logic block stored in the magnetoresistive random access memory is migrated to the NAND memory. as well as In response to determining that the read access frequency of a logic block in the NAND memory exceeds the threshold frequency, the data of that logic block stored in the NAND memory is migrated to the magnetoresistive random access memory.

8. The solid-state driver according to claim 1, wherein, The data allocation circuitry includes a machine learning model, which comprises a data allocation engine and a data migration engine. The machine learning model is configured to, in response to receiving a read command from the host for reading second data stored in the solid-state drive, execute: Calculate the read access frequency of the second data; Obtain the current state of the machine learning model; The read access frequency of the second data and the current state of the machine learning model are input into the data allocation engine so that the data allocation engine can determine whether the second data should be stored in the magnetoresistive random access memory or in the NAND memory and generate a determination result. The determination result of the data allocation engine is input into the data migration engine so that the data migration engine can determine whether to migrate the second data between the magnetoresistive random access memory and the NAND memory. Calculate the read access latency for accessing the second data stored in the solid-state drive; as well as Generate machine learning samples, which include the read access frequency of the second data, the current state of the machine learning model, the output of the data migration engine, and the read access latency.

9. The solid-state driver according to claim 1, wherein, The solid-state drive controller is also configured to flush all data in the solid-state drive data buffer to the magnetoresistive random access memory in response to a power failure.

10. An apparatus comprising a host and a solid-state drive, wherein the solid-state drive comprises: Magnetoresistive random access memory; NAND memory; as well as A solid-state drive controller coupled to the magnetoresistive random access memory and the NAND memory, wherein the solid-state drive controller includes: A data allocation circuit is configured to determine whether to store data into one of the magnetoresistive random access memory or the NAND memory; A magnetoresistive random access memory controller, coupled to the magnetoresistive random access memory, is configured to read data from the magnetoresistive random access memory or write data to the magnetoresistive random access memory. The solid-state drive controller is configured as follows: Receive the first data from the host; The first data is stored in the solid-state drive data buffer; The first data is extracted from the solid-state drive data buffer and written into the magnetoresistive random access memory through the magnetoresistive random access memory controller. Based on the characteristics of the first data, the data allocation circuit determines whether to store the first data in the magnetoresistive random access memory or in the NAND flash memory; and In response to determining that the first data is stored in the NAND memory, the first data is read from the magnetoresistive random access memory, the first data is written to the NAND memory, and the first data is erased from the magnetoresistive random access memory.

11. The device according to claim 10, wherein, The solid-state drive controller is also configured to retain the first data in the magnetoresistive random access memory in response to determining that the first data will be stored in the magnetoresistive random access memory.

12. The device according to claim 11, wherein, The solid-state drive controller is also configured to record the physical address of the first data in the magnetoresistive random access memory or the NAND memory in an addressing table.

13. The device according to claim 12, wherein, The solid-state drive controller is also configured to store the addressing table in the magnetoresistive random access memory or dynamic random access memory coupled to the solid-state drive controller.

14. The device according to claim 12, wherein, The solid-state driver controller is also configured to: Receive a read command from the host for reading the second data; The data allocation circuit uses the address table to determine whether the second data is stored in the magnetoresistive random access memory or in the NAND memory. In response to determining that the second data is stored in the magnetoresistive random access memory, the second data is retrieved from the magnetoresistive random access memory and the second data is stored in the solid-state drive data buffer; In response to determining that the second data is stored in the NAND memory, the second data is retrieved from the NAND memory and the second data is stored in the solid-state drive data buffer; as well as The second data is extracted from the solid-state drive data buffer and sent to the host.

15. The device according to claim 14, wherein, The solid-state driver controller is also configured to: Determine whether the number of times the host accesses the second data within a certain period of time exceeds a threshold; In response to the host accessing the second data more than a threshold number of times within a certain period of time and in response to determining that the second data is stored in the NAND memory, the second data is migrated from the NAND memory to the magnetoresistive random access memory, the second data is erased from the NAND memory, and the physical address of the second data is updated in the addressing table.

16. The device according to claim 10, wherein, The data distribution circuit is configured as follows: Calculate the read access frequency of each logic block in the magnetoresistive random access memory and the NAND memory; The threshold frequency is selected based on the storage capacity of the magnetoresistive random access memory. Determine whether the read access frequency of each logic block in the magnetoresistive random access memory and the NAND memory exceeds the threshold frequency; In response to determining that the read access frequency of the logic block in the magnetoresistive random access memory does not exceed the threshold frequency, the data of the logic block stored in the magnetoresistive random access memory is migrated to the NAND memory. as well as In response to determining that the read access frequency of a logic block in the NAND memory exceeds the threshold frequency, the data of that logic block stored in the NAND memory is migrated to the magnetoresistive random access memory.

17. The device according to claim 10, wherein, The data allocation circuitry includes a machine learning model, which comprises a data allocation engine and a data migration engine. The machine learning model is configured to, in response to receiving a read command from the host for reading second data stored in the solid-state drive, execute: Calculate the read access frequency of the second data; Obtain the current state of the machine learning model; The read access frequency of the second data and the current state of the machine learning model are input into the data allocation engine so that the data allocation engine can determine whether the second data should be stored in the magnetoresistive random access memory or in the NAND memory and generate a determination result. The determination result of the data allocation engine is input into the data migration engine so that the data migration engine can determine whether to migrate the second data between the magnetoresistive random access memory and the NAND memory. Calculate the read access latency for accessing the second data stored in the solid-state drive; as well as Generate machine learning samples, which include the read access frequency of the second data, the current state of the machine learning model, the output of the data migration engine, and the read access latency.

18. The device according to claim 10, wherein, The solid-state drive controller is also configured to flush all data in the solid-state drive data buffer to the magnetoresistive random access memory in response to a power failure.

19. A method of operating a solid-state drive, the solid-state drive including a magnetoresistive random access memory, a NAND flash memory, and a solid-state drive controller, the solid-state drive controller being coupled to the magnetoresistive random access memory and the NAND flash memory, the method of operating the solid-state drive including: Receive first data from the host via the solid-state drive controller; The first data is stored in the solid-state drive data buffer via the solid-state drive controller; The first data is extracted from the solid-state drive data buffer and written to the magnetoresistive random access memory via the solid-state drive controller. Based on the characteristics of the first data, the solid-state drive controller determines whether to store the first data in the magnetoresistive random access memory or in the NAND memory. as well as In response to determining that the first data should be stored in the NAND memory, the solid-state drive controller reads the first data from the magnetoresistive random access memory, writes the first data into the NAND memory, and erases the first data from the magnetoresistive random access memory.

20. The operating method according to claim 19, wherein, The solid-state drive controller includes a machine learning model, wherein the machine learning model includes a data allocation engine and a data migration engine, and the machine learning model is configured to execute, in response to receiving a read command from the host for reading second data stored in the solid-state drive: Calculate the read access frequency of the second data; Obtain the current state of the machine learning model; The read access frequency of the second data and the current state of the machine learning model are input into the data allocation engine so that the data allocation engine can determine whether the second data should be stored in the magnetoresistive random access memory or in the NAND memory and generate a determination result. The determination result of the data allocation engine is input into the data migration engine so that the data migration engine can determine whether to migrate the second data between the magnetoresistive random access memory and the NAND memory. Calculate the read access latency for accessing the second data stored in the solid-state drive; as well as Generate machine learning samples, which include the read access frequency of the second data, the current state of the machine learning model, the output of the data migration engine, and the read access latency.

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