Dormancy and wake-up system and method for enterprise-level solid state disk

By co-designing non-volatile cache units and hardware state machines, combined with ultra-low power wake-up detection circuits, ultra-low power consumption and fast wake-up of enterprise-grade solid-state drives are achieved, solving the problems of high power consumption and long wake-up latency in traditional solutions, and meeting the energy efficiency requirements of edge computing and data centers.

CN121523748APending Publication Date: 2026-02-13成都芯忆联信息技术有限公司
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Patent Information

Application Number
CN202511673757.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-11-14
Publication Date
2026-02-13

AI Technical Summary

Technical Problem

Existing technologies struggle to simultaneously achieve ultra-low power consumption and fast wake-up in enterprise-grade solid-state drives. Traditional solutions suffer from high power consumption, long wake-up latency, and high cost.

Method used

It employs a non-volatile cache unit and a hardware state machine to work together, and achieves fast wake-up by only powering necessary circuits during sleep and using an ultra-low power wake-up detection circuit to listen for wake-up events, combined with the standard PCIe protocol.

Benefits of technology

It achieves a reduction in power consumption of enterprise-grade solid-state drives to below 100mW during hibernation and a wake-up latency to less than 1ms, resolving the technical contradiction between ultra-low power consumption and fast response, and meeting the energy efficiency requirements of edge computing and data centers.

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Abstract

The invention discloses a dormancy and awakening system and method of an enterprise-level solid state disk, and belongs to the technical field of power consumption management of the enterprise-level solid state disk. According to the system, a nonvolatile cache unit, an independent hardware state machine and an ultra-low power consumption wake-up detection circuit are integrated in a main controller. When entering the dormancy state, key data such as an FTL mapping table are stored in a nonvolatile cache, then the power management module cuts off power supply to the NAND flash memory and the main control core, and only the operation of the minimum circuit is maintained, so that the dormancy power consumption is reduced to be below 100mW; and during wakeup, the detection circuit identifies a physical layer signal to trigger rapid power-on, and the hardware state machine directly recovers the system state from the cache and bypasses the software initialization process, so that wakeup is completed and the NAND access capability is reconstructed within 1ms, and the industrial problem that ultra-low power consumption and rapid wakeup cannot be considered at the same time is effectively solved.
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