Dormancy and wake-up system and method for enterprise-level solid state disk

Abstract

The invention discloses a dormancy and awakening system and method of an enterprise-level solid state disk, and belongs to the technical field of power consumption management of the enterprise-level solid state disk. According to the system, a nonvolatile cache unit, an independent hardware state machine and an ultra-low power consumption wake-up detection circuit are integrated in a main controller. When entering the dormancy state, key data such as an FTL mapping table are stored in a nonvolatile cache, then the power management module cuts off power supply to the NAND flash memory and the main control core, and only the operation of the minimum circuit is maintained, so that the dormancy power consumption is reduced to be below 100mW; and during wakeup, the detection circuit identifies a physical layer signal to trigger rapid power-on, and the hardware state machine directly recovers the system state from the cache and bypasses the software initialization process, so that wakeup is completed and the NAND access capability is reconstructed within 1ms, and the industrial problem that ultra-low power consumption and rapid wakeup cannot be considered at the same time is effectively solved.

Description

Technical Field

[0001] This invention relates to the field of enterprise-level solid-state drive power management technology, and in particular to a hibernation and wake-up system and method for an enterprise-level solid-state drive. Background Technology

[0002] With the rise of edge computing, the Internet of Things (IoT), and green data centers, enterprise-grade solid-state drives (ESSDs) are facing increasingly stringent power consumption and performance constraints. In edge devices powered by solar energy or batteries (such as smart traffic cameras), SSDs are required to consume less than 100mW in sleep mode. In data centers, to optimize power usage efficiency (PUE), single-disk sleep power consumption needs to be reduced by more than 90% compared to traditional methods. Meanwhile, real-time applications such as industrial automation require SSDs to wake up from sleep mode with a latency of less than 1ms. These diverse and stringent requirements pose unprecedented challenges to ESSD power management technologies.

[0003] Currently, existing low-power solutions in the industry all have significant drawbacks, making it difficult to simultaneously meet the requirements of ultra-low power consumption and fast wake-up. For example, traditional sleep protocols (such as Intel DevSleep) rely on DRAM self-refresh and tantalum capacitors for data backup, resulting in sleep power consumption typically exceeding 500mW and wake-up latency exceeding 10ms. Furthermore, the large-capacity tantalum capacitors significantly increase hardware cost and size. Another capacitor-assisted fast wake-up solution, while utilizing supercapacitors for data backup, suffers from short capacitor cycle life, easy capacity decay, and insufficient wake-up latency (3-5ms). In addition, some software-optimized solutions preserve state by predicting idle periods, but this exacerbates NAND flash write wear, affecting device lifespan, and typically requires customized host drivers, resulting in poor compatibility with the standard NVMe ecosystem. Therefore, there is an urgent need in this field for a new solution that can fundamentally resolve the aforementioned technical contradictions. Summary of the Invention

[0004] The technical problem to be solved by this invention is: how to enable enterprise-grade solid-state drives to achieve ultra-low power consumption during hibernation while also achieving fast wake-up, thereby overcoming the technical contradiction that traditional solutions cannot balance ultra-low power consumption and fast response.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: a hibernation and wake-up system for an enterprise-level solid-state drive, comprising a main controller, a NAND flash memory array, and a power management module, and further comprising: A non-volatile cache unit, connected to the main controller, is used to persistently save critical runtime data when the system is powered off; The hardware state machine is integrated inside the main controller and is independent of the main controller's CPU core. It is composed of dedicated logic circuits and is used to manage the system state saving and restoration process. An ultra-low power wake-up detection circuit, which is physically connected to the power management module and the host interface, is used to listen for wake-up events in sleep mode. The system is configured as follows: During the hibernation phase, in response to the hibernation trigger condition, the main controller saves the current FTL mapping table and I / O command context to the non-volatile cache unit. Subsequently, the power management module cuts off the power supply to the NAND flash array and the main controller core circuit, and only maintains the power supply to the non-volatile cache unit, the hardware state machine and the wake-up detection circuit. During the wake-up recovery phase, after the wake-up detection circuit detects a valid wake-up signal, it triggers the power management module to restore power supply, and the hardware state machine takes over control, loading the system state data stored in the non-volatile cache unit into the corresponding hardware to directly rebuild the ability to access NAND flash memory.

[0006] Furthermore, the non-volatile cache unit is implemented by a non-volatile memory, which is selected from the group consisting of magnetic random access memory, phase change memory, and NorFlash powered by a supercapacitor.

[0007] Furthermore, the hibernation triggering conditions include: a custom hibernation command sent by the host through the NVMe management interface, or the I / O idle time detected by the system exceeding a preset threshold.

[0008] Furthermore, the ultra-low power wake-up detection circuit includes: An ultra-low power comparator is used to continuously monitor the signal level of the host interface physical link and compare it with a preset reference voltage threshold. A digital logic unit, which is connected to the output of the comparator, is used to perform logical judgments on the signals output by the comparator. A control logic unit, connected to the output of the digital logic unit, is used to generate an enable signal to the power management module when the logic determines that a valid wake-up event has occurred, so as to control the restoration of power supply.

[0009] Furthermore, the effective wake-up signal is a physical layer training sequence that is distinct from normal data communication, specifically an ordered set of Electrical Idle Exit defined by the PCIe protocol.

[0010] This invention also provides a hibernation and wake-up method for an enterprise-grade solid-state drive, applied to the system described above, comprising: The host sends a hibernation command to the solid-state drive through the NVMe management interface and works with the solid-state drive to complete the low-power state switching of the PCIe link; In response to the hibernation command, the solid-state drive saves critical runtime data to its internal non-volatile cache unit; After the data is saved, the power management module of the solid-state drive cuts off the power supply to its NAND flash array and the core circuit of the main controller, so that the solid-state drive enters an ultra-low power sleep state in which only the non-volatile cache unit, the hardware state machine integrated in the main controller and the ultra-low power wake-up detection circuit are powered. During the ultra-low power sleep state, the wake-up detection circuit continuously monitors the signals of the host interface physical link; When the host needs to wake up the solid-state drive, it sends a preset physical layer wake-up signal to the physical link; Upon detecting the physical layer wake-up signal, the wake-up detection circuit triggers the power management module to restore power supply to the NAND flash memory array and the main controller; and After the power supply is stabilized, the hardware state machine directly loads the system state data stored in the non-volatile cache unit into the corresponding hardware registers and memory space to rebuild the access capability to NAND flash memory.

[0011] Furthermore, the step of saving critical runtime data to its internal non-volatile cache unit includes: freezing the register state of the main controller through the hardware state machine, and compressing the I / O command context data in the dynamic random access memory before writing it into the non-volatile cache unit.

[0012] Furthermore, the hardware state machine directly loads the saved system state data into the corresponding hardware registers and memory space to rebuild the access capability to NAND flash memory, so as to complete the system state recovery and prepare to respond to I / O requests within 1 millisecond.

[0013] Furthermore, the total power consumption of the solid-state drive in the ultra-low power hibernation state is less than 100 milliwatts.

[0014] Furthermore, the total latency from the moment the wake-up detection circuit identifies the physical layer wake-up signal to the moment the solid-state drive completes state recovery and is able to respond to host I / O requests is less than 1 millisecond.

[0015] The beneficial effects of this invention are as follows: by using non-volatile cache units to persist critical data, and by having an independent hardware state machine and an ultra-low power wake-up detection circuit work together, power is supplied to only the minimum necessary circuits during hibernation, thereby significantly reducing the hibernation power consumption of enterprise-grade solid-state drives from hundreds of milliwatts in traditional solutions to below 100mW; at the same time, the system state is directly and quickly restored through the hardware state machine during wake-up, bypassing the lengthy software initialization process, and the wake-up latency from hibernation to full-function operation is greatly shortened from the traditional 10ms level to less than 1ms, fundamentally solving the core technical problem of the inability to balance ultra-low power consumption and fast wake-up. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 This is a block diagram of a hibernation and wake-up system for an enterprise-level solid-state drive according to an embodiment of the present invention; Figure 2 This is a diagram showing the hibernation and wake-up state transition of an enterprise-level solid-state drive according to an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that the descriptions involving "first," "second," etc., in this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Furthermore, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0020] like Figure 1As shown, an embodiment of the present invention is: a hibernation and wake-up system for an enterprise-grade solid-state drive, comprising a main controller, a NAND flash memory array, and a power management module, and further comprising: A non-volatile cache unit, connected to the main controller, is used to persistently save critical runtime data when the system is powered off.

[0021] The non-volatile cache unit is implemented by a non-volatile memory, which is selected from one of the following groups: magnetic random access memory, phase change memory, and NorFlash powered by a supercapacitor.

[0022] In this embodiment, the non-volatile cache unit is used to persistently store critical runtime data such as the FTL mapping table and incomplete I / O command contexts. Several implementation options are available: Magnetic Random Access Memory (MRAM) offers advantages such as fast read / write speeds and high durability; Phase-Change Memory (PCM) is another high-density non-volatile option; and NorFlash powered by supercapacitors is a lower-cost alternative. This design provides flexibility and aims to eliminate reliance on traditional large-capacity tantalum capacitors, thereby reducing system cost and size, and avoiding reliability issues caused by capacitor aging.

[0023] The hardware state machine, integrated inside the main controller but independent of the main controller's CPU core, is composed of dedicated logic circuits and is used to manage the system state saving and restoration process.

[0024] In this embodiment, the hardware state machine is composed of dedicated logic circuits, independent of the main CPU and its running firmware. Its core function is to manage the maintenance of the hibernation state and the fast wake-up process. Because it uses hardware logic rather than software processes, its operation is deterministic and high-speed, and it can bypass the lengthy software initialization process during wake-up and directly restore the system state, which is the key to achieving microsecond-level wake-up latency.

[0025] An ultra-low power wake-up detection circuit, which is physically connected to the power management module and the host interface, is used to listen for wake-up events in sleep mode.

[0026] The ultra-low power wake-up detection circuit includes: An ultra-low power comparator is used to continuously monitor the signal level of the host interface physical link and compare it with a preset reference voltage threshold.

[0027] A digital logic unit, which is connected to the output of the comparator, is used to perform logical judgments on the signals output by the comparator.

[0028] A control logic unit, connected to the output of the digital logic unit, is used to generate an enable signal to the power management module when the logic determines that a valid wake-up event has occurred, so as to control the restoration of power supply.

[0029] In this embodiment, the circuit is powered by an independent low-power power domain during sleep mode, which is the basis for the system to achieve ultra-low power sleep mode of <100mW. During operation, the ultra-low power comparator continuously monitors the signal levels of physical links such as PCIe host interfaces; the digital logic unit makes a judgment; and the control logic unit ultimately generates an enable signal to drive the power management module. This hardware circuit achieves continuous monitoring of the wake-up signal while consuming extremely low power itself.

[0030] The system is configured as follows: During the hibernation phase, in response to the hibernation trigger condition, the main controller saves the current FTL mapping table and I / O command context to the non-volatile cache unit. Subsequently, the power management module cuts off the power supply to the NAND flash array and the main controller core circuit, maintaining power supply only to the non-volatile cache unit, the hardware state machine, and the wake-up detection circuit.

[0031] The hibernation trigger conditions include: a custom hibernation command sent by the host through the NVMe management interface, or the I / O idle time detected by the system exceeding a preset threshold.

[0032] In this embodiment, the triggering condition design balances active host control and intelligent device management. Before entering hibernation, the system saves critical data to a non-volatile cache. Subsequently, the power management module cuts off power to most circuits, including the NAND flash memory and the main controller core, maintaining power only to the three core units: the non-volatile cache, the hardware state machine, and the wake-up detection circuit. Through this fine-grained dynamic segmentation of the power domain, the system successfully reduces hibernation power consumption significantly from hundreds of milliwatts (e.g., above 500mW) in traditional solutions to below 100mW, achieving a power reduction of over 95%.

[0033] During the wake-up recovery phase, after the wake-up detection circuit detects a valid wake-up signal, it triggers the power management module to restore power supply, and the hardware state machine takes over control, loading the system state data stored in the non-volatile cache unit into the corresponding hardware to directly rebuild the ability to access NAND flash memory.

[0034] The effective wake-up signal is a physical layer training sequence that is distinct from normal data communication, specifically an ordered set of Electrical Idle Exit defined by the PCIe protocol.

[0035] In this embodiment, the effective wake-up signal utilizes the standard PCIe physical layer signal (Electrical Idle Exit ordered set), eliminating the need for the host to install specific drivers and ensuring good compatibility with the existing NVMe ecosystem. During the wake-up process, the hardware state machine takes over control, directly restoring register states and memory data from the non-volatile cache and initializing the most basic NAND access hardware module. This skips the traditional full power-on reset and firmware loading software processes, significantly reducing the wake-up latency from the traditional 10ms level to less than 1ms, achieving rapid response.

[0036] like Figure 2 As shown, the present invention also provides a hibernation and wake-up method for an enterprise-level solid-state drive, applied to the system described above, comprising: The host sends a hibernation command to the solid-state drive through the NVMe management interface and works with the solid-state drive to complete the low-power state switching of the PCIe link.

[0037] In response to the hibernation command, the solid-state drive saves critical runtime data to its internal non-volatile cache unit.

[0038] The step of saving critical runtime data to its internal non-volatile cache unit includes: freezing the register state of the main controller through the hardware state machine, and compressing the I / O command context data in the dynamic random access memory before writing it into the non-volatile cache unit.

[0039] In this embodiment, the state saving process freezes registers through a hardware state machine, compresses the I / O context in the DRAM, and then writes it to a non-volatile cache (such as MRAM). The compression process helps reduce the amount of data written, improves the saving speed, and reduces write wear on cache cells.

[0040] After the data is saved, the power management module of the solid-state drive cuts off the power supply to its NAND flash array and the core circuit of the main controller, so that the solid-state drive enters an ultra-low power sleep state in which only the non-volatile cache unit, the hardware state machine integrated in the main controller and the ultra-low power wake-up detection circuit are powered.

[0041] During the ultra-low power sleep state, the wake-up detection circuit continuously monitors the signals of the host interface physical link.

[0042] The total power consumption of the solid-state drive in the ultra-low power hibernation state is less than 100 milliwatts.

[0043] In this embodiment, through the above power supply control, the measured total power consumption of the solid-state drive in hibernation mode can be less than 80mW, which meets the stringent requirements for ultra-low power consumption in scenarios such as edge computing.

[0044] When the host needs to wake up the solid-state drive, it sends a preset physical layer wake-up signal to the physical link; Upon detecting the physical layer wake-up signal, the wake-up detection circuit triggers the power management module to restore power supply to the NAND flash memory array and the main controller; and After the power supply is stabilized, the hardware state machine directly loads the system state data stored in the non-volatile cache unit into the corresponding hardware registers and memory space to rebuild the access capability to NAND flash memory.

[0045] Specifically, the hardware state machine directly loads the saved system state data into the corresponding hardware registers and memory space to rebuild the access capability to NAND flash memory, so as to complete the system state recovery and prepare to respond to I / O requests within 1 millisecond.

[0046] The total latency from when the wake-up detection circuit identifies the physical layer wake-up signal to when the solid-state drive completes state recovery and is able to respond to host I / O requests is less than 1 millisecond.

[0047] In this embodiment, the entire wake-up and recovery process is dominated by a hardware state machine, achieving extremely fast state recovery. The total latency from detecting the wake-up signal to being able to respond to I / O requests is controlled to within 1 millisecond, which is an order of magnitude improvement compared to traditional solutions and can meet the needs of deterministic responses in scenarios such as industrial automation.

[0048] In summary, this invention achieves a breakthrough innovation in enterprise-level solid-state drive power management technology by constructing a three-in-one collaborative architecture of non-volatile cache unit, hardware state machine, and ultra-low power detection circuit. Specifically, it replaces the traditional DRAM + tantalum capacitor combination with non-volatile memory such as MRAM, fundamentally solving the problems of capacitor aging, bulky size, and high cost; it directly manages the system state saving and restoration process through a hardware state machine independent of the CPU core, realizing hardware-based and deterministic processes; and it designs a dedicated ultra-low power wake-up detection circuit to continuously monitor standard PCIe physical layer signals, ensuring driverless wake-up while maintaining ultra-low power consumption. The organic cooperation of these three core components forms a complete technology chain that runs through the entire process from hibernation entry, maintenance to wake-up and recovery.

[0049] At the protocol level, this invention innovatively extends the NVMe instruction set to support deep sleep mode and utilizes the Electrical Idle Exit ordered set defined by the PCIe protocol as a wake-up trigger signal, achieving standardized collaboration between the host and the SSD. This design ensures full compatibility with the existing NVMe ecosystem without relying on customized host drivers. At the architecture level, through fine-grained partitioning and dynamic management of the power domain, only the minimum necessary circuitry is powered during sleep, achieving ultimate optimization of power control.

[0050] The present invention offers significant and synergistic technical benefits: it drastically reduces the sleep power consumption of ESSD from over 500mW in traditional solutions to below 80mW, a power reduction of over 95%, fully meeting the extreme energy efficiency requirements of edge computing devices and green data centers; simultaneously, it shortens the wake-up latency from the traditional 10ms level to less than 1ms, improving response speed by an order of magnitude and effectively supporting the real-time requirements of scenarios such as industrial automation. This solution successfully resolves the long-standing technical contradiction between ultra-low power consumption and fast wake-up, providing a new technical paradigm for energy efficiency optimization of enterprise-level storage devices.

[0051] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A hibernation and wake-up system for an enterprise-grade solid-state drive, comprising a main controller, a NAND flash memory array, and a power management module, characterized in that, Also includes: A non-volatile cache unit, connected to the main controller, is used to persistently save critical runtime data when the system is powered off; The hardware state machine is integrated inside the main controller and is independent of the main controller's CPU core. It is composed of dedicated logic circuits and is used to manage the system state saving and restoration process. An ultra-low power wake-up detection circuit, which is physically connected to the power management module and the host interface, is used to listen for wake-up events in sleep mode. The system is configured as follows: During the hibernation phase, in response to the hibernation trigger condition, the main controller saves the current FTL mapping table and I / O command context to the non-volatile cache unit. Subsequently, the power management module cuts off the power supply to the NAND flash array and the main controller core circuit, and only maintains the power supply to the non-volatile cache unit, the hardware state machine and the wake-up detection circuit. During the wake-up recovery phase, after the wake-up detection circuit detects a valid wake-up signal, it triggers the power management module to restore power supply, and the hardware state machine takes over control, loading the system state data stored in the non-volatile cache unit into the corresponding hardware to directly rebuild the ability to access NAND flash memory.

2. The hibernation and wake-up system for an enterprise-level solid-state drive according to claim 1, characterized in that, The non-volatile cache unit is implemented by a non-volatile memory, selected from one of the following groups: magnetic random access memory, phase-change memory, and NorFlash powered by a supercapacitor.

3. The hibernation and wake-up system for an enterprise-level solid-state drive according to claim 1, characterized in that, The hibernation trigger conditions include: a custom hibernation command sent by the host through the NVMe management interface, or the I / O idle time detected by the system exceeding a preset threshold.

4. The hibernation and wake-up system for an enterprise-level solid-state drive according to claim 1, characterized in that, The ultra-low power wake-up detection circuit includes: An ultra-low power comparator is used to continuously monitor the signal level of the host interface physical link and compare it with a preset reference voltage threshold. A digital logic unit, which is connected to the output of the comparator, is used to perform logical judgments on the signals output by the comparator. A control logic unit, connected to the output of the digital logic unit, is used to generate an enable signal to the power management module when the logic determines that a valid wake-up event has occurred, so as to control the restoration of power supply.

5. The hibernation and wake-up system for an enterprise-level solid-state drive according to claim 4, characterized in that, The effective wake-up signal is a physical layer training sequence that is distinct from normal data communication, specifically an ordered set of ElectricalIdle Exit defined by the PCIe protocol.

6. A hibernation and wake-up method for an enterprise-grade solid-state drive, applied to the system as described in any one of claims 1-5, characterized in that, include: The host sends a hibernation command to the solid-state drive through the NVMe management interface and works with the solid-state drive to complete the low-power state switching of the PCIe link; In response to the hibernation command, the solid-state drive saves critical runtime data to its internal non-volatile cache unit; After the data is saved, the power management module of the solid-state drive cuts off the power supply to its NAND flash array and the core circuit of the main controller, so that the solid-state drive enters an ultra-low power sleep state in which only the non-volatile cache unit, the hardware state machine integrated in the main controller and the ultra-low power wake-up detection circuit are powered. During the ultra-low power sleep state, the wake-up detection circuit continuously monitors the signals of the host interface physical link; When the host needs to wake up the solid-state drive, it sends a preset physical layer wake-up signal to the physical link; After recognizing the physical layer wake-up signal, the wake-up detection circuit triggers the power management module to restore power supply to the NAND flash array and the main controller. as well as After the power supply is stabilized, the hardware state machine directly loads the system state data stored in the non-volatile cache unit into the corresponding hardware registers and memory space to rebuild the access capability to NAND flash memory.

7. The hibernation and wake-up method for an enterprise-grade solid-state drive according to claim 6, characterized in that, The method of saving critical runtime data to its internal non-volatile cache unit includes: freezing the register state of the main controller through the hardware state machine, and compressing the I / O command context data in the dynamic random access memory before writing it into the non-volatile cache unit.

8. The hibernation and wake-up method for an enterprise-grade solid-state drive according to claim 6, characterized in that, The hardware state machine directly loads the saved system state data into the corresponding hardware registers and memory space to rebuild the access capability to NAND flash memory, so as to complete the system state recovery and prepare to respond to I / O requests within 1 millisecond.

9. The hibernation and wake-up method for an enterprise-grade solid-state drive according to claim 6, characterized in that, The total power consumption of the solid-state drive in ultra-low power hibernation mode is less than 100 milliwatts.

10. The hibernation and wake-up method for an enterprise-grade solid-state drive according to claim 6, characterized in that, The total latency from the moment the wake-up detection circuit detects the physical layer wake-up signal to the moment the solid-state drive completes state recovery and is able to respond to host I / O requests is less than 1 millisecond.

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