Edge selection device
By generating reference pulses through the output sections on the Rise and Fall sides and using detection and selection components to handle pulse overlap, the problem of inaccurate frequency signal edge detection is solved, achieving higher frequency pulse detection accuracy and anti-jitter capability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ADVANTEST CORP
- Filing Date
- 2022-07-11
- Publication Date
- 2026-06-02
Smart Images
Figure CN115905091B_ABST
Abstract
Description
[Technical Field]
[0001] This invention relates to an edge selection device. [Background Technology]
[0002] Patent documents 1-3 describe the following: "Once the delay circuit 101 receives the input frequency signal CKA, it delays the signal by a fixed time td1 to generate a delayed frequency signal CKD and outputs it. Once the OR logic gate 102 receives the delayed frequency signal CKD and the input frequency signal CKA, it extends the width of the H level of the input frequency signal CKA by a fixed time td1 to generate an oscillation control signal CT1 and outputs it."
[0003] [Existing Technical Documents]
[0004] (Patent Documents)
[0005] Patent document 1: Japanese Patent Application Publication No. 2003-051737.
[0006] Patent document 2: Japanese Patent Application Publication No. 2017-112427.
[0007] Patent document 3: International Publication No. 2008 / 032701. [Summary of the Invention]
[0008] A first aspect of the present invention provides an apparatus. The apparatus may include: a first output unit that outputs a first pulse in response to at least one rising of a plurality of signals; a second output unit that outputs a second pulse in response to at least one falling of a plurality of signals; a detection unit that, in a non-detection state each time a pulse occurs, detects the leading pulse that is output first among the first and second pulses; and a selection unit that selects the edge of the leading pulse detected by the detection unit as the edge of a frequency pulse contained in the frequency.
[0009] The first output unit may include: a plurality of first pulse generators, each generating a reference pulse of a first reference width in response to a rise in any one of the plurality of signals. The first output unit may also include: a first OR logic gate, which outputs the logical sum of the reference pulses generated by the plurality of first pulse generators as the first pulse. The second output unit may include: a plurality of second pulse generators, each generating a reference pulse of a first reference width in response to a fall in any one of the plurality of signals. The second output unit may also include: a second OR logic gate, which outputs the logical sum of the reference pulses generated by the plurality of second pulse generators as the second pulse.
[0010] The first reference width, in the case where the rise and fall of a plurality of signals are generated one after another in the interval of frequency pulses, can be the pulse width in which the first pulse and the second pulse overlap by at least a portion.
[0011] The first reference width can be a pulse width larger than the maximum value of the rise and fall intervals of a plurality of signals that may be generated in the interval of a frequency pulse.
[0012] The first reference width can be a pulse width that is 0.4 times larger than the reference interval of the frequency pulse.
[0013] The first reference width is the pulse width of a first pulse formed by the partial overlap of two or more reference pulses generated in response to each of the two or more signals when there are two or more signals rising in the interval of the frequency pulses, and the pulse width of a second pulse formed by the partial overlap of two or more reference pulses generated in response to each of the two or more signals when there are two or more signals falling in the interval of the frequency pulses.
[0014] The detection unit may include: a pulse detection unit that detects the first pulse and the second pulse output from the first output unit and the second output unit, respectively. The detection unit may also include: a invalidation unit that invalidates the detection of the pulse detection unit for the later output pulse when the first pulse and the second pulse partially overlap in each interval of the frequency pulse.
[0015] The detection unit can detect the leading pulse by detecting the first pulse generated among the third pulse of the third reference width and the fourth pulse of the third reference width. The third pulse is generated in response to the output of the first pulse, and the fourth pulse is generated in response to the output of the second pulse.
[0016] The third reference width, in the case where the rise and fall of a plurality of signals are generated one after another in the interval of frequency pulses, can be the pulse width in which the third pulse and the fourth pulse overlap by at least a portion.
[0017] The third reference width can be a pulse width larger than the maximum value of the rise and fall intervals of a plurality of signals that may be generated in the interval of a frequency pulse.
[0018] The third reference width can be a pulse width that is 0.4 times larger than the reference interval of the frequency pulse.
[0019] The detection unit may include: a pulse detection unit that detects the third pulse and the fourth pulse respectively. The detection unit may also include: a invalidation unit that, when the third pulse and the fourth pulse partially overlap in each interval of the frequency pulse and are output, invalidates the detection of the pulse detection unit for the later output pulse.
[0020] Multiple signals can be three differential signals derived from signals transmitted via three lines from the Channel Physical Layer (C-PHY) based on the Mobile Industrial Processor Interface (MIPI).
[0021] Furthermore, the above description of the invention does not list all the essential features of the invention. Moreover, sub-combinations of these features can also constitute an invention. [Attached Image Description]
[0022] Figure 1 Device 1, which represents the implementation method.
[0023] Figure 2 The waveform representing the operation of device 1.
Detailed Implementation Methods
[0024] The present invention will now be described through embodiments thereof, but these embodiments do not limit the scope of the invention as claimed. Furthermore, the solutions of the invention do not necessarily require all combinations of the features described in the embodiments.
[0025] [1. Structure of Device 1]
[0026] Figure 1 Device 1, representing this embodiment.
[0027] Device 1 generates a frequency pulse clk from a complex signal. For example, device 1 can generate a frequency pulse clk from three signals, and can also read data (for example, image data) from these three signals. Device 1 includes: a Rise-side output unit 2, a Fall-side output unit 3, a detection unit 4, a selection unit 5, and a data reading unit 6. These configurations can be constructed using logic circuits. Furthermore, in this embodiment, as an example, device 1 is based on the Channel Physical Layer (C-PHY) of the Mobile Industrial Processor Interface (MIPI), therefore, the C-PHY will be described first before the description of each configuration.
[0028] [1.1.C-PHY]
[0029] In a C-PHY, the signals A, B, and C transmitted via three lines contain not only the data to be communicated but also embedded frequency signals. Each of the signals A, B, and C is set to a different value from three options: High, Middle, and Low. The three signals A, B, and C as a whole can be set to six states: "+x", "-x", "+y", "-y", "+z", and "-z" as shown in Table 1.
[0030] [Table 1]
[0031]
[0032]
[0033] The overall state of signals A, B, and C transitions to other states within each Unit Interval (UI). In this way, signals A, B, and C can transmit 5-value data (also called symbols) within each UI. A UI is a unit of time determined on the transmitting side of signals A, B, and C for transmitting one symbol, and can have a length of, for example, 12.5 to 1000 ns. Furthermore, since jitter occurs in the transmitted signals, on the receiving side of signals A, B, and C, a frequency pulse clk is generated based on the received signal level changes of signals A, B, and C, and data is obtained from signals A, B, and C based on the timing of this frequency pulse clk.
[0034] Here, as mentioned above, signals A, B, and C can be set to 6 states, and each state transitions to one of 5 states different from its original state, resulting in 30 (6 x 5) possible state transitions. However, these 30 state transitions include equivalent state transitions, and they utilize the differential signal Diff (also known as the signal Diff) corresponding to the differences between signals A, B, and C. (AB) Diff (BC) Diff (CA) The transitions can be categorized into the following three types.
[0035] The first type of state transition is signal Diff. (AB) Diff (BC) Diff (CA) All states cross the voltage 0 (also known as zero crossing). This state transition is, for example, a transition from state "+x" to state "-x". In this case, the signal Diff... (AB) Diff (BC) Diff (CA) Two zero-crossings cause the value to rise from negative to positive, and the remaining zero-crossing causes the value to fall from positive to negative, or the signal Diff... (AB) Diff (BC) Diff (CA) Two of the zeros cross from positive to negative, and the remaining zero crosses from negative to positive.
[0036] The second type of state transition is signal diff. (AB) Diff (BC) Diff (CA) The two cases where the voltage crosses 0. This state transition, for example, is a transition from state "+x" to state "+y". In this case, the signal Diff (AB)Diff (BC) Diff (CA) One of them crosses zero and rises from a negative value to a positive value, while the other crosses zero and falls from a positive value to a negative value.
[0037] The third type of state transition is signal diff. (AB) Diff (BC) Diff (CA) One of the cases where the voltage crosses 0. This state transition is, for example, a transition from state "+x" to state "-y". In this case, the signal Diff... (AB) Diff (BC) Diff (CA) One of the zeros in the value rises from a negative value to a positive value or falls from a positive value to a negative value.
[0038] Furthermore, in the first and second type of state transitions that generate two or more zero crossings, the zero crossings in the UI may be generated in a staggered manner. For example, in the first type of state transition that generates three zero crossings, ideally all zero crossings should occur simultaneously, but due to jitter or other factors, they may occur at intervals of up to 0.2 UI. Similarly, in the second type of state transition that generates two zero crossings, the zero crossings may occur at intervals of up to 0.4 UI.
[0039] In these cases, rising zero crossings within the UI will not occur consecutively, nor will falling zero crossings occur consecutively. For example, if a rising zero crossing occurs first within the UI, a falling zero crossing will inevitably follow in the same UI. Similarly, if a falling zero crossing occurs first within the UI, a rising zero crossing will inevitably follow in the same UI. After a rising zero crossing, no further rising zero crossing can occur without a falling zero crossing occurring. Likewise, after a falling zero crossing, no further falling zero crossing can occur without a rising zero crossing occurring.
[0040] Furthermore, when a second state transition occurs within a series of UIs, the order of the rising zero crossings and the falling zero crossings is the same in each of these UIs. That is, in each of these UIs, a falling zero crossing occurs after a rising zero crossing, or a rising zero crossing occurs after a falling zero crossing.
[0041] Furthermore, in consecutive UI sequences, if a second state transition occurs in the previous UI sequence and a first state transition occurs in the next UI sequence, the zero crossing that occurs first in the previous UI sequence will occur in the next UI sequence. That is, if a rising zero crossing occurs in the previous UI sequence followed by a falling zero crossing, a rising zero crossing will occur in the next UI sequence.
[0042] Similarly, in consecutive UI sequences, if a first state transition occurs in the previous UI and a second state transition occurs in the next UI, the zero crossing that occurs in the previous UI will occur first in the next UI. That is, if an upward zero crossing occurs in the previous UI, an upward zero crossing will occur first in the next UI, followed by a downward zero crossing.
[0043] In a C-PHY that transmits data as described above, it is possible to achieve signal diff (AB) Diff (BC) Diff (CA) A frequency pulse clk is generated during the zero-crossing timing. When multiple zero-crossings occur within UI, a frequency pulse clk can be generated at the first zero-crossing.
[0044] The apparatus 1 of this embodiment can obtain three diffs derived from signals A, B, and C. (AB) Diff (BC) Diff (CA) Signals A, B, and C are transmitted using three lines with C-PHY as the reference. For example, device 1 can obtain the signal Diff from the receiving device. (AB) Diff (BC) Diff (CA) The receiving device receives signals A, B, and C and generates a Diff signal. (AB) Diff (BC) Diff (CA) .
[0045] [1.2. Rise-side output section 2]
[0046] Rise-side output unit 2 is an example of the first output unit, responding to a plurality of signals Diff. (AB) Diff (BC) Diff (CA) A Rise-side pulse is output when at least one of the signals rises. (Diff signal) (AB) Diff (BC) Diff (CA) An increase can refer to the signal diff. (AB) Diff (BC) Diff (CA) It crosses zero and rises from a negative value to a positive value. The Rise-side output unit 2 has 3 pulse generators 20 (also called pulse generators 20). (AB) 20 (BC) 20 (CA) ) and OR logic gate 21. Additionally, pulse generator 20 (AB) 20 (BC) 20 (CA)The symbols in parentheses in the description indicate the signal Diff. (AB) Diff (BC) Diff (CA) The corresponding signal in.
[0047] 3 pulse generators 20 (AB) 20 (BC) 20 (CA) Response to multiple signals Diff (AB) Diff (BC) Diff (CA) For any of the corresponding signals Diff rising, a reference pulse P of reference width is generated respectively. rise (also known as reference pulse P) rise(AB) P rise(BC) P rise(CA) Reference pulse P rise The reference width is an example of the first reference width, as detailed later. Each pulse generator 20 can generate the reference pulse P that has already been generated. rise Supply to OR logic gate 21.
[0048] OR logic gate 21 is connected to each of the three pulse generators 20. OR logic gate 21 is an example of the first OR logic gate, which converts the reference pulse P generated by each of the three pulse generators 20 into a reference pulse P. rise The logic and output are used as a Rise-side pulse. OR logic gate 21 can supply the Rise-side pulse to the detection unit 4. Also, OR logic gate 21 can supply the Rise-side pulse to the "0" input terminal in the selection unit 5.
[0049] [1.3. Fall Side Output Section 3]
[0050] Fall-side output unit 3 is an example of the second output unit, responding to a plurality of signals Diff. (AB) Diff (BC) Diff (CA) A Fall-side pulse is output when at least one of the signals decreases. (Diff signal) (AB) Diff (BC) Diff (CA) A decrease can refer to the signal diff. (AB) Diff (BC) Diff (CA) It crosses zero and decreases from a positive value to a negative value. The Fall-side output section 3 has three pulse generators 30 (also called pulse generators 30). (AB) 30 (BC) 30 (CA) ) and OR logic gate 31.
[0051] 3 pulse generators 30 (AB) 30 (BC) 30 (CA) Response to multiple signals Diff (AB) Diff (BC) Diff (CA) For any of the corresponding signals Diff decreasing, a reference pulse P of reference width is generated respectively. fall (also known as reference pulse P) fall(AB) P fall(BC) P fall(CA) Each pulse generator 30 can generate a reference pulse P. fall Supply to OR logic gate 31.
[0052] OR logic gate 31 is connected to each of the three pulse generators 30. OR logic gate 31 is an example of the second OR logic gate, which converts the reference pulse P generated by each of the three pulse generators 30 into a reference pulse P. fall The logic and output are the Fall-side pulses. OR logic gate 31 can supply the Fall-side pulses to the detection unit 4. Also, OR logic gate 31 can supply the Fall-side pulses to the "1" input terminal in the selection unit 5.
[0053] [1.4. Reference Pulse P] rise , Pfall [Base width]
[0054] During the interval of the frequency pulse clk, the signal Diff (AB) Diff (BC) Diff (CA) When the rise and fall are generated one at a time, the reference pulse P rise P fall The reference width can be the Rise-side pulse from the Rise-side output unit 2 (here, the reference pulse P). rise The Fall-side pulse (here, the reference pulse P) from the Fall-side output unit 3 and the Fall-side pulse (here, the reference pulse P) fall (It itself) has at least a partially overlapping pulse width. For example, there is a signal Diff within the interval of the frequency pulse clk. (AB) Rising and signal Diff (BC) In the case of a drop, the pulse generator 20 of the Rise-side output unit 2 can be used. (AB) The generated reference pulse P rise(AB) Pulse generator 30 with Fall-side output section 3 (BC) The generated reference pulse P fall(BC) There must be some overlap in pulse width.
[0055] Furthermore, there is a signal Diff within the interval of the frequency pulse clk.(AB) Diff (BC) Diff (CA) In the case of two or more rising signals, the reference width can be two or more reference pulses P generated in response to each of the two or more signals. rise A portion overlaps, forming the pulse width of a single Rise-side pulse. Furthermore, within the intervals of the frequency pulse clk, there is a signal Diff. (AB) Diff (BC) Diff (CA) In the case of two or more signal drops, the reference width can be two or more reference pulses P generated in response to each of the two or more signals. fall Some overlaps to form the pulse width of one Fall-side pulse. For example, there are two signals Diff within the interval of the frequency pulse clk. (AB) Diff (BC) In the case of an increase, the reference width can be the response to the two signals Diff. (AB) Diff (BC) The two pulse generators 20 of the Rise output section 2 are respectively (AB) 20 (BC) The generated two reference pulses P rise(AB) P rise(BC) There must be some overlap, forming the pulse width of one Rise-side pulse. Furthermore, there are two signals diffing... (AB) Diff (BC) In the case of an increase, this increase is compared with the remaining signal diff. (CA) The descent can occur simultaneously, or it can occur during the period after the reference width following the previous rise, generating the remaining signal Diff. (CA) The decline.
[0056] Furthermore, the reference width can be greater than the signal Diff that may be generated during the interval of the frequency pulse clk. (AB) Diff (BC) Diff (CA) The pulse width is larger than the maximum rise and fall interval. The maximum rise and fall interval can be 0.4 times the length of the reference interval of the frequency pulse clk. Therefore, the reference width can be a pulse width larger than 0.4 times the reference interval of the frequency pulse clk. The length of the reference interval can be the length of UI set at the transmission source of signals A, B, and C. In this case, the reference width can be 0.45UI, or even 0.5UI or more.
[0057] [1.5. Inspection Department 4]
[0058] The detection unit 4 detects the first leading pulse output whenever the pulse is in a non-detection state (also known as a wait state). The non-detection state refers to a state where pulses output from the Rise-side output unit 2 and the Fall-side output unit 3 are not detected. In the non-detection state, the detection unit 4 detects the first pulse output from the Rise-side pulse and the Fall-side pulse output from the Rise-side output unit 2 and the Fall-side output unit 3, using this as the leading pulse. The detection unit 4 includes a pulse detection unit 40 and an invalidation unit 41.
[0059] The pulse detection unit 40 detects the Rise-side pulse and Fall-side pulse output from the Rise-side output unit 2 and the Fall-side output unit 3, respectively. In response to detecting either the Rise-side pulse or the Fall-side pulse, the pulse detection unit 40 supplies a selection signal Sel to the selection unit 5, which causes the selection unit 5 to make a selection. In this embodiment, as an example, when the pulse detection unit 40 detects a Rise-side pulse, it supplies a selection signal Sel representing "0" to the selection unit 5. This "0" signal indicates the presence of a Rise-side pulse input in the "0" and "1" input terminals of the selection unit 5. Similarly, when the pulse detection unit 40 detects a Fall-side pulse, it supplies a selection signal Sel representing "1" to the selection unit 5. This "1" signal indicates the presence of a Fall-side pulse input in the "0" and "1" input terminals of the selection unit 5. When the pulse detection unit 40 detects both the Rise-side pulse and the Fall-side pulse, it can provide the selection unit 5 with a selection signal Sel indicating "0" or a selection signal Sel indicating "1".
[0060] The invalidation unit 41 disables the detection of the later-output pulse by the pulse detection unit 40 when pulses from the Rise-side output unit 2 and the Fall-side output unit 3 partially overlap during intervals of the frequency pulse clk. For example, the invalidation unit 41 can disable the detection of output pulses when the detection unit 4 is in a state of detecting preceding pulses (also known as a busy state). Therefore, when pulses from the Rise-side and Fall-side partially overlap, only the preceding pulse is detected by the pulse detection unit 40. In other words, pulses output when the detection unit 4 is in a waiting state without detecting preceding pulses will be detected by the pulse detection unit 40. The invalidation unit 41 disables the detection function for later-output pulses in both the Rise-side pulse detection function and the Fall-side pulse detection function in the pulse detection unit 40. The invalidation unit 41 can prevent the detection performed by the pulse detection unit 40 from being invalidated when the Rise-side pulse and the Fall-side pulse are output simultaneously, or it can invalidate the pulse detection of one of the Rise-side pulse and the Fall-side pulse that is predetermined.
[0061] If the detection of one of the Rise-side pulses or Fall-side pulses is invalidated—that is, if the detection unit 4 becomes busy because the pulse of the other side is detected first—the detection unit 4 can enter a pulse non-detection state, or a waiting state, in response to the situation where the pulse of the other side is not detected. In other words, if the detection of a subsequent pulse that overlaps with the preceding pulse in the Rise-side pulse or Fall-side pulse is invalidated, the subsequent pulse will not be detected by the pulse detection unit 40. In this state, if the preceding pulse is not detected (that is, if the detected preceding pulse has decreased), then neither the Rise-side pulse nor the Fall-side pulse will be detected, and therefore the detection unit 4 can enter a non-detection state. Thus, the detection unit 4 can enter a state of waiting to detect the next preceding pulse.
[0062] When the pulse detection is invalidated by the invalidation unit 41, the invalidation can be released in response to the pulse's descent. For example, if the Rise-side pulse is detected as a preceding pulse and the later-rising Fall-side pulse is invalidated, the invalidation of the Fall-side pulse detection can be released in response to the Fall-side pulse's descent. Therefore, when one of the Rise-side and Fall-side pulses overlaps with the other and is output, and the other pulse is output again, the latter pulse can be detected as a preceding pulse. Furthermore, if the Rise-side and Fall-side pulses are output without overlapping, since the later-sent Fall-side pulse is not invalidated by the invalidation unit 41, the later-sent Fall-side pulse can be detected as the next preceding pulse.
[0063] The invalidation unit 41 can detect the start of a new interval for the frequency pulse clk by responding to the detection of the Rise-side pulse and Fall-side pulse by the pulse detection unit 40, or by responding to the output of the frequency pulse clk from the device 1, or by responding to the output of the selection signal Sel by the pulse detection unit 40.
[0064] [1.6. Selection Section 5]
[0065] The selection unit 5 selects the edge of the preceding pulse detected by the detection unit 4 as the edge of the frequency pulse clk contained in the frequency. The selection unit 5 can select the edge of either the rising-side pulse or the falling-side pulse as the edge of the frequency pulse clk based on the selection signal Sel from the detection unit 4. In this embodiment, as an example, the selection unit 5 selects the start edge (e.g., rising edge) and the end edge (e.g., falling edge) of the preceding pulse as the start and end edges of the frequency pulse clk, that is, it selects the preceding pulse as the frequency pulse clk.
[0066] Selection unit 5 can select the Rise-side pulse input from the Rise-side output unit 2 to the input terminal of "0" and the Fall-side pulse input from the Fall-side output unit 3 to the input terminal of "1" in response to whether the selection signal Sel represents "0" or "1". In this embodiment, as an example, selection unit 5 can be a multiplexer.
[0067] The selection unit 5 can supply the selected frequency pulse clk to the data reading unit 6. The selection unit 5 can also output the frequency pulse clk to the outside of the device 1.
[0068] [1.7. Data Reading Unit 6]
[0069] Data reading unit 6, lock signal Diff(AB) Diff (BC) Diff (CA) The data reading unit 6 can lock the signal Diff separately in conjunction with the frequency pulse clk supplied by the self-selection unit 5. (AB) Diff (BC) Diff (CA) Thus, for example, the signal diff of the nth (where n is a natural number) UI. (AB) Diff (BC) Diff (CA) The signal Diff can correspond to the (n+α)th UI (where α is an integer greater than or equal to 0). (AB) Diff (BC) Diff (CA) The generated frequency pulse clk is locked. As an alternative to the above, the signal Diff of the nth UI is... (AB) Diff (BC) Diff (CA) It can also correspond to the signal Diff of the (n-α)th UI. (AB) Diff (BC) Diff (CA) The generated frequency pulse clk is locked.
[0070] Data reading unit 6 can be used for signal diff (AB) Diff (BC) Diff (CA) The D flip-flop is configured for each of the components. The data reading unit 6 can read the locked signal Diff. (AB) Diff (BC) Diff (CA) The data is output to the outside. For example, the data reading unit 6 can supply the locked data to the display driver of the display.
[0071] Based on the above device 1, each response to multiple signals Diff (AB) Diff (BC) Diff (CA) When at least one of the rising or falling pulses in the signal diff is generated in a non-detected state, the earliest output preceding pulse is detected and selected as the frequency pulse clk. Therefore, during the rising and falling changes of the diff signal, a frequency pulse clk corresponding to the earlier change within the same UI can be generated, preventing accidental generation of a frequency pulse clk corresponding to a later change. This improves jitter tolerance and the accuracy of the frequency pulse clk.
[0072] Furthermore, the Rise-side output unit 2 and the Fall-side output unit 3 each have a plurality of pulse generators 20 and 30, which generate a reference pulse P of reference width in response to the rise or fall of any corresponding signal Diff. rise , benchmark P fall ; and OR logic gates 21 and 31, which will convert the generated reference P rise The logic and the benchmark P fall The logic is output as a pulse. Therefore, it is possible to detect the rising and falling changes of the signal Diff separately, and to accurately detect the change that occurs first.
[0073] Furthermore, the reference pulse P rise P fall The reference width, when a signal Diff is generated successively during the intervals of frequency pulse clk, is a pulse width in which the Rise-side pulse and Fall-side pulse partially overlap. Therefore, when one of the Rise-side pulse and Fall-side pulse is generated first within the same UI, and the other is generated later, it can prevent the later-generated pulse from being incorrectly detected as the preceding pulse of the next UI.
[0074] Furthermore, the reference pulse P rise P fall The reference width is a pulse width larger than the maximum value of the rise and fall intervals of the multiple signals Diff that may be generated within the interval of the frequency pulse clk. Therefore, when a rise and fall of a signal Diff is generated successively within the interval of the frequency pulse clk, the Rise-side pulse and the Fall-side pulse partially overlap. Therefore, when one of the Rise-side pulse and the Fall-side pulse is generated first within the same UI, and the other is generated later, it can prevent the later-generated pulse from being incorrectly detected as the preceding pulse of the next UI.
[0075] Furthermore, the reference pulse P rise P fall The reference width is a pulse width larger than 0.4 times the reference interval of the frequency pulse clk (0.4 UI in this embodiment as an example). Therefore, when the maximum value of the rise and fall interval of a plurality of signals Diff that may be generated in the interval of the frequency pulse clk is determined to be less than 0.4 times the reference interval, when one rise and fall of signal Diff is generated successively in the interval of the frequency pulse clk, the Rise-side pulse and the Fall-side pulse partially overlap. Therefore, when one of the Rise-side pulse and the Fall-side pulse is generated first in the same UI, and the other is generated later, it is possible to prevent the later-generated pulse from being mistakenly detected as the preceding pulse of the next UI. Furthermore, for example, by using the reference pulse P riseP fall With a base width of 0.5UI or more, even when the rise and fall intervals of multiple signal diffs are 0.5UI, the rise-side pulse and fall-side pulse can partially overlap, thus preventing the later-generated pulse from being mistakenly detected as the preceding pulse of the next UI.
[0076] Furthermore, when the Rise-side pulse and Fall-side pulse partially overlap during each interval of the frequency pulse clk, the detection of the later-output pulse is invalidated, thus ensuring the accurate detection of the earlier-occurring change in the rising and falling changes of the signal Diff. Also, when a pulse corresponding to a later-occurring change crosses into the next UI, the detection of that pulse is invalidated, ensuring the accurate detection of the earlier-occurring change in the next UI.
[0077] Furthermore, in the case of multiple signals Diff (AB) Diff (BC) Diff (CA) When two or more signals rise, the reference pulse P rise P fall The reference width can be two or more reference pulses P generated in response to each of the two or more signal Diffs. rise With P fall A portion overlaps to form the pulse width of a single Rise-side pulse. Furthermore, there are multiple Diff signals within the interval of the frequency pulse clk. (AB) Diff (BC) Diff (CA) In the case of two or more signal drops, the reference pulse P rise P fall The reference width can be two or more reference pulses P generated in response to each of the two or more signal Diffs. rise With P fall A portion overlaps to form the pulse width of a single Fall-side pulse. Therefore, in cases where two or more rises or falls occur within the same UI, it can prevent the later-arriving reference pulse P from being generated. rise P fall It was incorrectly detected as the leading pulse of the next UI element.
[0078] [2. Example of an action]
[0079] Figure 2 The diagram shows the waveform representing the operation of device 1. As an example, the following waveform is shown in the figure: Signals Diff are generated sequentially within the first UI. (AB) The rise and signal Diff (BC)The decrease, and the sequential generation of the Diff signal within the second UI. (AB) The decrease and signal Diff (BC) In the case of an increase, the self-pulse generator 20 (AB) 20 (BC) 30 (AB) 30 (BC) Output reference pulse P rise(AB) P rise(BC) P fall(AB) P fall(BC) The graph includes the Rise and Fall pulses output from OR logic gates 21 and 31, the selection signal Sel output from detection unit 4, and the frequency pulse clk output from selection unit 5. The horizontal axis represents time, and the vertical axis represents the signal level. Furthermore, the graph also illustrates the state of detection unit 4 at each time point: "Busy" and "Waiting." In this example, the reference pulse P... rise P fall The base width can be 0.6 UI.
[0080] First, at time t1, once Diff... (BC) Rising and signal Diff (AB) Diff (CA) The decrease is due to the pulse generator 20. (BC) 30 (BC) 30 (CA) Output the reference pulse P from time t1 to time t3 (=t1+0.6UI). rise(BC) P fall(AB) P fall(CA) Therefore, OR logic gates 21 and 31 output a Rise-side pulse and a Fall-side pulse with a pulse width of 0.6 UI from time t1 to time t3. In this example, the pulse detection unit 4 detects these Rise-side and Fall-side pulses, causing it to become busy and output a "0" selection signal Sel. As a result, the selection unit 5 selects the Rise-side pulse as the frequency pulse clk and outputs it. The detection unit 4 enters a waiting state in response to the decrease of the Rise-side and Fall-side pulses. Furthermore, the reference pulse P is omitted in this figure. fall(CA) The illustration.
[0081] Then, at time t5, once Diff (BC) The pulse generator 30 then decreases. (BC) Output the reference pulse P from time t5 to time t7 (=t5+0.6UI). fall(BC)Therefore, OR logic gate 31 outputs a Fall-side pulse with a pulse width of 0.6 UI from time t5 to time t7. Furthermore, the result of this Fall-side pulse being detected by pulse detection unit 4 causes detection unit 4 to enter a busy state and output a "1" selection signal Sel. As a result, selection unit 5 selects the Fall-side pulse as the frequency pulse clk and outputs it. Detection unit 4 enters a waiting state in response to the decrease of the Fall-side pulse.
[0082] On the other hand, in time t6 (=t5+0.5UI), once Diff... (AB) As it rises, it originates from pulse generator 20. (AB) Output the reference pulse P from time t6 to time t9 (=t6+0.6UI). rise(AB) Therefore, a Rise-side pulse with a pulse width of 0.6 UI is output from OR logic gate 21 from time t6 to time t9. Since this Rise-side pulse overlaps with the preceding Fall-side pulse, it is not detected by the pulse detection unit 40 as a result of the invalidation performed by the invalidation unit 41. Therefore, the selection signal Sel output from the detection unit 4 or the frequency pulse clk output from the selection unit 5 is not affected by the Rise-side pulse. Once the Rise-side pulse drops at time t9, the detection invalidation for this Rise-side pulse is released.
[0083] Furthermore, during time t8, from time t7 to time t9, once Diff... (AB) The pulse generator 30 then decreases. (AB) Output a reference pulse P with a reference width starting from time t8. fall(AB) Therefore, OR logic gate 31 outputs a Fall-side pulse with a pulse width of 0.6 UI starting from time t8. Furthermore, the result of this Fall-side pulse being detected by pulse detection unit 4 causes detection unit 4 to enter a busy state and output a "1" selection signal Sel. As a result, selection unit 5 selects the Fall-side pulse as the frequency pulse clk and outputs it.
[0084] [3. Examples of Variation]
[0085] Furthermore, in the above embodiments, it is explained that the device 1 generates the signal Diff from the received signals A, B, and C. (AB) Diff (BC) Diff (CA) The receiving device obtains the signal Diff (AB) Diff (BC) Diff (CA) However, it can also receive signals A, B, and C to generate the Diff signal. (AB) Diff (BC)Diff (CA) In this case, device 1 may further include: a receiving unit that receives signals A, B, and C; and a differential circuit unit that generates a signal Diff from the received signals A, B, and C. (AB) Diff (BC) Diff (CA) .
[0086] Furthermore, the above describes the case where device 1 is based on C-PHY, but it may also be non-C-PHY based. In this case, device 1 can acquire a plurality of signals of a different number than 3, and the Rise-side output unit 2 can output a Rise-side pulse in response to at least one rise of the plurality of signals, and the Fall-side output unit 3 can output a Fall-side pulse in response to at least one fall of the plurality of signals.
[0087] Furthermore, the above explains how to diff the signal. (AB) Diff (BC) Diff (CA) The maximum value of the rise and fall interval is taken as 0.4 times the length of the reference interval of the frequency pulse clk (UI in one example), but the reference interval can also be longer than 0.4 times. Even in this case, the reference pulse P rise P fall The reference width can also be the signal diff. (AB) Diff (BC) Diff (CA) The maximum value of the rise and fall interval is larger than the pulse width.
[0088] Furthermore, the above explains that the selection unit 5 selects the start and end edges of the leading pulse as the start and end edges of the frequency pulse clk. However, as long as the start edge of the leading pulse is selected as the start edge of the frequency pulse clk, the end edge of the leading pulse may not be selected as the end edge of the frequency pulse clk. For example, the selection unit 5 may generate a pulse that elongates the leading pulse, select the start edge of the leading pulse as the start edge of the frequency pulse clk, and use the end edge of the elongated pulse as the end edge of the frequency pulse clk.
[0089] Furthermore, the above describes how the detection unit 4 detects the Rise-side pulse and the Fall-side pulse, and detects the leading pulse that is output first among the Rise-side pulse and the Fall-side pulse. However, it can also detect the leading pulse by detecting the leading pulse that is output first among the third pulse and the fourth pulse of the third reference width. The third pulse is generated in response to the output Rise-side pulse, and the fourth pulse is generated in response to the output Fall-side pulse. In this case, the pulse detection unit 40 of the detection unit 4 can detect the third pulse and the fourth pulse respectively, and the invalidation unit 41 can invalidate the detection of the pulse detection unit 40 for the later output pulse when the third pulse and the fourth pulse partially overlap in each interval of the frequency pulse. Here, the third pulse and the fourth pulse can be generated by the output unit 2 or by the detection unit 4. In the interval of the frequency pulse clk, the signal Diff (AB) Diff (BC) Diff (CA) If the rise and fall are generated sequentially, the third reference width can be the pulse width where the third pulse and the fourth pulse at least partially overlap. Furthermore, the third reference width can be greater than the signal Diff that might be generated during the intervals of frequency pulse clk. (AB) Diff (BC) Diff (CA) The pulse width has a larger maximum value between the rise and fall intervals. Furthermore, the third reference width can be a pulse width larger than 0.4 times the reference interval of the frequency pulse clk. When the detection unit 4 detects the leading pulse by detecting the third and fourth pulses of the third reference width in this way, the pulse generators 20 and 30 can generate a reference pulse P with a reference width narrower than the third reference width. rise P fall As an example, the reference width of the third and fourth pulses can be 0.6UI, and the reference pulse P rise P fall The pulse width can be 0.25 μI.
[0090] The present invention has been described above using embodiments, but the scope of the present invention is not limited to the scope described in the above embodiments. Those skilled in the art will understand that various modifications or improvements can be made to the above embodiments. As can be understood from the claims, such modifications or improvements can also be included within the scope of the present invention.
[0091] It should be noted that the execution order of actions, sequences, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings can be implemented in any order, as long as it is not specifically stated that "before" or "beforehand," and as long as the output of the previous process is not used for the subsequent process. Even if the action flow in the claims, specifications, and drawings is described using terms such as "firstly," or "then," for convenience, it does not imply that it must be implemented in that specific order.
[0092] [Symbol Explanation]
[0093] 1: Device
[0094] 2: Rise side output section
[0095] 3: Fall-side output section
[0096] 4: Testing Department
[0097] 5: Selection Section
[0098] 6: Data Reading Department
[0099] 20: Pulse Generator
[0100] 21: OR logic gate
[0101] 30: Pulse Generator
[0102] 31: OR logic gate
[0103] 40: Pulse Detection Unit
[0104] 41: Invalidation Section
Claims
1. An edge selection device comprising: The first output unit outputs a first pulse in response to at least one rise of a plurality of signals; The second output unit outputs a second pulse in response to at least one decrease in the plurality of signals; The detection unit outputs a selection signal whenever it is in a non-detection state of a pulse and detects the leading pulse that is output first among the first pulse and the second pulse; and The selection unit, upon receiving the selection signal output by the detection unit, selects the edge of the preceding pulse detected by the detection unit as the edge of the frequency pulse contained in the frequency. The detection unit includes a invalidation unit that, when the first pulse and the second pulse partially overlap and are output in each interval of the frequency pulse, invalidates the detection of the later output pulse by the detection unit. By invalidating the selection signal through the invalidation section, the selection signal is made unaffected by the later output pulse.
2. The edge selection device as claimed in claim 1, wherein: The first output unit has: A plurality of first pulse generators, in response to the rise of any one of the plurality of signals, generate a reference pulse of the first reference width respectively; and The first OR logic gate outputs the first pulse as the logical sum of the reference pulses generated by each of the plurality of first pulse generators. The second output unit has: A plurality of second pulse generators, in response to a decrease in any of the signals among the plurality of signals, generate a reference pulse of the first reference width respectively; and The second OR logic gate outputs the second pulse as the logical sum of the reference pulses generated by each of the plurality of second pulse generators.
3. The edge selection device as claimed in claim 2, wherein: When the rise and fall of the plurality of signals are generated one by one during the interval of the frequency pulse, the first reference width is the pulse width in which at least a portion of the first pulse and the second pulse overlap.
4. The edge selection device as claimed in claim 2 or 3, wherein: The first reference width is a pulse width that is greater than the maximum value of the rise and fall intervals of the plurality of signals that can be generated in the interval of the frequency pulse.
5. The edge selection device as claimed in claim 2 or 3, wherein: The first reference width is a pulse width that is 0.4 times larger than the reference interval of the frequency pulse.
6. The edge selection device as claimed in claim 2 or 3, wherein: When two or more of the plurality of signals rise during the interval of the frequency pulses, the first reference width is the pulse width of one first pulse formed by overlapping portions of two or more reference pulses generated in response to each of the two or more signals; and when two or more of the plurality of signals fall during the interval of the frequency pulses, the first reference width is the pulse width of one second pulse formed by overlapping portions of two or more reference pulses generated in response to each of the two or more signals.
7. The edge selection device according to any one of claims 1 to 3, wherein: The detection unit also has: The pulse detection unit detects the first pulse and the second pulse output from the first output unit and the second output unit, respectively.
8. The edge selection device as claimed in claim 7, wherein: The detection unit detects the preceding pulse by detecting the first pulse generated among the third pulse of the third reference width and the fourth pulse of the third reference width, wherein the third pulse is generated in response to the output of the first pulse and the fourth pulse is generated in response to the output of the second pulse.
9. The edge selection device as claimed in claim 8, wherein: When the rise and fall of the plurality of signals are generated one by one during the interval of the frequency pulse, the third reference width is the pulse width in which at least a portion of the third pulse and the fourth pulse overlap.
10. The edge selection device as claimed in claim 8, wherein: The third reference width is a pulse width that is greater than the maximum value of the rise and fall intervals of the plurality of signals that can be generated in the interval of the frequency pulse.
11. The edge selection device as claimed in claim 8, wherein: The third reference width is a pulse width that is 0.4 times larger than the reference interval of the frequency pulse.
12. The edge selection device as claimed in claim 8, wherein: The detection unit further detects the third pulse and the fourth pulse respectively; The invalidation unit invalidates the detection of the later-output pulse by the detection unit when the third pulse and the fourth pulse partially overlap in each interval of the frequency pulse.
13. The edge selection device according to any one of claims 1 to 3, wherein: The plurality of signals are three differential signals derived from signals transmitted via three lines from the Channel Physical Layer (C-PHY) based on the Mobile Industrial Processor Interface (MIPI).