Vehicle control device and method therefor

Abstract

A vehicle control device and method thereof, wherein a main processor and a slave processor simultaneously receive, monitor or process signals of a vehicle, a power management module monitors the main processor through a first watchdog signal, and the main processor monitors the slave processor through a second watchdog signal. When the power management module sends the first watchdog signal to the main processor and no response message is received, the power management module sends a first reset signal to reset the main processor, and when the main processor sends the second watchdog signal to the slave processor and no response message is received, the main processor sends a second reset signal to reset the slave processor. When the power management module is abnormal, or both the main processor and the slave processor are abnormal, a forced wake-up module outputs a high potential signal to force the main processor and the slave processor to wake up.

Description

Technical Field

[0001] This invention relates to a vehicle control technology, and more particularly to a vehicle control device and method thereof. Background Technology

[0002] With the continuous development of vehicle electronic technology, the number of various intelligent vehicle control devices is increasing. However, in the confined installation space of a vehicle or in harsh environments, these control devices are easily affected by various factors (such as electromagnetic waves, temperature, humidity, noise, impact, aging, etc.) and may malfunction.

[0003] Furthermore, when the power management module malfunctions (e.g., a failure), the processor's reset pin will remain at a low level, causing the processor to malfunction or operate abnormally, and may even cause the vehicle control device or the entire system to shut down.

[0004] Therefore, how to provide an innovative vehicle control technology to solve any of the above problems has become a major research topic for those skilled in the art. Summary of the Invention

[0005] This invention provides an innovative vehicle control device and method, which can be composed of a power management module and a main processor to form a safety mechanism circuit to improve safety, monitoring, reset or forced wake-up capabilities; or composed of a main processor and a slave processor to form a safety mechanism circuit to double the system reliability or achieve a low failure rate; or composed of a first conversion module, a second conversion module and a comparison module to form a monitoring circuit to improve the system's judgment capability; or composed of a first logic circuit and a second logic circuit of a forced wake-up module to form a forced wake-up circuit to facilitate resetting or forcibly waking up the main processor and / or the slave processor.

[0006] The present invention provides a vehicle control device comprising: a power management module; a main processor and a slave processor, which simultaneously receive, monitor, or process at least one signal from the vehicle; the main processor being connected to both the power management module and the slave processor; the power management module monitoring the main processor via a first watchdog signal, and the main processor monitoring the slave processor via a second watchdog signal; wherein, when the power management module sends the first watchdog signal to the main processor and the main processor does not respond to the first watchdog signal, the power management module sends a first reset signal to the main processor to reset it; and when the main processor sends the second watchdog signal to the slave processor and the slave processor does not respond to the second watchdog signal, the main processor sends a second reset signal to the slave processor to reset it; and a forced wake-up module, which is connected to both the main processor and the slave processor; wherein, when the power management module is malfunctioning (abnormal operation), or when both the main processor and the slave processor are malfunctioning (abnormal operation), the forced wake-up module outputs a high-potential signal to the reset terminals of the main processor and the slave processor to forcibly wake up the main processor and the slave processor.

[0007] Another vehicle control device of the present invention includes: a power management module; a main processor and a slave processor, which simultaneously receive, monitor, or process at least one signal from the vehicle. The main processor and the slave processor dynamically adjust the frequencies of their respective output first pulse signal and second pulse signal based on the vehicle speed signal. The power management module monitors the main processor via a first watchdog signal, and the main processor monitors the slave processor via a second watchdog signal. When the power management module sends a first watchdog signal to the main processor, and the main processor does not respond to the first watchdog signal with a message to the power management module, the power management module... The system sends a first reset signal to the main processor to reset it. When the main processor sends a second watchdog signal to the slave processor, and the slave processor does not respond to the second watchdog signal to the main processor, the main processor sends a second reset signal to the slave processor to reset it. The system also includes a forced wake-up module, which is connected to the main processor and the slave processor respectively. When the power management module is abnormal (malfunctioning), or when both the main processor and the slave processor are abnormal (malfunctioning), the forced wake-up module outputs a high-level signal to the reset terminals of the main processor and the slave processor to forcibly wake up the main processor and the slave processor.

[0008] The vehicle control method of the present invention includes: providing a vehicle control device comprising a power management module, a main processor, a slave processor, and a forced wake-up module, wherein the main processor is connected to the power management module and the slave processor respectively, and the forced wake-up module is connected to the main processor and the slave processor respectively; the main processor and the slave processor simultaneously receive, monitor, or process at least one signal of the vehicle, such that the power management module monitors the main processor via a first watchdog signal, and the main processor monitors the slave processor via a second watchdog signal, wherein when the power management module sends the first watchdog signal to the main processor, and the main processor does not respond to the first watchdog signal... When the watchdog signal responds to the power management module, the power management module sends a first reset signal to the main processor to reset it. When the main processor sends a second watchdog signal to the slave processor, and the slave processor does not respond to the second watchdog signal to the main processor, the main processor sends a second reset signal to the slave processor to reset it. When the power management module is abnormal (malfunctioning), or when both the main processor and the slave processor are abnormal (malfunctioning), the forced wake-up module outputs a high-level signal to the reset terminals of the main processor and the slave processor to forcibly wake up the main processor and the slave processor.

[0009] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the first embodiment of the vehicle control device of the present invention.

[0011] Figure 2 This is a schematic diagram of a second embodiment of the vehicle control device of the present invention.

[0012] Figure 3 For the present invention Figure 2 The diagram shows the waveforms of the vehicle speed signal and the dynamic threshold voltage in the vehicle control device.

[0013] Figure 4 This is a schematic flowchart of the vehicle control method of the present invention.

[0014] In the attached figures, the following labels are used:

[0015] 1, 2: Vehicle control devices

[0016] 10: Power Management Module

[0017] 20: Main Processor

[0018] 30: From the processor

[0019] 40: First conversion module

[0020] 50: Second conversion module

[0021] 60: Comparison Module

[0022] 70: Forced wake-up module

[0023] 71: First Logic Circuit

[0024] 72: Second Logic Circuit

[0025] A: First safety mechanism circuit

[0026] B: Second security mechanism circuit

[0027] C1: First capacitor

[0028] C2: Second capacitor

[0029] C3: Third capacitor

[0030] D1: First diode

[0031] D2: Second diode

[0032] D3: Third diode

[0033] D4: Fourth diode

[0034] GND: Grounding

[0035] Out1, Out2, Out3: Output

[0036] P1: First pulse signal

[0037] P2: Second pulse signal

[0038] Pr: Power supply

[0039] Q1: First P-type transistor

[0040] Q2: Second P-type transistor

[0041] Q3: First N-type transistor

[0042] Q4: Second N-type transistor

[0043] Q5: Third P-type transistor

[0044] R1: First resistor

[0045] R2: Second resistor

[0046] R3: Third resistor

[0047] R4: Fourth resistor

[0048] R5: Fifth resistor

[0049] Re1: First reset signal

[0050] Re2: Second Reset Signal

[0051] S1 to S3: Steps

[0052] Sp: Vehicle Speed ​​Signal

[0053] Sv: signal

[0054] U1: First comparator

[0055] U2: Second comparator

[0056] V1: First voltage

[0057] V2: Second voltage

[0058] Vi: Initial voltage

[0059] Vt: Threshold voltage

[0060] W1: First watchdog signal

[0061] W2: Second watchdog signal. Detailed Implementation

[0062] The structural and working principles of the present invention will be described in detail below with reference to the accompanying drawings:

[0063] Figure 1 This is a schematic diagram of a first embodiment of the vehicle control device 1 of the present invention. As shown in the figure, the vehicle control device 1 may include a power management module 10, at least one master processor 20, at least one slave processor 30, a first conversion module 40, a second conversion module 50, a comparison module 60, and a forced wake-up module 70, wherein the forced wake-up module 70 may be composed of a first logic circuit 71 and a second logic circuit 72. Furthermore, in the present invention, "at least one" represents one or more (e.g., one, two, or three or more), "multiple" represents two or more (e.g., two, three, four, or ten or more), and "connected" represents electrical connection or signal connection, etc.

[0064] For example, the vehicle control device 1 can be a controller, control chip (chipset), or control circuit for a vehicle; the power management module 10 can be a power manager, power management chip (PMIC), or power management circuit. The main processor 20 can be a main microprocessor or main central processing unit (CPU), while the slave processor 30 can be a slave microprocessor or slave central processing unit (CPU). The first conversion module 40 or the second conversion module 50 can be a converter, conversion chip, or conversion circuit. The comparison module 60 can be a comparison chip or comparison circuit, and the first logic circuit 71 can be a NAND gate logic circuit or other types of logic circuits. However, the present invention is not limited thereto.

[0065] The power management module 10 can be connected to the main processor 20, the slave processor 30, the comparison module 60, and the forced wake-up module 70 (first logic circuit 71 and second logic circuit 72). The main processor 20 can be further connected to the slave processor 30, the first conversion module 40, or the forced wake-up module 70 (second logic circuit 72). The slave processor 30 can be further connected to the second conversion module 50 or the forced wake-up module 70 (second logic circuit 72). The first conversion module 40 and the second conversion module 50 can be further connected to the first comparator U1 and the second comparator U2 of the comparison module 60, respectively. The comparison module 60 can be further connected to the first logic circuit 71 of the forced wake-up module 70, and the first logic circuit 71 can be further connected to the second logic circuit 72. The power management module 10 can provide power Pr to the main processor 20, the slave processor 30, the first conversion module 40, the second conversion module 50, the comparison module 60, and the forced wake-up module 70 (first logic circuit 71 and second logic circuit 72), etc., and the power Pr may include one or more different power supplies such as 1.2 volts (V), 3.3 volts (V), 5 volts (V).

[0066] 1. The power management module 10 and the main processor 20 form a first security mechanism circuit A, which helps improve the security, monitoring, reset, or forced wake-up capabilities between the power management module 10 and the main processor 20. That is, the power management module 10 can monitor the main processor 20 through a first watchdog signal W1, and the first watchdog signal W1 can be a question-and-answer type watchdog signal, etc. When the power management module 10 sends the first watchdog signal W1 (for example, by sending a question through the first watchdog signal W1) to the main processor 20, and the main processor 20 does not respond to the first watchdog signal W1 with relevant information (for example, by not responding to the answer to the question) to the power management module 10, the power management module 10 will send a first reset signal Re1 to the main processor 20 to reset it.

[0067] When the power management module 10 supplies power Pr to the main processor 20, the main processor 20 can output a first pulse signal P1 with a fixed frequency to the first conversion module 40, and the first pulse signal P1 can be a pulse-width modulation (PWM) signal, etc. In addition, a first diode D1 can be provided between the power management module 10 and the reset terminal of the main processor 20, so as to control or limit the conduction direction of the first reset signal Re1 by means of the first diode D1, that is, to guide the first reset signal Re1 to the main processor 20 by means of the first diode D1, so as to prevent the first reset signal Re1 from being led back to the power management module 10, thereby avoiding the power management module 10 being short-circuited by the first reset signal Re1.

[0068] Second, the main processor 20 and the slave processor 30 form a second security mechanism circuit B, which helps to improve system reliability or achieve a low failure rate. That is, the main processor 20 and the slave processor 30 can simultaneously receive, monitor, or process at least one (or more) signals Sv from the vehicle based on a dual security mechanism or a redundancy security mechanism, so as to double the system reliability or achieve a low failure rate. For example, the vehicle signal Sv can be various vehicle body signals or sensing signals such as throttle signal, brake signal, headlight signal, vehicle temperature signal, oil temperature signal, fuel level signal, coolant temperature signal, and coolant level signal, and the vehicle can be a car, electric vehicle, bus (such as an electric bus), motorcycle (such as an electric motorcycle), etc., but is not limited thereto.

[0069] The main processor 20 can monitor the slave processor 30 via a second watchdog signal W2, which can be a question-and-answer type watchdog signal, etc. When the main processor 20 sends the second watchdog signal W2 (e.g., sends a question via the second watchdog signal W2) to the slave processor 30, and the slave processor 30 does not respond to the second watchdog signal W2 with a related message (e.g., does not provide an answer to the question) to the main processor 20, the main processor 20 will send a second reset signal Re2 to the slave processor 30 to reset it.

[0070] When the power management module 10 supplies power Pr to the slave processor 30, the slave processor 30 can output a second pulse signal P2 with a fixed frequency to the second conversion module 50, and the second pulse signal P2 can be a pulse width modulation (PWM) signal, etc. In addition, a second diode D2 can be provided between the reset terminals of the master processor 20 and the slave processor 30, so as to control or limit the conduction direction of the second reset signal Re2 by means of the second diode D2, that is, to guide the second reset signal Re2 to the slave processor 30 by means of the second diode D2, so as to prevent the second reset signal Re2 from being conducted back to the master processor 20, thereby avoiding the master processor 20 from being short-circuited by the second reset signal Re2.

[0071] Third, the monitoring circuit composed of the first conversion module 40, the second conversion module 50, and the comparison module 60 is beneficial for determining whether the output Out1 of the first comparator U1 and the output Out2 of the second comparator U2 are at a high potential (H) or a low potential (L), and can also effectively improve the system's judgment capability. That is, the first conversion module 40 may have a first resistor R1 and a first capacitor C1 connected (e.g., in parallel) to form a first conversion circuit, so as to convert the first pulse signal P1 with a fixed frequency output by the main processor 20 into a first voltage V1 with a fixed voltage value through the first conversion module 40 (e.g., the first conversion circuit composed of the first resistor R1 and the first capacitor C1). At the same time, the second conversion module 50 may have a second resistor R2 and a second capacitor C2 connected (e.g., in parallel) to form a second conversion circuit, so as to convert the second pulse signal P2 with a fixed frequency output by the processor 30 into a second voltage V2 with a fixed voltage value through the second conversion module 50 (e.g., the second conversion circuit composed of the second resistor R2 and the second capacitor C2).

[0072] The comparison module 60 may have a third resistor R3 and a fourth resistor R4 connected to each other (e.g., in parallel) to form a voltage divider circuit. The third resistor R3 and the fourth resistor R4 may have the same or different resistance values, so that the voltage from the power supply Pr from the power management module 10 can be divided into a threshold voltage Vt with a fixed voltage value through the voltage divider circuit formed by the third resistor R3 and the fourth resistor R4.

[0073] The comparison module 60 may have a first comparator U1 and a second comparator U2, and may also selectively provide a third diode D3 between a third resistor R3 and a fourth resistor R4, so that the threshold voltage Vt of the power supply Pr and its current are directed to both the first comparator U1 and the second comparator U2 by the third diode D3. Moreover, the third diode D3 may be connected to the first input terminal (e.g., the positive input terminal "+") of the first comparator U1 and the first input terminal (e.g., the positive input terminal "+") of the second comparator U2, so that both the first input terminal (e.g., the positive input terminal "+") of the first comparator U1 and the first input terminal (e.g., the positive input terminal "+") of the second comparator U2 have a threshold voltage Vt.

[0074] The first conversion module 40 (such as a first conversion circuit composed of a first resistor R1 and a first capacitor C1) can be connected to the second input terminal (such as the negative input terminal "-") of the first comparator U1, so that the second input terminal (such as the negative input terminal "-") of the first comparator U1 has the first voltage V1 converted by the first conversion module 40. At the same time, the second conversion module 50 (such as a second conversion circuit composed of a second resistor R2 and a second capacitor C2) can be connected to the second input terminal (such as the negative input terminal "-") of the second comparator U2, so that the second input terminal (such as the negative input terminal "-") of the second comparator U2 has the second voltage V2 converted by the second conversion module 50.

[0075] When the first comparator U1 determines that the first voltage V1 is less than the threshold voltage Vt, its output Out1 is high (H); and when the first comparator U1 determines that the first voltage V1 is greater than the threshold voltage Vt, its output is low (L). Similarly, when the second comparator U2 determines that the second voltage V2 is less than the threshold voltage Vt, its output is high (H); and when the second comparator U2 determines that the second voltage V2 is greater than the threshold voltage Vt, its output is low (L).

[0076] IV. The first logic circuit 71 and the second logic circuit 72 of the forced wake-up module 70 constitute a forced wake-up circuit, which is beneficial for resetting or forcibly waking up one or both of the main processor 20 and the slave processor 30. For example, the first logic circuit 71 may have a first P-type transistor Q1, a second P-type transistor Q2, a first N-type transistor Q3, and a second N-type transistor Q4, etc., while the second logic circuit 72 may have a third P-type transistor Q5, etc. The first logic circuit 71 may be a NAND gate logic circuit, etc., the first P-type transistor Q1, the second P-type transistor Q2, or the third P-type transistor Q5 may be a P-type MOSFET, etc., and the first N-type transistor Q3 or the second N-type transistor Q4 may be an N-type MOSFET, etc.

[0077] The output of the first comparator U1 is connected to the gate of the first P-type transistor Q1 and the gate of the first N-type transistor Q3. The output of the second comparator U2 is connected to the gate of the second P-type transistor Q2 and the gate of the second N-type transistor Q4. The sources of the first P-type transistor Q1 and the second P-type transistor Q2 are both connected to the power supply Pr of the power management module 10. The drains of the first P-type transistor Q1, the second P-type transistor Q2, and the first N-type transistor Q3 are all connected to the gate of the third P-type transistor Q5. The source of the first N-type transistor Q3 is connected to the drain of the second N-type transistor Q4. The source of the second N-type transistor Q4 is connected to ground (GND). The source of the third P-type transistor Q5 is connected to the power supply Pr of the power management module 10. The drain of the third P-type transistor Q5 is connected to the reset terminal of the main processor 20 and the reset terminal of the slave processor 30.

[0078] For example, when the output Out3 of the first logic circuit 71 is at a high potential (H), the third P-type transistor Q5 is turned off. Therefore, the power supply Pr will not flow from the source to the drain of the third P-type transistor Q5, and will not affect the first reset signal Re1 and the second reset signal Re2. Conversely, when the output Out3 of the first logic circuit 71 is at a low potential (L), the third P-type transistor Q5 is turned on. Therefore, the power supply Pr of the power management module 10 will flow from the source to the drain of the third P-type transistor Q5, causing the forced wake-up module 70 or the second logic circuit 72 to output a high potential (H) signal to the reset terminals of the main processor 20 and the slave processor 30 to forcibly wake up the main processor 20 and the slave processor 30.

[0079] The following will be explained according to: [1] the first situation is that both the main processor 20 and the slave processor 30 are operating normally; [2] the second situation is that one of the main processor 20 and the slave processor 30 is abnormal (not operating normally); [3] the third situation is that both the main processor 20 and the slave processor 30 are abnormal (not operating normally) or the power management module 10 is abnormal (not operating normally), and the input / output table of the three situations shown in Table 1 below will be used for explanation.

[0080] Table 1: Input / output table for three states. Taking the first logic circuit 71 as a NAND gate logic circuit as an example, the low potential (L) and high potential (H) in the input / output table for the following three states can correspond to logic "0" and logic "1" in the truth table of the NAND gate, respectively.

[0081]

[0082] [1] The first situation is that both the main processor 20 and the slave processor 30 are operating normally. When both the main processor 20 and the slave processor 30 are operating normally, the main processor 20 and the slave processor 30 output the first pulse signal P1 and the second pulse signal P2 normally, respectively. The first voltage V1 converted by the first conversion module 40 (such as the first conversion circuit composed of the first resistor R1 and the first capacitor C1) and the second voltage V2 converted by the second conversion module 50 (such as the second conversion circuit composed of the second resistor R2 and the second capacitor C2) are both greater than the threshold voltage Vt, and the outputs Out1 of the first comparator U1 and Out2 of the second comparator U2 are both at low potential (L). Therefore, the output of the first logic circuit 71 is at high potential (H), and the third P-type transistor Q5 of the second logic circuit 72 is turned off. Therefore, the power supply Pr will not reach the drain from the source of the third P-type transistor Q5, and will not affect the first reset signal Re1 and the second reset signal Re2.

[0083] [2] The second situation is that one of the main processor 20 and the slave processor 30 is abnormal (malfunctioning). When one of the main processor 20 and the slave processor 30 is abnormal (such as a fault occurs), the main processor 20 and the slave processor 30 abnormally output one of the corresponding first pulse signal P1 and second pulse signal P2, and the output of the first pulse signal P1 and the second pulse signal P2 is low potential (L).

[0084] One of the first voltage V1 converted by the first conversion module 40 (such as the first conversion circuit composed of the first resistor R1 and the first capacitor C1) and the second voltage V2 converted by the second conversion module 50 (such as the second conversion circuit composed of the second resistor R2 and the second capacitor C2) can be zero voltage (0V) or close to zero voltage and less than the threshold voltage Vt. One of the outputs Out1 of the first comparator U1 and Out2 of the second comparator U2 is low potential (L). Therefore, the output Out3 of the first logic circuit 71 is high potential (H), and the third P-type transistor Q5 of the second logic circuit 72 is turned off. Thus, the power supply Pr will not flow from the source to the drain of the third P-type transistor Q5, and will not affect the first reset signal Re1 and the second reset signal Re2.

[0085] If the main processor 20 malfunctions, the power management module 10 can obtain information that the main processor 20 is in an abnormal state through the first watchdog signal W1 (for example, the power management module 10 learns that the main processor 20 has not responded to the question posed by the first watchdog signal W1 and is therefore in an abnormal state), and the power management module 10 sends a first reset signal Re1 to the main processor 20 to reset it. Conversely, if the slave processor 30 malfunctions, the main processor 20 can obtain information that the slave processor 30 is in an abnormal state through the second watchdog signal W2 (for example, the main processor 20 learns that the slave processor 30 has not responded to the question posed by the second watchdog signal W2 and is therefore in an abnormal state), and the main processor 20 sends a second reset signal Re2 to the slave processor 30 to reset it.

[0086] [3] The third situation is that the power management module 10 is abnormal (malfunctioning) or both the main processor 20 and the slave processor 30 are abnormal (malfunctioning). When the power management module 10 is abnormal (such as a system crash), or both the main processor 20 and the slave processor 30 are abnormal (such as a malfunction), the reset terminals of the main processor 20 and the slave processor 30 are both at low potential (L), the output of the first pulse signal P1 and the output of the second pulse signal P2 are both at low potential (L), the first voltage V1 converted by the first conversion module 40 (such as the first conversion circuit composed of the first resistor R1 and the first capacitor C1) and the second voltage V2 converted by the second conversion module 50 (such as the second conversion circuit composed of the second resistor R2 and the second capacitor C2) are both at zero voltage (0V) or close to zero voltage and less than the threshold voltage Vt, and the outputs Out1 of the first comparator U1 and Out2 of the second comparator U2 are both at high potential (H). Therefore, the output Out3 of the first logic circuit 71 is at a low potential (L), and the third P-type transistor Q5 of the second logic circuit 72 is turned on. Thus, the power supply Pr of the power management module 10 will flow from the source to the drain of the third P-type transistor Q5, causing the forced wake-up module 70 or the second logic circuit 72 to output a high potential (H) signal to the reset terminal of the main processor 20 and the reset terminal of the slave processor 30 to forcibly wake up the main processor 20 and the slave processor 30.

[0087] Figure 2 This is a schematic diagram of a second embodiment of the vehicle control device 2 of the present invention. Figure 3 For the present invention Figure 2 The diagram shows the waveforms of the vehicle speed signal Sp and the dynamic threshold voltage Vt in the vehicle control device 2. The vehicle control device 2 is related to the aforementioned... Figure 1The main difference between the vehicle control device 1 and the vehicle control device 2 is that the vehicle control device 2 can dynamically adjust the frequencies (e.g., frequency-speed) of the first pulse signal P1 and the second pulse signal P2 based on the vehicle speed signal Sp, or dynamically adjust the threshold voltage Vt of the first comparator U1 and the second comparator U2 based on the vehicle speed signal Sp. Meanwhile, the main contents of the vehicle control device 2 are as follows, and the rest are the same as described above. Figure 1 The explanation of the author will not be repeated here.

[0088] like Figure 2 As shown, the vehicle control device 2 may include a power management module 10, at least one main processor 20, at least one slave processor 30, a first conversion module 40, a second conversion module 50, a comparison module 60, and a forced wake-up module 70. The forced wake-up module 70 may be composed of a first logic circuit 71 and a second logic circuit 72. Furthermore, the vehicle control device 2 or the comparison module 60 may further include a third capacitor C3, a fourth diode D4, and a fifth resistor R5, and be able to receive the vehicle speed signal Sp.

[0089] The power management module 10 can be connected to the main processor 20, the slave processor 30, the comparator module 60, and the forced wake-up module 70 (first logic circuit 71 and second logic circuit 72). The main processor 20 can be further connected to the slave processor 30, the first conversion module 40, or the forced wake-up module 70 (second logic circuit 72). The slave processor 30 can be further connected to the second conversion module 50 or the forced wake-up module 70 (second logic circuit 72). The first conversion module 40 and the second conversion module 50 can be further connected to the first comparator U1 and the second comparator U2 of the comparator module 60, respectively. The comparator module 60 can be further connected to the first logic circuit 71 of the forced wake-up module 70, and the first logic circuit 71 can be further connected to the second logic circuit 72. The power management module 10 can provide power Pr to the main processor 20, the slave processor 30, the first conversion module 40, the second conversion module 50, the comparator module 60, and the forced wake-up module 70 (first logic circuit 71 and second logic circuit 72).

[0090] I. The power management module 10 and the main processor 20 form a first security mechanism circuit A, which helps to improve the security, monitoring, reset, or forced wake-up capabilities between the power management module 10 and the main processor 20. The power management module 10 can monitor the main processor 20 through a first watchdog signal W1, and the first watchdog signal W1 can be a question-and-answer type watchdog signal, etc. When the power management module 10 sends the first watchdog signal W1 (for example, by sending a question through the first watchdog signal W1) to the main processor 20, and the main processor 20 does not respond to the first watchdog signal W1 with relevant information (for example, by not responding to the answer to the question) to the power management module 10, the power management module 10 will send a first reset signal Re1 to the main processor 20 to reset it.

[0091] When the power management module 10 supplies power Pr to the main processor 20, the main processor 20 can dynamically adjust the frequency (e.g., frequency speed) of the first pulse signal P1 output by the main processor 20 according to the vehicle speed signal Sp (vehicle speed) to transmit the first pulse signal P1 to the first conversion module 40, and the first pulse signal P1 can be a pulse width modulation (PWM) signal, etc. For example, the main processor 20 can dynamically increase the frequency (e.g., frequency speed) of the first pulse signal P1 according to the increase of the vehicle speed signal Sp (vehicle speed), or dynamically decrease the frequency (e.g., frequency speed) of the first pulse signal P1 according to the decrease of the vehicle speed signal Sp (vehicle speed). In addition, a first diode D1 can be provided between the power management module 10 and the reset terminal of the main processor 20 to control or limit the conduction direction of the first reset signal Re1. That is, the first diode D1 guides the first reset signal Re1 to the main processor 20 to prevent the first reset signal Re1 from being led back to the power management module 10, thereby avoiding the power management module 10 from being short-circuited by the first reset signal Re1.

[0092] Second, the main processor 20 and the slave processor 30 form a second security mechanism circuit B, which helps to improve system reliability or achieve a low failure rate. That is, the main processor 20 and the slave processor 30 can simultaneously receive, monitor or process at least one (or more) signals Sv from the vehicle based on a dual security mechanism or a redundant security mechanism, so as to double the system reliability or achieve a low failure rate.

[0093] The main processor 20 can monitor the slave processor 30 via a second watchdog signal W2, which can be a question-and-answer type watchdog signal, etc. When the main processor 20 sends the second watchdog signal W2 (e.g., sends a question via the second watchdog signal W2) to the slave processor 30, and the slave processor 30 does not respond to the second watchdog signal W2 with a related message (e.g., does not provide an answer to the question) to the main processor 20, the main processor 20 will send a second reset signal Re2 to the slave processor 30 to reset it.

[0094] When the power management module 10 provides power Pr to the slave processor 30, the slave processor 30 can dynamically adjust the frequency (e.g., frequency speed) of the second pulse signal P2 output by the slave processor 30 according to the vehicle speed signal Sp (vehicle speed) to transmit the second pulse signal P2 to the second conversion module 50. The second pulse signal P2 and the vehicle speed signal Sp can be a pulse width modulation (PWM) signal and a vehicle speed pulse signal, respectively. For example, the slave processor 30 can dynamically increase the frequency (e.g., frequency speed) of the second pulse signal P2 according to the increase of the vehicle speed signal Sp (vehicle speed), or dynamically decrease the frequency (e.g., frequency speed) of the second pulse signal P2 according to the decrease of the vehicle speed signal Sp (vehicle speed). In addition, a second diode D2 can be provided between the reset terminals of the main processor 20 and the slave processor 30 to control or limit the conduction direction of the second reset signal Re2. That is, the second diode D2 guides the second reset signal Re2 to the slave processor 30 to prevent the second reset signal Re2 from being conducted back to the main processor 20, thereby avoiding the main processor 20 from being short-circuited by the second reset signal Re2.

[0095] Third, the first conversion module 40, the second conversion module 50 and the comparison module 60 form a monitoring circuit, which is helpful in determining whether the output Out1 of the first comparator U1 and the output Out2 of the second comparator U2 are at a high potential (H) or a low potential (L), and can also effectively improve the system's judgment capability.

[0096] The first conversion module 40 may have a first resistor R1 and a first capacitor C1 connected (e.g., in parallel) to form a first conversion circuit, which converts the first pulse signal P1 with a dynamic frequency output by the main processor 20 into a first voltage V1 with a dynamic voltage value (i.e., an adjustable voltage value or a non-fixed voltage value). Simultaneously, the second conversion module 50 may have a second resistor R2 and a second capacitor C2 connected (e.g., in parallel) to form a second conversion circuit, which converts the second pulse signal P2 with a dynamic frequency output by the processor 30 into a second voltage V2 with a dynamic voltage value (i.e., an adjustable voltage value or a non-fixed voltage value).

[0097] The comparison module 60 may have a third resistor R3 and a fourth resistor R4 connected (e.g., in parallel) to form a voltage divider circuit. The third resistor R3 and the fourth resistor R4 may have the same or different resistance values, so that the voltage from the power supply Pr of the power management module 10 can be divided into an initial voltage Vi (e.g., ...) through the voltage divider circuit formed by the third resistor R3 and the fourth resistor R4. Figure 3The voltage range from 0V to 1V is used as the initial threshold voltage Vt.

[0098] The comparison module 60 may have a first comparator U1 and a second comparator U2, and may also selectively provide a third diode D3 between a third resistor R3 and a fourth resistor R4, so that the threshold voltage Vt of the power supply Pr and its current are directed to the first comparator U1 and the second comparator U2 by means of the third diode D3, and the third diode D3 may be connected to the first input terminal (such as the positive input terminal "+") of the first comparator U1 and the first input terminal (such as the positive input terminal "+") of the second comparator U2 respectively.

[0099] For example, when the vehicle control device 2 or the comparator module 60 has not yet received the vehicle speed signal Sp (e.g., the vehicle speed is zero), the voltage from the power supply Pr of the power management module 10 can be divided into an initial voltage Vi (e.g., the speed is zero) by a voltage divider circuit composed of the third resistor R3 and the fourth resistor R4. Figure 3 The initial threshold voltage Vt is set as a voltage between 0V and 1V. The first input terminal (e.g., positive input "+") of the first comparator U1 and the first input terminal (e.g., positive input "+") of the second comparator U2 are initially set as the threshold voltage Vt using the initial voltage Vi. Then, when the vehicle control device 2 or the comparator module 60 receives the vehicle speed signal Sp (e.g., the vehicle speed is not zero), the vehicle speed signal Sp is transmitted through a fourth diode D4 to a third conversion circuit composed of a fifth resistor R5 and a third capacitor C3. This third conversion circuit converts the vehicle speed signal Sp into a threshold voltage Vt with a dynamic voltage value (i.e., an adjustable voltage value or a non-fixed voltage value). The dynamic voltage value of this threshold voltage Vt increases as the vehicle speed signal Sp increases, causing the threshold voltage Vt to change from the initial voltage Vi (e.g., a voltage between 0V and 1V) to a threshold voltage Vt. Figure 3 The voltage range of 0V to 1V is dynamically adjusted to a higher threshold voltage (e.g., ...). Figure 3 (The voltage is above 1V). Subsequently, the dynamic voltage value of this threshold voltage Vt can increase as the vehicle speed signal Sp increases, or decrease as the vehicle speed signal Sp decreases and remains above the initial voltage Vi (such as a voltage above 1V).

[0100] The first conversion module 40 (such as a first conversion circuit composed of a first resistor R1 and a first capacitor C1) can be connected to the second input terminal (such as the negative input terminal "-") of the first comparator U1, so that the second input terminal (such as the negative input terminal "-") of the first comparator U1 has a first voltage V1 with a dynamic voltage value converted by the first conversion module 40 (such as the first conversion circuit composed of a first resistor R1 and a first capacitor C1). At the same time, the second conversion module 50 (such as a second conversion circuit composed of a second resistor R2 and a second capacitor C2) can be connected to the second input terminal (such as the negative input terminal "-") of the second comparator U2, so that the second input terminal (such as the negative input terminal "-") of the second comparator U2 has a second voltage V2 with a dynamic voltage value converted by the second conversion module 50 (such as the second conversion circuit composed of a second resistor R2 and a second capacitor C2).

[0101] When the first comparator U1 determines that the first voltage V1 is less than the threshold voltage Vt, its output Out1 is high (H); and when the first comparator U1 determines that the first voltage V1 is greater than the threshold voltage Vt, its output is low (L). Similarly, when the second comparator U2 determines that the second voltage V2 is less than the threshold voltage Vt, its output is high (H); and when the second comparator U2 determines that the second voltage V2 is greater than the threshold voltage Vt, its output is low (L).

[0102] IV. The first logic circuit 71 and the second logic circuit 72 of the forced wake-up module 70 constitute a forced wake-up circuit, which is beneficial for resetting or forcibly waking up one or both of the main processor 20 and the slave processor 30. For example, the first logic circuit 71 may have a first P-type transistor Q1, a second P-type transistor Q2, a first N-type transistor Q3, and a second N-type transistor Q4, etc., while the second logic circuit 72 may have a third P-type transistor Q5, etc. The first logic circuit 71 may be a NAND gate logic circuit, etc., the first P-type transistor Q1, the second P-type transistor Q2, or the third P-type transistor Q5 may be a P-type MOSFET, etc., and the first N-type transistor Q3 or the second N-type transistor Q4 may be an N-type MOSFET, etc.

[0103] The output of the first comparator U1 is connected to the gate of the first P-type transistor Q1 and the gate of the first N-type transistor Q3. The output of the second comparator U2 is connected to the gate of the second P-type transistor Q2 and the gate of the second N-type transistor Q4. The sources of the first P-type transistor Q1 and the second P-type transistor Q2 are both connected to the power supply Pr of the power management module 10. The drains of the first P-type transistor Q1, the second P-type transistor Q2, and the first N-type transistor Q3 are all connected to the gate of the third P-type transistor Q5. The source of the first N-type transistor Q3 is connected to the drain of the second N-type transistor Q4. The source of the second N-type transistor Q4 is connected to ground GND. The source of the third P-type transistor Q5 is connected to the power supply Pr of the power management module 10. The drain of the third P-type transistor Q5 is connected to the reset terminal of the main processor 20 and the reset terminal of the slave processor 30.

[0104] For example, when the output Out3 of the first logic circuit 71 is at a high level (H), the third P-type transistor Q5 is turned off. Therefore, the power supply Pr of the power management module 10 will not flow from the source to the drain of the third P-type transistor Q5, and will not affect the first reset signal Re1 and the second reset signal Re2. Conversely, when the output Out3 of the first logic circuit 71 is at a low level (L), the third P-type transistor Q5 is turned on to output a high-level (L) signal to the reset terminals of the main processor 20 and the slave processor 30, thereby forcibly waking up the main processor 20 and the slave processor 30.

[0105] The following will be explained according to: [1] the first situation is that both the main processor 20 and the slave processor 30 are operating normally; [2] the second situation is that one of the main processor 20 and the slave processor 30 is abnormal (not operating normally); [3] the third situation is that the power management module 10 is abnormal (not operating normally) or both the main processor 20 and the slave processor 30 are abnormal (not operating normally), and the input / output table of the three situations shown in Table 1 above will be used for explanation.

[0106] [1] The first situation is that both the main processor 20 and the slave processor 30 are operating normally. When both the main processor 20 and the slave processor 30 are operating normally, the main processor 20 and the slave processor 30 output the first pulse signal P1 and the second pulse signal P2 normally, respectively. The first voltage V1 converted by the first conversion module 40 (such as the first conversion circuit composed of the first resistor R1 and the first capacitor C1) and the second voltage V2 converted by the second conversion module 50 (such as the second conversion circuit composed of the second resistor R2 and the second capacitor C2) are both greater than the threshold voltage Vt, and the outputs Out1 of the first comparator U1 and Out2 of the second comparator U2 are both at low potential (L). Therefore, the output of the first logic circuit 71 is at high potential (H), and the third P-type transistor Q5 of the second logic circuit 72 is turned off. Therefore, the power supply Pr of the power management module 10 will not reach the drain from the source of the third P-type transistor Q5, and will not affect the first reset signal Re1 and the second reset signal Re2.

[0107] [2] The second situation is that one of the main processor 20 and the slave processor 30 is abnormal (malfunctioning). When one of the main processor 20 and the slave processor 30 is abnormal (such as a malfunction), the main processor 20 and the slave processor 30 abnormally output one of the corresponding first pulse signal P1 and second pulse signal P2, and the output of one of the first pulse signal P1 and the second pulse signal P2 is low potential (L) or lower than the frequency threshold value. One of the first voltage V1 converted by the first conversion module 40 (such as the first conversion circuit composed of the first resistor R1 and the first capacitor C1) and the second voltage V2 converted by the second conversion module 50 (such as the second conversion circuit composed of the second resistor R2 and the second capacitor C2) can be zero voltage (0V) or close to zero voltage and less than the threshold voltage Vt, and one of the outputs Out1 of the first comparator U1 and Out2 of the second comparator U2 is low potential (L). Therefore, the output Out3 of the first logic circuit 71 is at a high potential (H), and the third P-type transistor Q5 of the second logic circuit 72 is turned off. Thus, the power supply Pr of the power management module 10 will not reach the drain from the source of the third P-type transistor Q5, nor will it affect the first reset signal Re1 and the second reset signal Re2.

[0108] If the main processor 20 malfunctions, the power management module 10 can obtain information that the main processor 20 is in an abnormal state through the first watchdog signal W1 (for example, the power management module 10 learns that the main processor 20 has not responded to the question posed by the first watchdog signal W1 and is therefore in an abnormal state), and the power management module 10 sends a first reset signal Re1 to the main processor 20 to reset it. Conversely, if the slave processor 30 malfunctions, the main processor 20 can obtain information that the slave processor 30 is in an abnormal state through the second watchdog signal W2 (for example, the main processor 20 learns that the slave processor 30 has not responded to the question posed by the second watchdog signal W2 and is therefore in an abnormal state), and the main processor 20 sends a second reset signal Re2 to the slave processor 30 to reset it.

[0109] [3] The third situation is that the power management module 10 is abnormal (malfunctioning) or both the main processor 20 and the slave processor 30 are abnormal (malfunctioning). When the power management module 10 is abnormal (such as a system crash), or both the main processor 20 and the slave processor 30 are abnormal (such as a malfunction), the reset terminals of the main processor 20 and the slave processor 30 are both at low potential (L), the output of the first pulse signal P1 and the output of the second pulse signal P2 are both at low potential (L) or below the frequency threshold value, the first voltage V1 converted by the first conversion module 40 (such as the first conversion circuit composed of the first resistor R1 and the first capacitor C1) and the second voltage V2 converted by the second conversion module 50 (such as the second conversion circuit composed of the second resistor R2 and the second capacitor C2) can both be zero voltage (0V) or close to zero voltage and less than the threshold voltage Vt, and the outputs Out1 of the first comparator U1 and Out2 of the second comparator U2 are both at high potential (H). Therefore, the output Out3 of the first logic circuit 71 is at a low potential (L), and the third P-type transistor Q5 of the second logic circuit 72 is turned on. Thus, the power supply Pr of the power management module 10 will flow from the source to the drain of the third P-type transistor Q5, causing the forced wake-up module 70 or the second logic circuit 72 to output a high potential (H) signal to the reset terminal of the main processor 20 and the reset terminal of the slave processor 30 to forcibly wake up the main processor 20 and the slave processor 30.

[0110] Figure 4 This is a schematic flowchart of the vehicle control method of the present invention, and refers to... Figure 1 or Figure 2 This will be explained. The main contents of this vehicle control method are as follows; the rest are the same as described above. Figure 1 or Figure 2 The explanation will not be repeated here.

[0111] like Figure 4Step S1 and Figures 1 to 2 As shown, a vehicle control device 1(2) is provided, including a power management module 10, a main processor 20, a slave processor 30 and a forced wake-up module 70. The main processor 20 is connected to the power management module 10 and the slave processor 30 respectively, and the forced wake-up module 70 is connected to the main processor 20 and the slave processor 30 respectively.

[0112] like Figure 4 Step S2 and Figures 1 to 2 As shown, the main processor 20 and the slave processor 30 simultaneously receive, monitor, or process at least one (or more) signals Sv from the vehicle. The power management module 10 monitors the main processor 20 via a first watchdog signal W1, and the main processor 20 monitors the slave processor 30 via a second watchdog signal W2. When the power management module 10 sends the first watchdog signal W1 to the main processor 20, and the main processor 20 does not respond to the first watchdog signal W1, the power management module 10 sends a first reset signal Re1 to the main processor 20 to reset it. When the main processor 20 sends the second watchdog signal W2 to the slave processor 30, and the slave processor 30 does not respond to the second watchdog signal W2, the main processor 20 sends a second reset signal Re2 to the slave processor 30 to reset it.

[0113] like Figure 4 Step S3 and Figures 1 to 2 As shown, when the power management module 10 is abnormal (malfunctioning), or when both the main processor 20 and the slave processor 30 are abnormal (malfunctioning), the forced wake-up module 70 outputs a high potential (H) signal to the reset terminals of the main processor 20 and the slave processor 30 to forcibly wake up the main processor 20 and the slave processor 30.

[0114] like Figure 2 As shown, when the vehicle control device 2 has received the vehicle speed signal Sv, the conversion circuit composed of the fifth resistor R5 and the third capacitor C3 converts the vehicle speed signal Sv into a threshold voltage Vt with a dynamic voltage value. The dynamic voltage value of the threshold voltage Vt increases as the vehicle speed signal Sv increases or decreases as the vehicle speed signal Sv decreases.

[0115] like Figures 1 to 2As shown, when either the main processor 20 or the slave processor 30 malfunctions, the main processor 20 or the slave processor 30 outputs one of the corresponding first pulse signal P1 and second pulse signal P2, and the output of either the first pulse signal P1 or the second pulse signal P2 is at a low potential (H). If the main processor 20 malfunctions, the power management module 10 sends a first reset signal Re1 to the main processor 20 to reset it. If the slave processor 30 malfunctions, the main processor 20 sends a second reset signal Re2 to the slave processor 30 to reset it.

[0116] In summary, the vehicle control device and method of the present invention have at least the following features, advantages or technical effects.

[0117] I. The power management module of the present invention forms a security mechanism circuit with the main processor, which is beneficial to improving the security, monitoring, reset or forced wake-up capabilities between the power management module and the main processor.

[0118] Second, the main processor and the slave processor of the present invention form a security mechanism circuit, which can simultaneously receive, monitor or process various signals of the vehicle based on dual security mechanisms or redundant security mechanisms, so as to double the system reliability or achieve a low failure rate.

[0119] Third, the first conversion module, the second conversion module and the comparison module of the present invention form a monitoring circuit, which is beneficial to determine whether the output of the first comparator and the output of the second comparator are at a high potential or a low potential, and can also effectively improve the system's judgment capability.

[0120] IV. The first logic circuit and the second logic circuit of the forced wake-up module of the present invention constitute a forced wake-up circuit, which is beneficial for resetting or forcibly waking up the main processor and / or the slave processor.

[0121] Fifth, this invention can solve the problem that the main processor, slave processor or power management module is easily affected by various factors (such as electromagnetic waves, temperature, humidity, noise, impact, aging, etc.) in the harsh environment of the vehicle, which can cause abnormalities (such as malfunctions).

[0122] VI. This invention can improve system reliability or achieve a low failure rate, meet the requirements of various safety standards (such as ISO26262), and has the advantages of small circuit area and low cost.

[0123] VII. The present invention can dynamically adjust the threshold voltage of the first comparator and the second comparator according to the vehicle speed signal, so as to help determine whether the main processor or the slave processor can operate normally or process the first / second pulse signal in a timely manner by means of dynamic threshold voltage.

[0124] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A vehicle control device, characterized in that, include: Power management module; A main processor and a slave processor simultaneously receive, monitor, or process at least one signal from the vehicle. The main processor is connected to both the power management module and the slave processor. The power management module monitors the main processor via a first watchdog signal, and the main processor monitors the slave processor via a second watchdog signal. When the power management module sends the first watchdog signal to the main processor, and the main processor does not respond to the first watchdog signal, the power management module sends a first reset signal to the main processor to reset it. Conversely, when the main processor sends the second watchdog signal to the slave processor, and the slave processor does not respond to the second watchdog signal, the main processor sends a second reset signal to the slave processor to reset it. A forced wake-up module is connected to the main processor and the slave processor respectively. When the power management module is abnormal, or when both the main processor and the slave processor are abnormal, the forced wake-up module outputs a high-potential signal to the reset terminals of the main processor and the slave processor to forcibly wake up the main processor and the slave processor.

2. The vehicle control device as described in claim 1, characterized in that, It also includes a first diode disposed between the power management module and the reset terminal of the main processor, so as to control or limit the conduction direction of the first reset signal by means of the first diode, wherein the first diode directs the first reset signal to the main processor to prevent the first reset signal from being directed back to the power management module.

3. The vehicle control device as described in claim 2, characterized in that, It also includes a second diode disposed between the reset terminals of the master processor and the slave processor, so as to control or limit the conduction direction of the second reset signal by means of the second diode, wherein the second diode directs the second reset signal to the slave processor to prevent the second reset signal from being directed back to the master processor.

4. The vehicle control device as described in claim 1, characterized in that, It also includes a first conversion module and a second conversion module respectively connected to the main processor and the slave processor. When the power management module provides power to the main processor, the main processor outputs a first pulse signal to the first conversion module, so that the first pulse signal output by the main processor is converted into a first voltage by the first conversion module. When the power management module provides power to the slave processor, the slave processor outputs a second pulse signal to the second conversion module, so that the second pulse signal output by the slave processor is converted into a second voltage by the second conversion module.

5. The vehicle control device as described in claim 4, characterized in that, It also includes a comparison module with a first comparator and a second comparator, and the first comparator and the second comparator are respectively connected to the first conversion module and the second conversion module. When the first comparator finds that the first voltage is less than the threshold voltage, the output of the first comparator is high, and when the first comparator finds that the first voltage is greater than the threshold voltage, the output of the first comparator is low. And when the second comparator finds that the second voltage is less than the threshold voltage, the output of the second comparator is high, and when the second comparator finds that the second voltage is greater than the threshold voltage, the output of the second comparator is low.

6. The vehicle control device as described in claim 5, characterized in that, It also includes a voltage divider circuit consisting of one resistor and another resistor, which is connected to the power management module to divide the voltage of the power supply from the power management module into the threshold voltage through the voltage divider circuit.

7. The vehicle control device as described in claim 1, characterized in that, in, The forced wake-up module consists of a first logic circuit and a second logic circuit connected to each other. The first logic circuit has a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor connected to each other. The second logic circuit has a third P-type transistor. When the output of the first logic circuit is low, it turns on the third P-type transistor of the second logic circuit, so that the power supply of the power management module flows from the source to the drain of the third P-type transistor. This causes the forced wake-up module or the second logic circuit to output a high-level signal to the reset terminal of the main processor and the reset terminal of the slave processor to forcibly wake up the main processor and the slave processor.

8. The vehicle control device as described in claim 1, characterized in that, in, When either the main processor or the slave processor malfunctions, the main processor or the slave processor outputs one of the corresponding first pulse signal and second pulse signal, and the output of the first pulse signal and the second pulse signal is at a low potential. If the main processor malfunctions, the power management module sends the first reset signal to the main processor to reset it. If the slave processor malfunctions, the main processor sends the second reset signal to the slave processor to reset it.

9. A vehicle control device, characterized in that, include: Power management module; A master processor and a slave processor simultaneously receive, monitor, or process at least one signal from the vehicle. The master processor and the slave processor dynamically adjust the frequencies of their respective output first pulse signal and second pulse signal based on the vehicle's speed signal. A power management module monitors the master processor via a first watchdog signal, and the master processor monitors the slave processor via a second watchdog signal. Specifically, when the power management module sends the first watchdog signal to the master processor, and the master processor does not respond to the first watchdog signal, the power management module sends a first reset signal to the master processor to reset it. Conversely, when the master processor sends the second watchdog signal to the slave processor, and the slave processor does not respond to the second watchdog signal, the master processor sends a second reset signal to the slave processor to reset it. A forced wake-up module is connected to the main processor and the slave processor respectively. When the power management module is abnormal, or when both the main processor and the slave processor are abnormal, the forced wake-up module outputs a high-potential signal to the reset terminals of the main processor and the slave processor to forcibly wake up the main processor and the slave processor.

10. The vehicle control device as described in claim 9, characterized in that, It also includes a first diode disposed between the power management module and the reset terminal of the main processor, so as to control or limit the conduction direction of the first reset signal by means of the first diode, wherein the first diode directs the first reset signal to the main processor to prevent the first reset signal from being directed back to the power management module.

11. The vehicle control device as described in claim 10, characterized in that, It also includes a second diode disposed between the reset terminals of the master processor and the slave processor, so as to control or limit the conduction direction of the second reset signal by means of the second diode, wherein the second diode directs the second reset signal to the slave processor to prevent the second reset signal from being directed back to the master processor.

12. The vehicle control device as described in claim 9, characterized in that, It also includes a first conversion module and a second conversion module respectively connected to the main processor and the slave processor. When the power management module provides power to the main processor, the main processor dynamically adjusts the frequency of the first pulse signal output by the main processor according to the vehicle speed signal to transmit the first pulse signal to the first conversion module. When the power management module provides power to the slave processor, the slave processor dynamically adjusts the frequency of the second pulse signal output by the slave processor according to the vehicle speed signal to transmit the second pulse signal to the second conversion module.

13. The vehicle control device as described in claim 12, characterized in that, It also includes a comparison module having a first comparator and a second comparator, wherein the first comparator and the second comparator are respectively connected to the first conversion module and the second conversion module. When the first comparator finds that the first voltage converted by the first conversion module according to the first pulse signal is less than the threshold voltage, the output of the first comparator is high, and when the first comparator finds that the first voltage is greater than the threshold voltage, the output of the first comparator is low. And when the second comparator finds that the second voltage converted by the second conversion module according to the second pulse signal is less than the threshold voltage, the output of the second comparator is high, and when the second comparator finds that the second voltage is greater than the threshold voltage, the output of the second comparator is low.

14. The vehicle control device as described in claim 12, characterized in that, It also includes a conversion circuit, wherein when the vehicle control device has received the vehicle speed signal, the conversion circuit converts the vehicle speed signal into a threshold voltage with a dynamic voltage value, and the dynamic voltage value of the threshold voltage increases as the vehicle speed signal increases or decreases as the vehicle speed signal decreases.

15. The vehicle control device as described in claim 9, characterized in that, It also includes a voltage divider circuit consisting of one resistor and another resistor, which is connected to the power management module to divide the voltage from the power supply of the power management module into a threshold voltage.

16. The vehicle control device as described in claim 9, characterized in that, in, The forced wake-up module consists of a first logic circuit and a second logic circuit connected to each other. The first logic circuit has a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor connected to each other. The second logic circuit has a third P-type transistor. When the output of the first logic circuit is low, it turns on the third P-type transistor of the second logic circuit, so that the power supply of the power management module flows from the source to the drain of the third P-type transistor. This causes the forced wake-up module or the second logic circuit to output a high-level signal to the reset terminal of the main processor and the reset terminal of the slave processor to forcibly wake up the main processor and the slave processor.

17. The vehicle control device as described in claim 9, characterized in that, in, When either the main processor or the slave processor malfunctions, the main processor or the slave processor outputs one of the corresponding first pulse signal and second pulse signal, and the output of the first pulse signal and the second pulse signal is at a low potential. If the main processor malfunctions, the power management module sends the first reset signal to the main processor to reset it. If the slave processor malfunctions, the main processor sends the second reset signal to the slave processor to reset it.

18. A vehicle control method, characterized in that, include: A vehicle control device is provided, comprising a power management module, a main processor, a slave processor, and a forced wake-up module, wherein the main processor is connected to the power management module and the slave processor respectively, and the forced wake-up module is connected to the main processor and the slave processor respectively. The main processor and the slave processor simultaneously receive, monitor, or process at least one signal from the vehicle, so that the power management module monitors the main processor via a first watchdog signal, and the main processor monitors the slave processor via a second watchdog signal. Specifically, when the power management module sends the first watchdog signal to the main processor, and the main processor does not respond to the first watchdog signal, the power management module sends a first reset signal to the main processor to reset it. Conversely, when the main processor sends the second watchdog signal to the slave processor, and the slave processor does not respond to the second watchdog signal, the main processor sends a second reset signal to the slave processor to reset it. When the power management module malfunctions, or when both the main processor and the slave processor malfunction, the forced wake-up module outputs a high-potential signal to the reset terminals of the main processor and the slave processor to forcibly wake up the main processor and the slave processor.

19. The vehicle control method as described in claim 18, characterized in that, in, The method further includes, when the vehicle control device has received the vehicle speed signal, converting the vehicle speed signal into a threshold voltage with a dynamic voltage value by a conversion circuit, wherein the dynamic voltage value of the threshold voltage increases as the vehicle speed signal increases or decreases as the vehicle speed signal decreases.

20. The vehicle control method as described in claim 18, characterized in that, in, The method further includes, when one of the main processor and the slave processor is abnormal, the main processor and the slave processor output one of a corresponding first pulse signal and a second pulse signal, wherein the output of the first pulse signal and the second pulse signal is a low potential. If the main processor is abnormal, the power management module sends the first reset signal to the main processor to reset it. If the slave processor is abnormal, the main processor sends the second reset signal to the slave processor to reset it.

Images