Optimization method and application of simulation results in chip verification

Abstract

The application discloses a simulation result optimization method and application in chip verification and relates to the technical field of chip development.The method comprises the following steps: starting simulation on a to-be-tested chip to generate a simulation file;forming a signal line group by grabbing the signal lines of relevant signals in the simulation file based on a specified RTL layer;packing the signal values in the signal line group to form a data packet, extracting a key data packet from the data packet, comparing the values of the signal lines in the key data packet with expected values, and / or comparing the combined logic among the multiple signal lines in the key data packet with expected signal line combined logic;and generating a key data verification result text file according to the comparison result.The application realizes automatic analysis and checking of the simulation result of the required signal within a set range, improves the simulation result checking efficiency, and reduces the labor and computing resource cost of simulation debugging.

Description

Technical Field

[0001] This invention relates to the field of chip development technology, and in particular to a method and application for optimizing simulation results in chip verification. Background Technology

[0002] In the development and design of integrated circuit (IC) chips, it is necessary to simulate and verify the chip's functionality. Simulation verification technology is widely used to verify chip behavior before manufacturing. Chip simulation verification is usually accomplished using dedicated simulation tools, which are typically used in conjunction with waveform displays to show and analyze the simulation results. These waveform displays help IC verification engineers examine the device's operating status over time and the relationships between devices. Almost all current simulation tools have dedicated waveform displays, such as the DVE tool in VPD Synopsys simulation tools and the SimVision tool in Candence's ncverilog / irun simulation tools. The process of viewing signals and waveforms through a waveform display is generally as follows: click on a level in the simulation window, then select the desired signal in the object window, and then select the "add wave" option based on that signal. The waveform of the desired signal is added to the waveform window. Currently, in the IC design verification phase, IC verification engineers primarily use waveform displays to analyze the waveform result files generated by the simulation to verify whether the chip's behavior meets expectations.

[0003] When using waveform result files, the mainstream approach is to analyze them based on graphical waveform files (i.e., waveform diagrams): After opening the waveform result file using a associated waveform display (waveform viewing software), a graphical waveform diagram can be obtained. IC verification engineers then locate relevant signals on the waveform diagram to check if the waveform meets expectations. If necessary, print information can also be added to the simulation tool's log file. The log file's print information can include the values ​​of any signal at any given time, thus allowing the log file's print information to assist in waveform inspection.

[0004] The aforementioned mainstream practices have the following main drawbacks:

[0005] 1) The waveform of a signal is a graphical information. When analyzing this type of information, engineers need to process the graphical information into specific signal logic, signal values, etc. in their minds. At the same time, when using the waveform, it is often necessary to locate the required signal from a large number of signals and / or find the key time points from the time axis in order to obtain the waveform to be analyzed. Currently, the above series of operations are mainly completed manually, which consumes a lot of engineers' time and energy.

[0006] 2) Since the printed information in the log file cannot completely replace the information contained in the waveform file, various problems often arise in practical applications when using the printed information from the log file to assist in waveform inspection. For example, if the signal value to be analyzed was not written into the printing command in the simulation test beforehand, it may not be displayed in the log file. In this case, the command needs to be added and the simulation needs to be repeated. Another example is that in some cases, insufficient information about the module under test and the testing tools may lead to discrepancies between the output log file and the actual signal information, or failure to print correctly. In this case, corresponding modifications need to be made and the simulation repeated to obtain a log file containing the required information. However, a large-scale simulation often takes several days or more and consumes significant computing resources, thus affecting the entire chip development cycle.

[0007] 3) As simulation tools become more sophisticated, some tools also provide text-based waveform information (converting graphical information from waveform graphs into text). This is typically achieved by pre-setting relevant options on the waveform display; when the user selects an option, a text file containing the preset signal inversion values ​​is output – a relatively simple process. However, in practical applications, it has been found that because simulations often require processing a large number of signals, verification engineers need to manually add the corresponding options for the required signals (i.e., manually capture the required signals), which is not much more convenient than directly viewing the waveform graph. Furthermore, checking simulation results often requires complex logical judgments, and the pre-set options provided by the simulation tool are insufficient to meet the verification engineers' needs. Moreover, directly using the waveform display of the simulation tool often suffers from poor reusability.

[0008] In summary, in chip simulation verification, how to automate the optimization of simulation results to solve the problems of low efficiency in simulation result inspection and high consumption of manpower and computing resources is a technical problem that urgently needs to be solved. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a method and application for optimizing simulation results in chip verification. The simulation result optimization method provided by this invention can automatically capture relevant signals within a specified range to form signal line groups, automatically package relevant data into data packets based on the signal line groups, extract key data packets, and then automatically compare the data in the key data packets with preset values ​​to generate a text-based report containing key information. This achieves automatic analysis and inspection of simulation results for the required signals within a set range, improving the efficiency of simulation result inspection and reducing the manpower and computational resource costs of simulation debugging.

[0010] To achieve the above objectives, the present invention provides the following technical solution:

[0011] A method for optimizing simulation results in chip verification includes the following steps:

[0012] Simulation is started on the chip under test. After the simulation starts, a simulation file is generated. The simulation file is used to store the simulation waveforms and result records. As the simulation progresses, the generated simulation waveforms and result records are updated to the aforementioned simulation file.

[0013] Based on the specified RTL layer, after obtaining all signal information under that RTL layer in the simulation file, the signals are filtered based on keywords to obtain relevant signal lines, and the relevant signal lines are packaged to form signal line groups.

[0014] The signal values ​​in the aforementioned signal line group are packaged into a data packet, wherein the data packet contains the values ​​of all or part of the signal lines of the signal line group within a complete transmission cycle;

[0015] Extract key data packets from the aforementioned data packets, compare the values ​​of signal lines in the key data packets with the expected values ​​of the signal lines, and / or compare the combinational logic between multiple signal lines in the key data packets with the expected combinational logic of the signal lines;

[0016] Based on the aforementioned comparison results, a key data verification result text file is generated, which contains key data packets and their corresponding comparison result information.

[0017] Furthermore, the steps to obtain the relevant signal lines are as follows: collect the keyword information set in the current bus protocol, or collect the keyword information set by the user through the keyword collection bar;

[0018] Obtain the signal line containing the aforementioned keywords as the aforementioned related signal line.

[0019] Furthermore, the step of packaging the signal values ​​in the aforementioned signal line group into a data packet is as follows: obtain the signal transmission rules of the current bus protocol, obtain the signal values ​​corresponding to each special signal line in the signal line group according to the special signal line information configured in the signal transmission rules, and package the aforementioned signal values ​​to form a data packet.

[0020] Furthermore, the special signal lines include clock signals and / or handshake signals.

[0021] Furthermore, the data packet can be one or more; when there is one data packet, the data packet contains the values ​​of all signal lines of the signal line group within a complete transmission cycle; when there are multiple data packets, each data packet contains the values ​​of some signal lines of the signal line group within a complete transmission cycle.

[0022] Furthermore, the transmission period is the complete transmission period configured in the current bus protocol to complete one full transmission;

[0023] Alternatively, the transmission period can be the complete transmission period set by the user.

[0024] Furthermore, the steps for extracting key data packets include: obtaining preset key focus signal lines, wherein each key focus signal line is configured with a signal value standard; determining whether the value of the key focus signal line in the aforementioned data packet meets the corresponding standard, and if it is determined that it meets the standard, the data packet containing the key focus signal line is extracted as a key data packet.

[0025] Furthermore, the expected value of the signal line is the value output by the reference model in the verification test;

[0026] Alternatively, the expected value of the signal line is the expected value set by the system;

[0027] Alternatively, the expected value of the signal line is the expected value set by the user;

[0028] Alternatively, the expected value of the signal line may be a theoretical value calculated from a preset logic model and / or mathematical operation model.

[0029] Furthermore, determine whether the simulation process has ended. If it has ended, stop updating the simulation file and the text file containing the key data verification results.

[0030] The present invention also provides an optimization device for simulation results in chip verification, comprising:

[0031] The simulation module is used to start the simulation of the chip under test. After the simulation starts, a simulation file is generated, which is used to store the simulation waveforms and result records. As the simulation progresses, the generated simulation waveforms and result records are updated to the aforementioned simulation file.

[0032] The signal group capture module is used to obtain all signal information under a specified RTL layer in the simulation file, filter the signals based on keywords to obtain relevant signal lines, and package the relevant signal lines to form signal line groups.

[0033] A data packet generation module is used to package the signal values ​​in the aforementioned signal line group into a data packet, wherein the data packet contains the values ​​of all or part of the signal lines of the signal line group within a complete transmission cycle;

[0034] The key data packet extraction module is used to extract key data packets from the aforementioned data packets, compare the value of the signal line in the key data packet with the expected value of the signal line, and / or compare the combination logic between multiple signal lines in the key data packet with the expected combination logic of the signal lines;

[0035] The comparison module is used to generate a key data verification result text file based on the aforementioned comparison results. The key data verification result text file contains key data packets and their corresponding comparison result information.

[0036] Compared with the prior art, the present invention, by adopting the above technical solution, has the following advantages and positive effects: The simulation result optimization method provided by the present invention can automatically capture relevant signals within a specified range to form signal line groups, and automatically package relevant data into data packets based on the signal line groups and extract key data packets. Then, it realizes automatic comparison between the data in the key data packets and preset values ​​and generates a text report containing key information. This realizes automatic analysis and inspection of the simulation results of the required signals within a set range, improves the efficiency of simulation result inspection, and reduces the manpower and computing resource costs of simulation debugging. Attached Figure Description

[0037] Figure 1 A flowchart outlining the method for optimizing simulation results in chip verification according to an embodiment of the present invention.

[0038] Figure 2 This is a schematic diagram illustrating the process of extracting key data packets from a simulation waveform file, provided as an embodiment of the present invention.

[0039] Figure 3 The circuit module structure diagram of the device for optimizing simulation results in chip verification provided in the embodiments of the present invention. Detailed Implementation

[0040] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the optimization method and application of simulation results in chip verification disclosed in this invention. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be considered isolated; they can be combined to achieve better technical effects. In the accompanying drawings of the following embodiments, the same reference numerals in each drawing represent the same features or components, which can be applied to different embodiments. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0041] It should be noted that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes and to aid those skilled in the art in understanding and reading the invention. They are not intended to limit the conditions under which the invention can be implemented. Any modifications to the structure, changes in proportions, or adjustments to size, provided they do not affect the effectiveness or purpose of the invention, should fall within the scope of the technical content disclosed in the invention. The scope of the preferred embodiments of the present invention includes other implementations, wherein functions may be performed not in the order stated or discussed, including substantially simultaneously or in reverse order, depending on the functions involved. This should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0042] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. The plurality described in this invention refers to two or more. Example

[0043] See Figure 1 The diagram illustrates a method for optimizing simulation results in chip verification, provided by this invention. The method includes the following steps.

[0044] S100, start the simulation and generate the simulation file.

[0045] Simulation of the chip under test is initiated using a simulation tool, and a simulation file is generated after the simulation starts. This simulation file stores the simulation waveforms and result records. As the simulation progresses, the generated simulation waveforms and result records are updated in the aforementioned simulation file.

[0046] S200, captures signal groups from simulation files.

[0047] Specifically, during the simulation process, based on the specified RTL (Register Transfer Level) layer, after obtaining all signal information under that RTL layer from the simulation file, the signals are filtered based on keywords to obtain relevant signal lines, and the relevant signal lines are packaged to form signal line groups.

[0048] The specified RTL layer is preferably defined by the user, thereby enabling the automatic capture of relevant signals to form signal line groups within the user-specified range. For example, if the user specifies the RTL layer as the top layer, meaning the user wants to capture the changes of all relevant signals below the top layer of the RTL from the simulation file.

[0049] In this embodiment, signals are filtered based on keywords. The keyword used for filtering can be a single keyword or a group of keywords. Specifically, the filtering rule is configured as follows: keyword information set in the current bus protocol is collected, and signal lines containing the aforementioned keywords are identified as the relevant signal lines. That is, matching is performed according to keywords in the existing bus protocol, and signal lines with relevant keywords are organized and packaged to form signal line groups.

[0050] Alternatively, the filtering rules can be configured as follows: collect keyword information set by the user through the keyword collection bar; obtain signal lines containing the aforementioned keywords as the aforementioned related signal lines. That is, signal lines can be organized and packaged using user-preset keywords to form signal line groups.

[0051] S300 generates data packets and extracts key data packets.

[0052] The signal values ​​in the aforementioned signal line group are packaged into a data packet, wherein the data packet contains the values ​​of all or part of the signal lines in the signal line group within a complete transmission cycle. Then, a key data packet is extracted from the aforementioned data packet, and the value of the signal line in the key data packet is compared with the expected value of the signal line, and / or the combination logic between multiple signal lines in the key data packet is compared with the expected combination logic of the signal lines.

[0053] When generating data packets, the data in the signal line group can be packaged based on the user-preset data packaging rules, or it can be based on the content of the existing bus protocol.

[0054] Preferably, the step of packaging the signal values ​​in the aforementioned signal line group into a data packet is as follows: obtaining the signal transmission rules of the current bus protocol, obtaining the signal values ​​corresponding to each special signal line in the signal line group according to the special signal line information configured in the signal transmission rules, and packaging the aforementioned signal values ​​to form a data packet.

[0055] The special signal lines, such as clock signals and handshake signals, can package the signal values ​​of each signal line in the aforementioned signal line group into one or more data packets;

[0056] The packet formed can be one or more. When there is one packet, the packet contains the values ​​of all signal lines of the signal line group within a complete transmission cycle. When there are multiple packets, each packet contains the values ​​of a portion of the signal lines of the signal line group within a complete transmission cycle.

[0057] The transmission period can be the complete transmission period configured in the current bus protocol to complete one transmission, or it can be a complete transmission period set by the user.

[0058] In this embodiment, the key data packet is important data used to determine whether the simulation test results for verification have passed. When extracting the key data packet, it is preferable to focus on important signals with preset comparison standards. The steps for extracting the key data packet can be as follows: obtain preset key focus signal lines, wherein each key focus signal line is configured with a signal value standard; determine whether the value of the key focus signal line in the aforementioned data packet conforms to the corresponding standard; if it is determined to conform to the standard, the data packet containing the key focus signal line is extracted as the key data packet.

[0059] In other words, when filtering key data packets from data packets, it is based on the values ​​of some preset important signal lines. When the value of the important signal line meets a certain preset signal value standard, the data packet is extracted as a key data packet.

[0060] In this embodiment, when comparing the data of a critical data packet, the value of a signal line in the critical data packet can be compared with the expected value of that signal line, or the combinational logic between multiple signal lines in the critical data packet can be compared with the expected combinational logic of the signal lines. In this way, it can be determined whether the value of the signal line meets expectations, and it can also be determined whether the complex combinational logic relationship between multiple signal lines (groups) meets expectations.

[0061] The following is combined Figure 2 Describe in detail the steps to extract the key data packets.

[0062] See Figure 2 As shown, for example, a signal line group may include a clk signal (clock signal line), which is a preset key signal line. When packaging data into a data packet, the rising edge data of the clk signal can be collected. The signal where both the valid and ready signals are high simultaneously is considered valid. Recording the values ​​on each signal line at this time (the time when both the valid and ready signals are high simultaneously) forms a data packet. Figure 2 The example shows three data packets, namely packet 1, packet 2 and packet 3, which correspond to addresses addr1, addr2 and addr3 respectively.

[0063] A data packet is considered critical when the value of the clk signal in the packet matches a preset value. For example, the preset condition might be: when the addr value equals addr1 (addr=addr1), the data packet is considered critical. Figure 2 Data packet 1 was the critical data packet and was extracted, while data packets 2 and 3 were not critical data packets.

[0064] S400, data comparison, and generation of a verification result text file based on the comparison structure.

[0065] Based on the aforementioned comparison results, a key data verification result text file is generated. This text file contains key data packets and their corresponding comparison result information. During the simulation process, the generated key data packets and comparison result information are updated in the key data verification result text file.

[0066] In this embodiment, the expected value of the signal line is the value output by the reference model in the verification test. Alternatively, the expected value of the signal line is the expected value set by the system. Alternatively, the expected value of the signal line is the expected value set by the user. Alternatively, the expected value of the signal line is the theoretical value calculated by a preset logical model and / or mathematical operation model.

[0067] In this embodiment, preferably, the simulation process is monitored, and when the simulation process is detected to be over, the updating of the simulation file and the text file of the key data verification results is stopped.

[0068] See Figure 3 As shown, this invention provides an optimization device for simulation results in chip verification.

[0069] The device includes a simulation module, a signal group capture module, a data packet generation module, a key data packet extraction module, and a comparison module.

[0070] The simulation module is used to start the simulation of the chip under test. After the simulation starts, a simulation file is generated. The simulation file is used to store the simulation waveforms and result records. As the simulation progresses, the generated simulation waveforms and result records are updated to the aforementioned simulation file.

[0071] The signal group capture module is used to obtain all signal information under the specified RTL layer in the simulation file, filter the signals based on keywords to obtain relevant signal lines, and package the relevant signal lines to form signal line groups.

[0072] The data packet generation module is used to package the signal values ​​in the aforementioned signal line group into a data packet, wherein the data packet contains the values ​​of all or part of the signal lines of the signal line group within a complete transmission cycle.

[0073] The key data packet extraction module is used to extract key data packets from the aforementioned data packets, compare the value of the signal line in the key data packet with the expected value of the signal line, and / or compare the combination logic between multiple signal lines in the key data packet with the expected combination logic of the signal lines.

[0074] The comparison module is used to generate a key data verification result text file based on the comparison results. The key data verification result text file contains key data packets and their corresponding comparison result information.

[0075] Other technical features are described in the previous embodiments and will not be repeated here.

[0076] In the above description, the disclosure of this invention is not intended to limit itself to these aspects. Rather, within the scope of the objectives of this disclosure, components can be selectively and operationally combined in any number. Furthermore, terms such as “comprising,” “encompassing,” and “having” should be interpreted by default as inclusive or open-ended, rather than exclusive or closed, unless explicitly defined as such. All technical, scientific, or other terms are to be understood by those skilled in the art, unless defined as such. Public terms found in dictionaries should not be interpreted in the context of the relevant technical documents in an overly idealistic or impractical manner, unless explicitly defined as such in this disclosure. Any modifications or alterations made by those skilled in the art based on the foregoing disclosure are within the scope of the claims.

Claims

1. A method for optimizing simulation results in chip verification, characterized in that... Includes the following steps: Simulation is started on the chip under test. After the simulation starts, a simulation file is generated. The simulation file is used to store the simulation waveforms and result records. As the simulation progresses, the generated simulation waveforms and result records are updated to the aforementioned simulation file. Based on the specified RTL layer, after obtaining all signal information under that RTL layer in the simulation file, the signals are filtered based on keywords to obtain relevant signal lines, and the relevant signal lines are packaged to form signal line groups. The signal values ​​in the aforementioned signal line group are packaged into a data packet, wherein the data packet contains the values ​​of all or part of the signal lines of the signal line group within a complete transmission cycle; Extracting key data packets from the aforementioned data packets involves comparing the values ​​of signal lines in the key data packets with the expected values ​​of those signal lines, and / or comparing the combinational logic between multiple signal lines in the key data packets with the expected combinational logic of the signal lines. The steps for extracting key data packets include: obtaining preset key signal lines of interest, wherein each key signal line of interest is configured with a signal value standard; determining whether the values ​​of the key signal lines of interest in the aforementioned data packets meet the corresponding standards, and if the standards are met, extracting the data packet containing the key signal line of interest as a key data packet. Based on the aforementioned comparison results, a key data verification result text file is generated, which contains key data packets and their corresponding comparison result information.

2. The method according to claim 1, characterized in that, The steps to obtain the relevant signal lines are as follows: Collect keyword information set in the current bus protocol, or collect keyword information set by the user through the keyword collection bar; Obtain the signal line containing the aforementioned keywords as the aforementioned related signal line.

3. The method according to claim 1, characterized in that, The steps for packaging the signal values ​​in the aforementioned signal line group into a data packet are as follows: Obtain the signal transmission rules of the current bus protocol, and according to the special signal line information configured in the signal transmission rules, obtain the signal values ​​corresponding to each special signal line in the signal line group, and package the aforementioned signal values ​​to form a data packet.

4. The method according to claim 3, characterized in that: The special signal lines include clock signals and / or handshake signals.

5. The method according to claim 3, characterized in that: The data packet may be one or more; when there is one data packet, the data packet contains the values ​​of all signal lines of the signal line group within a complete transmission cycle; when there are multiple data packets, each data packet contains the values ​​of a portion of the signal lines of the signal line group within a complete transmission cycle.

6. The method according to claim 5, characterized in that: The transmission period is the complete transmission period configured in the current bus protocol to complete one full transmission. Alternatively, the transmission period can be the complete transmission period set by the user.

7. The method according to claim 1, characterized in that: The expected value of the signal line is the value output by the reference model in the verification test; Alternatively, the expected value of the signal line is the expected value set by the system; Alternatively, the expected value of the signal line is the expected value set by the user; Alternatively, the expected value of the signal line may be a theoretical value calculated from a preset logic model and / or mathematical operation model.

8. The method according to claim 1, characterized in that: Determine whether the simulation process has ended. If it has ended, stop updating the simulation file and the text file containing the key data verification results.

9. An optimization device for simulation results in chip verification, characterized in that... include: The simulation module is used to start the simulation of the chip under test. After the simulation starts, a simulation file is generated, which is used to store the simulation waveforms and result records. As the simulation progresses, the generated simulation waveforms and results are recorded and updated in the aforementioned simulation file; The signal group capture module is used to obtain all signal information under a specified RTL layer in the simulation file, filter the signals based on keywords to obtain relevant signal lines, and package the relevant signal lines to form signal line groups. A data packet generation module is used to package the signal values ​​in the aforementioned signal line group into a data packet, wherein the data packet contains the values ​​of all or part of the signal lines of the signal line group within a complete transmission cycle; The critical data packet extraction module is used to extract critical data packets from the aforementioned data packets, compare the values ​​of signal lines in the critical data packets with the expected values ​​of the signal lines, and / or compare the combination logic between multiple signal lines in the critical data packets with the expected combination logic of the signal lines. The steps for extracting critical data packets include: obtaining preset key focus signal lines, wherein each key focus signal line is configured with a signal value standard; determining whether the values ​​of the key focus signal lines in the aforementioned data packets meet the corresponding standards, and if it is determined that they meet the standards, extracting the data packet containing the key focus signal line as a critical data packet. The comparison module is used to generate a key data verification result text file based on the aforementioned comparison results. The key data verification result text file contains key data packets and their corresponding comparison result information.

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