Electro-optical devices and electronic devices

Abstract

An electro-optical device and an electronic device are provided, which fully ensure the light emission period without increasing the speed of line sequential writing. In an odd frame (V_odd), a plurality of scanning lines (12) are sequentially selected. In a pixel circuit (110), a first selector (122) electrically connects one end of a capacitor element (C1a) to a data line (14) when the scanning line (12) corresponding to the pixel circuit (110) is selected, and a second selector (123) electrically connects one end of a capacitor element (C1b) to a gate node (g) of a transistor (121). In an even frame (V_eve), a plurality of scanning lines (12) are sequentially selected. When the scanning line (12) is selected, the first selector (122) electrically connects one end of a capacitor element (C1b) to a data line (14), and a second selector (123) electrically connects one end of a capacitor element (C1a) to a gate node (g).

Description

Technical Field

[0001] The present invention relates to electro-optical devices and electronic equipment. Background Art

[0002] Electro-optical devices using, for example, OLEDs as light-emitting elements are known. OLED stands for Organic Light Emitting Diode. In such electro-optical devices, pixel circuits, including transistors for passing current through the light-emitting elements, are provided corresponding to the pixels of the displayed image. The transistors supply a current corresponding to the grayscale level to the light-emitting elements. As a result, the light-emitting elements emit light at a brightness corresponding to the current.

[0003] As an example of a technology for driving such light-emitting elements, there is known a technology for causing light-emitting elements to emit light simultaneously after sequentially writing data signals during one frame period, as described in Patent Documents 1 and 2, for example.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2018-28590

[0005] Patent Document 2: Japanese Patent Application Laid-Open No. 2011-34038

[0006] However, in Patent Documents 1 and 2, the process from line-sequential writing of data signals to simultaneous light emission of the light-emitting elements must be performed within a limited time period, namely, a single frame period. Consequently, there are issues such as the need to increase the speed of line-sequential writing or the inability to ensure a sufficient light emission period, resulting in a dark displayed image. Summary of the Invention

[0007] An electro-optical device according to one embodiment of the present invention includes a plurality of pixel circuits arranged corresponding to intersections of a data line and a plurality of scanning lines, each of the pixel circuits including a first selector, a second selector, a first capacitor, a second capacitor, a driving transistor, and a light-emitting element, wherein the driving transistor is capable of supplying a current corresponding to a voltage at a gate node to the light-emitting element. In a first frame, the plurality of scanning lines are selected in sequence, and the first selector of one pixel circuit among the plurality of pixel circuits electrically connects one end of the first capacitor to the data line when a scanning line corresponding to the pixel circuit is selected, and the second selector in the pixel circuit electrically connects one end of the second capacitor to the gate node. In a second frame different from the first frame, the plurality of scanning lines are selected in sequence, and the first selector in the pixel circuit electrically connects one end of the second capacitor to the data line when the scanning line is selected, and the second selector in the pixel circuit electrically connects one end of the first capacitor to the gate node. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a block diagram of a head-mounted display to which the electro-optical device according to the first embodiment is applied.

[0009] Figure 2 It is a perspective view showing the structure of a head-mounted display.

[0010] Figure 3 A diagram showing the optical structure of a head-mounted display.

[0011] Figure 4 It is a perspective view of an electro-optical device.

[0012] Figure 5 This is a block diagram showing the electrical structure of an electro-optical device.

[0013] Figure 6 This is a diagram showing a pixel circuit in an electro-optical device.

[0014] Figure 7 This is a timing chart showing the operation of the electro-optical device.

[0015] Figure 8 This is a timing chart showing the operation of the first modified example of the electro-optical device.

[0016] Figure 9 This is a timing chart showing the operation of the second modified example of the electro-optical device.

[0017] Figure 10 This is a timing chart showing the operation of the third modified example of the electro-optical device.

[0018] Figure 11 This is a diagram showing a pixel circuit of the electro-optical device according to the first embodiment.

[0019] Figure 12 This is a diagram showing a pixel circuit of an electro-optical device according to a second embodiment.

[0020] Figure 13 This is a timing chart showing the operation of the electro-optical device.

[0021] Figure 14 This is a flowchart showing the operation of the electro-optical device.

[0022] Figure 15 This is a diagram showing a pixel circuit in the second embodiment.

[0023] Figure 16A A diagram showing display distortion in an electro-optical device.

[0024] Figure 16B A diagram showing display distortion in an electro-optical device.

[0025] Figure 16CA diagram showing display distortion in an electro-optical device.

[0026] Label Description

[0027] 1: head-mounted display; 10: electro-optical device; 12: scanning line; 14: data line; 100: display area; 110: pixel circuit; 116: power wiring (high-order power wiring); 118: power wiring (low-order power wiring); 121: transistor (driving transistor); 122a: transistor (first switching element); 122b: transistor (second switching element); 123a: transistor (third switching element); 123b: transistor (fourth switching element); 124: transistor (fifth switching element); 126: transistor (sixth switching element); 300: head-mounted device (headset); C1a: capacitor element (first capacitor element); C1b: capacitor element (second capacitor element); C2: capacitor element (third capacitor element). DETAILED DESCRIPTION

[0028] Hereinafter, an electro-optical device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0029] In addition, in each figure, the size and scale of each part are appropriately different from the actual one. In addition, the embodiment described below is a preferred specific example, and therefore various technically preferred limitations are added, but as long as there is no record of the meaning of the present invention being particularly limited in the following description, the scope of the present invention is not limited to these embodiments.

[0030] <First embodiment>

[0031] Figure 1 This is a block diagram showing the configuration of a head-mounted display system 1, which is an electronic device that uses the electro-optical device according to the first embodiment. As shown in the figure, the head-mounted display system 1 includes a main controller 5 and a head-mounted device 300. The head-mounted device 300 includes electro-optical devices 10L and 10R and a timing controller 350.

[0032] The electro-optical device 10L is for the left eye, and the electro-optical device 10R is for the right eye. Each is a microdisplay that displays color images. Electro-optical devices 10L and 10R have multiple pixel circuits and driver circuits for driving these pixel circuits formed on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but other semiconductor substrates may also be used.

[0033] The main controller 5 outputs video data Vid_L representing a video to be viewed by the left eye, video data Vid_R representing a video to be viewed by the right eye, and a control signal Ctr. The video data Vid_L and Vid_R specify the grayscale level of pixels in the video to be displayed using, for example, 8 bits.

[0034] The timing controller 350 receives the control signal Ctr and image data Vid_L and Vid_R from the main controller 5 and generates timing signals for driving the electro-optical devices 10L and 10R based on the received signals. Furthermore, the timing signal Sync is a signal used to perform vertical and horizontal scanning on the electro-optical devices 10L and 10R. Specifically, there are vertical synchronization signals, horizontal synchronization signals, and clock signals. The vertical synchronization signal specifies the start of vertical scanning in the electro-optical devices 10L and 10R, while the horizontal synchronization signal specifies the start of horizontal scanning in the electro-optical devices 10L and 10R. Furthermore, the clock signal is used as a synchronization signal when transmitting image data Vid_L to the electro-optical device 10L and image data Vid_R to the electro-optical device 10R.

[0035] In addition, the timing controller 350 transmits the received image data Vid_L to the electro-optical device 10L, and transmits the received image data Vid_R to the electro-optical device 10R.

[0036] Figure 2 is a perspective view showing a head-mounted device of a head-mounted display system. Figure 3 This diagram shows the optical structure of a head-mounted device.

[0037] like Figure 2 As shown in FIG, the head mounted device 300 has temples 310, a nose bridge 320, and lenses 301L and 301R in appearance similar to ordinary glasses. Figure 3 As shown, the head mounted device 300 is provided with an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye near the nose bridge 320 and on the back side (lower side in the figure) of the lenses 301L and 301R. Furthermore, a timing controller 350 is built into the head mounted device 300 and generates a timing signal Sync for driving the electro-optical devices 10L and 10R based on a signal received from the main controller 5 via the cable 7.

[0038] The image display surface of the electro-optical device 10L is Figure 3 . The image display surface of the electro-optical device 10R is configured so as to be on the right side opposite to the electro-optical device 10L. As a result, the display image of the electro-optical device 10R is emitted in the direction of 9 o'clock in the figure through the optical lens 302L. The semi-transparent half-reflecting mirror 303L reflects the display image of the electro-optical device 10L in the direction of 6 o'clock, and on the other hand, allows light incident from the direction of 12 o'clock to pass through. The image display surface of the electro-optical device 10R is configured so as to be on the right side opposite to the electro-optical device 10L. As a result, the display image of the electro-optical device 10R is emitted in the direction of 3 o'clock in the figure through the optical lens 302R. The semi-transparent half-reflecting mirror 303R reflects the display image of the electro-optical device 10R in the direction of 6 o'clock, and on the other hand, allows light incident from the direction of 12 o'clock to pass through.

[0039] In this configuration, a user wearing the head mounted device 300 can observe the display images of the electro-optical devices 10L and 10R in a see-through state that overlaps with the external scenery.

[0040] Furthermore, in this head mounted device 300, when the electro-optical device 10L displays the left-eye image of a binocular image with parallax, and the electro-optical device 10R displays the right-eye image, the wearer can perceive the displayed image as having depth and a sense of three-dimensionality. However, if a sense of three-dimensionality is not required, the image data Vid_L and Vid_R can be shared to display the same image.

[0041] Since the electro-optical devices 10L and 10R have the same structure, they are not particularly distinguished from each other below, and the suffixes L and R are omitted and the reference numeral is simply described as 10. The image data Vid_L and Vid_R are also simply described as image data Vid.

[0042] Figure 4 is a perspective view showing the electro-optical device 10, Figure 5 1 is a block diagram showing the electrical structure of the electro-optical device 10. The electro-optical device 10 includes a light-emitting element formed on a semiconductor substrate or a glass substrate. In this embodiment, an OLED is used as an example of the light-emitting element.

[0043] like Figure 4 As shown, the electro-optical device 10 is housed in a frame-shaped housing 192 that is opened in the display area 100. The electro-optical device 10 is connected to one end of an FPC board 194. FPC is an abbreviation of Flexible Printed Circuits.

[0044] A plurality of terminals 196 connected to the timing controller 350 are provided at the other end of the FPC substrate 194. Figure 5 As shown, video data Vid, a timing signal Sync, and the like are supplied to the electro-optical device 10 via the FPC board 194 .

[0045] In the figure, the X direction indicates the direction in which the scanning lines extend in the electro-optical device 10, and the Y direction indicates the direction in which the data lines extend. The two-dimensional plane defined by the X and Y directions represents the substrate surface of the semiconductor substrate. The Z direction, perpendicular to the X and Y directions, indicates the direction in which light emitted from the light-emitting element is emitted.

[0046] As shown in the figure, the electro-optical device 10 is roughly divided into a control circuit 30 , a data signal output circuit 50 , a display area 100 , and a scan line driving circuit 120 .

[0047] In the display area 100, m rows of scanning lines 12 are arranged along the X direction in the figure, and n columns of data lines 14 are arranged along the Y direction in the figure to ensure electrical insulation between the scanning lines 12. Note that m and n are integers greater than 2.

[0048] In the display area 100, pixel circuits 110 are provided corresponding to the intersections of m rows of scan lines 12 and n columns of data lines 14. Therefore, the pixel circuits 110 are arranged in a matrix with m rows and n columns in the figure. In this matrix arrangement, to distinguish between rows, the figures sometimes refer to the 1st, 2nd, 3rd, ..., (m-1), and mth rows from the top. Similarly, to distinguish between columns, the figures sometimes refer to the 1st, 2nd, 3rd, ..., (n-1), and nth columns from the left.

[0049] Furthermore, an integer i of 1 to m is used to generally describe the scanning line 12. Similarly, an integer j of 1 to n is used to generally describe the data line 14.

[0050] The control circuit 30 controls each component based on the video data Vid and the timing signal Sync supplied from the main controller 5 and the timing controller 350. As described above, the video data Vid specifies the grayscale level of a pixel using, for example, 8 bits. However, the brightness characteristics represented by the grayscale level of a pixel in an image to be displayed do not match the brightness of the pixel circuit 110 corresponding to the pixel (more specifically, the brightness characteristics of the OLED included in the pixel circuit 110).

[0051] Therefore, in order to make the OLED emit light at a brightness corresponding to the grayscale level specified by the image data Vid, the control circuit 30 converts 8 bits of the image data Vid into 10 bits in this embodiment, for example, and outputs it as image data Vdata specifying the brightness of the OLED.

[0052] In such up-conversion, a lookup table is used that stores in advance the correspondence between 8 bits of input video data Vid and 10 bits of output video data Vdata.

[0053] In addition, the control circuit 30 generates various control signals in order to control each component, and the details will be described later.

[0054] The scan line driver circuit 120 is a circuit for driving the pixel circuits 110 arranged in m rows and n columns, row by row, under the control of the control circuit 30. The scan line driver circuit 120 sequentially supplies scan signals Scan(1), Scan(2), ..., Scan(m-1), and Scan(m) to the scan lines 12 in the 1st, 2nd, 3rd, ..., (m-1), and mth rows. Typically, the scan signal supplied to the scan line 12 in the i-th row is denoted as Scan(i).

[0055] In addition, Figure 5 In order to avoid complicating the drawing, the number of scan lines 12 per row is set to one, but in reality, the number of scan lines per row is "2." The scan signals supplied to the two scan lines 12 corresponding to the i-th row are Scan_a(i) and Scan_b(i).

[0056] The data signal output circuit 50 is a circuit that outputs a data signal having a voltage corresponding to the luminance to the pixel circuit 110 located in the row selected by the scan line driving circuit 120 .

[0057] Specifically, the data signal output circuit 50 latches one line of image data Vdata supplied from the control circuit 30 , converts the latched one line of image data Vdata into an analog data signal, and outputs the analog data signal to the corresponding data line 14 .

[0058] Furthermore, the potentials of the data lines 14 in the 1st, 2nd, ..., (n-1), and nth columns are sequentially represented as Vd(1), Vd(2), ..., Vd(n-1), and Vd(n). Typically, the potential of the data line 14 in the jth column is represented as Vd(j).

[0059] In this description, the reference for zero voltage is the logic level L (ground potential). However, except for the voltage between two points (threshold voltage), no strict distinction is made between potential and voltage. Furthermore, in this description, the term "power supply" refers to a voltage or potential that is substantially constant over time.

[0060] Figure 6 1 is a diagram showing a pixel circuit 110. The pixel circuits 110 arranged in m rows and n columns are electrically identical to each other. Therefore, the pixel circuit 110 located in the i row and j column will be described as a representative.

[0061] As shown, the pixel circuit 110 includes an OLED 130, P-channel MOS transistors 121, 122a, 122b, 123a, 123b, and 124, and capacitors C1a and C1b. MOS is the abbreviation for Metal-Oxide-Semiconductor field-effect transistor.

[0062] The pixel circuit 110 in the i-th row is supplied with a scanning signal Scan_a(i) via one scanning line 12a of the two scanning lines 12 corresponding to the i-th row, and is supplied with a scanning signal Scan_b(i) via the other scanning line 12b.

[0063] Furthermore, the selection signals Sel_a and Sel_b and the control signal Enb are commonly supplied from the control circuit 30 to all the pixel circuits 110 in the 1st to mth rows.

[0064] The OLED 130 is a light-emitting element consisting of a pixel electrode 131 and a common electrode 133, sandwiching a light-emitting functional layer 132. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 is both light-reflective and light-transmissive. In the OLED 130, when current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to form excitons, producing white light.

[0065] In the case of color display, the generated white light resonates in an optical resonator composed of, for example, a reflective layer and a semi-reflective, semi-transmissive layer (not shown), and is emitted at a resonant wavelength set corresponding to one of the colors R (red), G (green), or B (blue). A color filter corresponding to the color is provided on the light exiting the optical resonator. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and the color filter before being viewed by the observer. The optical resonator is not shown in the figure. Furthermore, when the electro-optical device 10 displays a monochrome image consisting only of light and dark, the color filter is omitted.

[0066] In the pixel circuit 110 in the i-th row and j-th column, the source node of the transistor 122a is connected to the data line 14 in the j-th column, the drain node is connected to one end of the capacitor C1a and the source node of the transistor 123a, and the gate node is connected to the scan line 12a. The source node of the transistor 122b is connected to the data line 14 in the j-th column, the drain node is connected to one end of the capacitor C1b and the source node of the transistor 123b, and the gate node is connected to the scan line 12b. The other end of the capacitor C1a and the other end of the capacitor C1b are connected to the power supply wiring 116 to which the high power supply potential ELvdd is supplied.

[0067] The gate node of transistor 123a is connected to control line 13a to which selection signal Sel_a is supplied. The gate node of transistor 123b is connected to control line 13b to which selection signal Sel_b is supplied. The drain nodes of transistors 123a and 123b are connected to gate node g of transistor 121.

[0068] The source node s of the transistor 121 is connected to the power supply wiring 116, and the drain node d is connected to the source node of the transistor 124. The control signal Enb is supplied to the gate node of the transistor 124, and the drain node is connected to the pixel electrode 131 of the OLED 130. In addition, in the OLED 130, the low power supply potential ELvss is supplied to the common electrode 133 via the power supply wiring 118.

[0069] In addition, in this description, "electrical connection" or simply "connection" refers to a direct or indirect connection or combination between two or more elements, and also includes situations where, for example, in a semiconductor substrate, two or more elements are not directly connected but are connected via different wiring layers and contact holes.

[0070] Figure 7 This is a timing chart for explaining the operation of the electro-optical device 10 .

[0071] The operation of the electro-optical device 10 is divided into odd frames V_odd and even frames V_eve. Note that the terms odd and even frames V_odd and V_eve are used simply to distinguish consecutive frames. In this description, a frame refers to the period required to display a single frame of an image specified by the video data Vid. If the length of a single frame is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the timing signal Sync is 60 Hz, then the length is 16.7 milliseconds, equivalent to one cycle of the vertical synchronization signal.

[0072] In the odd-numbered frame V_odd, the scanning signals Scan_a(1), Scan_a(2), ..., Scan_a(m-1), and Scan(m)_a are sequentially and exclusively at the L level during each horizontal scanning period. Furthermore, in the even-numbered frame V_eve, the scanning signals Scan_b(1), Scan_b(2), ..., Scan_b(m-1), and Scan(m)_b are sequentially and exclusively at the L level during each horizontal scanning period.

[0073] The period from when the scanning signal Scan_a(m) changes to the H level to when the scanning signal Scan_b(1) changes to the L level and the period from when the scanning signal Scan_b(m) changes to the H level to when the scanning signal Scan_a(1) changes to the L level are the vertical scanning retrace period V_blnk.

[0074] In the present embodiment, the control signal Enb becomes H level in the vertical scanning retrace period V_blnk.

[0075] In addition, the period from when the scanning signal Scan_a(1) changes to the L level to when the scanning signal Scan_a(m) changes to the H level in the odd-numbered frame V_odd, and the period from when the scanning signal Scan_b(1) changes to the L level to when the scanning signal Scan_b(m) changes to the H level in the even-numbered frame V_eve are sometimes referred to as the horizontal effective scanning period. In this embodiment, for convenience, the horizontal effective scanning period in the odd-numbered frame V_odd is made to coincide with the light-emitting period L_eve, and the horizontal effective scanning period in the even-numbered frame V_eve is made to coincide with the light-emitting period L_odd.

[0076] In this embodiment, the control signal Enb becomes the L level in the light emission periods L_eve and L_odd.

[0077] During the vertical scan retrace period V_blnk before the start of the odd-numbered frame V_odd, the selection signal Sel_a changes from the L level to the H level first, and the selection signal Sel_b changes from the H level to the L level later. Furthermore, during the vertical scan retrace period V_blnk before the start of the even-numbered frame V_eve, the selection signal Sel_b changes from the L level to the H level first, and the selection signal Sel_a changes from the H level to the L level later.

[0078] That is, the selection signals Sel_a and Sel_b are in a relationship where their phases are shifted by 180 degrees.

[0079] First, the operation of the odd-numbered frame V_odd will be described. When the scanning signal Scan_a(i) is at an L level in the odd-numbered frame V_odd, the transistor 122a is turned on in the pixel circuit 110 in the i-th row and j-th column. While the scanning signal Scan_a(i) is at an L level, the scanning signal Scan_b(i) is at an H level, so the transistor 122b is turned off in the pixel circuit 110 in the i-th row and j-th column.

[0080] In this specification, the "on / conducting state" of a switching element or transistor refers to a state in which both ends of the switching element, or the source / drain nodes of a transistor, are electrically closed, resulting in a low-impedance state. Furthermore, the "off / cut-off state" of a switching element or transistor refers to a state in which both ends of the switching element, or the source / drain nodes, are electrically disconnected, resulting in a high-impedance state.

[0081] During the period in the odd-numbered frame V_odd when the scanning signal Scan_a(i) is at the L level, the data signal output circuit 50 converts the grayscale levels of the pixels in rows i and columns 1 to i and columns n, represented by the image data Vdata, into analog potentials Vd(1) to Vd(n), and outputs them as data signals to the data lines 14 in columns 1 to n. For the j-th column, the data signal output circuit 50 converts the grayscale levels of the pixels in rows i and columns j into an analog signal potential Vd(j), and outputs them as data signals to the data line 14 in column j.

[0082] The data signal of the potential Vd(j) is sequentially held by the capacitor C1 a via the data line 14 of the j-th column and the transistor 122 a in the pixel circuit 110 of the i-th row and j-th column.

[0083] Furthermore, although the pixel circuit 110 in the i-th row and j-th column has been described here, the data signal is also held in the capacitor element C1 a in the pixel circuits 110 other than the i-th row and j-th column.

[0084] In the odd-numbered frame V_odd, except for the i-th row, the scanning signals Scan_a(1) to Scan_a(m) are sequentially changed to L level, whereby a data signal having a potential corresponding to the grayscale level of the pixel is held in the capacitor element C1a.

[0085] During the light emission period L_eve in the odd frame V_odd, the selection signal Sel_a is at H level, so the transistor 123a is turned off in all pixel circuits 110. Also, during the light emission period L_eve, the selection signal Sel_b is at L level, so the transistor 123b is turned on in all pixel circuits 110.

[0086] Therefore, in all pixel circuits 110 , one end of the capacitor C1 b is electrically connected to the gate node g of the transistor 121 via the transistor 123 b , so that the voltage held in the capacitor C1 b is applied between the gate node and the source node of the transistor 121 .

[0087] Furthermore, during the light emission period L_eve, the control signal Enb is at the L level, and thus the transistor 124 is in the on state.

[0088] Therefore, in the light emission period L_eve, in all pixel circuits 110 , the transistor 121 allows the voltage between the gate node and the source node, that is, the current corresponding to the grayscale level of the pixel, to flow through the OLED 130 .

[0089] The voltage held in the capacitor C1b during the light emission period L_eve is based on the data signal supplied via the data line 14 in the even frame V_eve preceding the odd frame V_odd. Therefore, during the light emission period L_eve of the odd frame V_odd, the OLEDs 130 in all pixel circuits 110 emit light at a brightness corresponding to the data signal supplied to the even frame V_eve preceding it.

[0090] Next, the operation of the even-numbered frame V_eve will be described. When the scanning signal Scan_b(i) is at an L level in the even-numbered frame V_eve, transistor 122b is turned on in the pixel circuit 110 in row i and column j. While the scanning signal Scan_b(i) is at an L level, the scanning signal Scan_a(i) is at an H level, so transistor 122a is turned off in the pixel circuit 110 in row i and column j.

[0091] During the period in the even frame V_eve when the scanning signal Scan_b(i) is at the L level, the data signal output circuit 50 converts the grayscale levels of the pixels in rows i and columns 1 to i and n, represented by the image data Vdata, into analog potentials Vd(1) to Vd(n), and outputs them as data signals to the data lines 14 in columns 1 to n. For the j-th column, the data signal output circuit 50 converts the grayscale levels of the pixels in rows i and columns j into an analog signal potential Vd(j), and outputs them as data signals to the data line 14 in column j.

[0092] The data signal of the potential Vd(j) is sequentially held by the capacitor C1b via the data line 14 of the j-th column and the transistor 122b in the pixel circuit 110 of the i-th row and j-th column.

[0093] Furthermore, although the pixel circuit 110 in the i-th row and j-th column has been described here, the data signal is also held in the capacitor element C1 b in the pixel circuits 110 other than those in the i-th row and j-th column.

[0094] Furthermore, in the even frame V_eve, except for the i-th row, the scanning signals Scan_b( 1 ) to Scan_b(m) are sequentially changed to L level, whereby a data signal having a potential corresponding to the grayscale level of the pixel is held in the capacitor element C1 b .

[0095] During the light emission period L_eve, the selection signal Sel_b is at H level, so the transistor 123b is turned off in all pixel circuits 110. During the light emission period L_odd, the selection signal Sel_a is at L level, so the transistor 123a is turned on in all pixel circuits 110.

[0096] Therefore, in all pixel circuits 110 , one end of the capacitor C1 a is electrically connected to the gate node g of the transistor 121 via the transistor 123 a , so that the voltage held in the capacitor C1 a is applied between the gate node and the source node of the transistor 121 .

[0097] Furthermore, during the light emission period L_odd, the control signal Enb is at the L level, and thus the transistor 124 is in the on state.

[0098] During the light emission period L_odd, in all pixel circuits 110 , the transistor 121 allows the voltage between the gate node and the source node, that is, the current corresponding to the grayscale level of the pixel, to flow through the OLED 130 .

[0099] As described above, the voltage held in the capacitive element C1 a during the light emission period L_odd is based on the data signal supplied via the data line 14 in the previous odd-numbered frame V_odd.

[0100] Therefore, during the light emission period L_odd, the OLEDs 130 in all the pixel circuits 110 emit light at a brightness corresponding to the data signal of the previous odd frame V_odd supplied thereto.

[0101] In this embodiment, in the odd frame V_odd, the potential of the data signal is sequentially maintained in the capacitor element C1a from the 1st row to the mth row, and in the next even frame V_eve, the control signal Enb becomes L level, thereby simultaneously emitting light in all pixel circuits 110 from the 1st row to the mth row.

[0102] On the other hand, in the even frame V_eve, the potential of the data signal is sequentially held in the capacitor element C1b from the 1st row to the mth row, and in the next odd frame V_odd, the control signal Enb becomes L level, thereby simultaneously emitting light in all pixel circuits 110 from the 1st row to the mth row.

[0103] As described above, in this embodiment, the OLEDs 130 in all the pixel circuits 110 emit light simultaneously based on the voltage held in the previous frame.

[0104] Therefore, in this embodiment, high-speed operation is not required in the operation of making the capacitor element C1a or C1b maintain the potential of the data signal in the 1st to mth rows. In addition, the horizontal effective scanning period can be ensured as the light-emitting period L_eve or Lodd, so the displayed image will not become dark.

[0105] Furthermore, according to this embodiment, when a user wearing the head-mounted display system 1 sees the display image of the electro-optical device 10 superimposed on an actual landscape, it is possible to prevent the displayed image from being distorted when the user moves their head. This point will be described.

[0106] Figure 16A 、 Figure 16B as well as Figure 16C This diagram illustrates how a distorted display image appears in a conventional line-sequential OLED light-emitting configuration. Line-sequential OLED light-emitting configurations are those in which the OLED emits light at approximately the same time as the data signal is held in the capacitor element by the selection of a scan line. In other words, the OLED emits light for each scan line (row).

[0107] In these figures, the frame T represents the visual field of the user wearing the head mounted device 300. Assume that the electro-optical device 10 displays a rectangular object Dj in the visual field T. In this case, Figure 16A 、 Figure 16B as well as Figure 16C As shown in the sequence, when the user moves their head to the right, causing their visual field T to shift dramatically, the timing of light emission in the object Dj changes for each row in a line-sequential OLED light emission configuration. Specifically, for a scene that moves relative to the user's head, the top row Lns in the object Dj begins emitting light first, the roughly middle row Lnc begins emitting light later than row Lns, and the bottom row Lnf begins emitting light last.

[0108] In this way, the start timing of the line becomes delayed as the object Dj moves downward relative to the relatively moving scenery. Therefore, the user sees that the object Dj displayed in the rectangular shape is deformed like the shape Djp.

[0109] In contrast, in this embodiment, the OLED 130 starts emitting light at the same time in all pixel circuits 110, rather than at a different timing for each row. Therefore, this embodiment prevents the displayed image from being distorted when the user moves his head.

[0110] <Modification of the First Embodiment>

[0111] The first embodiment described above can be modified as follows.

[0112] In the first embodiment, as Figure 7As shown, the structure is as follows: after the scanning signal Scan_b(m) changes to the H level, the selection signal Sel_a changes from L to the H level, and then the selection signal Sel_b changes from H to the L level. After the scanning signal Scan_a(m) changes to the H level, the selection signal Sel_b changes from L to the H level, and then the selection signal Sel_a changes from H to the L level.

[0113] Not limited to this structure, such as Figure 8 As shown, the timing at which the scanning signal Scan_b(m) changes to the H level may be aligned with the timing at which the selection signal Sel_a changes from the L level to the H level, and the timing at which the scanning signal Scan_a(m) changes to the H level may be aligned with the timing at which the selection signal Sel_b changes from the L level to the H level. In other words, the timing at which the vertical scanning retrace period V_blnk starts may be aligned with the timing at which the previously connected capacitor element C1a or C1b is disconnected from the gate node g of the transistor 121.

[0114] like Figure 9 As shown, the selection signal Sel_a or the selection signal Sel_b may be changed to H level before the control signal Enb is changed to H level. That is, the capacitor element C1a or C1b may be disconnected from the gate node g of the transistor 121 before the OLED 130 is turned off.

[0115] In addition, in the first embodiment, the period during which the scanning signals Scan_a(1) to Scan_a(m) sequentially become the L level and the period during which the scanning signals Scan_b(1) to Scan_b(m) sequentially become the L level (that is, the entire period of the horizontal effective scanning period) are used as the light-emitting period and the control signal Enb is set to the L level, that is, the OLED 130 is made to emit light.

[0116] Not limited to this structure, such as Figure 10 As shown, a configuration can also be employed to shorten the light-emission period during which the control signal Enb is at an L level, thereby shortening the light-emission period of the OLED 130. With this configuration, shortening the light-emission period of the OLED 130 allows the display characteristics of the electro-optical device 10 to approach a so-called impulse response, thereby reducing the afterimage effect during the display of moving images. Furthermore, the pixel circuit 110 can render darker grayscales.

[0117] In addition, when a part of the horizontal effective scanning period is set as the light-emitting period, Figure 10 As shown, the light-emitting period can be moved forward in time, backward in time, or made into an intermittent period.

[0118] In the first embodiment and the modification of the first embodiment described above, the pixel circuit 110 can be understood as follows: Figure 11 The structure shown.

[0119] like Figure 11 As shown, Figure 6 The transistors 122a and 122b in FIG1 can be understood as the first selector 122. Specifically, when the scan line 12a is selected and the scan signal Scan_a(i) becomes L level in the odd-numbered frame V_odd, the first selector 122 electrically connects one end of the capacitor C1a to the data line 14 of the j-th column. When the scan line 12b is selected and the scan signal Scan_b(i) becomes L level in the even-numbered frame V_eve, the first selector 122 electrically connects one end of the capacitor C1b to the data line 14 of the j-th column.

[0120] In addition, if Figure 11 As shown, Figure 6 The transistors 123a and 123b in FIG1 can be understood as the second selector 123. Specifically, if the selection signal Sel_a is at an H level and the selection signal Sel_b is at an L level in an odd-numbered frame V_odd, the second selector 123 electrically connects one end of the capacitor C1b to the gate node g of the transistor 121. If the selection signal Sel_a is at an L level and the selection signal Sel_b is at an H level in an even-numbered frame V_eve, the second selector 123 electrically connects one end of the capacitor C1a to the gate node g.

[0121] That is, transistor 121 is an example of a driving transistor, transistor 122a is an example of a first switching element, transistor 122b is an example of a second switching element, transistor 123a is an example of a third switching element, and transistor 123b is an example of a fourth switching element. Furthermore, capacitor C1a is an example of a first capacitor, and capacitor C1b is an example of a second capacitor.

[0122] <Second embodiment>

[0123] It is also possible to configure the transistor 121 that controls the current flowing through the OLED 130 to compensate for the threshold voltage. Therefore, a second embodiment in which the threshold voltage of the transistor 121 is compensated will be described.

[0124] The second embodiment differs from the first embodiment only in the configuration of the pixel circuit 110. Therefore, the second embodiment will be described mainly focusing on the differences in the pixel circuit 110.

[0125] Figure 12 1 is a diagram showing a pixel circuit 110 in the electro-optical device 10 according to the second embodiment. Figure 12 In the pixel circuit 110 shown in FIG. Figure 6 In comparison, a capacitor element C2 and p-channel MOS transistors 125 and 126 are added.

[0126] exist Figure 12 In FIG. 1 , the drain node of transistor 123 a and the drain node of transistor 123 b are connected to the drain node of transistor 125 and one end of capacitor C2. The other end of capacitor C2 is connected to gate node g of transistor 121 and the drain node of transistor 126. The source node of transistor 125 is connected to power supply wiring 116, and a control signal Yb is supplied to the gate node. The source node of transistor 126 is connected to drain node d of transistor 121, and a control signal Ya is supplied to the gate node.

[0127] Figure 13 This is a timing chart for explaining the operation of the electro-optical device 10 according to the second embodiment.

[0128] Control signals Ya, Yb are sent from the control circuit 30 (see Figure 5 ) is commonly supplied throughout all pixel circuits 110. Figure 13 Specifically, during the vertical scanning retrace period V_blnk, control signal Yb first becomes L level, then control signal Ya becomes L level, and then control signal Yb first becomes H level, then control signal Ya becomes H level.

[0129] In addition, in this embodiment, the phases of the selection signals Sel_a and Sel_b are shifted by 180 degrees, similar to the first embodiment. The selection signals Sel_a and Sel_b change to H level at the start of the vertical scanning retrace period V_blnk, and change to L level after the control signal Ya changes to H level and before the end of the vertical scanning retrace period V_blnk.

[0130] During the vertical scanning retrace period V_blnk, when the control signal Yb goes low, transistor 125 is turned on, and one end of capacitor C2 reaches the power supply potential ELvdd. Subsequently, when the control signal Ya goes low, transistor 126 is turned on, and the drain and gate nodes of transistor 121 are connected, i.e., diode-connected. Consequently, the voltage between gate node g and source node s of transistor 121 converges to the threshold voltage of transistor 121, and this threshold voltage is maintained by capacitor C2.

[0131] When the control signal Ya goes to H level, the transistor 126 is turned off, and when the control signal Yb goes to H level, the transistor 125 is turned off.

[0132] After the vertical scanning retrace period V_blnk ends, in the light-emission period L_eve, transistor 123b is turned on, so that capacitors C1b and C2 are connected in series between power supply wiring 116 and gate node g of transistor 121. Therefore, the threshold voltage is added to the voltage corresponding to the grayscale level supplied in the previous even-numbered frame V_eve, and this added voltage is applied to gate node g of transistor 121.

[0133] After the vertical scanning retrace period V_blnk ends, during the light-emission period L_odd in the even frame V_eve, transistor 123a is turned on, and capacitors C1a and C2 are connected in series between power supply wiring 116 and gate node g of transistor 121. Therefore, a threshold voltage is added to the voltage corresponding to the grayscale level supplied in the previous odd frame V_odd, and this added voltage is applied to gate node g of transistor 121.

[0134] Figure 14 This is a flowchart showing the operation of the electro-optical device 10 according to the second embodiment. Assuming that step S1 is an operation during the light-emission period L_eve of an odd-numbered frame V_odd, step S1 concurrently executes an operation for causing capacitor element C1a to line-sequentially hold the voltage of the data signal corresponding to the grayscale level, and an operation for causing a current to flow through the OLED 130 to emit light by compensating the threshold voltage of the transistor 121 using the held voltages of capacitor elements C1b and C2.

[0135] In the next step S2 , which is a vertical scanning retrace period V_blnk, an operation is performed to turn off the OLED 130 and to make the capacitor element C2 hold the threshold voltage of the transistor 121 .

[0136] In step S3 , the capacitor C1b line-sequentially holds the voltage of the data signal corresponding to the grayscale level, and the threshold voltage of the transistor 121 is compensated by the held voltages of the capacitors C1a and C2 to flow current through the OLED 130 for light emission.

[0137] In the next step S4 , which is a vertical scanning retrace period V_blnk, an operation is performed to turn off the OLED 130 and to make the capacitor C2 hold the threshold voltage of the transistor 121 .

[0138] Hereinafter, the operations of steps S1 → S2 → S3 → S4 → ( S1 ) are repeatedly executed.

[0139] According to the second embodiment, in any of the odd frames V_odd and the even frames V_eve, the transistor 121 allows a current corresponding to the grayscale to flow through the OLED 130 while compensating the threshold voltage, thereby achieving high-quality display with little variation among the pixel circuits 110 .

[0140] In the second embodiment, it is also possible to Figure 10 As described in , the period during which the control signal Enb is at the L level is shortened, thereby shortening the light emission period of the OLED 130.

[0141] In the second embodiment described above, the pixel circuit 110 can be understood as follows: Figure 15 The structure shown.

[0142] like Figure 15 As shown, if the control signal Ya is at L level during the vertical scanning retrace period V_blnk, then Figure 12 The transistor 126 in FIG. 1 functions as a switching element that electrically short-circuits the gate node g and the drain node d of the transistor 121 to put the transistor 121 into a diode-connected state. That is, the transistor 126 is an example of a sixth switching element.

[0143] Furthermore, capacitor C2 maintains the threshold voltage of transistor 121 when transistors 125 and 126 are in the on state. Furthermore, capacitor C2, which maintains the threshold voltage, is electrically inserted between one end of capacitor C1b and gate node g of transistor 121 during odd-numbered frames V_odd when transistors 125 and 126 are in the off state, selection signal Sel_a is at an H level, and selection signal Sel_b is at an L level. In even-numbered frames V_eve, capacitor C2 is electrically inserted between one end of capacitor C1a and gate node g of transistor 121 when transistors 125 and 126 are in the off state, selection signal Sel_a is at an L level, and selection signal Sel_b is at an H level. That is, capacitor C2 is an example of a third capacitor.

[0144] In this description, “electrically inserted” means inserted between two or more elements when viewed in a circuit.

[0145] <Application Examples / Modifications>

[0146] The first and second embodiments described above (hereinafter referred to as "embodiments, etc.") can be variously applied or modified. Specific modifications applicable to the embodiments, etc. are exemplified below. Two or more arbitrarily selected from the following examples can be combined to the extent that they do not conflict with each other.

[0147] In the electro-optical device 10 of the embodiments, transistor 124 is provided between transistor 121 and OLED 130. However, the location of transistor 124 is not limited to the aforementioned location. Transistor 124 functions to block the path of the current controlled by transistor 121 from flowing through OLED 130. Therefore, any configuration in which transistors 121 and 124 are connected in series between power supply lines 116 and 118 is sufficient. Transistor 124 is an example of a fifth switching element.

[0148] Originally, in the electro-optical device 10, a transistor 124 is provided in the pixel circuit 110, but in an embodiment, the light-emitting period of the OLED 130 in all pixel circuits 110 is the same, so, for example, a power supply circuit not shown in the figure may be configured to supply the power supply potential ELvdd supplied to the power supply wiring 116 corresponding to the light-emitting period.

[0149] In the embodiments, the OLED 130 is described as an example of a light-emitting element, but other light-emitting elements may be used. For example, LEDs (Light Emitting Diodes), mini LEDs, micro LEDs, etc. may be used as light-emitting elements.

[0150] The channel types of the transistors 121 , 122 a , 122 b , 123 a , 123 b , 124 , 125 , and 126 are not limited to those in the embodiments, etc. In addition, these transistors other than the transistor 121 may be replaced with transmission gates as appropriate.

[0151] The electronic device including the electro-optical device 10 is applicable not only to the head-mounted display system 1 but also to projection systems and any other device that allows a user to see an image displayed by the electro-optical device 10 superimposed on an actual scene.

[0152] <Note>

[0153] Based on the above description, for example, preferred embodiments of the present disclosure can be understood as follows. In addition, in order to facilitate understanding of each embodiment, the following figures are collectively described in parentheses for convenience, but this does not mean that the present invention is limited to the illustrated embodiments.

[0154] Note 1

[0155] An electro-optical device (10) of a mode (mode 1) includes a plurality of pixel circuits (110) arranged corresponding to intersections of a data line (14) and a plurality of scanning lines (12), each pixel circuit (110) including a first selector (122), a second selector (123), a first capacitor (C1a), a second capacitor (C1b), a driving transistor (121), and a light-emitting element (130), wherein the driving transistor (121) is capable of supplying a current corresponding to the potential of a gate node (g) to the light-emitting element (130), and in a first frame (V_odd): a plurality of scanning lines (12) are sequentially selected, and the first selector (122) of one pixel circuit (110) among the plurality of pixel circuits (110) is connected to the first selector (122) of the pixel circuit (110) when the first selector (122) is connected to the first selector (123). When a scanning line (12) corresponding to a pixel circuit (110) is selected, one end of the first capacitor element (C1a) is electrically connected to the data line (14), and a second selector (123) in a pixel circuit (110) electrically connects one end of the second capacitor element (C1b) to the gate node (g). In a second frame (V_eve) different from the first frame (V_odd): a plurality of scanning lines (12) are selected in sequence, and when a scanning line (12) is selected, the first selector (122) in a pixel circuit (110) electrically connects one end of the second capacitor element (C1b) to the data line (14), and a second selector (123) in a pixel circuit (110) electrically connects one end of the first capacitor element (C1a) to the gate node (g).

[0156] According to mode 1, in a first frame (V_odd), the potential of the data line (14) is held in a first capacitor element (C1a) in line order, and in a second frame (V_eve), one end of the first capacitor element (C1a) is connected to a gate node (g) of a driving transistor (121), thereby simultaneously lighting the OLED (130). That is, after the line-sequential holding operation in the first frame (V_odd), the light-emitting elements (130) can simultaneously emit light based on the held voltage in the second frame (V_eve).

[0157] Therefore, according to method 1, a longer light emitting period can be ensured without speeding up the line sequential holding operation. In addition, since the light emitting elements (130) can emit light simultaneously, it is possible to prevent the display image from being distorted due to the line sequential light emission.

[0158] Note 2

[0159] In an electro-optical device (10) as a specific embodiment (embodiment 2) of embodiment 1, a first selector (122) includes: a first switching element (122a) that is turned on or off between a data line (14) and one end of a first capacitor (C1a); and a second switching element (122b) that is turned on or off between a data line (14) and one end of a second capacitor (C1b). A second selector (123) includes: a third switching element (123a) that is turned on or off between one end of the first capacitor (C1a) and a gate node (g); and a fourth switching element (123b) that is turned on or off between one end of the second capacitor (C1b) and a gate node (g). According to embodiment 2, the first selector (122) and the second selector (123) can be specifically configured.

[0160] Note 3

[0161] In an electro-optical device (10) that is a specific embodiment (embodiment 3) of embodiment 2, a pixel circuit (110) includes a fifth switching element (124) connected in series with a driving transistor (121) between a high-level power supply wiring (116) and a low-level power supply wiring (118).

[0162] According to mode 3, the driving transistor (121) can supply a current corresponding to the potential of the gate node (g) to the light emitting element (130) by turning on the fifth switching element (124).

[0163] Note 4

[0164] In an electro-optical device (10) as a specific embodiment (embodiment 4) of embodiment 2 or embodiment 3, a pixel circuit (110) includes a third capacitor (C2) for maintaining a threshold voltage of a driving transistor (121), wherein the third capacitor (C2) is inserted between one end of a second capacitor (C1b) and a gate node (g) in a first frame (V_odd), and is inserted between one end of a first capacitor (C1a) and the gate node (g) in a second frame (V_eve). According to embodiment 4, the threshold voltage of the driving transistor (121) can be compensated.

[0165] <Note 5>

[0166] In an electro-optical device (10) as a specific embodiment (embodiment 5) of embodiment 4, a pixel circuit (110) includes a sixth switching element (126) for placing a driving transistor (121) in a diode-connected state. According to embodiment 5, compensation of a threshold voltage in the driving transistor (121) can be specifically configured.

[0167] <Note 6>

[0168] In an electro-optical device (10) as a specific embodiment (embodiment 6) of embodiment 3, 4, or 5, a fifth switching element (124) is turned on during all or part of a period (L_odd or L_eve) during which a plurality of scanning lines (12) are sequentially selected one by one. According to embodiment 6, the light emission period caused by the flow of current through the OLED 130 can be controlled. Specifically, by extending the light emission period, the brightness of the displayed image can be ensured, and by shortening the light emission period, the blurriness of the dynamic image display can be reduced.

[0169] <Note 7>

[0170] An electronic device according to any specific aspect (aspect 7) of aspects 1 to 6 includes the electro-optical device according to any of the above aspects.

[0171] According to aspect 7, a long light emission period can be ensured without increasing the speed of the line-sequential holding operation, thereby preventing the image from being viewed in a distorted manner.

Claims

1. An electro-optical device, wherein: The electro-optical device includes a plurality of pixel circuits arranged corresponding to intersections of a data line and a plurality of scanning lines. Each of the pixel circuits includes a first selector, a second selector, a first capacitor, a second capacitor, a driving transistor, and a light emitting element. The first selector is provided between the data line and one end of the first capacitor and the second capacitor. The second selector is provided between one end of the first capacitor and the second capacitor and the gate node of the driving transistor. The other ends of the first capacitor and the second capacitor are connected to a high-voltage power supply wiring. The driving transistor can supply a current corresponding to the voltage of the gate node to the light emitting element. In frame 1: sequentially selecting the plurality of scan lines, The first selector of one pixel circuit among the plurality of pixel circuits electrically connects one end of the first capacitor element to the data line when a scanning line corresponding to the pixel circuit is selected. The second selector in the one pixel circuit electrically connects one end of the second capacitor to the gate node. In the second frame that is continuous with the first frame: sequentially selecting the plurality of scan lines, The first selector in the one pixel circuit electrically connects one end of the second capacitor to the data line when the one scanning line is selected. The second selector in the one pixel circuit electrically connects one end of the first capacitor to the gate node.

2. The electro-optical device according to claim 1, wherein The first selector includes: a first switching element that is in an on-state or an off-state between the data line and one end of the first capacitor; and a second switching element that is in an on-state or an off-state between the data line and one end of the second capacitor element; The second selector includes: a third switching element that is in an on-state or an off-state between one end of the first capacitor and the gate node; and A fourth switching element is configured to be in an on state or an off state between one end of the second capacitor and the gate node.

3. The electro-optical device according to claim 2, wherein: The pixel circuit includes a fifth switching element connected in series with the driving transistor between the high-voltage power supply wiring and the low-voltage power supply wiring.

4. The electro-optical device according to claim 2 or 3, wherein: The pixel circuit includes a third capacitor element for holding a threshold voltage of the driving transistor. The third capacitor is inserted between one end of the second capacitor and the gate node in the first frame, and is inserted between one end of the first capacitor and the gate node in the second frame.

5. The electro-optical device according to claim 4, wherein The pixel circuit includes a sixth switching element that places the driving transistor in a diode-connected state. The electro-optical device according to claim 3 , wherein: The fifth switching element is turned on during all or part of a period in which the plurality of scanning lines are sequentially selected one by one.

7. An electronic device, wherein: This electronic device comprises the electro-optical device according to any one of claims 1 to 6.

Images