A MF-TDMA frequency hopping anti-interference system based on secondary interference judgment

Abstract

The present invention relates to an MF-TDMA frequency hopping anti-interference system based on secondary interference judgment. The method includes an AD sampling unit, a digital branch filtering unit, a power estimation and secondary interference judgment unit, and a digital demodulation unit. Combining the characteristics of the MF-TDMA system, the method performs power estimation after AD sampling and power estimation after digital branch filtering on multi-carrier signals. The method utilizes the two power estimates combined with secondary interference judgment to accurately detect and identify interference. Furthermore, based on a joint discrimination flag, the method determines whether the signal participates in timing error calculation and data interpolation. Furthermore, the method scales the useful signal through digital forward automatic gain control (AGC). This method can effectively counteract the effects of narrowband interference on a multi-mode, multi-carrier frequency hopping anti-interference communication system.

Description

Technical Field

[0001] The present invention relates to the technical field of communication anti-interference. Background Art

[0002] Currently, to meet the needs of multi-user, high-capacity access, the MF-TDMA frequency-hopping system has become a key communication method in satellite communications. Due to its strong anti-interference and anti-interception capabilities, frequency-hopping communication is widely used in military communications. As a widely used communication method in the field of anti-interference communications, frequency-hopping communication uses a pseudo-random pattern to control the carrier frequency to continuously jump to avoid interference signals, ensuring high-quality and high-precision signal transmission. However, different types of interference are a major factor affecting the performance of this communication system. Accurately detecting and identifying interference and effectively mitigating interference are key factors in improving the performance of this communication system.

[0003] The frequency-hopping processor utilizes multi-mode, multi-carrier frequency-hopping interference mitigation technology. The medium-rate mode utilizes the MF-TDMA system, supporting flexible multi-user and multi-service access, variable communication rates, and robustness against both wideband and narrowband interference. This technology offers significant engineering value for ensuring reliable satellite communications. Traditional single-carrier interference mitigation systems detect and identify interference by estimating signal power within a single hop and comparing power values ​​between hops within a time slot. In multi-carrier systems, when a receiver encounters narrowband interference, only a portion of the received signal may be affected. In this case, applying interference mitigation to multiple carriers as a whole can degrade the performance of unaffected carriers. Furthermore, since multiple carriers share nonlinear components such as receiver front-end amplifiers, high-power interference on a single carrier (causing channel saturation) can cause significant power fluctuations in the other signals after branch filtering, compromising interference detection methods based on power estimation. Due to these phenomena, interference mitigation in multi-carrier systems cannot adopt the simpler strategies used in single-carrier systems. Summary of the Invention

[0004] The purpose of the present invention is to accurately identify and detect interference and provide an MF-TDMA frequency hopping anti-interference system based on secondary interference judgment.

[0005] The above object of the present invention is achieved through the following technical solution: an MF-TDMA frequency hopping anti-interference system based on secondary interference judgment, comprising an AD sampling unit, a digital branch filtering unit, a power estimation and secondary interference judgment unit, and a digital demodulation unit, wherein:

[0006] AD sampling unit: completes analog-to-digital conversion of N intermediate frequency signals to obtain N carrier signals S(n); the N carrier signals are all TDMA frequency hopping signals;

[0007] Digital branch filter unit: performs digital down-conversion sampling on the N carrier signals S(n) after AD sampling to N carrier frequency points; and performs matched filtering on each of the N signals independently to obtain N single-carrier signals; and inputs them into the power estimation and secondary interference judgment unit and the digital demodulation unit;

[0008] The power estimation and secondary interference decision unit performs single-hop power estimation on the N-channel carrier signal S(n) after AD sampling and the N-channel single-carrier signal after digital branch filtering. The unit time slot is used as the minimum decision unit. The results of the two power estimates in different dimensions are combined to make a secondary interference decision, and the decision result is sent to the digital demodulation unit.

[0009] Digital demodulation unit: performs interference suppression on N-channel single-carrier signals based on the received judgment results and completes the demodulation processing.

[0010] Preferably, the power estimation and secondary interference decision unit includes a power estimation I module, an interference detection I module, an N-way power estimation II module and an interference detection II module and an interference decision unit;

[0011] Power Estimation I and Interference Detection I modules: This module compares the average power of the N carrier signals sampled by the AD with the power reference threshold on a hop-by-hop basis to determine whether a particular hop signal in the current timeslot is interfered with. The module then sends an interference indication flag to the Power Estimation II module and the Interference Detection Unit.

[0012] The power estimation II and interference detection II modules eliminate the interfered hop signals based on the received interference indicator flag, and determine whether a hop signal of the corresponding single-carrier signal is interfered with by comparing the average power with the power reference threshold in units of hops. The interference indicator flag is sent to the interference decision unit, and the average power is sent to the digital demodulation unit.

[0013] The interference determination unit sends the interference indication flag to the digital demodulation unit.

[0014] Preferably, the determining whether a certain hop signal in the current time slot is interfered with includes:

[0015] Calculate the average power P of the i-th hop signal in the unit time slot Xi , compare the average power of the single-hop signal in the unit time slot and obtain a minimum power value P min1 ;

[0016] According to the minimum power P min1 and the power reference threshold TH1, P Xi -P min1 >TH1, the signal of the i-th hop in the time slot is considered to be interfered with, and the interference indication flag Flag1 is given. iIf it is 1, otherwise it is considered that the signal of the i-th hop in the time slot is not interfered with, and the interference indication flag Flag1 is given. i is 0.

[0017] Preferably, the power reference threshold TH1 is set according to the channel fluctuation and the normal fluctuation range of the N-channel multi-carrier signal. The reference threshold TH1 should be greater than the power value of the normal fluctuation range of the N-channel multi-carrier signal considering the channel fluctuation.

[0018] Preferably, the determining whether a certain hop signal of the corresponding single-carrier signal is interfered with comprises:

[0019] The average signal power of each single carrier signal output by the digital branch filter unit is calculated independently in units of hops. The average power of the i-th hop in the unit time slot on the N-th carrier is recorded as P N-i , where 1≤i≤M; a single carrier signal in a single time slot contains M hops;

[0020] Ignoring the interfered hops detected by the power estimation I and interference detection I modules on each carrier, the average power of the remaining (Mi) hop signals in the unit time slot on the N carriers is compared to obtain the minimum power value P min2 If P N-i -P min2 >TH2, it is considered that the i-th hop signal on the carrier is interfered with, and the interference indication flag Flag2 is given. i Otherwise, it is considered that the i-th hop signal on the carrier is not interfered with, and the interference indication flag Flag2 i Is 0; set the indicator Flag2 i The average power of the carrier at the ith hop is sent to the digital demodulation unit while being sent to the interference decision unit.

[0021] Preferably, the power reference threshold TH2 is set according to the channel fluctuation and the normal fluctuation range of the single carrier signal. The reference threshold TH2 should be greater than the power value of the normal fluctuation range of the Nth signal considering the channel fluctuation.

[0022] Preferably, the digital demodulation unit includes a parallel-to-serial conversion module, a forward automatic gain control (AGC) module, a unit time slot RAM buffer module, a timing error extraction module, a data interpolation module, and an interference suppression module; wherein:

[0023] The parallel-to-serial conversion module processes the N-channel single-carrier signals after digital branch filtering through RAM buffer to achieve parallel storage and serial output processing;

[0024] The forward automatic gain control (AGC) module performs gain control on the data stream signal after parallel-to-serial conversion based on the average power value received per hop, so that its output power equals the target power, and obtains adjusted per-hop data that is consistent with the target power.

[0025] The unit time slot RAM cache module caches the data in the current unit time slot and delays the corresponding time to match the processing delay of the timing error extraction module;

[0026] The interference suppression module performs interference suppression on the bit timing error of single-hop data in a unit time slot and the data interpolation module based on the interference situation determined by the power estimation and secondary interference decision unit;

[0027] The timing error extraction module extracts the timing error of the unit symbol from the data in the unit time slot after interference suppression, and averages these errors in units of time slots to obtain the timing error value;

[0028] The data interpolation module performs interpolation operation based on the original signal output by the RAM buffer module in the current unit time slot and the timing error value of the timing error extraction module to complete the demodulation processing.

[0029] Preferably, the gain control calculates a gain change factor of each hop signal according to the received average power value, and multiplies the current hop signal by the gain change factor to complete the gain control.

[0030] Preferably, the gain variation factor of each hop signal is calculated in the following manner:

[0031] Calculate the logarithm of the difference between the power of each hop signal and the target power, and then convert the logarithm into a linear value to obtain the gain change factor FN-i of the hop signal = 10^((PA-P N-i ) / 10), where 1≤i≤M, PA is the target power of this time slot, which is determined by the data processing bit width.

[0032] Preferably, the interference suppression of the bit timing error and data interpolation module of the single-hop data in the unit time slot includes:

[0033] If Flag1 i =1 and Flag2 i =1, indicating that both power estimation and interference discrimination detect that the current hop is interfered with. In this case, the timing error contribution of this hop is filtered out when calculating the average timing error in this time slot, and the contribution of the data of this hop is filtered out when using this timing error to perform data interpolation.

[0034] If Flag1 i =1 and Flag2 i = 0, indicating that the signal on this carrier is not interfered with, but the signal on other carriers is interfered with. The contribution of the timing error of this signal should be filtered out when calculating the average timing error in this timeslot.

[0035] If Flag1 i =0 and Flag2 i=0, indicating that the current hopping signals on the N carriers are not interfered with and all hopping signals in this time slot are demodulated normally.

[0036] Compared with the prior art, the present invention has the following beneficial effects: the present invention provides a method for combining dual power estimation to perform secondary interference judgment, and judges whether the signal participates in timing error calculation and data demodulation based on the joint judgment flag, and at the same time scales the useful signal through digital forward automatic gain control (AGC), which can effectively resist the influence of narrowband interference on multi-mode multi-carrier frequency hopping anti-interference communication system.

[0037] The present invention provides an MF-TDMA frequency-hopping anti-interference system based on secondary interference determination. Taking advantage of the unique characteristics of MF-TDMA frequency-hopping systems, this system employs a dual-power combined action mechanism operating in different dimensions to accurately identify the specific location of interference affecting the signal. Compared to existing technologies, this system can more accurately identify interference within the MF-TDMA frequency-hopping system, resulting in more precise and reliable interference determination results.

[0038] The MF-TDMA frequency-hopping anti-interference system based on secondary interference determination, proposed in this paper, utilizes different interference suppression methods based on the power estimation and secondary interference determination results of the forward automatic gain control (AGC) module, the timing error extraction module, and the data interpolation module. Compared to existing technologies, this method can more accurately and reliably suppress the impact of interference on the MF-TDMA frequency-hopping system, effectively improving anti-interference performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a block diagram of the MF-TDMA frequency hopping anti-interference system based on secondary interference judgment;

[0040] Figure 2 This is the flow chart of the N-th carrier power estimation and interference judgment;

[0041] Figure 3 This is the processing block diagram of the demodulation unit. DETAILED DESCRIPTION

[0042] The following is combined with Figure 1-3 The present invention is further introduced.

[0043] like Figure 1 As shown in the system implementation block diagram, the MF-TDMA anti-interference system based on secondary interference judgment of the present invention includes an AD sampling unit, a digital branch filtering unit, a power estimation and secondary interference judgment unit, and a digital demodulation unit, wherein:

[0044] (1) AD sampling unit: completes the analog-to-digital conversion of N intermediate frequency signals to obtain N carrier signals S(n);

[0045] (2) Digital branching unit: Multiply the N-channel AD-sampled signals with the local carrier to convert them to the required local frequency, then perform filtering and signal downsampling. Finally, design the corresponding variable coefficient matched filter according to the required different rates to output N-channel separated signals with different sampling rates.

[0046] The digital branch filter unit includes N channels of carrier signals S(n) after AD sampling to realize N channels of down-conversion to N carrier frequency points f1(n), f2(n), ... f N (n); down sampling filtering and N-way signal independent variable rate matching filtering module, obtain N-way single carrier signals S1(n), S2(n), ..., S N (n). The N carriers are all TDMA frequency-hopping signals, a single carrier signal contains Y time slots, a single time slot contains M hops, and a single unit hop contains X symbols.

[0047] (3) Power Estimation and Secondary Interference Decision Unit: This module completes the interference decision function by performing two-stage power estimation and combining dual power estimation. This module includes the Power Estimation I module, the Interference Detection I module, the N-way Power Estimation II module, and the Interference Detection II module.

[0048] like Figure 2 As shown, the steps are as follows:

[0049] Step 1: Calculate the average power P of the input AD intermediate frequency sampling signal S(n) based on a single hop Xi (average power of the i-th hop signal in the unit time slot), go to Step 2;

[0050] Step 2: Set the power reference threshold TH1 according to the channel fluctuation and the normal fluctuation range of the N-channel multi-carrier signal, and compare the average power of the single-hop signal in the unit time slot to obtain a minimum power value P min1 , go to Step 3;

[0051] Step 3: If the average power of the i-th hop signal in the unit time slot is equal to the minimum power value P in this time slot min1 The difference is greater than the power reference threshold TH1 (ie P Xi -P min1 >TH1), it is considered that the i-th hop signal in the time slot is interfered with, and an interference indication flag Flag1 is given. i Flag1 i If it is 1, it means it is interfered with, and if it is 0, it means it is not interfered with, go to Step 4; otherwise, it is considered that the signal of the i-th hop in the time slot is not interfered with, go to Step 7. i Sent to the power estimation II module and the interference decision unit;

[0052] Step 4: Calculate the average signal power of the N-channel single-carrier signals after digital branching and filtering in units of hops. The average power of the i-th hop in the unit time slot on the N-th carrier is recorded as P N-i , where 1≤i≤M, go to Step 5;

[0053] Step 5: Set the power reference threshold TH2 according to the channel fluctuation and the normal fluctuation range of the single carrier signal, ignoring the interference jump (i.e. Flag1) detected by the first interference on each carrier. i =1), compare the average power of the remaining (Mi) hop signals in the unit time slot on the N carriers respectively, and obtain the minimum power value P min2 , go to Step 6;

[0054] Step 6: If the average power of the i-th hop signal in the unit time slot is equal to the minimum power value P in this time slot min2 The difference is greater than the power reference threshold TH2 (ie P N-i -P min2 >TH2), it is considered that the i-th hop signal on the carrier is interfered with, and the interference indication flag Flag2 is given. i Flag2 i =1 indicates interference, and =0 indicates no interference); otherwise, it is considered that the i-th hop signal on the carrier is not interfered. i Send to the interference judgment unit and go to Step 7;

[0055] Step 7: Send the indication flag of the interference judgment unit to the digital demodulation module.

[0056] Assuming that the channel fluctuates by 3dB and the single-channel signal fluctuates by 1dB, the reference threshold TH1 value should be set to 4dB. Assuming that the channel fluctuates by 3dB and the single-channel signal fluctuates by 15dB, the reference threshold TH2 value can be set to 18dB.

[0057] (4) Digital demodulation unit: Figure 3 As shown, the N signals output by the digital branch are converted from parallel to serial. Forward automatic gain control (AGC) is performed on the serial signal. A bit timing algorithm is used to demodulate the digital signal. While buffering the data of X symbols per time slot, the bit timing algorithm extracts the bit timing error per symbol and averages these errors on a hop-by-hop basis. Interference suppression is performed on the timing error of the digital demodulation unit and the digital interpolation module based on the dual power interference indicator generated by the power estimation and secondary interference decision module. While buffering the data per time slot, the bit timing algorithm extracts the bit timing error per symbol and averages these errors on a hop-by-hop basis. Decisions are made based on the dual power interference indicator generated by the power estimation and interference decision module.

[0058] The digital demodulation unit includes a parallel-to-serial conversion module, a forward automatic gain control (AGC) module, a unit time slot RAM buffer module, a timing error extraction module, a data interpolation module, and an interference suppression module.

[0059] The parallel-to-serial conversion module processes the N parallel signals after digital branch filtering through RAM cache to achieve parallel storage and serial output processing. The subsequent unit time slot RAM cache module and timing error extraction module use serial data stream processing to reduce resource overhead.

[0060] The forward automatic gain control (AGC) module performs gain control and data slicing on the data stream signal after parallel-to-serial conversion. The gain control module calculates the gain change factor for each hop based on the average power values ​​from the Power Estimation II and Interference Detection II modules. The output signal is multiplied by the gain change factor, and then subjected to slicing and truncation to obtain the output signal of the current module. The gain change factor for each hop is calculated as follows:

[0061] Calculate the difference (logarithmic value) between the power of each hop signal and the target power, and then convert the logarithmic value into a linear value to obtain the gain change factor FN-i of the hop signal = 10^((PA-P N-i ) / 10), where 1≤i≤M, PA is the target power of this time slot, which is determined by the data processing bit width.

[0062] The unit time slot RAM cache module caches the data in the current unit time slot and delays the corresponding time to match the processing delay of the timing error extraction module.

[0063] The timing error extraction module extracts the timing error of the unit symbol (multiple symbols constitute one hop, and multiple hops constitute one time slot) from the data in the unit time slot after interference suppression, and averages these errors in units of hops.

[0064] The data interpolation module performs interpolation operation based on the original signal output by the RAM buffer of the current time slot (the original signal is the signal output by the digital filter module after being buffered by the RAM) and the timing error value of the timing error extraction module.

[0065] The interference suppression module performs interference suppression on the bit timing error of single-hop data in a unit time slot and the data interpolation module according to the power estimation and the interference situation determined by the secondary interference decision unit.

[0066] (4.1) If Flag1 i =1 and Flag2 i=1, indicating that both power estimation and interference discrimination detect that the i-th hop signal is interfered with. In this case, the contribution of the timing error of the i-th hop signal is filtered out when calculating the average timing error in this time slot. At the same time, the contribution of the i-th hop data is filtered out when using this timing error to perform data interpolation.

[0067] (4.2) If Flag1 i =1 and Flag2 i = 0, indicating that the i-th hop signal on the N-th carrier is not interfered with, but the i-th hop signals on other carriers are interfered with. However, due to the nonlinear effects of active devices, the interference with the i-th hop signal on other carriers will suppress the i-th hop signal on the N-th carrier, resulting in a decrease in the effective power of the i-th hop signal on the N-th carrier. This will affect the calculation of the average timing error, so the contribution of the timing error of the i-th hop signal should be filtered out when calculating the average timing error in this time slot.

[0068] (4.3) If Flag1 i =0 and Flag2 i =0, indicating that the i-th hop signal on the N-channel carrier is not interfered with and all hop signals in this time slot are demodulated normally;

[0069] Due to the existence of the automatic gain control (AGC) module, the power of the i-th hop signal can be adjusted within a certain range. Therefore, when performing data interpolation, the influence of the i-th hop signal of the N-th carrier should be considered (that is, data interpolation operation should be performed on the current hop signal), thereby reducing the impact of interference on the performance of the communication system.

[0070] The contents not described in detail in the specification of the present invention belong to the common knowledge of professionals in this field.

Claims

1. A MF-TDMA frequency hopping anti-interference system based on secondary interference judgment, characterized in that It includes AD sampling unit, digital branch filtering unit, power estimation and secondary interference judgment unit, and digital demodulation unit, among which: AD sampling unit: completes analog-to-digital conversion of N intermediate frequency signals to obtain N carrier signals S(n); the N carrier signals are all TDMA frequency hopping signals; Digital branch filter unit: performs digital down-conversion sampling on the N carrier signals S(n) after AD sampling to N carrier frequency points; and performs matched filtering on each of the N signals independently to obtain N single-carrier signals; and inputs them into the power estimation and secondary interference judgment unit and the digital demodulation unit; The power estimation and secondary interference decision unit performs single-hop power estimation on the N-channel carrier signal S(n) after AD sampling and the N-channel single-carrier signal after digital branch filtering. The unit time slot is used as the minimum decision unit. The results of the two power estimates in different dimensions are combined to make a secondary interference decision, and the decision result is sent to the digital demodulation unit. Digital demodulation unit: performs interference suppression on N-channel single-carrier signals based on the received judgment results and completes the demodulation process; The power estimation and secondary interference decision unit includes a power estimation I module, an interference detection I module, an N-way power estimation II module and an interference detection II module and an interference decision unit; Power Estimation I and Interference Detection I modules: This module compares the average power of the N carrier signals sampled by the AD with the power reference threshold on a hop-by-hop basis to determine whether a particular hop signal in the current timeslot is interfered with. The module then sends an interference indication flag to the Power Estimation II module and the Interference Detection Unit. The power estimation II and interference detection II modules eliminate the interfered hop signals based on the received interference indicator flag, and determine whether a hop signal of the corresponding single-carrier signal is interfered with by comparing the average power with the power reference threshold in units of hops. The interference indicator flag is sent to the interference decision unit, and the average power is sent to the digital demodulation unit. The interference determination unit sends the interference indication flag to the digital demodulation unit.

2. The system according to claim 1, wherein: Determining whether a certain hop signal in the current time slot is interfered with includes: Calculate the average power P of the i-th hop signal in the unit time slot Xi , compare the average power of the single-hop signal in the unit time slot and obtain a minimum power value P min1 ; According to the minimum power P min1 and the power reference threshold TH1, P Xi -P min1 >TH1, the signal of the i-th hop in the time slot is considered to be interfered with, and the interference indication flag Flag1 is given. i If it is 1, otherwise it is considered that the signal of the i-th hop in the time slot is not interfered with, and the interference indication flag Flag1 is given. i is 0.

3. The system according to claim 2, characterized in that: The power reference threshold TH1 is set according to the channel fluctuation and the normal fluctuation range of the N-channel multi-carrier signal. The reference threshold TH1 should be greater than the power value of the normal fluctuation range of the N-channel multi-carrier signal considering the channel fluctuation.

4. The system according to claim 1, wherein: The determining whether a certain hop signal of the corresponding single carrier signal is interfered with comprises: The average signal power of each single carrier signal output by the digital branch filter unit is calculated independently in units of hops. The average power of the i-th hop in the unit time slot on the N-th carrier is recorded as P N-i , where 1≤i≤M; a single carrier signal in a single time slot contains M hops; Ignoring the interfered hops detected by the power estimation I and interference detection I modules on each carrier, the average power of the remaining (Mi) hop signals in the unit time slot on the N carriers is compared to obtain the minimum power value P min2 If P N-i -P min2 >TH2, it is considered that the i-th hop signal on the carrier is interfered with, and the interference indication flag Flag2 is given. i Otherwise, it is considered that the i-th hop signal on the carrier is not interfered with, and the interference indication flag Flag2 i Is 0; set the indicator Flag2 i The average power of the carrier at the ith hop is sent to the digital demodulation unit while being sent to the interference decision unit.

5. The system according to claim 4, characterized in that: The power reference threshold TH2 is set according to the channel fluctuation and the normal fluctuation range of the single carrier signal. The reference threshold TH2 should be greater than the power value of the normal fluctuation range of the Nth signal considering the channel fluctuation.

6. The system according to claim 4, characterized in that: The digital demodulation unit includes a parallel-to-serial conversion module, a forward automatic gain control module, a unit time slot RAM buffer module, a timing error extraction module, a data interpolation module and an interference suppression module; wherein: The parallel-to-serial conversion module processes the N-channel single-carrier signals after digital branch filtering through RAM buffer to achieve parallel storage and serial output processing; The forward automatic gain control module performs gain control on the data stream signal after parallel-to-serial conversion based on the average power value of each hop received, so that its output power is equal to the target power, and the adjusted data per hop is consistent with the target power. The unit time slot RAM cache module caches the data in the current unit time slot and delays the corresponding time to match the processing delay of the timing error extraction module; The interference suppression module performs interference suppression on the bit timing error of single-hop data in a unit time slot and the data interpolation module based on the interference situation determined by the power estimation and secondary interference decision unit; The timing error extraction module extracts the timing error of the unit symbol from the data in the unit time slot after interference suppression, and averages these errors in units of time slots to obtain the timing error value; The data interpolation module performs interpolation operation based on the original signal output by the RAM buffer module in the current unit time slot and the timing error value of the timing error extraction module to complete the demodulation processing.

7. The system according to claim 6, characterized in that: The gain control calculates the gain change factor of each hop signal according to the received average power value, and multiplies the current hop signal by the gain change factor to complete the gain control.

8. The system according to claim 7, characterized in that: The gain change factor of each hop signal is calculated as follows: Calculate the logarithm of the difference between the power of each hop signal and the target power, and then convert the logarithm into a linear value to obtain the gain change factor FN-i of the hop signal = 10^((PA-P N-i ) / 10), where 1≤i≤M, PA is the target power of this time slot, which is determined by the data processing bit width.

9. The system according to claim 6, characterized in that: The interference suppression of the bit timing error and data interpolation module of the single-hop data in the unit time slot includes: If Flag1 i =1 and Flag2 i =1, indicating that both power estimation and interference discrimination detect that the current hop is interfered with. In this case, the timing error contribution of this hop is filtered out when calculating the average timing error in this time slot, and the contribution of the data of this hop is filtered out when using this timing error to perform data interpolation. If Flag1 i =1 and Flag2 i = 0, indicating that the signal on this carrier is not interfered with, but the signal on other carriers is interfered with. The contribution of the timing error of this signal should be filtered out when calculating the average timing error in this timeslot. If Flag1 i =0 and Flag2 i =0, indicating that the current hopping signals on the N carriers are not interfered with and all hopping signals in this time slot are demodulated normally.

Images