Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes a first display area and a second display area. The transmittance of the first display area is greater than that of the second display area. The first display area includes a plurality of first light-emitting elements, and the second display area includes a plurality of second light-emitting elements. The first and second light-emitting elements have the same distribution density. The second display area includes a plurality of first pixel circuits and a plurality of second pixel circuits. The first pixel circuits are electrically connected to the first light-emitting elements in a one-to-one correspondence, and the second pixel circuits are electrically connected to the second light-emitting elements in a one-to-one correspondence. The technical solutions of the embodiments of the present invention can improve the display effect of the first display area while maintaining the transmittance of the first display area.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display devices, full-screen technology has received widespread attention and research.

[0003] In order to enable the display device to have both full-screen display and front-facing light-sensing functions, such as realizing fingerprint recognition, front-facing camera and other functions in the display area, the photosensitive element is usually built into the bottom of the screen, and by adjusting the pixel design of the photosensitive functional area, the area can both display and transmit light, so that the display device has both full-screen display and front-facing light-sensing functions.

[0004] Existing technologies usually adopt methods such as reducing the pixel density of the photosensitive functional area or placing the pixel circuit therein in the transition area around the photosensitive functional area to meet the transmittance requirements of the photosensitive functional area. However, most of the above methods have problems such as poor display effect of the photosensitive functional area. Summary of the Invention

[0005] The present invention provides a display panel and a display device, which can improve the display effect of the first display area while ensuring the light transmittance of the first display area.

[0006] According to one aspect of the present invention, there is provided a display panel comprising a first display area and a second display area, wherein the light transmittance of the first display area is greater than the light transmittance of the second display area;

[0007] The first display area includes a plurality of first light-emitting elements, and the second display area includes a plurality of second light-emitting elements, and the distribution density of the first light-emitting elements and the second light-emitting elements is the same;

[0008] The second display area includes a plurality of first pixel circuits and a plurality of second pixel circuits; the first pixel circuits are electrically connected to the first light-emitting elements in a one-to-one correspondence; and the second pixel circuits are electrically connected to the second light-emitting elements in a one-to-one correspondence.

[0009] According to another aspect of the present invention, a display device is provided, comprising the display panel provided by any embodiment of the present invention.

[0010] The technical solution of the embodiment of the present invention is to provide a display panel including a first display area and a second display area, and to provide the first display area including a plurality of first light-emitting elements, and the second display area including a plurality of second light-emitting elements, a plurality of first pixel circuits, and a plurality of second pixel circuits, so that the distribution density of the first light-emitting elements and the second light-emitting elements is the same, and the first pixel circuits are electrically connected to the first light-emitting elements in a one-to-one correspondence, and the second pixel circuits are electrically connected to the second light-emitting elements in a one-to-one correspondence. In this way, since only the first light-emitting elements are provided in the first display area, the transmittance requirement of the first display area can be guaranteed. Furthermore, since the space in the second display area is more sufficient, the size of at least part of the pixel circuits can be compressed, and the first pixel circuit corresponding to the first light-emitting element in the first display area and the second pixel circuit corresponding to the second light-emitting element in the second display area can both be provided in the second display area, and one first pixel circuit drives one first light-emitting element, and one second pixel circuit drives one second light-emitting element. Since the distribution density of the first light-emitting elements and the second light-emitting elements is the same, the first display area and the second display area can have the same display PPI, thereby improving the display effect of the first display area.

[0011] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 This is a structural diagram of an existing display panel;

[0014] Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0015] Figure 3 is a schematic diagram of an enlarged structure of a display panel provided by an embodiment of the present invention;

[0016] Figure 4 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0017] Figure 5 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0018] Figure 6 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0019] Figure 7 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 8 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0021] Figure 9 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0022] Figure 10 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0023] Figure 11 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0024] Figure 12 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0025] Figure 13 is with Figure 12 A schematic diagram of the enlarged structure of a display panel corresponding to the middle area Q4;

[0026] Figure 14 is a schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0027] Figure 15 is with Figure 12 A schematic diagram of an enlarged structure of another display panel corresponding to the middle area Q4;

[0028] Figure 16 is with Figure 12 A schematic diagram of an enlarged structure of another display panel corresponding to the middle area Q4;

[0029] Figure 17 is with Figure 12 A schematic diagram of an enlarged structure of another display panel corresponding to the middle area Q4;

[0030] Figure 18 is with Figure 12 A schematic diagram of an enlarged structure of another display panel corresponding to the middle area Q4;

[0031] Figure 19 is with Figure 12 A schematic diagram of an enlarged structure of another display panel corresponding to the middle area Q4;

[0032] Figure 20 is with Figure 12A schematic diagram of an enlarged structure of another display panel corresponding to the middle area Q4;

[0033] Figure 21 is with Figure 12 A schematic diagram of an enlarged structure of another display panel corresponding to the middle area Q4;

[0034] Figure 22 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0035] Figure 23 is a schematic cross-sectional structural diagram of a display panel provided by an embodiment of the present invention;

[0036] Figure 24 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only embodiments of a part of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention. It should be noted that the terms "first", "second", "third", "fourth" and so on in the embodiments of the present invention are only used for distinction and have no substantive meaning.

[0038] Figure 1 This is a schematic diagram of the structure of an existing display panel, such as Figure 1 As shown, the display area FA of the display panel includes a first area Q1, a second area Q2 and a third area Q3, and the second area Q2 is located between the first area Q1 and the third area Q3. Among them, the first area Q1 is the above-mentioned photosensitive functional area, which has both display and photosensitive functions, and can realize photosensitive functions such as front camera or fingerprint recognition. The second area Q2 and the third area Q3 are areas with only display functions. The display panel realizes the display function by emitting light from sub-pixels arranged in an array. The sub-pixels include light-emitting elements and pixel circuits for driving the light-emitting elements to emit light. The correspondence between the light-emitting elements and the pixel circuits can be one pixel circuit corresponding to one light-emitting element, or one pixel circuit corresponding to at least two light-emitting elements. In order to ensure the display effect, the pixel circuits are usually set to correspond one to one with the light-emitting elements.

[0039] In the prior art, to meet the transmittance requirements of the first zone Q1, the pixel circuits corresponding to the light-emitting elements in the first zone Q1 are disposed in the second zone Q2 (i.e., the aforementioned transition zone). To do so, it is necessary to compress the sizes of the pixel circuits corresponding to the light-emitting elements in the first zone Q1 and the light-emitting elements in the second zone Q2 so that these pixel circuits can be integrated into the second zone Q2. Due to the smaller area of ​​the second zone Q2, the compression space for the pixel circuits is limited. When the resolution of the light-emitting elements in the first zone Q1 is high, it is difficult to achieve a one-to-one correspondence between the pixel circuits and the light-emitting elements. Instead, a solution is usually adopted in which one pixel circuit drives multiple light-emitting elements simultaneously. This results in the actual display PPI (Pixels Per Inch) of the first zone Q1 being lower than that of the third zone Q3, resulting in a poorer display effect in the first zone Q1.

[0040] To solve the above problems, an embodiment of the present invention provides a display panel, including a first display area and a second display area, the transmittance of the first display area is greater than the transmittance of the second display area; the first display area includes a plurality of first light-emitting elements, the second display area includes a plurality of second light-emitting elements, and the distribution density of the first light-emitting elements and the second light-emitting elements is the same; the second display area includes a plurality of first pixel circuits and a plurality of second pixel circuits; the first pixel circuits and the first light-emitting elements are electrically connected in a one-to-one correspondence; the second pixel circuits and the second light-emitting elements are electrically connected in a one-to-one correspondence.

[0041] By adopting the above scheme, since the first light-emitting element is provided in the first display area but the corresponding pixel circuit is not provided, the transmittance requirement of the first display area can be guaranteed. Furthermore, since the space in the second display area is more sufficient, the first pixel circuit corresponding to the first light-emitting element in the first display area and the second pixel circuit corresponding to the second light-emitting element in the second display area can be arranged in the second display area by compressing the size of at least part of the pixel circuit, and the first pixel circuit is electrically connected to the first light-emitting element in a one-to-one correspondence, and the second pixel circuit is electrically connected to the second light-emitting element in a one-to-one correspondence. Since the distribution density of the first light-emitting element and the second light-emitting element is the same, the first display area and the second display area can have the same display PPI, thereby improving the display effect of the first display area.

[0042] The above is the core concept of this application. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application. The following will clearly and completely describe the technical solutions in the embodiments of this application in conjunction with the accompanying drawings.

[0043] Figure 2 is a structural diagram of a display panel provided by an embodiment of the present invention, Figure 3This is a schematic diagram of the enlarged structure of a display panel provided by an embodiment of the present invention, combined with Figure 2 and Figure 3 As shown, the display panel 100 provided by the embodiment of the present invention includes a first display area S1 and a second display area S2, the transmittance of the first display area S1 is greater than the transmittance of the second display area S2; the first display area S1 includes a plurality of first light-emitting elements P1, the second display area S2 includes a plurality of second light-emitting elements P2, and the distribution density of the first light-emitting elements P1 and the second light-emitting elements P2 is the same; the second display area S2 includes a plurality of first pixel circuits C1 and a plurality of second pixel circuits C2; the first pixel circuits C1 and the first light-emitting elements P1 are electrically connected in a one-to-one correspondence; the second pixel circuits C2 and the second light-emitting elements P2 are electrically connected in a one-to-one correspondence.

[0044] The first display area S1 is the aforementioned light-sensing area, which can be used to implement light-sensing functions such as front-facing camera and fingerprint recognition, as well as display functions. The second display area S2 is the display area of ​​the total display area FA of the display panel excluding the first display area S1, and has a display function.

[0045] It should be noted that Figure 2 For illustration, the display panel includes a first display area S1, which is located within the total display area FA of the display panel. In other embodiments, the display panel may include a larger number of first display areas S1, and any first display area S1 may be adjacent to at least one edge of the total display area FA of the display panel. The embodiment of the present invention does not impose any particular limitation on the number and location of the first display areas S1.

[0046] like Figure 2 As shown, the first display area S1 includes multiple first light-emitting elements P1, and the second display area S2 includes multiple second light-emitting elements P2. The distribution density of the first light-emitting elements P1 and the second light-emitting elements P2 is the same. In other words, the number of first light-emitting elements P1 and the number of second light-emitting elements P2 in the same space are the same.

[0047] Optionally, the plurality of first light emitting elements P1 may include at least two light emitting elements with different luminous colors, and the plurality of second light emitting elements P2 may include at least two light emitting elements with different luminous colors, so as to achieve color display. Figure 2, the first light-emitting element P1 and the second light-emitting element P2 both include a red light-emitting element R emitting red light, a green light-emitting element G emitting green light, and a blue light-emitting element B emitting blue light. Further, the first light-emitting element P1 and the second light-emitting element P2 have the same distribution density. This means that within the first display area S1 and the second display area S2, the number of red light-emitting elements R in the same space is the same, the number of green light-emitting elements G in the same space is the same, and the number of blue light-emitting elements B in the same space is the same, that is, the distribution density of light-emitting elements of the same light-emitting color is the same in the first display area S1 and the second display area S2.

[0048] It should be noted that the areas of the first light-emitting element P1 and the second light-emitting element P2 of the same luminous color in the first display area S1 and the second display area S2 may be equal or unequal. For example, in order to further improve the transmittance of the first display area S1, the area of ​​the first light-emitting element P1 may be set to be smaller than the area of ​​the second light-emitting element P2 of the same luminous color. Alternatively, since the first pixel circuit C1 electrically connected to the first light-emitting element P1 is not provided in the first display area S1 in the embodiment of the present invention, in other embodiments, while ensuring the transmittance requirement of the first display area S1, the area of ​​the first light-emitting element P1 may be appropriately increased so that the area of ​​the first light-emitting element P1 is larger than the area of ​​the second light-emitting element P2 of the same luminous color. The embodiment of the present invention is not limited to this.

[0049] It should also be noted that Figure 2 In the display panel shown, the arrangement of the first light-emitting elements P1 and the second light-emitting elements P2 is for illustration only and is not intended to be limiting. Those skilled in the art may configure the pixel arrangement as needed, and this is not limited in the present invention. The only requirement is that the first light-emitting elements P1 and the second light-emitting elements P2 have the same distribution density.

[0050] Optionally, the first light-emitting element P1 and the second light-emitting element P2 are organic light-emitting diodes (OLEDs). OLEDs include an anode, a light-emitting layer, and a cathode that are stacked. Figure 2 The shape of the first light emitting element P1 or the second light emitting element P2 shown can be understood as the shape of the positive projection of the anode in the light emitting element on the plane where the display panel is located. Figure 2 In the display panel shown, the first light emitting element P1 and the second light emitting element P2 having the same luminous color have the same shape and are both polygonal, which is only for illustration and not for limitation.

[0051] Figure 4 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, such as Figure 4As shown, in other embodiments, the first light-emitting element P1 optionally includes a first anode D1, and the orthographic projection of the first anode D1 on the plane of the display panel is circular. This configuration can improve the diffraction phenomenon in the first display area S1, which is beneficial for improving the imaging quality of the photosensitive element disposed below the display panel corresponding to the first display area S1. It should be noted that in other embodiments, the shape of the first anode of the first light-emitting element P1 can also be quasi-circular, such as an elliptical shape, and this is not limited in the present embodiment.

[0052] also, Figure 5 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, such as Figure 5 As shown, the second display area S2 optionally includes a first display area S21 and a second display area S22, and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first display area S21 is located in the second display area S22. Specifically, the first display area S21 is provided with multiple second light-emitting elements P2, but no second pixel circuit C2 corresponding to these second light-emitting elements P2 is provided. In this way, the first display area S21 also has a certain light transmittance and can serve as a photosensitive functional area. A photosensitive element is provided below the display panel corresponding to the first display area S21. In a specific embodiment, optionally, the first display area S1 corresponds to the camera area, and the first display area portion S21 corresponds to the area where other photosensitive elements are located, for example, a photosensitive element whose requirements for incident light are lower than the camera's requirements for incident light for face recognition (Face ID). In this way, the transmittance of the first display area portion S21 may be lower than the transmittance of the first display area S1. In addition, the diffraction phenomenon of light has little effect on the face recognition result. Therefore, the second light-emitting element P2 in the first display area portion S21 can maintain the same area and polygonal shape as the second light-emitting element P2 in the second display area portion S22, and there is no need to adjust it to a circular or quasi-circular shape to improve diffraction.

[0053] Furthermore, in this embodiment, the pixel circuit for driving the first light-emitting element P1 to emit light is referred to as the first pixel circuit C1, and the pixel circuit for driving the second light-emitting element P2 to emit light is referred to as the second pixel circuit C2, for purposes of distinction. For example, the first pixel circuit C1 and the second pixel circuit C2 may be pixel circuits composed of thin-film transistors and storage capacitors, such as a 7T1C (T represents a thin-film transistor, and C represents a capacitor) pixel circuit commonly used in the industry, but this is not limited in the embodiment of the present invention.

[0054] In the embodiment of the present invention, the first pixel circuit C1 corresponding to the first light-emitting element P1 and the second pixel circuit C2 corresponding to the second light-emitting element P2 are both arranged in the second display area S2, so that the first light-emitting element P1 is arranged in the first display area S1 but the first pixel circuit C1 is not arranged, thereby ensuring the transmittance requirement of the first display area S1.

[0055] In addition, since there is sufficient space in the second display area S2, the size of at least part of the pixel circuit (the first pixel circuit C1 and / or the second pixel circuit C2) can be compressed to achieve the arrangement of the first pixel circuit C1 and the second pixel circuit C2 in the second display area S2, while ensuring that the first pixel circuit C1 and the first light-emitting element P1 are electrically connected in a one-to-one correspondence, and the second pixel circuit C2 and the second light-emitting element P2 are electrically connected in a one-to-one correspondence, thereby achieving a one-to-one driving of the pixel circuit to the light-emitting element. In this way, when the first pixel circuit C1 and the second pixel circuit C2 have the same driving capability, compared with one first pixel circuit C1 driving multiple first light-emitting elements P1 to emit light, the one-to-one driving is conducive to improving the light-emitting brightness of the first light-emitting element P1. degree, ensuring that the actual luminance of the first light-emitting element P1 reaches the expected brightness, thereby improving the display effect of the first display area S1; in addition, while ensuring the luminance of each light-emitting element, if one pixel circuit drives multiple light-emitting elements to emit light, it is necessary to improve the driving capability of the pixel circuit. In contrast, the embodiment of the present invention sets the first pixel circuit C1 to be electrically connected to the first light-emitting element P1 in a one-to-one correspondence, and the second pixel circuit C2 to be electrically connected to the second light-emitting element P2 in a one-to-one correspondence, which is conducive to reducing the requirements on the driving capability of the pixel circuit and extending the service life of the components in the pixel circuit; in addition, by setting the pixel circuit to drive the light-emitting elements one-to-one, it is conducive to more flexible and individual adjustment of the luminance of each light-emitting element, thereby improving the display effect.

[0056] In this embodiment, since the first pixel circuits C1 and the first light-emitting elements P1 are electrically connected in a one-to-one correspondence, and the second pixel circuits C2 and the second light-emitting elements P2 are electrically connected in a one-to-one correspondence, and the first light-emitting elements P1 and the second light-emitting elements P2 are distributed at the same density, the first display area S1 and the second display area S2 can have the same display PPI, effectively improving the display quality of the first display area S1. Specifically, when the distribution density of the first light-emitting elements P1 and the second light-emitting elements P2 are the same, if one first pixel circuit C1 simultaneously drives multiple first light-emitting elements P1, and one second pixel circuit C2 drives one second light-emitting element P2, and the driving capabilities of the first pixel circuits C1 and the second pixel circuits C2 are the same, the luminance of the multiple first light-emitting elements P1 in the first display area S1 is only equivalent to the luminance of one second light-emitting element P2 in the second display area S2, resulting in the actual number of display pixels per inch in the first display area S1 being lower than the actual number of display pixels per inch in the second display area S2, resulting in a poor display quality in the first display area S1. In contrast, the embodiment of the present invention sets a one-to-one electrical connection between the first pixel circuit C1 and the first light-emitting element P1, a one-to-one electrical connection between the second pixel circuit C2 and the second light-emitting element P2, and sets the distribution density of the first light-emitting element P1 and the second light-emitting element P2 to be the same, so that the display pixels per inch of the first display area S1 and the second display area S2 can be consistent, so that the two have the same display PPI, thereby effectively improving the display effect of the first display area.

[0057] Exemplarily, the size of the pixel circuit can be compressed by reducing the line width, line spacing, etc. in the pixel circuit. Specifically, the display panel includes a plurality of scan lines and a plurality of data lines, the extension directions of the scan lines and the data lines intersect, and both the scan lines and the data lines overlap and are electrically connected to the setting area of ​​the pixel circuit. The size of the pixel circuit can be compressed by compressing the length of the pixel circuit along the extension direction of the scan lines, and / or by compressing the length of the pixel circuit along the extension direction of the data lines. For example, the length of the pixel circuit along the extension direction of the data lines can be compressed by compressing the width of the scan lines along the extension direction of the data lines, and / or by compressing the distance between two adjacent scan lines in the extension direction of the data lines. For another example, the length of the pixel circuit along the extension direction of the scan lines can be compressed by compressing the width of the data lines or the PVDD power signal lines along the extension direction of the scan lines, and / or by compressing the distance between at least one pair of signal lines among two adjacent data lines, two adjacent PVDD power signal lines, and two adjacent data lines and PVDD power signal lines in the extension direction of the scan lines.

[0058] like Figure 3As shown, the first light-emitting element P1 and its corresponding first pixel circuit C1 are located in different areas, and the two can be electrically connected by a connecting line 8. Specifically, the light-emitting element (first light-emitting element P1 / second light-emitting element P2) and the pixel circuit (first pixel circuit C1 / second pixel circuit C2) overlapping at both ends of a connecting line 8 represent the pixel circuit and light-emitting element connected by the connecting line (the same below). Figure 3 In the figure, the first light-emitting element P1-1 is electrically connected to the first pixel circuit C1-1 via the connecting line 8. In addition, since the area of ​​the first display area S1 is much smaller than that of the second display area S2, it may only be necessary to adjust the area and position of part of the second pixel circuit C2 to achieve the setting of the first pixel circuit C1 in the second display area S2. At this time, the relative position relationship between part of the second light-emitting element P2 and the corresponding second pixel circuit C2 is not adjusted, and the two still overlap in the direction perpendicular to the plane of the display panel. Therefore, the two can be electrically connected through a via. Figure 3 A second light emitting element P2 overlaps with a second pixel circuit C2, and both overlap with a solid dot, indicating that the second light emitting element P2 is electrically connected to the second pixel circuit C2 (the same applies below). Figure 3 In FIG, the second light emitting element P2-1 overlaps with the second pixel circuit C2-1, and both overlap with a solid dot, indicating that the second light emitting element P2-1 is electrically connected to the second pixel circuit C2-1.

[0059] It should be noted that Figure 3 The distribution of the first pixel circuits C1 and the second pixel circuits C2 shown is for illustrative purposes only and is not intended to be limiting. The first pixel circuits C1 and the second pixel circuits C2 may be distributed in any manner within the second display area S2. This is not limited in the present embodiment and will be described exemplarily later. Furthermore, a second light-emitting element P2 may be electrically connected to at least one second pixel circuit C2 that is adjacent to but not electrically connected to it.

[0060] In summary, the embodiment of the present invention provides a display panel including a first display area and a second display area, and provides the first display area including a plurality of first light-emitting elements, and the second display area including a plurality of second light-emitting elements, a plurality of first pixel circuits, and a plurality of second pixel circuits, so that the distribution density of the first light-emitting elements and the second light-emitting elements is the same, and the first pixel circuits are electrically connected to the first light-emitting elements in a one-to-one correspondence, and the second pixel circuits are electrically connected to the second light-emitting elements in a one-to-one correspondence. In this way, since only the first light-emitting elements are provided in the first display area, the transmittance requirement of the first display area can be guaranteed. Furthermore, since the space in the second display area is more sufficient, the size of at least part of the pixel circuits can be compressed, and the first pixel circuit corresponding to the first light-emitting element in the first display area and the second pixel circuit corresponding to the second light-emitting element in the second display area are both provided in the second display area, and one first pixel circuit drives one first light-emitting element, and one second pixel circuit drives one second light-emitting element. Since the distribution density of the first light-emitting elements and the second light-emitting elements is the same, the first display area and the second display area can have the same display PPI, thereby improving the display effect of the first display area.

[0061] Based on the above embodiments, Figure 6 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, such as Figure 6 As shown, optionally, the second display area S2 includes a first sub-display area 1 and a second sub-display area 2, the first sub-display area 1 is adjacent to the first display area S1, and the second sub-display area 2 is adjacent to the first sub-display area 1; at least one second light-emitting element P2 (such as Figure 6 The second pixel circuit C2 corresponding to the second light-emitting element P2-1 and the second light-emitting element P2-2 is located in the second sub-display area 2.

[0062] It should be noted that Figure 6 Taking the first light-emitting element P1 as a circle and the second light-emitting element P2 as a diamond as an example, part of the first light-emitting element P1 and part of the second light-emitting element P2 are schematically shown, and the electrical connection relationship between the first light-emitting element P1 and the first pixel circuit C1, the electrical connection relationship between the second light-emitting element P2 and the second pixel circuit C2, and the areas where the first pixel circuit C1 and the second pixel circuit C2 are located are displayed. Figure 6 The arrangement of the first light emitting element P1 and the second light emitting element P2 and the arrangement of the first pixel circuit C1 and the second pixel circuit C2 do not limit the actual arrangement.

[0063] Specifically, the first sub-display area 1 may be adjacent to at least a portion of the boundary of the first display area S1. Figure 6Taking the case where the entire boundary of the first sub-display area 1 is adjacent to the first display area S1 as an example, the first display area S1 is adjacent only to the first sub-display area 1 , and the second sub-display area 2 is adjacent only to the first sub-display area 1 . Figure 7 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, such as Figure 7 As shown, in other embodiments, the first sub-display area 1 may be adjacent to a portion of the boundary of the first display area S1 , and in this case, the second sub-display area 2 is also adjacent to the first display area S1 .

[0064] Reference Figure 3 If only the first pixel circuit C1 is set in the second display area S2, for example, the first pixel circuit C1 is set in the first sub-display area 1 below the first display area S1 and adjacent to it, so that the pixel circuits corresponding to the light-emitting elements in the same row (the first light-emitting element P1 and the second light-emitting element P2 in the same row, or the second light-emitting element P2 in the same row) are misaligned in the second direction y, and the distribution in the display panel is relatively scattered, then it is necessary to wind the scan line Gate so that a scan line is electrically connected to the pixel circuits corresponding to the light-emitting elements in the same row, so that during the display driving process, the scan signal is sent to the pixel circuits corresponding to the light-emitting elements in the same row through the scan line, so that the light-emitting elements in the same row are lit at the same time. Similarly, it can be understood that if the first pixel circuit C1 is set in the first sub-display area 1 adjacent to the first display area S1 along the first direction x, it is necessary to wind the data line so that during the display driving process, the data signal is sent to the pixel circuits corresponding to the light-emitting elements in the same column through the data line. Compared to only setting the first pixel circuit C1 in the second display area S2, this embodiment reduces the dispersion of pixel circuits corresponding to light-emitting elements in the same row or column in the display panel by placing the second pixel circuit C2 corresponding to at least one second light-emitting element P2 in the first sub-display area 1 adjacent to the first display area S1 outside the second sub-display area 2. This reduces or avoids the winding of signal lines (such as scan lines and data lines), thereby reducing the difficulty of signal line arrangement. In addition, in one embodiment, by placing the second pixel circuit C2 corresponding to at least one second light-emitting element P2 in the first sub-display area 1 inside the second sub-display area 2, the area in the first sub-display area 1 corresponding to the second light-emitting element P2 outside the second sub-display area 2 can be reused as the first display area portion S21 described above, so that this area can be used to implement functions such as face recognition, thereby enriching the functional diversity of the display device.

[0065] Figure 8 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, such as Figure 8As shown, optionally, the first sub-display area 1 includes a first partition 11 and a second partition 12, the first partition 11 and the first display area S1 are adjacent along a first direction x, the second partition 12 and the first display area S1 are adjacent along a second direction y, and the first direction x and the second direction y intersect; the first pixel circuit C1 is located in at least one of the first partition 11 and the second partition 12.

[0066] Optionally, the first direction x and the second direction y are orthogonal, and such an arrangement facilitates simplifying the difficulty of rearranging the first pixel circuit C1 and the second pixel circuit C2. Figure 8 The first direction x is used as the row direction and the second direction y is used as the column direction for illustration. In other embodiments, the first direction x may be the column direction and the second direction y may be the row direction, and this is not limited in the present embodiment. For example, the row direction may coincide with the direction in which the scan lines extend, and correspondingly, the column direction may coincide with the direction in which the data lines extend. The following description will only take the first direction x as the row direction and the second direction y as the column direction as an example.

[0067] Optionally, according to the position of the first display area S1 in the total display area FA of the display panel, the first sub-display area 1 may include at least one first partition 11 and at least one second partition 12. For example, Figure 8 In the embodiment, the first display area S1 is located within the total display area FA of the display panel. In this case, the first sub-display area 1 includes two first sub-areas 11 located on opposite sides of the first display area S1 along the first direction x, and two second sub-areas 12 located on opposite sides of the first display area S1 along the second direction y. This arrangement is for illustration only and is not limiting. For example, in other embodiments, the first sub-display area 1 may include two first sub-areas 11 adjacent to the first display area S1 along the first direction x, and one second sub-area 12 adjacent to the first display area S1 along the second direction y.

[0068] Specifically, all the first pixel circuits C1 can be set in the first partition 11; all the first pixel circuits C1 can also be set in the second partition 12; part of the first pixel circuits C1 can also be set in the first partition 11, and another part of the first pixel circuits C1 can be set in the second partition 12. This embodiment of the present invention is not limited to this.

[0069] For example, Figure 8 Take the example that all the first pixel circuits C1 are located in the first partition 11. Figure 9 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, such as Figure 9 As shown, in other embodiments, the first pixel circuits C1 may be arranged to be located in the second partition 12. Figure 6, multiple first pixel circuits C1 are respectively located in the first subarea 11 and the second subarea 12. In this embodiment of the present invention, by disposing the first pixel circuits C1 in at least one of the first subarea 11 and the second subarea 12 adjacent to the first display area S1, the difficulty of connecting the first pixel circuits C1 and the first light-emitting element P1, as well as the difficulty of wiring within the display panel, is reduced, thereby reducing the impact on product yield.

[0070] It should be noted that when the number of first partitions 11 is two, the first pixel circuit C1 can be set in at least one of the first partitions 11 as needed. Similarly, when the number of second partitions 12 is two, the first pixel circuit C1 can be set in at least one of the second partitions 12 as needed. The embodiment of the present invention is not limited to this.

[0071] It should also be noted that when the first pixel circuit C1 is located in at least one of the first partition 11 and the second partition 12, the second pixel circuit C2 corresponding to at least one second light-emitting element P2 in the first partition 11 and / or the second partition 12 (i.e., the first sub-display area 1) can be selected whether to be set in the second sub-display area 2 according to actual needs, and the embodiment of the present invention is not limited to this. Figure 8 The second pixel circuit C2 corresponding to the second light emitting element P2 in the first partition 11 is taken as an example to illustrate that it is still located in the first partition 11. Figure 9 Only the second pixel circuit C2 corresponding to the second light emitting element P2 in the second partition 12 is still located in the second partition 12 as an example for illustration. In other embodiments, reference may be made to FIG. Figure 6 , a second pixel circuit C2 corresponding to at least one second light-emitting element P2 in the first partition 11 and / or the second partition 12 is set in the second sub-display area 2.

[0072] Continue to see Figure 6 Optionally, the maximum width H4 of the first display area S1 along the first direction x is equal to the maximum width H2 of the second subarea 12 along the first direction x; and the maximum width H3 of the first display area S1 along the second direction y is equal to the maximum width H1 of the first subarea 11 along the second direction y. With this arrangement, the first pixel circuit C1 and / or the second pixel circuit C2 can be positioned within at least one of the first subarea 11 and the second subarea 12 by shifting and compressing the size of the first pixel circuit C1 and / or the second pixel circuit C2. This further reduces the difficulty of pixel circuit layout and display panel wiring, thereby minimizing the impact on product yield.

[0073] It should be noted that Figure 6 The first display area S1 being a rectangle is taken as an example for illustration only and is not intended to be limiting. Figure 10 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, such as Figure 10 As shown, in other embodiments, the first display area S1 may also be circular. Of course, the first display area S1 may also be any other shape known to those skilled in the art, and the embodiment of the present invention is not limited thereto.

[0074] like Figure 10 As shown, when the first display area S1 is circular, the first sub-display area 1 can also be set to include a first partition 11 and a second partition 12, the first partition 11 and the first display area S1 are adjacent to each other along the first direction x, the second partition 12 and the first display area S1 are adjacent to each other along the second direction y, the maximum width H4 of the first display area S1 along the first direction x is equal to the maximum width H2 of the second partition 12 along the first direction x, and the maximum width H3 of the first display area S1 along the second direction y is equal to the maximum width H1 of the first partition 11 along the second direction y.

[0075] It should be noted that Figure 10 The embodiment shown is Figure 6 The difference is that, since the first display area S1 is circular, when the maximum width H4 of the first display area S1 along the first direction x is equal to the maximum width H2 of the second partition 12 along the first direction x, and the maximum width H3 of the first display area S1 along the second direction y is equal to the maximum width H1 of the first partition 11 along the second direction y, the first partition 11 and the second partition 12 have an overlapping area. For example, Figure 10 The triangular area enclosed by the middle dashed line b, dashed line c, and the outer boundary d of the first display area S1 represents the overlapping region between the first subarea 11 to the right of the first display area S1 and the second subarea 12 below the first display area S1. To reduce the difficulty of pixel circuit layout, if the first display area S1 is circular, the second pixel circuit C2 corresponding to the second light-emitting element P2 within the overlapping region of the first subarea 11 and the second subarea 12 can be moved, along with the first pixel circuit C1, to the first subarea 11 and / or the second subarea 12 outside the overlapping region.

[0076] Figure 11 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Figure 12 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, such as Figure 11 and Figure 12As shown, when the first sub-display area 1 includes a first partition 11 and a second partition 12, the first pixel circuit C1 is located in at least one of the first partition 11 and the second partition 12, and the second pixel circuit C2 corresponding to at least one second light-emitting element P2 of the first sub-display area 1 is located in the second sub-display area 2, optionally, the first pixel circuit C1 is located in the first area 3; the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second area 4 is located in the second sub-display area 2; wherein the first area 3 is one of the first partition 11 and the second partition 12, and the second area 4 is the other of the first partition 11 and the second partition 12. Exemplarily, Figure 11 Take the first area 3 as the first partition 11 and the second area 4 as the second partition 12 as an example. Figure 11 As shown, in one embodiment, the optional first pixel circuit C1 is located in the first sub-area 11, and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second sub-area 12 is located in the second sub-display area 2. With this arrangement, the first pixel circuit C1 corresponding to the first light-emitting element P1 in the first display area S1, and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second sub-area 12 adjacent to the first display area S1 along the second direction y, are respectively located in the first sub-area 11 and the second sub-display area 2 adjacent to each other along the second direction y. This helps reduce the dispersion of pixel circuits corresponding to light-emitting elements in the same column along the second direction y in the first direction x, and can even ensure that pixel circuits corresponding to light-emitting elements in the same column are located in the same column, thereby reducing data line routing and reducing wiring difficulty. Furthermore, since no pixel circuits are provided in the first display area S1 and the second sub-area 12, data line routing can be avoided in the border area surrounding the first display area S1, thereby reducing the border width and improving the display effect.

[0077] It should be noted that Figure 11 Taking the circular first light-emitting element P1 and the diamond-shaped second light-emitting element P2 as an example, a filled rectangle represents the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second sub-area 12, and an unfilled rectangle represents the original second pixel circuit C2 in the first sub-area 11 and the second sub-display area 2. In addition, to facilitate illustrating the relocation of the first pixel circuit C1, the rectangle representing the first pixel circuit C1 is also filled. The same filling method is subsequently used to distinguish the second pixel circuits corresponding to the second light-emitting elements in different areas.

[0078] For example, Figure 12 Take the first area 3 as the second partition 12 and the second area 4 as the first partition 11 as an example. Figure 12As shown, in another embodiment, the first pixel circuit C1 may be optionally located in the second partition 12, and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first partition 11 may be located in the second sub-display area 2. With this arrangement, the first pixel circuit C1 corresponding to the first light-emitting element P1 in the first display area S1, and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first partition 11 adjacent to the first display area S1 along the first direction x, may be located in the second partition 12 and the second sub-display area 2 adjacent to each other along the first direction x, respectively. This helps reduce the dispersion of pixel circuits corresponding to light-emitting elements in the same row along the first direction x in the second direction y, and may even allow pixel circuits corresponding to light-emitting elements in the same row to be located in the same row, thereby reducing the routing of scan lines and lowering the wiring difficulty. Furthermore, since no pixel circuits are provided in the first display area S1 and the first partition 11, the routing of scan lines in the border area surrounding the first display area S1 can be avoided, thereby reducing the border width and improving the display effect.

[0079] It should be noted that Figure 12 Taking the circular first light-emitting element P1 and the diamond-shaped second light-emitting element P2 as an example, a filled rectangle represents the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first subarea 11, and an unfilled rectangle represents the original second pixel circuit C2 in the second subarea 12 and the second sub-display area 2. In addition, to facilitate illustrating the positional shift of the first pixel circuit C1, the rectangle representing the first pixel circuit C1 is also filled. The same filling method is subsequently used to distinguish the second pixel circuits corresponding to the second light-emitting elements in different areas.

[0080] It should also be noted that Figure 12 For illustration purposes only, an example is provided in which all first pixel circuits C1 are located in the second sub-area 12 below the first display area S1, and all second pixel circuits C2 corresponding to the second light-emitting elements P2 in the first sub-area 11 are located in the second sub-display area 2 below the first sub-area 11. This arrangement is not limiting. For example, in other embodiments, some first pixel circuits C1 may be located in the second sub-area 12 above the first display area S1, while another portion of the first pixel circuits C1 may be located in the second sub-area 12 below the first display area S1. The second pixel circuits C2 corresponding to the second light-emitting elements P2 in the first sub-area 11 may be located in the second sub-display area 2 above the first sub-area 11 and in the second sub-display area 2 below the first sub-area 11, respectively.

[0081] Since the first partition 11 and the second partition 12 are adjacent to the first display area S1 along the first direction x and the second direction y, respectively, in the embodiment of the present invention, by arranging the first pixel circuit C1 in the first area 3 (such as the first partition 11) and arranging the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second area 4 (such as the second partition 12) in the second sub-display area 2, the first pixel circuit corresponding to the first light-emitting element P1 in the first display area S1 and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second area 4 can be moved along the same direction to an area of ​​the second display area S2 other than the second area 4, which is conducive to reducing the layout difficulty of the pixel circuits, reducing the dispersion of the pixel circuits, and thus reducing the wiring difficulty of the display panel.

[0082] Below, taking the first area 3 as the second partition 12 and the second area 4 as the first partition 11 as an example, the layout of the first pixel circuit C1 and the second pixel circuit C2 in the second partition 12 and the second sub-display area 2 is exemplarily described.

[0083] Figure 13 is with Figure 12 The enlarged structural diagram of a display panel corresponding to the middle area Q4 is shown as follows: Figure 13 As shown, optionally, the first area 3 includes at least one first circuit group 51 and at least one second circuit group 52, the first circuit group 51 includes a first pixel circuit C1, the second circuit group 52 includes a second pixel circuit C2, and at least one first circuit group 51 is located on a side of the second circuit group 52 close to the first display area S1; the second sub-display area 2 includes at least one third circuit group 53 and at least one fourth circuit group 54, the third circuit group 53 includes a second pixel circuit C2 corresponding to the second light-emitting element P2 of the second area 4, the fourth circuit group 54 includes other second pixel circuits C2 in the second sub-display area 2, and at least one third circuit group 53 is located on a side of the fourth circuit group 54 close to the second area 4.

[0084] Specifically, the first circuit group 51 including the first pixel circuit C1 means that one first circuit group 51 may include one first pixel circuit C1, or one first circuit group 51 may include at least two adjacent first pixel circuits C1. Similarly, one second circuit group 52 may include one second pixel circuit C2 within the first region 3, or one second circuit group 52 may include at least two adjacent second pixel circuits C2 within the first region 3. The third circuit group 53 and the fourth circuit group 54 can be understood with reference to the configuration of the first circuit group 51, and will not be further described here.

[0085] It should be noted that the sizes of the multiple first pixel circuits C1 within the same first circuit group 51 can be the same or different; the number and sizes of the first pixel circuits C1 within different first circuit groups 51 can be the same or different, and this is not limited in the embodiment of the present invention. Similarly, for the second circuit group 52, the third circuit group 53, and the fourth circuit group 54, the sizes of the multiple second pixel circuits C2 within the same circuit group (second circuit group 52 / third circuit group 53 / fourth circuit group 54) can be the same or different, and the number and sizes of the second pixel circuits C2 within different circuit groups (second circuit group 52 / third circuit group 53 / fourth circuit group 54) can be the same or different, and this is also not limited in the embodiment of the present invention.

[0086] Optionally, the pixel circuits (the first pixel circuit C1 and / or the second pixel circuit C2) located in the same row have equal sizes along the column direction (such as the y direction), and the pixel circuits (the first pixel circuit C1 and / or the second pixel circuit C2) located in the same column have equal sizes along the row direction (such as the x direction). Such an arrangement facilitates the setting of signal lines such as scan lines and data lines, reduces winding, and reduces the difficulty of designing and manufacturing the display panel.

[0087] For example, Figure 13 For example, the first area 3 includes a plurality of first circuit groups 51 and a plurality of second circuit groups 52, and the second sub-display area 2 includes a plurality of third circuit groups 53 and a plurality of fourth circuit groups 54. Figure 13 , multiple adjacent first pixel circuits C1 located in the same row in the first area 3 can constitute a first circuit group 51; multiple adjacent second pixel circuits C2 located in the same row in the first area 3 can constitute a second circuit group 52 (such as 52-1); in addition, second pixel circuits C2 located in at least two adjacent rows in the first area 3 can also constitute a second circuit group 52 (such as 52-2); in the second sub-display area 2, corresponding to the second light-emitting element P2 in the second area 4, multiple adjacent second pixel circuits C2 located in the same row can constitute a third circuit group 53; among other second pixel circuits C2 in the second sub-display area 2, multiple adjacent second pixel circuits C2 located in the same row can constitute a fourth circuit group 54 (such as 54-1). In addition, second pixel circuits C2 located in at least two adjacent rows can also constitute a fourth circuit group 54 (such as 54-2). Due Figure 13Taking the example that the first pixel circuit C1 is located in the second partition 12 and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first partition 11 is located in the second sub-display area 2, at this time, by setting the first circuit group 51 to be composed of the first pixel circuits C1 in the same row or several adjacent rows, and the second circuit group 52 / the third circuit group 53 / the fourth circuit group 54 to be composed of the second pixel circuits C2 in the same row or several adjacent rows in the area where they are located, the first light-emitting element P1 and / or the second light-emitting element P2 in the same row can be set correspondingly to the first pixel circuit C1 and / or the second pixel circuit C2 in the same row, so that only one direction ( Figure 13 The second direction y) is used to adjust the position and size of the pixel circuit, reduce the layout difficulty of the pixel circuit, reduce the wiring difficulty of the display panel, and reduce the impact on product yield.

[0088] For example, Figure 14 is a schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention, such as Figure 14 As shown, the first pixel circuit C1 in the same row of the same first circuit group 51 is electrically connected to the first light-emitting element P1 in the same row, the second pixel circuit C2 in the same row of the same second circuit group 52 is electrically connected to the second light-emitting element P2 in the same row in the second partition 12, the second pixel circuit C2 in the same row of the same third circuit group 53 is electrically connected to the second light-emitting element P2 in the same row in the first partition 11, and the second pixel circuit C2 in the same row of the same fourth circuit group 54 is electrically connected to the second light-emitting element P2 in the same row in the second sub-display area 2. With such an arrangement, the pixel circuits (first pixel circuit C1 and / or second pixel circuit C2) corresponding to the light-emitting elements in the same row (first light-emitting element P1 and / or second light-emitting element P2) are located in the same row, thereby avoiding winding the scan line Gate, reducing the difficulty of pixel circuit layout, reducing the difficulty of wiring the display panel, and reducing the impact on product yield.

[0089] It should be noted that Figure 13 The alternating arrangement of the first circuit group 51 and the second circuit group 52 in the first area 3 and the alternating arrangement of the third circuit group 53 and the fourth circuit group 54 in the second sub-display area 2 are taken as an example for illustration only, and this arrangement is not limiting. Figure 15 is with Figure 12 The enlarged structural diagram of another display panel corresponding to the middle area Q4 is shown as follows: Figure 15As shown, in other embodiments, a first region 3 (such as the second subregion 12) adjacent to one side of the first display region S1 may optionally include a first circuit group 51 and a second circuit group 52, with the first circuit group 51 located on the side of the second circuit group 52 near the first display region S1. Similarly, a second sub-display region 2 adjacent to one side of the second region 4 (such as the first subregion 11) may optionally include a third circuit group 53 and a fourth circuit group 54, with the third circuit group 53 located on the side of the fourth circuit group 54 near the second region 4. With this arrangement, the first pixel circuit C1 and the first light-emitting element P1 can be positioned close together, and the second pixel circuit C2 in the third circuit group 53 and the second light-emitting element P2 in the second region 4 can be positioned close together, facilitating electrical connection between the first pixel circuit C1 and the first light-emitting element P1, and between the second pixel circuit C2 in the third circuit group 53 and the second light-emitting element P2 in the second region 4, thereby reducing wiring complexity.

[0090] Reference Figure 13 Optionally, the size of the first pixel circuit C1 is equal to the size of the second pixel circuit C2 in the third circuit group 53; the size of the first pixel circuit C1 is equal to the size of at least one second pixel circuit C2 in the second circuit group 52; the size of the second pixel circuit C2 in the third circuit group 53 is equal to the size of at least one second pixel circuit C2 in the fourth circuit group 54.

[0091] Among them, the size of the first pixel circuit C1 includes the first side length L1 of the area where the first pixel circuit C1 is located along the first direction x and the second side length L2 along the second direction y; the size of the second pixel circuit C2 includes the third side length L3 of the area where the second pixel circuit C2 is located along the first direction x and the fourth side length L4 along the second direction y; if the first side length L1 corresponding to the first pixel circuit C1 and the third side length L3 corresponding to the second pixel circuit C2 are equal, and the second side length L2 corresponding to the first pixel circuit C1 and the fourth side length L4 corresponding to the second pixel circuit C2 are equal, then the sizes of the first pixel circuit C1 and the second pixel circuit C2 are equal; otherwise, if the first side length L1 corresponding to the first pixel circuit C1 and the third side length L3 of the second pixel circuit C2 are not equal, and / or the second side length L2 corresponding to the first pixel circuit C1 and the fourth side length L4 corresponding to the second pixel circuit C2 are not equal, then the sizes of the first pixel circuit C1 and the second pixel circuit C2 are not equal. Similarly, if the first side length L1 and the second side length L2 of the area where the two first pixel circuits C1 are located are respectively equal, then the sizes of the two first pixel circuits C1 are equal; otherwise, the sizes of the two first pixel circuits C1 are unequal; if the third side length L3 and the fourth side length L4 of the area where the two second pixel circuits C2 are located are respectively equal, then the sizes of the two second pixel circuits C2 are equal; otherwise, the sizes of the two second pixel circuits C2 are unequal.

[0092] Specifically, the size of the first pixel circuit C1 being equal to the size of the second pixel circuit C2 in the third circuit group 53 means that the size of each second pixel circuit C2 in the third circuit group 53 is equal and equal to the size of the first pixel circuit C1. With this arrangement, since the first pixel circuit C1 and the second pixel circuit C2 in the third circuit group 53 are located in different regions from their corresponding first light-emitting elements P1 or second light-emitting elements P2, by setting the size of the first pixel circuit C1 equal to the size of the second pixel circuit C2 in the third circuit group 53, the positions and sizes of these first pixel circuits C1 and second pixel circuits C2 can be adjusted in the same manner, which helps reduce the difficulty of pixel circuit layout.

[0093] Specifically, the size of the first pixel circuit C1 being equal to the size of at least one second pixel circuit C2 in the second circuit group 52 means that, for all second pixel circuits C2 in the second circuit group 52, the size of the first pixel circuit C1 is equal to the size of at least one second pixel circuit C2. Similarly, the size of the second pixel circuit C2 in the third circuit group 53 being equal to the size of at least one second pixel circuit C2 in the fourth circuit group 54 means that, for all second pixel circuits C2 in the fourth circuit group 54, the size of the second pixel circuit C2 in the third circuit group 53 is equal to the size of at least one second pixel circuit C2.

[0094] For different display panels, the compressibility of the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first area 3 and the second sub-display area 2 is different. When the line width and line spacing requirements are met, it may be necessary to compress the size of part of the second pixel circuit C2 to achieve the goal of setting the first pixel circuit C1 corresponding to the first light-emitting element P1 in the first display area S1 in the first area 3 and setting the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second area 4 in the second sub-display area 2.

[0095] For example, Figure 13In the embodiment, the sizes of the second pixel circuits C2 in the second circuit group 52-1 are equal and equal to the sizes of the first pixel circuit C1 group; the sizes of the second pixel circuits C2 in the second circuit group 52-2 are equal, but not equal to the sizes of the first pixel circuit C1 (the fourth side length L4 of the second pixel circuit C2 in the second circuit group 52-2 is greater than the second side length L2 of the first pixel circuit C1); the sizes of the second pixel circuits C2 in the fourth circuit group 54-1 are equal and equal to the sizes of the second pixel circuit C2 in the third circuit group 53; the sizes of the second pixel circuits C2 in the fourth circuit group 54-2 are equal, but not equal to the sizes of the second pixel circuit C2 in the third circuit group 53 (the fourth side length L4 of the second pixel circuit C2 in the fourth circuit group 54-2 is greater than the fourth side length L4 of the second pixel circuit C2 in the third circuit group 53).

[0096] certainly, Figure 13 The embodiment shown is only one possible embodiment. In other embodiments, see Figure 15 Optionally, the second circuit group 52 includes a first circuit group 521 and a second circuit group 522, the sizes of the second pixel circuits C2 in the first circuit group 521 and the second circuit group 522 are not equal, and the first circuit group 521 is located on the side of the second circuit group 522 close to the first circuit group 51; the size of the second pixel circuit C2 in the first circuit group 521 is equal to the size of the first pixel circuit C1; the fourth circuit group 54 includes a third circuit group 541 and a fourth circuit group 542, the sizes of the second pixel circuits C2 in the third circuit group 541 and the fourth circuit group 542 are not equal, and the third circuit group 541 is located on the side of the fourth circuit group 542 close to the third circuit group 53; the size of the second pixel circuit C2 in the third circuit group 541 is equal to the size of the second pixel circuit C2 in the third circuit group 53.

[0097] Specifically, in this embodiment, the second circuit group 52 is located on the side of the first circuit group 51 away from the first display area S1, and the second circuit group 52 is divided into a first circuit group 521 and a second circuit group 522, wherein the sizes of the second pixel circuits C2 in the first circuit group 521 are equal, and the sizes of the second pixel circuits C2 in the second circuit group 522 are equal, the sizes of the second pixel circuits C2 in the first circuit group 521 and the second pixel circuits C2 in the second circuit group 522 are not equal (the fourth side length L4 is not equal), the first circuit group 521 is located on the side of the second circuit group 522 close to the first circuit group 51, and the size of the second pixel circuit C2 in the first circuit group 521 is equal to the size of the first pixel circuit C1. At this time, it is only necessary to compress the size of part of the original second pixel circuit C2 in the first area 3 to form the first circuit group 521, so that the compressed first pixel circuit C1 can be set in the first area 3. In addition, such a setting can make the first circuit group 51 closer to the first display area S1, facilitate the electrical connection between the first pixel circuit C1 and the corresponding first light-emitting element P1, reduce wiring difficulty, and reduce the impact on product yield.

[0098] In addition, in this embodiment, the third circuit group 53 is located on the side of the fourth circuit group 54 close to the second area 4, and the fourth circuit group 54 includes a third circuit group 541 and a fourth circuit group 542, wherein the sizes of the second pixel circuits C2 in the third circuit group 541 are equal, and the sizes of the second pixel circuits C2 in the fourth circuit group 542 are equal, the sizes of the second pixel circuits C2 in the third circuit group 541 and the second pixel circuits C2 in the fourth circuit group 542 are not equal (the fourth side length L4 is not equal), the third circuit group 541 is located on the side of the fourth circuit group 542 close to the third circuit group 53, and the size of the second pixel circuit C2 in the third circuit group 541 is equal to the size of the second pixel circuit C2 in the third circuit group 53. At this time, it is only necessary to compress the size of part of the original second pixel circuit C2 in the second sub-display area 2 to form the third circuit group 541, so that the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second area 4 can be compressed and set in the second sub-display area 2. In addition, such a setting can make the third circuit group 53 closer to the second area 4, making it easier to electrically connect the second pixel circuit C2 in the third circuit group 53 with the corresponding second light-emitting element P2 in the second area 4, reducing wiring difficulty and reducing the impact on product yield.

[0099] In other embodiments, under the premise of meeting the line width and line spacing requirements, the sizes of all first pixel circuits C1 and second pixel circuits C2 can be compressed so that the sizes of each first pixel circuit C1 and each second pixel circuit C2 are equal. In this way, the first pixel circuits C1 and the second pixel circuits C2 can have the same driving capabilities, which is conducive to display uniformity.

[0100] Figure 16 is with Figure 12 The enlarged structural diagram of another display panel corresponding to the middle area Q4 is shown as follows: Figure 16 As shown, optionally, the sizes of each first pixel circuit C1 and each second pixel circuit C2 are equal; the display panel 100 also includes a plurality of first virtual pixel circuits C01, the first virtual pixel circuit C01 is located in the first area 3 and the second sub-display area 2, and the orthographic projection of the first virtual pixel circuit C01 on the plane where the display panel is located does not overlap with the orthographic projection of the first pixel circuit C1 and the second pixel circuit C2 on the plane where the display panel is located.

[0101] Specifically, when the sizes of each first pixel circuit C1 and each second pixel circuit C2 are equal, if the sizes of the first pixel circuit C1 and the second pixel circuit C2 are compressed to a large extent, it is possible that after accommodating the first pixel circuit C1 and the second pixel circuit C2, there is still empty space in the first area 3 and the second sub-display area 2. The metal structure in the pixel circuit will reflect ambient light. In this embodiment of the present invention, by disposing a first virtual pixel circuit C01 in the first area 3 and the second sub-display area 2, the orthographic projection of the first virtual pixel circuit C01 on the plane where the display panel is located does not overlap with the orthographic projection of the first pixel circuit C1 and the second pixel circuit C2 on the plane where the display panel is located. The first virtual pixel circuit C01 can be used to balance the distribution of pixel circuits in the display panel, thereby balancing the reflectivity differences between different areas of the display panel and avoiding the appearance of a split screen phenomenon to the human eye due to the lack of pixel circuits in some areas.

[0102] Similarly, see Figure 15 or Figure 16 Optionally, a second virtual pixel circuit C02 is provided in the second area 4. It should be noted that the structure of the first virtual pixel circuit C01 / the second virtual pixel circuit C02 is the same as that of the first pixel circuit C1 / the second pixel circuit C2, the only difference being that the first virtual pixel circuit C01 and the second virtual pixel circuit C02 are unable to drive either the first light-emitting element P1 or the second light-emitting element P2 to emit light. Those skilled in the art may adopt any method to achieve the purpose of the virtual pixel circuit being unable to drive the light-emitting element to emit light, such as the virtual pixel circuit is not electrically connected to the scan line, the data line, or the PVDD line, or the virtual pixel circuit is not electrically connected to the light-emitting element, or the virtual pixel circuit is electrically connected to the light-emitting element, but the light-emitting element itself cannot be driven to emit light (such as at least one of the cathode, the anode, the pixel defining layer opening, and the light-emitting layer is missing), and the embodiment of the present invention is not limited to this. In addition, the size of the first virtual pixel circuit C01 / the second virtual pixel circuit C02 may be the same as or different from the size of the first pixel circuit C1 / the second pixel circuit C2, and the embodiment of the present invention is not limited to this.

[0103] The following is an exemplary description of the layout of the first virtual pixel circuit C01 in the first area 3 and the second sub-display area 2 .

[0104] See also Figure 16 Optionally, the first dummy pixel circuit C01 is located on a side of the second circuit group 52 away from the first circuit group 51, and is located on a side of the fourth circuit group 54 away from the third circuit group 53. This arrangement can reduce the impact on the layout of the first pixel circuit C1 and the second pixel circuit C2, and reduce the difficulty of pixel circuit layout.

[0105] certainly, Figure 16 The configuration of the first virtual pixel circuit C01 shown is only one feasible implementation method. In other embodiments, such as Figure 17 As shown, Figure 17 is with Figure 12 The enlarged structural diagram of another display panel corresponding to the middle area Q4, optionally, at least one first virtual pixel circuit C01 is located between two adjacent first pixel circuits C1 and / or second pixel circuits C2.

[0106] Specifically, the first virtual pixel circuit C01 can be inserted into the layout of the first pixel circuit C1 and the second pixel circuit C2. For example, a first virtual pixel circuit C01 can be located between two adjacent first pixel circuits C1, between two adjacent second pixel circuits C2, or between two adjacent first pixel circuits C1 and second pixel circuits C2, which is not limited in this embodiment of the present invention.

[0107] Reference Figure 17 Optionally, any two first virtual pixel circuits C01 adjacent along the first direction x include m actual pixel circuits; wherein m is a natural number; when m>0, the m actual pixel circuits include at least one of the first pixel circuit C1 and the second pixel circuit C2; any two first virtual pixel circuits C01 adjacent along the second direction y include n actual pixel circuits; wherein n is a natural number; when n>0, the n actual pixel circuits include at least one of the first pixel circuit C1 and the second pixel circuit C2; m and n are not 0 at the same time.

[0108] The actual pixel circuit refers to a pixel circuit such as the first pixel circuit C1 and the second pixel circuit C2 that is electrically connected to the first light-emitting element P1 or the second light-emitting element P2. When an actual pixel circuit exists between two adjacent first virtual pixel circuits C01 along the first direction x or the second direction y, the actual pixel circuit may be at least one of the first pixel circuit C1 and the second pixel circuit C2.

[0109] For example, Figure 17 Taking m=0 and n=3 as an example, at this time, there is no actual pixel circuit between any two first virtual pixel circuits C01 adjacent along the first direction x, and there are 3 actual pixel circuits between any two first virtual pixel circuits C01 adjacent along the second direction y. Multiple first virtual pixel circuits are arranged in the same row and interspersed between several rows of actual pixel circuits.

[0110] Figure 18 is with Figure 12 The enlarged structural diagram of another display panel corresponding to the middle area Q4 is shown as follows: Figure 18 As shown, in other embodiments, m≠0 ( Figure 18 Taking m=3 as an example, n=0, at this time, there are 3 actual pixel circuits between any two first virtual pixel circuits C01 adjacent along the first direction x, and there is no actual pixel circuit between any two first virtual pixel circuits C01 adjacent along the second direction y. Multiple first virtual pixel circuits C01 are arranged in the same column and interspersed between several columns of actual pixel circuits.

[0111] Of course, in other embodiments, both m and n may not be equal to 0. For example, Figure 19 is with Figure 12 The enlarged structural diagram of another display panel corresponding to the middle area Q4 is shown. Figure 19 Taking m=3 and n=2 as an example, three actual pixel circuits are located between any two adjacent first virtual pixel circuits C01 along the first direction x, and two actual pixel circuits are located between any two adjacent first virtual pixel circuits C01 along the second direction y. Each first virtual pixel circuit is independently interspersed between two adjacent actual pixel circuits. It is understood that when m=n, the first virtual pixel circuits C01 are evenly interspersed between two adjacent actual pixel circuits.

[0112] Figure 20 is with Figure 12 The enlarged structural diagram of another display panel corresponding to the middle area Q4 is shown as follows: Figure 20 As shown, optionally, the sizes of the first pixel circuits C1 and the second pixel circuits C2 are equal and are distributed in the second display area S2 except for the second area 4. Specifically, in this embodiment, the first dummy pixel circuits C01 are not provided in the first area 3 and the second sub-display area 2. In this way, the compression degree of the first pixel circuits C1 and the second pixel circuits C2 can be relatively small. That is, compared with the solution in which the first dummy pixel circuits C01 are provided in the first area 3 and the second sub-display area 2, the sizes of the first pixel circuits C1 and the second pixel circuits C2 can be relatively large, ensuring a certain design margin for line width and line spacing, thereby reducing the risk of short circuits and ensuring product yield.

[0113] It should be noted that Figure 20 For illustration, a first region 3 includes a first circuit group 51 and a second circuit group 52, with the first circuit group 51 located on the side of the second circuit group 52 near the first display region S1; a second sub-display region 2 includes a third circuit group 53 and a fourth circuit group 54, with the third circuit group 53 located on the side of the fourth circuit group 54 near the second region 4; and the sizes of the first pixel circuits C1 in the first circuit group 51 and the sizes of the second pixel circuits C2 in the second, third, and fourth circuit groups 52, 53, and 54 are all equal. This arrangement is not limiting; in other embodiments, a first region 3 may include multiple alternating first circuit groups 51 and second circuit groups 52, and a second sub-display region 2 may include multiple alternating third circuit groups 53 and fourth circuit groups 54. The present embodiment does not limit the arrangement of the first pixel circuits C1 and the second pixel circuits C2, as long as the sizes of the first pixel circuits C1 and the second pixel circuits C2 are equal.

[0114] It should also be noted that, for ease of presentation, Figure 13-Figure 20 Only the first area 3 is the second partition 12, the second area 4 is the first partition 11, and the first sub-display area 1 includes a first partition 11 and a second partition 12 as an example for illustration. Figure 12 The layout of the first pixel circuit C1 and the second pixel circuit C2 in the other second partitions 12 and the second sub-display area 2 can refer to Figure 13-Figure 20 Any of the settings in the above table can be used for symmetrical layout, which will not be described in detail here.

[0115] Reference Figure 12 It should also be noted that when the first display area S1 is the camera area, the first pixel circuit C1 is located in the second sub-area 12, and the second pixel circuit C2 corresponding to the second light-emitting element P2 of the first sub-area 11 is located in the second sub-display area 2, due to Figure 12 The areas of the second partition 12 above the first display area S1 and the two second sub-display areas 2 above the first partition 11 are usually small. Therefore, the second partition 12 can be used to set part of the first pixel circuit C1 according to actual conditions. Similarly, the two second sub-display areas 2 above the first partition 11 can be used to set part of the second pixel circuit C2 corresponding to the second light-emitting element P2 of the first partition 11 according to actual conditions. The embodiment of the present invention is not limited to this.

[0116] In summary, the above embodiment describes in detail the arrangement of the first pixel circuit C1 and the second pixel circuit C2, taking the example of the first region 3 being the second sub-region 12, the second region 4 being the first sub-region 11, the first pixel circuit C1 being located in the second sub-region 12, and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the first sub-region 11 being located in the second sub-display region 2. Any of the above embodiments can be applied to the embodiment in which the first region 3 is the first sub-region 11 and the second region 4 is the second sub-region 12. Below, a brief example of the arrangement of the first pixel circuit C1 and the second pixel circuit C2 is provided, taking the example of the first region 3 being the first sub-region 11 and the second region 4 being the second sub-region 12.

[0117] For example, Figure 21 is with Figure 12 The enlarged structural diagram of another display panel corresponding to the middle area Q4 is shown as follows: Figure 21 As shown, the first area 3 is the first partition 11, the second area 4 is the second partition 12, the first pixel circuit C1 is located in the first partition 11, and the second pixel circuit C2 corresponding to the second light-emitting element P2 in the second partition 12 is located in the second sub-display area 2. Figure 21 The rectangles representing the first pixel circuit C1 and the area where the second pixel circuit C2 corresponding to the second light emitting element P2 in the second partition 12 is located are filled for distinction. Figure 21 In the illustrated embodiment, one of the first sub-areas 11 of the display panel includes a first circuit group 51 and a second circuit group 52, with the first circuit group 51 located on the side of the second circuit group 52 near the first display area S1. One of the second sub-display areas 2 of the display panel includes a third circuit group 53 and a fourth circuit group 54, with the third circuit group 53 located on the side of the fourth circuit group 54 near the second sub-area 12. Each first pixel circuit C1 and each second pixel circuit C2 are of equal size, and a second dummy pixel circuit C02 is provided in the first sub-area 11. Other possible configurations of the first pixel circuits C1 and the second pixel circuits C2 can be referred to in the related embodiment where the first area 3 is the second sub-area 12 and the second area 4 is the first sub-area 11, and will not be further described here.

[0118] Based on the above embodiments, Figure 22 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, such as Figure 22 As shown, optionally, along the direction from the first display area S1 to the second area 4, the first light-emitting elements P1 located in the same row are electrically connected one-to-one with the first pixel circuits C1 located in the same row, and the second light-emitting elements P2 located in the same row are electrically connected one-to-one with the second pixel circuits C2 located in the same row.

[0119] As described above, the second area 4 may be one of the first partition 11 and the second partition 12. Figure 6 , taking the first direction x as the row direction and the second direction y as the column direction as an example, if the second area 4 is the first partition 11, then the direction along the first display area S1 pointing to the second area 4 is the row direction, the first light-emitting elements P1 located in the same row are the first light-emitting elements P1 located in the same row, the first pixel circuits C1 located in the same row are the first pixel circuits C1 located in the same row, the second light-emitting elements P2 located in the same row are the second light-emitting elements P2 located in the same row, and the second pixel circuits C2 located in the same row are the second pixel circuits C2 located in the same row.

[0120] Similarly, continue to refer to Figure 6 If the second area 4 is the second partition 12, then along the direction from the first display area S1 to the second area 4, that is, the column direction, the first light-emitting elements P1 located in the same row are the first light-emitting elements P1 located in the same column, the first pixel circuits C1 located in the same row are the first pixel circuits C1 located in the same column, the second light-emitting elements P2 located in the same row are the second light-emitting elements P2 located in the same column, and the second pixel circuits C2 located in the same row are the second pixel circuits C2 located in the same column.

[0121] For example, Figure 22 Take the second area 4 as the first partition 11 as an example. Figure 22 As shown, the first light-emitting elements P1 in the same row are electrically connected in a one-to-one correspondence with the first pixel circuits C1 in the same row, and the second light-emitting elements P2 in the same row are electrically connected in a one-to-one correspondence with the second pixel circuits C2 in the same row. In other embodiments, the second region 4 may be optionally a second subarea 12. In this case, the first light-emitting elements P1 in the same column are electrically connected in a one-to-one correspondence with the first pixel circuits C1 in the same column, and the second light-emitting elements P2 in the same column are electrically connected in a one-to-one correspondence with the second pixel circuits C2 in the same column.

[0122] Along the direction from the first display area S1 to the second area 4, the embodiment of the present invention arranges the first light-emitting elements P1 located in the same row to be electrically connected in sequence with the first pixel circuits C1 located in the same row, and arranges the second light-emitting elements P2 located in the same row to be electrically connected in sequence with the second pixel circuits C2 located in the same row. This allows the first pixel circuits C1 and the second pixel circuits C2 corresponding to the first light-emitting elements P1 and the second light-emitting elements P2 located in the same row in the first display area S1 and the second area 4 to be located in the same row, thereby reducing the degree of dispersion of the pixel circuits. This is beneficial to the wiring of signal lines such as scan lines or data lines, reducing winding, and reducing the impact on product yield.

[0123] It should be noted that the two rows of first pixel circuits C1 corresponding to two adjacent rows (rows / columns) of first light-emitting elements P1 can be arranged adjacent to each other or not. Similarly, the two rows of second pixel circuits C2 corresponding to two adjacent rows of second light-emitting elements P2 can be arranged adjacent to each other or not. The embodiment of the present invention does not limit this.

[0124] Continue to see Figure 22 , further optionally, the first light-emitting element P1 and the corresponding first pixel circuit C1 are electrically connected via a first connection line 81; at least part of the second light-emitting element P2 and the corresponding second pixel circuit C2 are electrically connected via a second connection line 82; along the direction from the first area 3 to the first display area S1, the closer the first pixel circuit C1 is to the first display area S1, the longer the length of the first connection line 81 corresponding to the first pixel circuit C1 is, and the closer the second pixel circuit C2 is to the first display area S1 or the second area 4, the longer the length of the second connection line 82 corresponding to the second pixel circuit C2 is. Figure 22 As shown, the connection line electrically connected to the first pixel circuit C1 is the first connection line 81. The closer the first pixel circuit C1 is to the first display area S1, the longer the length of the first connection line 81 is (for example, Z1>Z2). The connection line electrically connected to the second pixel circuit C2 is the second connection line 82. The closer the second pixel circuit C2 is to the first display area S1 or the second region 4, the longer the length of the second connection line 82 is (for example, Z4>Z5). For ease of observation, Figure 22 Only a portion of the first connection line 81 between the first light emitting element P1 and the first pixel circuit C1 and a portion of the second connection line 82 between the second light emitting element P2 and the second pixel circuit C2 are illustrated.

[0125] Specifically, when the first area 3 is the second partition 12, the direction from the first area 3 to the first display area S1 is parallel to the second direction y (the same as or opposite to the y direction in the figure); when the first area 3 is the first partition 11, the direction from the first area 3 to the first display area S1 is parallel to the first direction x (the same as or opposite to the x direction in the figure). Figure 12 Taking the first area 3 as the second partition 12 as an example, the direction of the second partition 12 below the first display area S1 pointing to the first display area S1 is the same as the y direction, and the direction of the second partition 12 above the first display area S1 pointing to the first display area S1 is opposite to the y direction.

[0126] Regardless of which first region 3 the first pixel circuit C1 is located in, by setting the first connecting line 81 corresponding to the first pixel circuit C1 closer to the first display area S1 to be longer, the relative positional relationship of multiple first pixel circuits C1 located in the same first region 3 and arranged along the direction pointing from the first region 3 to the first display area S1 can be made the same as the relative positional relationship of the multiple first light-emitting elements P1 corresponding thereto (the multiple first light-emitting elements P1 are also arranged along the direction pointing from the first region 3 where the first pixel circuit C1 is located to the first display area S1). This is beneficial for improving the wiring regularity of the first connecting line 81, reducing wiring complexity, and reducing the impact on product yield. Similarly, by setting the length of the second connecting line 82 corresponding to the second pixel circuit C2 closer to the first display area S1 or the second area 4 to be longer, the relative position relationship of the multiple second pixel circuits C2 located in the same first area 3 and arranged along the direction of the first area 3 pointing to the first display area S1 can be made the same as the relative position relationship of the multiple second light-emitting elements P2 corresponding to them. In addition, the relative position relationship of the multiple second pixel circuits C2 located in the same second sub-display area 2 and arranged along the direction of the second sub-display area 2 pointing to the second area 4 can be made the same as the relative position relationship of the multiple second light-emitting elements P2 corresponding to them, which is beneficial to improving the wiring regularity of the second connecting line 82, reducing the wiring complexity, and reducing the impact on product yield.

[0127] It should be noted that Figure 22 Taking as an example a plurality of first pixel circuits C1 arranged in a direction from the first area 3 to the first display area S1, which are adjacently arranged and close to the first display area S1, and a plurality of second pixel circuits C2 arranged in a direction from the second sub-display area 2 to the second area 4, which are corresponding to the second light-emitting element P2 in the second area 4, and which are adjacently arranged and close to the second area 4, as an example, in other embodiments, among the plurality of first pixel circuits C1 arranged in a direction from the first area 3 to the first display area S1, a plurality of second pixel circuits C2 may be included between two adjacent first pixel circuits C1, and a plurality of second pixel circuits C2 in the fourth circuit group 54 may be included between the second pixel circuits C2 corresponding to the second light-emitting element P2 in the second area 4 (refer to Figure 13 ), which is not limited in this embodiment of the present invention.

[0128] like Figure 22As shown, in one embodiment, optionally, the display panel 100 further includes a non-display area FNA, the non-display area FNA includes a binding area S3, the first sub-display area 1 includes at least one first area 3, one of the first areas 3 is located between the first display area S1 and the binding area S3, the first pixel circuits C1 are all located in the first area 3, and the second pixel circuits C2 corresponding to the second light-emitting elements P2 in the second area 4 are all located in the second sub-display area 2 adjacent to the first area 3, along the direction from the first display area S1 to the second area 4, the first light-emitting elements P1 located in the same row are electrically connected one-to-one with the first pixel circuits C1 located in the same row, and the second light-emitting elements P2 located in the same row are electrically connected one-to-one with the second pixel circuits C2 located in the same row, and along the direction from the first display area S1 to the binding area S3, the light-emitting devices in the i-th row are electrically connected to the actual pixel circuits in the i-th row, where i is a positive integer; wherein, a row of light-emitting devices includes at least one of the first light-emitting element P1 and the second light-emitting element P2, and a row of actual pixel circuits includes at least one of the first pixel circuit C1 and the second pixel circuit C2.

[0129] Typically, the binding area S3 is located at the lower border of the display panel, that is, at the bottom of the display panel along the column direction. Therefore, when the second direction y is the column direction, the first area 3 is the second partition 12, and the second area 4 is the first partition 11. The number of first areas 3 is the same as the number of second partitions 12, and the number of second areas 4 is the same as the number of first partitions 11. The specific details can be determined according to the position of the first display area S1 as described above.

[0130] Taking the first display area S1 as a camera area as an example, the first display area S1 is usually adjacent to or close to the upper boundary of the total display area. Figure 22 Taking the first display area S1 adjacent to the upper boundary of the total display area as an example, a first area 3 is included between the first display area S1 and the binding area S3, and the area of ​​the first area 3 is relatively large. Figure 22It can be seen that in this embodiment, by arranging the first pixel circuit C1 in the first area 3 between the first display area S1 and the binding area S3, arranging the second pixel circuit C2 corresponding to the second light-emitting element P2 of the second area 4 in the second sub-display area 2 adjacent to the first area 3, the first light-emitting elements P1 located in the same row along the direction from the first display area S1 to the second area 4 are electrically connected one-to-one with the first pixel circuit C1 located in the same row, and the second light-emitting elements P2 located in the same row along the direction from the first display area S1 to the second area 4 are electrically connected one-to-one with the second pixel circuit C2 located in the same row, and the light-emitting devices in the i-th row are electrically connected to the i-th row of actual pixel circuits along the direction from the first display area S1 to the binding area S3, so that the length of the connection line corresponding to the i-th row of actual pixel circuits can be greater than the length of the connection line corresponding to the i+1-th row of actual pixel circuits, that is, the closer the connection line corresponding to the actual pixel circuit to the first display area S1 (the first connection line 81 or the second connection line 82) is, the longer the length. Figure 22 As shown in the figure, the lengths of the connecting lines corresponding to the first three green light-emitting elements G in the second column are Z1, Z2, and Z3 respectively. The above setting method can make Z1>Z2>Z3.

[0131] In this way, since the driver chip is electrically connected to the binding area S3 and transmits data signals to each actual pixel circuit through the data line, the farther the actual pixel circuit is from the binding area S3, the greater the data line load, that is, there is a load gradient when the data signal is transmitted to the actual pixel circuit through the data line. The existing technology can improve display uniformity by adopting a certain software algorithm, and this embodiment adopts the above-mentioned setting method to make the length of the connecting line corresponding to the actual pixel circuit farther away from the binding area S3 longer, thereby maintaining the load gradient without breaking the existing driver software algorithm, which is conducive to ensuring display uniformity.

[0132] Figure 23 is a schematic cross-sectional view of a display panel provided by an embodiment of the present invention, such as Figure 23 As shown, the display panel 100 includes a substrate 901, a pixel circuit layer 6 and a light emitting element layer 7. The pixel circuit layer 6 includes a plurality of first pixel circuits and a plurality of second pixel circuits. Figure 23 Only one thin film transistor T1 in the first pixel circuit and one thin film transistor T2 in the second pixel circuit are shown. The light emitting element layer 7 includes a plurality of first light emitting elements P1 and a plurality of second light emitting elements P2. The first light emitting elements P1 are located in the first display area S1, and the second light emitting elements P2 are located in the second display area S2. The pixel circuits in the pixel circuit layer 6 are electrically connected to the corresponding light emitting elements. Figure 23As shown, the first light emitting element P1 is electrically connected to the first pixel circuit C1 through a first connection line 81 , and the second light emitting element P2 is electrically connected to the second pixel circuit C2 through a second connection line 82 .

[0133] Continue to see Figure 23 The substrate 901 and the light emitting element layer 7 include a buffer layer 902, an active layer 911, a gate insulating layer 903, a first metal layer 912, a first interlayer dielectric layer 904, a capacitor plate layer 913, a second interlayer dielectric layer 905, a third interlayer dielectric layer 906, a second metal layer 914, a fourth interlayer dielectric layer 907, Figure 23 The first planarization layer 908, the third metal layer 915, the second planarization layer 909, the conductive film layer where the first connecting line 81 and the second connecting line 82 are located, the third planarization layer 910 and the pixel defining layer 911; the first light-emitting element P1 and the second light-emitting element P2 each include an anode 916, a light-emitting layer 917 and a cathode 918. Among them, the first metal layer 912 is at least used to form the gate of the thin film transistor, the capacitor plate layer 913 is at least used to form the capacitor plate of the storage capacitor, the second metal layer 914 is at least used to form the source and drain of the thin film transistor, and the third metal layer 915 is used to form a metal structure connecting the source (drain) of the thin film transistor and the connecting line (the first connecting line 81 or the second connecting line 82). The pixel defining layer 911 has a pixel opening, which exposes the anode 916 of the light-emitting element, and the material of the light-emitting layer 917 is deposited in the pixel opening. Optionally, the first connecting line 81 and the second connecting line 82 are located between the second planarization layer 909 and the third planarization layer 910.

[0134] It should be noted that Figure 23 The first connecting line 81 and the second connecting line 82 are located in the same layer as an example. In other embodiments, at least one first connecting line 81 and / or at least one second connecting line 82 can be located in a different film layer from other first connecting lines 81 and second connecting lines 82. This is not limited in the embodiments of the present invention.

[0135] Reference Figure 23 Optionally, the first connection line 81 includes a first connection sub-portion 811, and the first connection sub-portion 811 is located in the first display area S1; at least one first connection sub-portion 811 is a transparent wiring.

[0136] Among them, the transmittance of transparent wiring to light is much greater than the reflectivity of transparent wiring to light. The reflectivity of transparent wiring to light can even be zero, which can be determined according to the material of the selected transparent wiring.

[0137] The first connection segment 811 being located in the first display area S1 can be understood as meaning that the orthographic projection of the first connection segment 811 on the plane of the display panel is located in the first display area S1. Because the first display area S1 requires light carrying object information to pass through the display panel and be emitted to the photosensitive element on the back side (non-display side) of the display panel for reception and recognition, the first display area S1 has high requirements for light transmittance. In this embodiment of the present invention, by configuring at least one first connection segment 811 as a transparent trace, this helps reduce the impact on the light transmittance of the first display area S1.

[0138] It should be noted that all or some of the first connection segments 811 of the first connection lines 81 may be transparent, and this is not limited in the present embodiment. For example, if the first connection segment 811 of a first connection line 81 is located at the edge of the first display area S1, since the light transmittance at the edge of the first display area S1 has a relatively small impact on imaging quality, the first connection segment 811 may also be a metal segment.

[0139] It should also be noted that the first connecting line 81 can be configured as a transparent line in its entirety, or only the first connecting section 811 located in the first display area S1 can be configured as a transparent line, with the remaining portion configured as a metal line. This is not limited in the present embodiment. Furthermore, the second connecting line 82 can be configured as a transparent line or a metal line, and this is also not limited in the present embodiment.

[0140] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 24 is a structural diagram of a display device provided by an embodiment of the present invention, such as Figure 24 As shown, the display device 200 includes a photosensitive element 210 and a display panel 100 provided in any of the above embodiments. The photosensitive element 210 is provided corresponding to the first display area S1. Since the display device includes the display panel provided in any of the above embodiments, it has the same beneficial effects as the above display panel. The similarities can be referred to the description of the above display panel embodiments, which will not be repeated here. The display device 200 provided in the embodiment of the present invention can be Figure 24 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0141] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: comprising a first display area and a second display area, wherein the light transmittance of the first display area is greater than the light transmittance of the second display area; The first display area includes a plurality of first light-emitting elements, and the second display area includes a plurality of second light-emitting elements, and the distribution density of the first light-emitting elements and the second light-emitting elements is the same; The second display area includes a plurality of first pixel circuits and a plurality of second pixel circuits; the first pixel circuits are electrically connected to the first light-emitting elements in a one-to-one correspondence; the second pixel circuits are electrically connected to the second light-emitting elements in a one-to-one correspondence; The second display area includes a first sub-display area and a second sub-display area, the first sub-display area is adjacent to the first display area, and the second sub-display area is adjacent to the first sub-display area; The second pixel circuit corresponding to at least one second light-emitting element in the first sub-display area is located in the second sub-display area; and the transmittance of the first sub-display area is greater than the transmittance of the second sub-display area.

2. The display panel according to claim 1, wherein: The first sub-display area includes a first sub-area and a second sub-area, the first sub-area and the first display area are adjacent to each other along a first direction, the second sub-area and the first display area are adjacent to each other along a second direction, and the first direction and the second direction intersect; The first pixel circuit is located in at least one of the first partition and the second partition.

3. The display panel according to claim 2, wherein: The maximum width of the first display area along the first direction is equal to the maximum width of the second subarea along the first direction; The maximum width of the first display area along the second direction is equal to the maximum width of the first partition along the second direction.

4. The display panel according to claim 2, wherein: The first pixel circuit is located in the first area; The second pixel circuit corresponding to the second light-emitting element in the second area is located in the second sub-display area; The first area is one of the first partition and the second partition, and the second area is the other of the first partition and the second partition.

5. The display panel according to claim 4, wherein: The first area includes at least one first circuit group and at least one second circuit group, the first circuit group includes the first pixel circuit, the second circuit group includes the second pixel circuit, and at least one first circuit group is located on a side of the second circuit group close to the first display area; The second sub-display area includes at least one third circuit group and at least one fourth circuit group, the third circuit group includes the second pixel circuit corresponding to the second light-emitting element in the second area, and the fourth circuit group includes other second pixel circuits in the second sub-display area. At least one of the third circuit groups is located on a side of the fourth circuit group close to the second area.

6. The display panel according to claim 5, wherein: The size of the first pixel circuit is equal to the size of the second pixel circuit in the third circuit group; The size of the first pixel circuit is equal to the size of at least one of the second pixel circuits in the second circuit group; The size of the second pixel circuit in the third circuit group is equal to the size of at least one second pixel circuit in the fourth circuit group; Among them, the size of the first pixel circuit includes the first side length of the area where the first pixel circuit is located along the first direction and the second side length along the second direction; the size of the second pixel circuit includes the third side length of the area where the second pixel circuit is located along the first direction and the fourth side length along the second direction; if the first side length corresponding to the first pixel circuit and the third side length corresponding to the second pixel circuit are equal, and the second side length corresponding to the first pixel circuit and the fourth side length corresponding to the second pixel circuit are equal, then the sizes of the first pixel circuit and the second pixel circuit are equal.

7. The display panel according to claim 6, wherein: The second circuit group includes a first circuit group and a second circuit group, the sizes of the second pixel circuits in the first circuit group and the second circuit group are different, and the first circuit group is located on a side of the second circuit group close to the first circuit group; the size of the second pixel circuit in the first circuit group is equal to the size of the first pixel circuit; The fourth circuit group includes a third circuit grouping and a fourth circuit grouping, the sizes of the second pixel circuits in the third circuit grouping and the fourth circuit grouping are different, and the third circuit grouping is located on the side of the fourth circuit grouping close to the third circuit group; the size of the second pixel circuit in the third circuit grouping is equal to the size of the second pixel circuit in the third circuit group.

8. The display panel according to claim 6, wherein: The sizes of the first pixel circuits and the second pixel circuits are equal; The display panel also includes multiple first virtual pixel circuits, which are located in the first area and the second sub-display area, and the orthographic projection of the first virtual pixel circuit on the plane where the display panel is located does not overlap with the orthographic projection of the first pixel circuit and the second pixel circuit on the plane where the display panel is located.

9. The display panel according to claim 8, wherein: The first dummy pixel circuit is located on a side of the second circuit group away from the first circuit group, and is located on a side of the fourth circuit group away from the third circuit group.

10. The display panel according to claim 8, wherein At least one of the first virtual pixel circuits is located between two adjacent first pixel circuits and / or second pixel circuits.

11. The display panel according to claim 10, wherein: There are m actual pixel circuits between any two adjacent first virtual pixel circuits along the first direction; wherein m is a natural number; when m>0, the m actual pixel circuits include at least one of the first pixel circuit and the second pixel circuit; n actual pixel circuits are included between any two adjacent first virtual pixel circuits along the second direction; wherein n is a natural number; when n>0, the n actual pixel circuits include at least one of the first pixel circuit and the second pixel circuit; m and n are not 0 at the same time.

12. The display panel according to claim 6, wherein: The first pixel circuits and the second pixel circuits have the same size and are distributed in areas other than the second area of ​​the second display area.

13. The display panel according to claim 4, wherein: A second virtual pixel circuit is disposed in the second area.

14. The display panel according to claim 4, wherein: Along the direction from the first display area to the second area, the first light-emitting elements in the same row are electrically connected to the first pixel circuits in the same row in a one-to-one correspondence, and the second light-emitting elements in the same row are electrically connected to the second pixel circuits in the same row in a one-to-one correspondence.

15. The display panel according to claim 14, wherein: The first light-emitting element and the corresponding first pixel circuit are electrically connected via a first connecting line; at least part of the second light-emitting element and the corresponding second pixel circuit are electrically connected via a second connecting line; Along the direction from the first area to the first display area, the closer the first pixel circuit is to the first display area, the longer the length of the first connection line corresponding to the first pixel circuit is, and the closer the second pixel circuit is to the first display area or the second area, the longer the length of the second connection line corresponding to the second pixel circuit is.

16. The display panel according to claim 15, wherein: The first connecting line includes a first connecting sub-portion, and the first connecting sub-portion is located in the first display area; At least one of the first connection sections is a transparent wiring.

17. The display panel according to claim 1, wherein: The first light-emitting element includes a first anode, and the orthographic projection of the first anode on the plane where the display panel is located is a circle.

18. A display device, characterized in that: It comprises a photosensitive element and the display panel according to any one of claims 1 to 17, wherein the photosensitive element is arranged corresponding to the first display area.

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