Light-emitting substrate, method of manufacturing the same, backlight, display device

Abstract

The present disclosure provides a light-emitting substrate and a manufacturing method thereof, a backlight, and a display device. The light-emitting substrate includes a substrate including a plurality of light-emitting regions arranged in an array, each of the plurality of light-emitting regions including a driving circuit and at least one light-emitting unit connected to the driving circuit; a first conductive portion on the substrate and connected to the driving circuit and the at least one light-emitting unit within each light-emitting region; and a second conductive portion on the substrate and including a plurality of pads. The first conductive portion and the second conductive portion are on the same layer.

Description

Technical Field

[0001] This disclosure relates to the field of optical technology, and in particular to a light-emitting substrate and a method for manufacturing the same, a backlight source including the light-emitting substrate, and a display device including the light-emitting substrate. Background Technology

[0002] With the continuous development of display technology, users are placing increasingly higher demands on the contrast ratio, brightness uniformity, and stability of display devices. Display devices are generally divided into two main categories: liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays. LCDs are widely used due to their advantages such as thinness, shock resistance, wide viewing angle, and high contrast. An LCD typically includes a display panel and a backlight. The backlight is usually located on the non-display side of the display panel to provide light for its operation. The contrast ratio, brightness uniformity, and stability of an LCD are related to the structure and performance of the backlight. Summary of the Invention

[0003] According to one aspect of this disclosure, a light-emitting substrate is provided, comprising: a substrate including a plurality of light-emitting regions arranged in an array, each of the plurality of light-emitting regions including a driving circuit and at least one light-emitting unit connected to the driving circuit; a first conductive portion located on the substrate and connected to the driving circuit and the at least one light-emitting unit in each light-emitting region; and a second conductive portion located on the substrate and including a plurality of pads. The first conductive portion and the second conductive portion are located on the same layer.

[0004] In some embodiments, the plurality of light-emitting regions are arranged in M ​​rows along a first direction and in N columns along a second direction intersecting the first direction, where M and N are both positive integers greater than or equal to 1. The first conductive portion includes N driving voltage signal lines and N common voltage signal lines extending along the first direction. Each column of light-emitting regions includes one driving voltage signal line and one common voltage signal line. Within each column of light-emitting regions, the driving voltage signal line is connected to the first end of each light-emitting unit within that column, and the common voltage signal line is connected to each driving circuit within that column. Within each column of light-emitting regions, the driving voltage signal line, the light-emitting unit, the driving circuit, and the common voltage signal line are arranged sequentially along the second direction.

[0005] In some embodiments, the driving voltage signal line, the light-emitting unit, the driving circuit, and the orthogonal projection of the common voltage signal line onto the substrate do not overlap with each other.

[0006] In some embodiments, each driving circuit includes a plurality of terminals arranged in an array, the plurality of terminals being arranged in at least two columns along the second direction. The plurality of terminals includes at least one output terminal and at least one common voltage terminal, the at least one output terminal and the at least one common voltage terminal being located in different columns of the plurality of terminals. Within each column of light-emitting areas, the at least one output terminal of each driving circuit is connected one-to-one with the second end of the at least one light-emitting unit connected to that driving circuit, and the at least one common voltage terminal of each driving circuit is connected to the common voltage signal line within that column of light-emitting areas.

[0007] In some embodiments, the plurality of terminals further include address terminals, relay terminals, and power terminals. Each driving circuit in each column of light-emitting areas is cascaded sequentially. The address terminal of the i-th stage driving circuit is located on the side of the i-th stage driving circuit closer to the (i-1)-th stage driving circuit, and the relay terminal of the i-th stage driving circuit is located on the side of the i-th stage driving circuit closer to the (i+1)-th stage driving circuit, where 1 < i < M and i is a positive integer. The address terminal is configured to receive an address signal, the relay terminal is configured to output a relay signal, and the power terminal is configured to receive a power supply voltage signal.

[0008] In some embodiments, the extension direction of the first conductive portion is parallel to the cascading direction of the driving circuit.

[0009] In some embodiments, the plurality of terminals of the driving circuit are arranged in a first column and a second column along the second direction. In each column of light-emitting area, the first column of terminals of the driving circuit is located on the side of the driving circuit adjacent to the driving voltage signal line, and the second column of terminals of the driving circuit is located on the side of the driving circuit adjacent to the common voltage signal line.

[0010] In some embodiments, the first conductive portion further includes N power signal lines, each column of light-emitting areas including one power signal line, each power signal line including a main body portion and a first connecting portion, the main body portion of the power signal line extending along the first direction. Within each column of light-emitting areas, the power signal line is connected to the power terminal of each driving circuit within that column of light-emitting area via the first connecting portion, and the orthographic projections of the first column of terminals on the substrate and the orthographic projections of the second column of terminals on the substrate are respectively located on opposite sides of the orthographic projection of the power signal line on the substrate.

[0011] In some embodiments, the first conductive portion further includes N address signal lines extending along the first direction, with each column of light-emitting areas including one address signal line. Within each column of light-emitting areas, the address signal line is connected to the address terminal of the first-stage driving circuit.

[0012] In some embodiments, the first conductive portion further includes cascaded traces extending along the first direction, the cascaded traces being located between two adjacent cascaded driving circuits in each column of light-emitting regions, and the relay terminal of the i-th stage driving circuit being connected to the address terminal of the (i+1)-th stage driving circuit via the cascaded traces.

[0013] In some embodiments, the first conductive portion further includes N feedback signal lines extending along the first direction, with each column of light-emitting areas including one feedback signal line. Within each column of light-emitting areas, the feedback signal line is connected to the relay terminal of the last-stage driving circuit, and the feedback signal line is at least partially located on the side of the common voltage signal line in that column of light-emitting areas away from the driving circuit.

[0014] In some embodiments, the orthogonal projections of the drive voltage signal line, the address signal line, the cascaded trace, the power signal line, the common voltage signal line, and the feedback signal line onto the substrate do not overlap.

[0015] In some embodiments, the plurality of terminals of the driving circuit includes the address terminal, the power supply terminal, the common voltage terminal, and the output terminal. The first column of terminals includes the output terminal and the address terminal, and the second column of terminals includes the common voltage terminal and the power supply terminal.

[0016] In some embodiments, the output terminal and the relay terminal of the driving circuit are the same terminal. The driving circuit is configured to output a relay signal through the output terminal during a first time period as the address signal of the next-level driving circuit cascaded with the driving circuit, and to provide a driving signal to the at least one light-emitting unit connected to the driving circuit through the output terminal during a second time period.

[0017] In some embodiments, the plurality of terminals of the drive circuit further include data terminals, which are located in different columns of the plurality of terminals than the power supply terminals.

[0018] In some embodiments, the number of output terminals of the drive circuit is multiple and the number of common voltage terminals is at least one. The first column of terminals includes the power supply terminals and the multiple output terminals, and the second column of terminals includes the address terminals, the relay terminals, the data terminals, and the at least one common voltage terminal.

[0019] In some embodiments, the first conductive portion further includes N data driving signal lines, each column of light-emitting regions includes one data driving signal line, and each data driving signal line includes a main body portion and a second connecting portion, the main body portion of the data driving signal line extending along the first direction. Within each column of light-emitting regions, the data driving signal line is connected to the data terminal of each driving circuit within that column of light-emitting regions via the second connecting portion, and the orthographic projections of the first column of terminals on the substrate and the second column of terminals on the substrate are respectively located on opposite sides of the orthographic projection of the data driving signal line on the substrate, and the orthographic projections of the data driving signal line on the substrate do not overlap with the orthographic projections of the power signal line on the substrate.

[0020] In some embodiments, the plurality of output terminals of the driving circuit are connected one-to-one with the second terminals of the plurality of light-emitting units connected to the driving circuit. The driving circuit is configured to output a relay signal through the relay terminal during a first time period as the address signal of the next-stage driving circuit cascaded with the driving circuit, and to provide driving signals to the plurality of light-emitting units through the plurality of output terminals during a second time period.

[0021] In some embodiments, the spacing between the drive voltage signal line and other adjacent signal lines is greater than or equal to 0.2 mm.

[0022] In some embodiments, the light-emitting substrate further includes a plurality of flexible circuit boards and a fan-out region. Each signal line of the first conductive portion includes a straight portion and a bent portion. The bent portion of each signal line is located within the fan-out region, and each signal line is connected to the plurality of flexible circuit boards through its bent portion. Furthermore, the width of the bent portion of each signal line along the second direction is smaller than the width of two adjacent columns of light-emitting regions along the second direction.

[0023] In some embodiments, the angle between the straight portion and the bent portion of each signal line is 80° to 100°.

[0024] In some embodiments, the materials of the first conductive portion and the second conductive portion include copper.

[0025] In some embodiments, each light-emitting unit includes a plurality of light-emitting elements connected to each other, each of the plurality of light-emitting elements including a sub-millimeter light-emitting diode or a micro light-emitting diode.

[0026] In some embodiments, the light-emitting substrate further includes a shielding ring surrounding the periphery of the plurality of light-emitting regions, and the electrical signal received by the shielding ring is the same as the electrical signal received by the common voltage signal line.

[0027] In some embodiments, the light-emitting substrate further includes a buffer layer and an insulating layer. The buffer layer is located between the layer containing the first conductive portion and the second conductive portion and the substrate, and the insulating layer is located on the side of the layer containing the first conductive portion and the second conductive portion away from the substrate.

[0028] According to another aspect of this disclosure, a backlight source is provided, which includes a light-emitting substrate described in any of the preceding embodiments.

[0029] According to another aspect of this disclosure, a display device is provided, which includes a light-emitting substrate described in any of the preceding embodiments.

[0030] According to another aspect of this disclosure, a method for manufacturing a light-emitting substrate is provided, the method comprising the steps of: providing a substrate; forming a conductive layer on the substrate, patterning the conductive layer to simultaneously form a first conductive portion and a second conductive portion including a plurality of pads; and mounting a plurality of driving circuits and a plurality of light-emitting units on the substrate to form a plurality of light-emitting regions arranged in an array, each of the plurality of light-emitting regions including a driving circuit and at least one light-emitting unit connected to the driving circuit. The first conductive portion is connected to the driving circuit and the at least one light-emitting unit in each light-emitting region. Attached Figure Description

[0031] To more clearly describe the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A schematic diagram of the arrangement of a light-emitting substrate according to an embodiment of the present disclosure is shown;

[0033] Figure 2 A wiring diagram of a light-emitting substrate provided according to an embodiment of the present disclosure is shown;

[0034] Figure 3 It shows Figure 2 A schematic diagram of the terminal arrangement of the driving circuit of the light-emitting substrate;

[0035] Figure 4 It shows Figure 2 A schematic diagram of the arrangement of the first pad on the light-emitting substrate;

[0036] Figure 5 It shows Figure 2 A magnified view of a portion of the image;

[0037] Figure 6A wiring diagram of a light-emitting substrate provided according to an embodiment of the present disclosure is shown;

[0038] Figure 7 A wiring diagram of a light-emitting substrate provided according to another embodiment of the present disclosure is shown;

[0039] Figure 8 It shows Figure 7 A schematic diagram of the arrangement of the first pad on the light-emitting substrate;

[0040] Figure 9 It shows Figure 7 A magnified view of a portion of the image;

[0041] Figure 10 It shows Figure 9 A magnified view of a portion of the image;

[0042] Figure 11A A schematic diagram of the arrangement of a flexible circuit board for a light-emitting substrate provided according to an embodiment of the present disclosure is shown;

[0043] Figure 11B It shows Figure 11A A magnified view of region I in the image;

[0044] Figure 12 A schematic diagram showing the arrangement of light-emitting units in a light-emitting substrate provided according to an embodiment of the present disclosure is shown;

[0045] Figure 13 A schematic diagram of the structure of a light-emitting substrate provided according to an embodiment of the present disclosure is shown;

[0046] Figure 14 A block diagram of a backlight source provided according to yet another embodiment of the present disclosure is shown;

[0047] Figure 15 A block diagram of a display device according to another embodiment of the present disclosure is shown; and

[0048] Figure 16 A flowchart is shown of a method for manufacturing a light-emitting substrate according to another embodiment of the present disclosure. Detailed Implementation

[0049] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0050] Embodiments of this disclosure provide a light-emitting substrate, Figure 1A schematic diagram of the arrangement of the light-emitting substrate 100 is shown. (As shown...) Figure 1 As shown, the light-emitting substrate 100 includes a substrate 101, a first conductive portion 105 disposed on the substrate 101, and a second conductive portion 106. The substrate 101 includes a plurality of light-emitting regions 102 arranged in an array, each light-emitting region 102 including a driving circuit 103 and at least one light-emitting unit 104 connected to the driving circuit 103. The first conductive portion 105 is connected to the driving circuit 103 and the light-emitting unit 104 in each light-emitting region 102, and for example, the first conductive portion 105 may include multiple signal traces. Figure 1 The dashed box on the left shows an enlarged schematic diagram of a light-emitting area 102. As shown in the enlarged schematic diagram, the second conductive part 106 includes multiple pads, such as multiple first pads 107 and multiple second pads 108. The driving circuit 103 is mounted on the first pads 107, and the light-emitting unit 104 is mounted on the second pads 108. The first conductive part 105 and the second conductive part 106 are located in the same layer. It should be noted that in this application, the term "A and B are located in the same layer" means that A and B are located on the surface of the same film layer and are both in direct contact with the surface. In some embodiments, A and B are formed by the same film layer using the same process. In some embodiments, A and B are located on the surface of the same film layer and are both in direct contact with the surface, and A and B have substantially the same height or thickness.

[0051] Understandable Figure 1 The drawings are for illustrative purposes only, showing the connection relationships between the driving circuit 103, the light-emitting unit 104, the first conductive part 105, and the second conductive part 106. The dimensions of the driving circuit 103, the light-emitting unit 104, the first conductive part 105, and the second conductive part 106 are not drawn to scale, and their relative positions may not correspond exactly to their actual positions. For clarity, the proportions of certain areas and layers may be exaggerated in the drawings.

[0052] By placing the first conductive portion 105 and the second conductive portion 106 on the same layer, a single conductive layer can not only be used to fabricate the first pad 107 and the second pad 108 of the second conductive portion 106, as well as the traces connecting the driving circuit 103 and the light-emitting unit 104, but also to fabricate multiple signal lines of the first conductive portion 105 to transmit corresponding electrical signals to the driving circuit 103 and the light-emitting unit 104 in each light-emitting area 102. In contrast, related technologies typically use at least two conductive layers to achieve the above-mentioned electrical connection relationship; that is, the first pad and the second pad are fabricated using the first conductive layer, and the signal lines are fabricated using the second conductive layer located on a different layer from the first conductive layer to transmit corresponding electrical signals. Since the first conductive layer and the second conductive layer often inevitably overlap in the direction perpendicular to the substrate, and the overlapping area is a weak performance area, short circuits or open circuits are very likely to occur between the first conductive layer and the second conductive layer, thereby affecting the light-emitting performance of the light-emitting substrate. Moreover, different masks are required when fabricating the first conductive layer and the second conductive layer located on different layers, which greatly increases the production cost. Compared to related technologies, in this application, the first conductive portion 105 and the second conductive portion 106 are located on the same layer. On the one hand, since a single conductive layer does not have the overlapping problem of double conductive layers, short circuits or open circuits caused by the overlap of the first conductive portion 105 and the second conductive portion 106 in the direction perpendicular to the substrate 101 can be completely avoided, thereby improving the light-emitting performance and light-emitting stability of the light-emitting substrate 100. On the other hand, during the manufacturing process, the first conductive portion 105 and the second conductive portion 106 can be formed simultaneously from the same material using the same process, thus reducing the number of photomasks used, lowering production costs, simplifying the manufacturing process, and improving production efficiency.

[0053] like Figure 1As shown, multiple light-emitting regions 102 are arranged in M ​​rows along a first direction D1 and in N columns along a second direction D2 intersecting the first direction D1, where M and N are both positive integers greater than or equal to 1. The first direction D1 can be the vertical direction shown in the figure, and the second direction D2 can be the horizontal direction shown in the figure. The first direction D1 and the second direction D2 can be perpendicular to each other. The first conductive part 105 includes N driving voltage signal lines VLEDL and N common voltage signal lines GNDL extending along the first direction D1, such that each column of light-emitting regions 001 includes one driving voltage signal line VLEDL and one common voltage signal line GNDL. In each column of light-emitting regions 001, one driving voltage signal line VLEDL is connected to the first end of each light-emitting unit 104 in that column of light-emitting regions 001, and one common voltage signal line GNDL is connected to each driving circuit 103 in that column of light-emitting regions 001. The driving voltage signal line VLEDL is configured to provide a driving voltage to the light-emitting unit 104, and the common voltage signal line GNDL is configured to provide a common voltage (e.g., ground voltage) to the driving circuit 103. For example, when it is necessary to make the light-emitting unit 104 in a certain light-emitting area 102 emit light, by making the driving voltage high and the common voltage low, a voltage difference is generated on both sides of the light-emitting unit 104, thereby driving the light-emitting unit 104 to emit light. In each column of light-emitting areas 001, the driving voltage signal line VLEDL, the light-emitting unit 104, the driving circuit 103, and the common voltage signal line GNDL are arranged sequentially along the second direction D2. Figure 1 Taking the first column of light-emitting regions 001 as an example, each light-emitting unit 104 (i.e., the light-emitting units 104 in rows 1 to M) in this column of light-emitting regions 001 is arranged as a column of light-emitting units, and each driving circuit 103 (i.e., the driving circuits 103 in rows 1 to M) in this column of light-emitting regions 001 is arranged as a column of driving circuits. Along the second direction D2, from left to right in the figure, they are arranged sequentially in the order of driving voltage signal line VLEDL, light-emitting unit column, driving circuit column, and common voltage signal line GNDL. In some embodiments, within each column of light-emitting regions 001, the orthographic projections of the driving voltage signal line VLEDL, light-emitting unit column, driving circuit column, and common voltage signal line GNDL onto the substrate 101 do not overlap. With this arrangement, short circuits or open circuits can be completely avoided between the driving voltage signal line VLEDL and the common voltage signal line GNDL of the first conductive part 105 and the first pad 107 and the second pad 108 of the second conductive part 106, thereby improving the light-emitting performance of the light-emitting substrate 100 and enhancing the light-emitting stability of the light-emitting substrate 100.

[0054] The driving circuit 103 can be an integrated circuit, particularly a packaged chip with multiple terminals. The driving circuit 103 can include one output terminal, or at least two output terminals, such as two, three, four, or more output terminals. The arrangement of the terminals in the driving circuit 103 of this application is optimized compared to related technologies, thereby better accommodating the wiring of each signal line, ensuring that there is no overlap between the signal lines, whether in the direction perpendicular to or parallel to the substrate 101.

[0055] Below, for reference Figure 2 and Figure 7 To describe some common characteristics of the light-emitting substrate 200 and the light-emitting substrate 300.

[0056] like Figure 2 and Figure 7 As shown, each driving circuit 103 includes a plurality of terminals arranged in an array along a first direction D1 and a second direction D2, with the plurality of terminals arranged in at least two columns along the second direction D2. The plurality of terminals includes at least one output terminal Out and at least one common voltage terminal GND, located in different columns of the plurality of terminals. Within each column of light-emitting area 001, at least one output terminal Out of each driving circuit 103 is connected one-to-one with the second end of at least one light-emitting unit 104 connected to that driving circuit 103 to transmit a driving signal to at least one light-emitting unit 104; at least one common voltage terminal GND of each driving circuit 103 is connected to a common voltage signal line GNDL to receive a common voltage (e.g., ground voltage) transmitted by the common voltage signal line GNDL.

[0057] The driving circuit 103 also includes address terminals Di / Di_in, relay terminals Out / Di_out, and power supply terminals Pwr / Vcc. Each driving circuit 103 within each column of light-emitting areas 001 is cascaded sequentially. The address terminal Di / Di_in of the i-th stage driving circuit 103 is located on the side of the i-th stage driving circuit 103 closest to the (i-1)-th stage driving circuit 103, and the relay terminal Out / Di_out of the i-th stage driving circuit 103 is located on the side of the i-th stage driving circuit 103 closest to the (i+1)-th stage driving circuit 103, where 1 < i < M and i is a positive integer. In the embodiments of this disclosure, each driving circuit 103 within each column of light-emitting areas 001 is cascaded sequentially from bottom to top along the first direction D1. The i-th stage driving circuit 103 refers to the i-th driving circuit 103 counting upwards from the M-th row of driving circuits 103 within each column of light-emitting areas 001. For example, taking the first column of light-emitting area 001 as an example, the driving circuit 103 located in the Mth row of the first column is the first-level driving circuit, the driving circuit 103 located in the (M-1)th row of the first column is the second-level driving circuit, and so on, the driving circuit 103 located in the second row of the first column is the (M-1)th-level driving circuit, and the driving circuit 103 located in the first row of the first column is the Mth-level driving circuit. Figure 2 In the driver circuit 103 shown, the address terminal is Di, the relay terminal is Out, and the power supply terminal is Pwr. In this driver circuit 103, the output terminal Out is multiplexed as a relay terminal; that is, the output terminal Out and the relay terminal are the same terminal. The output terminal Out outputs different signals at different times, for example, it can output a relay signal as a relay terminal and a drive signal as an output terminal. In such cases... Figure 7 In the driving circuit 103 shown, the address terminal is Di_in, the relay terminal is Di_out, and the power supply terminal is Vcc. In this driving circuit 103, the output terminal Out and the relay terminal Di_out are two different terminals. The address terminals Di / Di_in are configured to receive address signals, the relay terminals Out / Di_out are configured to output relay signals, and the power supply terminals Pwr / Vcc are configured to receive power supply voltage signals. Multiple terminals of the driving circuit 103 are arranged in a first column and a second column along the second direction D2. Within each column of light-emitting area 001, the first column of terminals of the driving circuit 103 is located on one side of the driving voltage signal line VLEDL (i.e., on the left side of the driving circuit 103), and the second column of terminals of the driving circuit 103 is located on one side of the driving circuit 103 adjacent to the common voltage signal line GNDL (i.e., on the right side of the driving circuit 103). This arrangement of the terminals of the drive circuit 103 helps to promote the orderly arrangement of each signal trace, so that the signal traces do not overlap with each other, thereby avoiding short circuits / open circuits or signal crosstalk caused by overlapping of the signal traces.

[0058] like Figure 2 and Figure 7 As shown, the first conductive portion 105 also includes N address signal lines ADDRL extending along the first direction D1, such that each column of light-emitting regions 001 includes one address signal line ADDRL. Although Figure 2 and Figure 7 The diagram only shows a partial screenshot of the light-emitting substrate, which includes four light-emitting regions 102 arranged in a 2x2 grid. In reality, the substrate typically includes multiple light-emitting regions 102 arranged in M ​​rows and N columns, where M and N are any positive integers greater than or equal to 1. Therefore, each column of light-emitting regions 001 includes multiple driving circuits 103, which are cascaded sequentially via cascaded traces 111 extending along the first direction D1. The address signal line ADDRL is connected to the address terminals Di / Di_in of the first-stage driving circuit 103, and the relay terminals Out / Di_out of the previous-stage driving circuit are connected to the address terminals Di / Di_in of the next-stage driving circuit 103 via the cascaded traces 111. Figure 2 In the example, each column of light-emitting areas 001 is shown as including two driving circuits 103, which are cascaded sequentially via a cascaded trace 111 extending along a first direction D1. The address signal line ADDRL is connected to the address terminal Di of the first-stage driving circuit 103, and the relay terminal Out of the first-stage driving circuit is connected to the address terminal Di of the second-stage driving circuit 103 via the cascaded trace 111. Figure 7 In the example, each column of light-emitting areas 001 is shown to include two driving circuits 103, which are cascaded sequentially via a cascaded trace 111 extending along a first direction D1. The address signal line ADDRL is connected to the address terminal Di_in of the first-stage driving circuit 103, and the relay terminal Di_out of the first-stage driving circuit is connected to the address terminal Di_in of the second-stage driving circuit 103 via the cascaded trace 111.

[0059] The address selection signal line ADDRL is configured to transmit an address signal to the address terminals Di / Di_in of the first-stage driving circuit 103 within each column of light-emitting area 001. After receiving the address signal, the first-stage driving circuit 103 can parse, obtain, and store the address information within it as its own address information. Simultaneously, it can increment the address information by 1 or another fixed amount and modulate the incremented address information (the new address information) into a relay signal. The relay terminal Out / Di_out of the first-stage driving circuit 103 transmits this relay signal to the address terminals Di / Di_in of the second-stage driving circuit 103 via cascaded wiring 111, serving as the address information for the second-stage driving circuit 103. Alternatively, the first-stage driving circuit 103 can use any other suitable function to transform its address information to generate a relay signal. The second-stage driving circuit 103 transmits the relay signal to the third-stage driving circuit 103 in a similar manner, and so on. In this way, corresponding address information can be configured for each of the multiple cascaded drive circuits 103 within each column of light-emitting areas 001. It can be seen that for a column of light-emitting areas 001, only one address signal line (ADDRL) is needed to provide an address signal, which enables all drive circuits 103 within that column of light-emitting areas 001 to obtain their respective address information. This greatly reduces the number of signal lines, saves wiring space, and simplifies the control method.

[0060] like Figure 2 and Figure 7 As shown, the first conductive portion 105 also includes N feedback signal lines FBL extending along the first direction D1, with each column of light-emitting areas 001 including one feedback signal line FBL. Within each column of light-emitting areas 001, the feedback signal line FBL is connected to the relay terminal Out / Di_out of the last-stage driving circuit 103. The feedback signal line FBL bypasses the common voltage signal line GNDL within the column of light-emitting areas 001 and is located on the side of the common voltage signal line GNDL away from the driving circuit 103.

[0061] The first conductive portion 105 also includes N power signal lines PwrL / VccL, with each column of light-emitting areas 001 including one power signal line PwrL / VccL. Each power signal line PwrL / VccL includes a main body and a first connecting portion 118, with the main body extending along a first direction D1. Within each column of light-emitting areas 001, one power signal line PwrL / VccL is connected to the power terminals Pwr / Vcc of all driving circuits 103 within that column of light-emitting areas 001 via the first connecting portion 118. The orthographic projections of the first and second columns of terminals of each driving circuit 103 on the substrate 101 are located on opposite sides of the orthographic projection of the power signal line PwrL / VccL on the substrate 101, respectively. That is, the power signal line PwrL / VccL is arranged within the area occupied by each driving circuit 103 and does not overlap with the first and second columns of terminals of each driving circuit 103. By arranging the power signal line PwrL / VccL within each column of light-emitting area 001 within the area occupied by each driving circuit 103, wiring space can be saved, and overlap between the power signal line PwrL / VccL and other signal lines can be avoided.

[0062] It should be noted that, in the embodiments of this disclosure, the signal line typically includes a main body and a connecting portion. The main body defines the primary extension direction of the signal line, while the connecting portion is used to connect the signal line to a desired component. For example, the driving voltage signal line VLEDL is connected to the second end of the light-emitting unit 104 through its connecting portion; the power signal line PwrL / VccL is connected to the power terminal Pwr / Vcc of the driving circuit 103 through the first connecting portion 118; and the common voltage signal line GNDL is connected to the common voltage terminal GND of the driving circuit 103 through its connecting portion. The connecting portion of each signal line is much smaller in length or width compared to its main body. Therefore, in the specification of this application, phrases such as "X signal line extending along the first direction D1" only specify that the main body of the X signal line extends along the first direction D1, but do not specify that the connecting portion of the X signal line extends along the first direction D1. For example, the main body of each power signal line PwrL / VccL extends along the first direction D1, but its first connection portion 118 does not extend along the first direction D1, but extends along a direction that intersects the first direction D1 (e.g., the second direction D2).

[0063] In each column of light-emitting areas 001, the power signal line PwrL / VccL is configured to transmit a power voltage signal to the power terminal Pwr / Vcc of each drive circuit 103, thereby providing a power voltage for each drive circuit 103. In one example, the power voltage signal is a power line carrier communication signal. In this case, the power signal line PwrL / VccL can not only provide a power voltage to each drive circuit 103, but also provide communication data to each drive circuit 103. This communication data can be used to control the light-emitting duration of at least one light-emitting unit 104 connected to the drive circuit 103, thereby controlling its visual brightness. The power line carrier communication signal contains information corresponding to the communication data. For example, the communication data is data reflecting the light-emitting duration, which in turn represents the required brightness. Compared to the conventional Serial Peripheral Interface (SPI) protocol, this embodiment of the disclosure effectively reduces the number of signal lines by employing the Power Line Carrier Communication (PLC) protocol, which superimposes the communication data onto the power signal line PwrL / VccL.

[0064] pass Figure 2 and Figure 7 As can be seen from the example, the terminals of the driving circuit 103 are arranged as described above, ensuring that the orthographic projections of the driving voltage signal line VLEDL, address signal line ADDRL, cascaded trace 111, power signal line PwrL / VccL, common voltage signal line GNDL, and feedback signal line FBL of the first conductive portion 105 on the substrate 101 do not overlap. Furthermore, the orthographic projections of the driving voltage signal line VLEDL, common voltage signal line GNDL, and feedback signal line FBL of the first conductive portion 105 on the substrate 101 do not overlap with the orthographic projections of the first pad 107 and the second pad 108 of the second conductive portion 106 on the substrate 101. Therefore, short circuits or open circuits caused by the overlap of the first conductive portion 105 and the second conductive portion 106 located on the same layer can be completely avoided, thereby improving the light-emitting performance and stability of the light-emitting substrate.

[0065] The above describes some common characteristics of the light-emitting substrate 200 and the light-emitting substrate 300. Below, two examples will be used to describe the specific arrangement of the light-emitting substrate 200 and the light-emitting substrate 300, respectively.

[0066] Figure 2 The arrangement of the light-emitting substrate 200 is shown. Although Figure 2Only four light-emitting regions 102 are shown, arranged in a 2x2 row and 2x2 column configuration. However, this is only a partial screenshot of the light-emitting substrate 200. The light-emitting substrate 200 can include any suitable number of light-emitting regions 102, which can be arranged in multiple rows and columns. This disclosure does not impose a specific limitation on the number of light-emitting regions 102 included in the light-emitting substrate 200. As shown in the figure, each light-emitting region 102 includes a driving circuit 103 and a light-emitting unit 104 connected to the driving circuit 103. Figure 3 This refers to the arrangement of the terminals of the drive circuit 103.

[0067] like Figure 2 and Figure 3 As shown, each driving circuit 103 includes four terminals: address terminal Di, power supply terminal Pwr, common voltage terminal GND, and output terminal Out. Output terminal Out and address terminal Di form the first column of terminals for driving circuit 103, located on the side of driving circuit 103 adjacent to the driving voltage signal line VLEDL (i.e., on the left side of driving circuit 103); common voltage terminal GND and power supply terminal Pwr form the second column of terminals for driving circuit 103, located on the side of driving circuit 103 adjacent to the common voltage signal line GNDL (i.e., on the right side of driving circuit 103). Address terminal Di and power supply terminal Pwr are located in the second row of terminals, while common voltage terminal GND and output terminal Out are located in the first row of terminals. As previously mentioned, output terminal Out is multiplexed as a relay terminal. Within each column of light-emitting area 001, the first-stage driving circuit 103 (i.e.,... Figure 2 One end of the output terminal Out of the driving circuit 103 located in the second row and first column is connected to the light-emitting unit 104 corresponding to the driving circuit 103, and the other end is connected to the second-stage driving circuit 103 (i.e., the second-stage driving circuit 103) via the cascaded wiring 111. Figure 2The address terminal Di of the driving circuit 103 located in the first row and first column is specified. One end of the output terminal Out of the second-stage driving circuit 103 is connected to the light-emitting unit 104 corresponding to the driving circuit 103, and the other end is connected to the feedback trace FBL. The output terminal Out can output different signals at different time periods. For example, the output terminal Out of the driving circuit 103 outputs a relay signal as the address signal of the next-stage driving circuit 103 cascaded with the driving circuit 103 during one time period, and provides a driving signal to the light-emitting unit 104 connected to the driving circuit 103 during another time period to make the light-emitting unit 104 emit light. The one time period and the other time period are two independent time periods, for example, the other time period immediately follows the one time period. The driving signal can be, for example, a driving current, used to drive the light-emitting unit 104 to emit light. It should be noted that when the driving signal is a driving current, the driving current can flow from the output terminal Out to the light-emitting unit 104, or it can flow from the light-emitting unit 104 to the output terminal Out. The direction of the driving current flow can be determined according to actual needs, and the embodiments of this disclosure do not limit this.

[0068] The spacing between the terminals of the driving circuit 103 of the light-emitting substrate 200 is typically determined based on various factors (such as process limits, linewidth requirements between two columns of terminals, electrical design requirements, etc.), and the embodiments disclosed herein do not impose specific limitations on this. For example, the spacing between the first column of terminals and the second column of terminals can be 70–300 μm, and the spacing between the first row of terminals and the second row of terminals can be 70–300 μm. Figure 3As shown, in one example, the spacing S1 between the first column terminals and the second column terminals is 140 μm, and the spacing S2 between the first row terminals and the second row terminals is 120 μm. That is, the spacing between the output terminal Out and the common voltage terminal GND is 140 μm, and the spacing between the address terminal Di and the power supply terminal Pwr is 140 μm; the spacing between the output terminal Out and the address terminal Di is 120 μm, and the spacing between the common voltage terminal GND and the power supply terminal Pwr is 120 μm. The four terminals of the drive circuit 103 occupy substantially the same area and have substantially the same length and width. The width S3 of each terminal along the second direction D2 is 80 μm, and the length S4 of each terminal along the first direction D1 is 100 μm. The distance S5 between the second row of terminals and the first side of the drive circuit 103 (i.e., the lower edge of the drive circuit 103) is 25μm, that is, the distance S5 between the address terminal Di and the power supply terminal Pwr and the lower edge of the drive circuit 103 is 25μm; the distance S5 between the first row of terminals and the second side of the drive circuit 103 (i.e., the upper edge of the drive circuit 103) is 25μm, that is, the distance S5 between the output terminal Out and the common voltage terminal GND and the upper edge of the drive circuit 103 is 25μm. The distance S6 between the first column of terminals and the third side (i.e., the left edge of the driving circuit 103) is 25 μm, meaning the distance S6 between the output terminal Out and the address terminal Di and the left edge of the driving circuit 103 is 25 μm. Similarly, the distance S6 between the second column of terminals and the fourth side (i.e., the right edge of the driving circuit 103) is 25 μm, meaning the distance S6 between the common voltage terminal GND and the power supply terminal Pwr and the right edge of the driving circuit 103 is 25 μm. Therefore, the length L of the driving circuit 103 along the first direction D1 is 370 μm, and the width W of the driving circuit 103 along the second direction D2 is 350 μm. Within each column of light-emitting area 001, the distance between the power signal line PwrL and the first and second column of terminals can be 10–100 μm, respectively. In one example, the width of the power signal line PwrL between the first and second column of terminals along the second direction D2 is greater than or equal to 40 μm.

[0069] exist Figure 2 In the example, each column of light-emitting regions 001 includes a driving voltage signal line VLEDL, an addressing signal line ADDRL, a cascaded trace 111, a power signal line PwrL, a common voltage signal line GNDL, and a feedback signal line FBL. These signal lines do not overlap with each other, whether in the direction perpendicular to the substrate 101 or in the direction parallel to the substrate 101. The function and arrangement of these signal lines have been described above and will not be repeated here for the sake of brevity.

[0070] Below is a brief introduction. Figure 2 The working mode of the light-emitting substrate 200.

[0071] When the driving circuit 103 starts working, it first provides power voltage to the power terminals Pwr of each driving circuit 103 in each column of light-emitting area 001 through the power signal line PwrL to complete the initialization. In this way, the driving circuit 103 is in the power-on state.

[0072] Next, the address write operation is performed during the first time period. That is, the ADDRL signal line inputs the address signal to the first-stage driver circuit 103 through the address terminal Di, thereby writing the address.

[0073] Next, in the second time period, drive configuration is performed, and the first-stage drive circuit 103 outputs a relay signal through the output terminal Out. This relay signal is transmitted via cascaded trace 111 to the address terminal Di of the second-stage drive circuit 103 as the address signal of the second-stage drive circuit 103. This process continues until all drive circuits 103 have completed address information configuration.

[0074] Then, in the third time period, a drive voltage is provided to the drive voltage signal line VLEDL. For example, this third time period is entered after multiple drive circuits 103 have obtained the corresponding address information. At this time, the drive voltage transmitted on the drive voltage signal line VLEDL becomes high.

[0075] Next, in the fourth time period, the output terminal Out of each driving circuit 103 provides a driving signal (e.g., driving current) according to the required light emission duration. At this time, the driving voltage signal line VLEDL, the light emission unit 104, the output terminal Out electrically connected to the light emission unit 104, and the common voltage signal line GNDL form a signal loop, and the light emission unit 104 emits light according to the required light emission duration.

[0076] Finally, in the fifth period, the system shuts down, that is, the drive circuit 103 is de-energized, and the drive voltage provided by the drive voltage signal line VLEDL becomes low, and the light-emitting unit 104 stops emitting light.

[0077] Figure 2The illustrated light-emitting substrate 200 enables zoned dimming. The substrate 200 includes multiple light-emitting regions 102, each region comprising a driving circuit 103 and a light-emitting unit 104 connected to and controlled by the driving circuit 103, allowing the brightness of each light-emitting unit 104 to be independently controlled. For example, by setting address signals and power supply voltage signals provided to each driving circuit 103, the light-emitting duration of each light-emitting unit 104 connected to each driving circuit 103 can be controlled separately, thereby controlling the visual brightness. This light-emitting substrate 200 enables independent zoned brightness control, making it widely applicable. Furthermore, each driving circuit 103 has a small number of ports, requiring fewer control signals, resulting in a simple control method, low power consumption, and ease of operation. The substrate 200 has high integration and can be used with liquid crystal display devices to achieve high-contrast displays.

[0078] Figure 4 The arrangement of the first pad 107 and its surrounding traces is shown. The first pad 107 is equipped with... Figure 2 The driving circuit 103 shown is electrically connected to the first pad 107, which has four sub-pads at the positions corresponding to the four terminals of the driving circuit 103. These are: a first sub-pad for mounting the address terminal Di, a second sub-pad for mounting the power terminal Pwr, a third sub-pad for mounting the common voltage terminal GND, and a fourth sub-pad for mounting the output terminal Out. The first sub-pad is connected to the address terminal Di of the driving circuit 103, the second sub-pad is connected to the power terminal Pwr, the third sub-pad is connected to the common voltage terminal GND, and the fourth sub-pad is connected to the output terminal Out. The first sub-pad is connected to the address selection signal line ADDRL to transmit the address signal on the address selection signal line ADDRL to the address terminal Di. The second sub-pad is connected to the power signal line PwrL to transmit the power voltage signal on the power signal line PwrL to the power terminal Pwr. The third sub-pad is connected to the common voltage signal line GNDL to transmit the common voltage signal on the common voltage signal line GNDL to the common voltage terminal GND. One end of the fourth sub-pad is connected to the cascaded trace 111 to output a relay signal for a period of time as an address signal for the next stage driver circuit 103 cascaded with the driver circuit 103; the other end of the fourth sub-pad is connected to the trace 109 to transmit the drive signal to the light-emitting unit 104 connected to the driver circuit 103 via the trace 109 for another period of time.

[0079] Figure 5 yes Figure 2A partial schematic diagram shows two columns of light-emitting regions 001. Within each column of light-emitting regions 001, four second pads 108 are connected in series to a first pad 107. Each column of light-emitting regions 001 shows an addressing signal line ADDRL, a power signal line PwrL, a common voltage signal line GNDL, and a feedback signal line FBL. The drive voltage signal line VLEDL is not shown, but as previously mentioned, each column of light-emitting regions 001 includes the drive voltage signal line VLEDL, it's just not shown in the diagram. As shown in the figure, the end of the address signal line ADDRL in the first column of light-emitting area 001 near the first pad 107 is basically flush with the end of the address signal line ADDRL in the second column of light-emitting area 001 near the first pad 107, meaning that the address signal lines ADDRL in the first column of light-emitting area 001 and ADDRL in the second column of light-emitting area 001 have basically the same length; the end of the power signal line PwrL in the first column of light-emitting area 001 near the first pad 107 is basically flush with the end of the power signal line PwrL in the second column of light-emitting area 001 near the first pad 107, meaning that the power signal lines PwrL in the first column of light-emitting area 001 and PwrL in the second column of light-emitting area 001 have basically the same length. Length; The end of the common voltage signal line GNDL in the first column of light-emitting area 001 near the first pad 107 is basically flush with the end of the common voltage signal line GNDL in the second column of light-emitting area 001 near the first pad 107, that is, the common voltage signal line GNDL in the first column of light-emitting area 001 and the common voltage signal line GNDL in the second column of light-emitting area 001 have basically the same length; The end of the feedback signal line FBL in the first column of light-emitting area 001 near the first pad 107 is basically flush with the end of the feedback signal line FBL in the second column of light-emitting area 001 near the first pad 107, that is, the feedback signal line FBL in the first column of light-emitting area 001 and the feedback signal line FBL in the second column of light-emitting area 001 have basically the same length. Although not shown in the figure, the end of the driving voltage signal line VLEDL in the first column of light-emitting areas 001 near the first pad 107 is basically flush with the end of the driving voltage signal line VLEDL in the second column of light-emitting areas 001 near the first pad 107. That is, the driving voltage signal lines VLEDL in the first column of light-emitting areas 001 and VLEDL in the second column of light-emitting areas 001 have basically the same length. When the light-emitting substrate 200 includes N columns of light-emitting areas 001, the same signal lines in each column of light-emitting areas 001 have basically the same length to maintain the uniformity of each column of light-emitting areas 001. Here, "the same signal lines in each column of light-emitting areas 001" refers to signal lines with the same function in each column of light-emitting areas 001. For example, the driving voltage signal lines VLEDL in the first to Nth columns of light-emitting areas 001 are the same signal lines.This arrangement ensures that the same signal lines in each column of light-emitting areas 001 have essentially the same length. Therefore, the signal lines in each column of light-emitting areas 001 have roughly the same resistance and voltage drop, resulting in better brightness uniformity among the columns of light-emitting areas 001.

[0080] The light-emitting substrate 200 may also include a shielding ring (GND ESD Ring). Figure 6 The shielding ring GND ESD Ring is shown. The GND ESD Ring surrounds the periphery of multiple light-emitting areas 102 to provide electrostatic shielding. The electrical signal received by the GND ESD Ring is the same as the electrical signal received by the common voltage signal line GNDL. For example, both the GND ESD Ring and the common voltage signal line GNDL are connected to the bonding electrodes of the bonding area. The bonding electrodes connecting the GND ESD Ring and the bonding electrodes connecting the common voltage signal line GNDL have the same definition, thereby ensuring that the electrical signal received by the GND ESD Ring is the same as the electrical signal received by the common voltage signal line GNDL. The GND ESD Ring can be located in the same layer as the first conductive portion 105 and the second conductive portion 106. The shape of the GND ESD Ring is not limited to... Figure 6 The shape shown can have any suitable shape, as long as it can provide electrostatic shielding for the light-emitting area 102. In one example, the width of the shielding ring GND ESD Ring is greater than or equal to 200µm.

[0081] Figure 7 The light-emitting substrate 300 is shown. Figure 8 The arrangement of the terminals of the driving circuit 103 of the light-emitting substrate 300 is shown. Figure 7 The light-emitting substrate 300 shown has the same characteristics as in the image. Figure 2 The light-emitting substrate 200 shown in the figure has a substantially the same structure, and therefore the same reference numerals are used to refer to the same components. Therefore, Figure 7 It has with Figure 2 For detailed descriptions of the functions and uses of components with the same reference numerals in the accompanying drawings, please refer to the [reference needed]. Figure 2 The explanations will not be repeated here. For the sake of brevity, the following discussion will mainly focus on the different parts.

[0082] refer to Figure 7 and Figure 8 ,and Figure 2 The light-emitting substrate 200 in the middle is different from that in the middle. Figure 7 The driving circuit 103 of the light-emitting substrate 300 has more terminals, including multiple output terminals Out and at least one common voltage terminal GND. Figure 7The diagram shows four output terminals (Out) and two common voltage terminals (GND), but this is only an example. The number of output terminals (Out) may be more or less than four, and the number of common voltage terminals (GND) may be more or less than two. In embodiments of this disclosure, the number of output terminals (Out) is at least two, and the number of common voltage terminals (GND) is at least one. Furthermore, the drive circuit 103 also includes a data terminal (Data). Figure 7 and Figure 8 As shown, the drive circuit 103 includes two columns of terminals. The first column includes a power supply terminal Vcc and four output terminals Out1, Out2, Out3, and Out4. This first column is located on the side of the drive circuit 103 adjacent to the drive voltage signal line VLEDL (i.e., on the left side of the drive circuit 103). The second column includes an address terminal Di_in, a relay terminal Di_out, a data terminal Data, and two common voltage terminals GND. This second column is located on the side of the drive circuit 103 adjacent to the common voltage signal line GNDL (i.e., on the right side of the drive circuit 103). The multiple terminals of the drive circuit 103 are arranged in five rows, with the address terminal Di_in located in the fifth row and the relay terminal Di_out located in the first row. Although... Figure 8 The diagram shows the power terminal Vcc located in the 3rd row of the first column of terminals and the data terminal Data located in the 2nd row of the second column of terminals. However, this is merely an example, and the embodiments disclosed herein do not limit the specific positions of the power terminal Vcc in the first column of terminals or the data terminal Data in the second column of terminals. For example, the power terminal Vcc can be located in any one of the rows 1 to 5 of the first column of terminals, and the data terminal Data can be located in any one of the rows 2 to 4 of the second column of terminals.

[0083] As shown in the figure, the four output terminals Out1, Out2, Out3, and Out4 of the driving circuit 103 are connected one-to-one with the second terminals of the four light-emitting units 104 to provide driving signals for the light-emitting units 104. Figure 7In the example, the output terminal and the relay terminal of the driving circuit 103 are different terminals. The driving circuit 103 is configured to output a relay signal through the relay terminal Di_out during one time period as an address signal for the next-stage driving circuit 103 cascaded with it, and to provide driving signals to the four light-emitting units 104 through four output terminals Out1, Out2, Out3, and Out4 during another time period. The one time period and the other time period are two independent time periods; for example, the other time period immediately follows the first time period. The driving signal can be, for example, a driving current, used to drive the light-emitting units 104 to emit light. It should be noted that when the driving signal is a driving current, the driving current can flow from the output terminals Out1, Out2, Out3, and Out4 to the light-emitting units 104, or vice versa. The direction of the driving current flow can be determined according to actual needs, and the embodiments of this disclosure do not limit this.

[0084] Although Figure 7 Only four light-emitting regions 102 are shown, arranged in a 2x2 row and 2x2 column configuration. However, this is only a partial screenshot of the light-emitting substrate 300. The light-emitting substrate 300 may include any suitable number of light-emitting regions 102, which may be arranged in M ​​rows and N columns, where M and N can be any positive integer greater than or equal to 1. This disclosure does not impose a specific limitation on the number of light-emitting regions 102 included in the light-emitting substrate 300.

[0085] As previously described, each column of light-emitting regions 001 includes a driving voltage signal line VLEDL, an addressing signal line ADDRL, a cascaded trace 111, a power signal line VccL, a common voltage signal line GNDL, and a feedback signal line FBL extending along the first direction D1. Their orthogonal projections onto the substrate 101 do not overlap. The function and arrangement of these signal lines are as described previously and will not be repeated here for the sake of simplicity. In addition, each column of light-emitting regions 001 also includes a data driving signal line DataL. Each data driving signal line DataL includes a main body portion and a second connection portion 119, with the main body portion of the data driving signal line DataL extending along the first direction D1. In each column of light-emitting areas 001, a data driving signal line DataL is connected to the data terminals Data of all driving circuits 103 within that column of light-emitting areas 001 via a second connection portion 119. The orthographic projections of the first and second columns of terminals of each driving circuit 103 on the substrate 101 are located on opposite sides of the orthographic projection of the data driving signal line DataL on the substrate 101. That is, the data driving signal line DataL is arranged within the area occupied by each driving circuit 103 and does not overlap with the first and second columns of terminals of each driving circuit 103. The orthographic projection of the data driving signal line DataL on the substrate 101 also does not overlap with the orthographic projection of the power signal line VccL within that column of light-emitting areas 001. By arranging the data driving signal line DataL within the area occupied by each driving circuit 103 in each column of light-emitting areas 001, wiring space can be saved, and overlap between the data driving signal line DataL and other signal lines can be avoided.

[0086] In each column of light-emitting areas 001, a data drive signal line DataL is configured to provide drive data to the data terminals Data of each drive circuit 103. Multiple different drive data can be loaded onto this data drive signal line DataL. Each drive circuit 103 can determine the corresponding drive data based on its address information and drive its connected light-emitting unit 104 according to its corresponding drive data. In this embodiment, drive data is transmitted to the data terminals Data of the drive circuit 103 via the data drive signal line DataL, thus avoiding the problem of too many pads and traces caused by using SPI (Serial Peripheral Interface) for data transmission, thereby simplifying the structure of the light-emitting substrate 300, external circuits, and drive circuits 103.

[0087] The spacing between the terminals of the driving circuit 103 of the light-emitting substrate 300 is typically determined by various factors (such as process limits, linewidth requirements between two rows of terminals, electrical design requirements, etc.), and the embodiments of this disclosure do not specifically limit this. For example, the spacing between the first and second rows of terminals can be 70–500 μm, and the spacing between any two adjacent rows of terminals in the five rows of terminals can be 70–500 μm. Figure 8As shown, in one example, the spacing S1 between the first and second column terminals is 210 μm, and the spacing S2 between any two adjacent rows of terminals is 90 μm. That is, the spacing between the first output terminal Out1 and the relay terminal Di_out, the spacing between the second output terminal Out2 and the data terminal Data, the spacing between the power supply terminal Vcc and the common voltage terminal GND, the spacing between the third output terminal Out3 and the common voltage terminal GND, and the spacing between the fourth output terminal Out4 and the address terminal Di_in are all S1, which is 210 μm; the spacing between the first output terminal Out1 and the second output terminal Out2, the spacing between the second output terminal Out2 and the power supply terminal Vcc, the spacing between the power supply terminal Vcc and the third output terminal Out3, the spacing between the third output terminal Out3 and the fourth output terminal Out4, the spacing between the relay terminal Di_out and the data terminal Data, the spacing between the data terminal Data and the common voltage terminal GND, the spacing between the common voltage terminal GND and adjacent common voltage terminals GND, and the spacing between the common voltage terminal GND and the address terminal Di_in are all S2, which is 90 μm. The ten terminals of the drive circuit 103 occupy essentially the same area and have essentially the same length and width. The width S3 of each terminal along the second direction D2 is 110 μm, and the length S4 of each terminal along the first direction D1 is 100 μm. The distance S5 between the fifth row terminals and the first side edge (i.e., the lower edge of the drive circuit 103) is 35 μm, meaning the distance S5 between the fourth output terminal Out4 and the address terminal Di_in and the lower edge of the drive circuit 103 is 35 μm. The distance S5 between the first row terminals and the second side edge (i.e., the upper edge of the drive circuit 103) is 35 μm, meaning the distance S5 between the first output terminal Out1 and the relay terminal Di_out and the upper edge of the drive circuit 103 is 35 μm. The distance S6 between the first column of terminals and the third side (i.e., the left edge of the driving circuit 103) is 25 μm, and the distance S6 between the second column of terminals and the fourth side (i.e., the right edge of the driving circuit 103) is 25 μm. Therefore, the length L of the driving circuit 103 along the first direction D1 is 930 μm, and the width W of the driving circuit 103 along the second direction D2 is 480 μm. Within each column of light-emitting area 001, the distance between the power signal line VccL and the first and second column terminals can be 10–100 μm, and the distance between the data driving signal line DataL and the first and second column terminals can also be 10–100 μm. In one example, the widths of the power signal line VccL and the data driving signal line DataL along the second direction D2 are both greater than or equal to 40 μm.

[0088] Figure 7 The driving circuit 103 shown includes four output terminals, so one driving circuit 103 can connect four light-emitting units 104 simultaneously, thereby significantly reducing the number of driving circuits 103 used and lowering the cost of the light-emitting substrate 300. Furthermore, the reduced number of driving circuits 103 also reduces the fabrication difficulty of the light-emitting substrate 300, lessens the impact of the bonding yield of the driving circuits 103 on the yield of the light-emitting substrate 300, and thus improves the yield of the light-emitting substrate 300. In addition, the terminals of the driving circuit 103 are arranged as described above, ensuring that the orthogonal projections of the driving voltage signal line VLEDL, address signal line ADDRL, cascaded trace 111, power signal line VccL, data driving signal line DataL, common voltage signal line GNDL, and feedback signal line FBL of the first conductive portion 105 onto the substrate 101 do not overlap. In addition, the orthographic projections of the driving voltage signal line VLEDL, the common voltage signal line GNDL, and the feedback signal line FBL of the first conductive portion 105 onto the substrate 101 do not overlap with the orthographic projections of the first pad 107 and the second pad 108 of the second conductive portion 106 onto the substrate 101. Therefore, short circuits or open circuits caused by the overlap of the first conductive portion 105 and the second conductive portion 106 can be completely avoided, thereby improving the light-emitting performance of the light-emitting substrate 300 and enhancing its light-emitting stability.

[0089] Below is a brief introduction. Figure 7 The working process of the light-emitting substrate 300 in the process.

[0090] When the driving circuit 103 starts working, it first provides power voltage to the power terminals Vcc of each driving circuit 103 in each column of light-emitting area 001 through the power signal line VccL to complete the initialization. In this way, the driving circuit 103 is in the power-on state.

[0091] Next, during the first time period, an address write operation is performed. That is, the ADDRL signal line inputs the address signal to the first-stage driver circuit 103 through the address terminal Di_in, thereby writing the address. Furthermore, the first-stage driver circuit 103 outputs a relay signal through the relay terminal Di_out. This relay signal is transmitted via cascaded trace 111 to the address terminal Di_in of the second-stage driver circuit 103, serving as the address signal for the second-stage driver circuit 103. This process continues until all driver circuits 103 have completed address information configuration.

[0092] Next, during the second time period, drive configuration is performed. In each column of light-emitting area 001, each data drive signal line DataL transmits drive data signals to the data terminal Data of each drive circuit 103 for initialization configuration.

[0093] Then, during the third time period, a drive voltage is supplied to the drive voltage signal line VLEDL, at which time the drive voltage transmitted on the drive voltage signal line VLEDL becomes high.

[0094] Next, during the fourth time period, each driving circuit 103 generates a driving control signal corresponding to its respective output terminal based on the received driving data. The driving control signal is used to control the current flowing through the corresponding output terminal. Thus, under the action of the driving voltage applied on the driving voltage signal line VLEDL, the driving circuit 103 can control the current flowing through the light-emitting unit 104, achieving the purpose of driving each connected light-emitting unit 104 according to the driving circuit 103.

[0095] Finally, during the fifth time period, the system shuts down, that is, the drive circuit 103 is de-energized, and the drive voltage provided by the drive voltage signal line VLEDL becomes low, and the light-emitting unit 104 stops emitting light.

[0096] Figure 7The illustrated light-emitting substrate 300 can achieve local dimming. Each driving circuit 103 includes four output terminals Out1, Out2, Out3, and Out4. The driving circuit 103 also includes a logic control module CTR and a control module CLM (not shown). The logic control module CTR includes four modulation modules: a first modulation module PWMM1, a second modulation module PWMM2, a third modulation module PWMM3, and a fourth modulation module PWMM4. The first output terminal Out1 to the fourth output terminal Out4 are connected one-to-one with the first modulation module PWMM1 to the fourth modulation module PWMM4. The control module CLM generates a first drive control signal, a second drive control signal, a third drive control signal, and a fourth drive control signal based on the drive data provided by the data drive signal line DataL, and transmits these signals to the first modulation module PWMM1, the second modulation module PWMM2, the third modulation module PWMM3, and the fourth modulation module PWMM4, respectively. Taking the first output terminal Out1 as an example, the first modulation module PWMM1 is electrically connected to the first output terminal Out1 and can be turned on or off under the control of the first drive control signal, so that the first output terminal Out1 is connected or disconnected from the common voltage signal line GNDL. When the first modulation module PWMM1 is turned on, the common voltage signal line GNDL, the first output terminal Out1, the light-emitting unit 104 electrically connected to the first output terminal Out1, and the drive voltage signal line VLEDL form a signal loop, and the light-emitting unit 104 works; when the first modulation module PWMM1 is turned off, the above signal loop is disconnected, and the light-emitting unit 104 does not work. In this way, the first modulation module PWMM1 can modulate the current flowing through the light-emitting unit 104 under the control of the first drive control signal, so that the current flowing through the light-emitting unit 104 presents a pulse width modulation signal. The first modulation module PWMM1 can modulate the duty cycle and other factors of the pulse width modulation signal flowing through the light-emitting unit 104 according to the first drive control signal, thereby controlling the working state of the light-emitting unit 104. When the light-emitting unit 104 includes an LED, by increasing the duty cycle of the pulse width modulation signal, the total light-emitting time of the LED within a display frame can be increased, thereby increasing the total light-emitting brightness of the LED within that display frame, and thus increasing the brightness of the light-emitting substrate 300 in that area. Conversely, by decreasing the duty cycle of the pulse width modulation signal, the total light-emitting time of the LED within a display frame can be decreased, thereby decreasing the total light-emitting brightness of the LED within that display frame, and thus decreasing the brightness of the light-emitting substrate 300 in that area. This achieves controllable brightness of the light-emitting unit 104 electrically connected to the first output terminal Out1. In a similar manner, the brightness of the light-emitting units 104 electrically connected to the second output terminal Out2, the third output terminal Out3, and the fourth output terminal Out4 can be controlled respectively, thereby achieving brightness control of each light-emitting unit 104 within the light-emitting substrate 300.

[0097] Figure 9 It shows Figure 7 A magnified view of a row of light-emitting regions 001 of the light-emitting substrate 300. Figure 10 It shows Figure 9 A further enlarged view within the dashed box. (See attached image.) Figure 9 and Figure 10 As shown, the first pad 107 is equipped with Figure 7 The driving circuit 103 is shown, and the first pad 107 is electrically connected to the driving circuit 103. The second pad 108 includes two sub-pads, which are electrically connected to, for example, the anode and cathode of the light-emitting unit 104, respectively. The first pad 107 has ten sub-pads at the positions corresponding to the ten terminals of the driving circuit 103. These are the first to fourth sub-pads for mounting and electrically connecting the four output terminals Out1 to Out4, the fifth sub-pad for mounting and electrically connecting the power supply terminal Vcc, the sixth and seventh sub-pads for mounting and electrically connecting the two common voltage terminals GND, the eighth sub-pad for mounting and electrically connecting the address terminal Di_in, the ninth sub-pad for mounting and electrically connecting the relay terminal Di_out, and the tenth sub-pad for mounting and electrically connecting the data terminal Data. The fourth sub-pad is connected to the two sub-pads of the second pad 108 via a trace to transmit the drive signal to the light-emitting unit 104 electrically connected to the fourth terminal Out4. The fifth sub-pad is connected to the power signal line VccL to transmit the power voltage signal on the power signal line VccL to the power terminal Vcc. The sixth and seventh sub-pads are connected to the common voltage signal line GNDL to transmit the common voltage signal on the common voltage signal line GNDL to the two common voltage terminals GND. The eighth sub-pad is connected to the address signal line ADDRL to transmit the address signal on the address signal line ADDRL to the address terminal Di_in. The ninth sub-pad is connected to the cascade trace to output a relay signal for a period of time as the address signal for the next stage drive circuit 103 cascaded with this drive circuit 103. The tenth sub-pad is connected to the data drive signal line DataL to transmit the data drive signal on the data drive signal line DataL to the data terminal Data.

[0098] In the light-emitting substrates provided in various embodiments of this disclosure, such as light-emitting substrate 100, light-emitting substrate 200, and light-emitting substrate 300, the spacing between each driving voltage signal line VLEDL and other adjacent signal lines needs to be greater than or equal to 0.2 mm. This is because the voltage on the driving voltage signal line VLEDL is relatively high (e.g., approximately 10–50 V), while the voltage of other signal lines adjacent to the driving voltage signal line VLEDL is usually relatively low. If the spacing is too small, it is easy to cause defects such as line breakdown. The spacing between other signal lines on the light-emitting substrate can be designed according to the process limits, and this disclosure does not specifically limit this. For example, if the process limit is 20 μm, the spacing between other signal lines on the light-emitting substrate can be 20 μm.

[0099] The materials of the first conductive portion 105 and the second conductive portion 106 can be any suitable conductive material, and this embodiment of the present disclosure does not specifically limit this. For example, the materials of the first conductive portion 105 and the second conductive portion 106 include copper. In one example, the first conductive portion 105 and the second conductive portion 106 can be a stack of Cu and CuNi. The side of the stack closest to the substrate 101 is a Cu layer, the thickness of which can be, for example, 2 μm, and Cu is a preferred material as an electrical signal transmission channel. The side of the stack furthest from the substrate 101 is a CuNi layer, the thickness of which can be, for example, 0.6 μm, and the CuNi layer can be used to protect the Cu layer and prevent oxidation of the low resistivity Cu layer surface. In another example, the first conductive portion 105 and the second conductive portion 106 are, for example, a stack of MoNb / Cu / MoNb, in which the side of the stack closest to the substrate 101 is a MoNb layer with a thickness of approximately [missing information]. The thickness is approximately [value missing], mainly used to improve the adhesion between the stacked layers and the substrate 101; the middle layer of the stack is a Cu layer, and Cu is a preferred material for electrical signal transmission channels; the side of the stack furthest from the substrate 101 is a MoNb layer, with a thickness of approximately [value missing]. The MoNb layer can be used to protect the intermediate Cu layer, preventing oxidation of the low resistivity intermediate Cu layer surface.

[0100] The light-emitting substrate described in any of the above embodiments may further include a plurality of flexible circuit boards 110. Figure 11A The connection relationships between multiple flexible circuit boards 110 and signal lines are shown. Figure 11B It shows Figure 11A The image shows a magnified view of region I, illustrating the connection between a flexible circuit board 110 and the signal lines. (See image for details.) Figure 11A and 11B As shown, the flexible circuit board 110 is disposed in the bonding area on the light-emitting substrate and is electrically connected to each signal line of the first conductive part 105 through the bonding electrode 120 of the bonding area. Figure 2In the example, the flexible circuit board 110 is electrically connected to the drive voltage signal line VLEDL, address signal line ADDRL, power signal line PwrL, common voltage signal line GNDL, feedback signal line FBL, and shielding ring GND ESD Ring of the first conductive portion 105. The flexible circuit board 110 provides the same signal to the common voltage signal line GNDL and the shielding ring GND ESD Ring. Figure 7 In the example, the flexible circuit board 110 is electrically connected to the drive voltage signal line VLEDL, address signal line ADDRL, power signal line VccL, drive data signal line DataL, common voltage signal line GNDL, feedback signal line FBL, and shielding ring GND ESD Ring of the first conductive part 105. The flexible circuit board 110 provides the same signal for the common voltage signal line GNDL and the shielding ring GND ESD Ring. Figure 11B Only the last row of light-emitting areas, i.e., the Mth row, is shown, which includes four columns of light-emitting areas: the kth column, the (k+1)th column, the (k+2)th column, and the (k+3)th column. The area occupied by each column is indicated by a dashed box. These four columns can be any four adjacent columns of light-emitting areas within the N columns. Each column includes a light-emitting unit 104. Each signal line (for simplicity, only the drive voltage signal line VLEDL and the common voltage signal line GNDL are shown in the figure) includes a straight portion 116 extending along the first direction D1 and a bent portion 117. The bent portion 117 is located within the fan-out area 114. Each signal line is connected to the bonding electrode 120 through its bent portion 117. The bonding electrode 120 is connected to the flexible circuit board 110, thereby achieving electrical connection between each signal line and the flexible circuit board 110. The width of the bent portion 117 of each signal line along the second direction D2 is smaller than the width of the adjacent two columns of light-emitting areas along the second direction D2. Taking the k-th column of light-emitting regions in Figure 11 as an example, the width T1 of the bent portion 117 of the driving voltage signal line VLEDL along the second direction D2 is smaller than the width T2 of the light-emitting regions of the two adjacent columns (e.g., the k-th and k+1-th columns) along the second direction D2. Within the fan-out region 114, the angle between the straight portion 116 and the bent portion 117 of each signal line is between 80° and 100°. In one example, the angle between the straight portion 116 and the bent portion 117 of each signal line is 90°. In related technologies, each flexible circuit board corresponds to 5 to 15 columns of light-emitting regions, that is, each flexible circuit board is electrically connected to the signal lines within 5 to 15 columns of light-emitting regions. In this application, by increasing the number of flexible circuit boards 110, each flexible circuit board corresponds to 3 to 8 columns of light-emitting regions 001, that is, each flexible circuit board 110 is electrically connected to the signal lines within 3 to 8 columns of light-emitting regions 001. For example, in Figure 11BIn the example, each flexible circuit board 110 is electrically connected to signal lines within four columns of light-emitting areas 001. By increasing the number of flexible circuit boards 110 and using a near-right-angle bend design for the signal lines, each signal line can extend substantially in a straight line to the bonding area and connect to the flexible circuit board 110. Compared to related technologies, the fan-out area 114 of the light-emitting substrate provided in this disclosure embodiment has a narrower width, thereby reducing the width of the lower border of the light-emitting substrate and facilitating the achievement of a narrow border.

[0101] Figure 12 Several alternative arrangements of each light-emitting unit 104 are shown as examples. Each light-emitting unit 104 includes a plurality of light-emitting elements connected to each other, the first end of which is electrically connected to the drive voltage signal line VLEDL, and the second end of which is electrically connected to the output terminal Out of the drive circuit 103. Figure 12 (a) shows that each light-emitting unit 104 includes four light-emitting elements connected in series with each other, and the four light-emitting elements are arranged in 1 column * 4 rows; Figure 12 (b) shows that each light-emitting unit 104 includes four light-emitting elements connected in series with each other, and the four light-emitting elements are arranged in 2 columns * 2 rows; Figure 12 (c) illustrates that each light-emitting unit 104 includes nine light-emitting elements connected in series, arranged in 3 columns * 3 rows. Of course, the multiple light-emitting elements in each light-emitting unit 104 are not limited to the above arrangement; they can be arranged in any suitable manner. In one example, the multiple light-emitting elements in each light-emitting unit 104 can be connected in parallel. In another example, the multiple light-emitting elements in each light-emitting unit 104 can be connected in a combination of series and parallel. The number of light-emitting elements included in each light-emitting unit 104 can be determined according to actual needs, such as the size of the light-emitting substrate and the required brightness. Each light-emitting element can be an organic light-emitting diode or an inorganic light-emitting diode. In some embodiments, each light-emitting element can be a sub-millimeter light-emitting diode (Mini LED) or a micro light-emitting diode (Micro LED). The size of a sub-millimeter light-emitting diode is, for example, in the range of 100 micrometers to 500 micrometers; the size of a micro light-emitting diode is, for example, less than 100 micrometers. The embodiments of this disclosure do not limit the type and size of the light-emitting elements in the light-emitting unit 104. By using sub-millimeter or micro-LEDs as the light-emitting elements of the light-emitting unit 104, and combining this with the independent controllability of the brightness of each light-emitting unit 104, high dynamic range (HDR) display can be achieved. When this type of light-emitting substrate is applied to a display device, the contrast of the display device can be significantly improved.

[0102] like Figure 13As shown, the light-emitting substrate provided in various embodiments of this disclosure may further include a buffer layer 112 and a first insulating layer 113. The buffer layer 112 is located between the layer containing the first conductive portion 105 and the second conductive portion 106 and the substrate 101, and the first insulating layer 113 is located on the side of the layer containing the first conductive portion 105 and the second conductive portion 106 away from the substrate 101. The buffer layer 112 can be used to reduce the stress on the substrate 101 during the fabrication of the first conductive portion 105 and the second conductive portion 106, thereby preventing the substrate 101 from bending and deforming; the buffer layer 112 can also prevent impurities in the substrate 101 from adversely affecting the conductivity of the first conductive portion 105 and the second conductive portion 106. The buffer layer 112 can be any suitable material, for example, SiN. The first insulating layer 113 can be used to protect the first conductive portion 105 and the second conductive portion 106 from oxidation and corrosion by water, oxygen, etc. in the environment. The material of the first insulating layer 113 can be an organic material, an inorganic material, or a combination of organic and inorganic materials. The first insulating layer 113 can be a single film layer or include multiple film layers. The substrate 101 can be any suitable substrate such as a plastic substrate, silicon substrate, ceramic substrate, glass substrate, or quartz substrate. The embodiments of this disclosure do not limit the material of the substrate 101. Optionally, the light-emitting substrate may further include a second insulating layer 115, which is located on the side of the first insulating layer 113 away from the substrate 101. The material of the second insulating layer 115 can be an organic material, an inorganic material, or a combination of organic and inorganic materials. The second insulating layer 115 can be a single film layer or may include multiple film layers.

[0103] According to another aspect of this disclosure, a backlight source is provided. Figure 14 A block diagram of a backlight 400 is shown, which includes a light-emitting substrate described in any of the preceding embodiments. The backlight 400 can serve as a backlight in a display device, providing a display light source for the display panel in the display device. Of course, the backlight 400 can also be used in any other device that requires a light source, and the embodiments of this disclosure do not specifically limit the application of the backlight 400.

[0104] Since the backlight 400 can have essentially the same technical effect as the light-emitting substrate described in the previous embodiments, for the sake of brevity, the technical effect of the backlight 400 will not be described again here.

[0105] According to another aspect of this disclosure, a display device is provided. Figure 15A block diagram of a display device 500 is shown, which includes a light-emitting substrate described in any of the preceding embodiments. In some embodiments, the display device 500 may be a liquid crystal display device, which includes a liquid crystal panel and a backlight disposed on the non-display side of the liquid crystal panel. The backlight includes a light-emitting substrate described in any of the preceding embodiments, and may be used, for example, to implement HDR dimming for display operation. The liquid crystal display device may have more uniform backlight brightness and better display contrast. The display device 500 may be any suitable display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, navigators, e-readers, and any other products or components with display functions.

[0106] Since the display device 500 can have essentially the same technical effects as the light-emitting substrates described in the preceding embodiments, for the sake of brevity, the technical effects of the display device 500 will not be described again here.

[0107] According to another aspect of this disclosure, a method for manufacturing a light-emitting substrate is provided. Figure 16 A flowchart of method 600 is shown, which is applicable to the light-emitting substrate described in any of the preceding embodiments. Reference Figure 2 , Figure 7 and Figure 16 Method 600 may include the following steps:

[0108] S601: Provides substrate 101.

[0109] S602: A conductive layer is formed on the substrate 101, and the conductive layer is patterned to simultaneously form a first conductive portion 105 and a second conductive portion 106 including a plurality of pads 107 and 108.

[0110] S603: A plurality of driving circuits 103 and a plurality of light-emitting units 104 are mounted on a substrate 101 to form a plurality of light-emitting regions 102 arranged in an array. Each light-emitting region 102 includes a driving circuit 103 and at least one light-emitting unit 104 connected to the driving circuit 103. A first conductive portion 105 is configured to transmit electrical signals to the driving circuit 103 and at least one light-emitting unit 104 in each light-emitting region 102.

[0111] The steps of method 600 will be described in more detail below with a specific example.

[0112] First, a substrate 101 is provided. The substrate 101 can be any suitable substrate such as a plastic substrate, a silicon substrate, a ceramic substrate, a glass substrate, or a quartz substrate. The embodiments of this disclosure do not limit the material of the substrate 101.

[0113] Then, a buffer layer 112 is formed on the substrate 101, for example, by magnetron sputtering. The buffer layer 112 can be used to reduce the stress on the substrate 101 during the subsequent fabrication of the first conductive portion 105 and the second conductive portion 106, thereby preventing the substrate 101 from bending or deforming; the buffer layer 112 can also prevent impurities in the substrate 101 from adversely affecting the conductivity of the subsequently formed first conductive portion 105 and second conductive portion 106. The buffer layer 112 can be any suitable material, for example, SiN.

[0114] Next, a conductive layer is formed on the substrate 101 by magnetron sputtering or electroplating. The conductive layer is patterned to simultaneously form a first conductive portion 105 and a second conductive portion 106. The first conductive portion 105 may include the drive voltage signal line VLEDL, the address signal line ADDRL, the cascaded trace 111, the power signal line VccL, the data drive signal line DataL, the common voltage signal line GNDL, the feedback signal line FBL, and an optional shielding ring GND ESD Ring, as described above. The second conductive portion 106 includes a first pad 107 and a second pad 108. The first pad 107 is used to mount the drive circuit 103, and the second pad 108 is used to mount the light-emitting unit 104. Since the thickness of a single magnetron sputtering operation is generally no more than 1 μm, multiple sputtering operations are typically required to form a conductive layer thicker than 1 μm. In one example, the formation process of the first conductive portion 105 and the second conductive portion 106 can be described as follows: First, a Cu layer with a thickness of, for example, 2 μm is formed on the buffer layer 112 to transmit various electrical signals; then, a CuNi layer with a thickness of, for example, 0.6 μm is formed on the Cu layer. This CuNi layer can be used to protect the Cu layer and prevent oxidation of the low resistivity Cu layer surface due to exposure. In another example, the formation process of the first conductive portion 105 and the second conductive portion 106 can be described as follows: First, a Cu layer with a thickness of approximately 1 μm is formed on the buffer layer 112. A MoNb layer is formed to improve the adhesion between the film and the substrate 101; then a Cu layer is formed on the MoNb layer to transmit various electrical signals; finally, a film with a thickness of approximately [missing information] is formed on the Cu layer. A MoNb layer is used to protect the intermediate Cu layer and prevent oxidation of the low-resistivity intermediate Cu layer surface. When forming the first conductive portion 105 and the second conductive portion 106 on the substrate 101 using electroplating, a seed layer can be formed using MoNiTi to increase the nucleation density of metal grains in subsequent electroplating processes. Then, a low-resistivity Cu layer is formed by electroplating, followed by an anti-oxidation layer, which can be made of MoNiTi. The conductive layer can be formed by processes such as cleaning, coating, baking, photolithography, development, hard baking, etching, and stripping to form the first conductive portion 105 and the second conductive portion 106. Fabricating the first conductive portion 105 and the second conductive portion 106 located in the same layer requires only two photomasks, compared to at least three photomasks required in related technologies to form conductive structures in different layers. This reduces the number of photomasks needed, simplifies the process, and lowers production costs.

[0115] Then, a first insulating layer 113 is formed on the side of the layer containing the first conductive portion 105 and the second conductive portion 106 away from the substrate 101 by magnetron sputtering. The first insulating layer 113 can be used to protect the first conductive portion 105 and the second conductive portion 106 from oxidation and corrosion by water, oxygen, etc. in the environment. The material of the first insulating layer 113 can be an organic material, an inorganic material, or a combination of organic and inorganic materials. The first insulating layer 113 can be a single film layer or can include multiple film layers.

[0116] Optionally, a second insulating film layer can be coated on the side of the first insulating layer 113 away from the substrate 101. The second insulating film layer 115 is formed by performing several processes such as curing, exposure, development, and etching. The material of the second insulating layer 115 can be an organic material, an inorganic material, or a combination of organic and inorganic materials. The second insulating layer 115 can be a single film layer or comprise multiple film layers. When the second insulating layer 115 is formed on the light-emitting substrate, the second insulating layer 115 and the first insulating layer 113 are etched to form multiple vias.

[0117] Finally, the light-emitting substrate is cut into a specified shape, and the driving circuit 103 and the light-emitting unit 104 are electrically connected to the first pad 107 and the second pad 108 of the second conductive part 103 through the aforementioned plurality of vias, so as to mount the driving circuit 103 and the light-emitting unit 104 on the corresponding pads. Each signal line of the first conductive part 105 is connected to the flexible circuit board 110 at the bonding area, thereby realizing the electrical connection between the driving circuit 103 and the flexible circuit board 110, and finally obtaining the desired light-emitting substrate.

[0118] The technical effects achieved by method 600 can be referred to the technical effects of the light-emitting substrate described in the previous embodiments. Therefore, for the sake of brevity, the technical effects of method 600 will not be described again here.

[0119] In the description of this disclosure, the terms "upper," "lower," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and are not intended to require this disclosure to be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0120] In the description of this specification, references to terms such as "one embodiment," "another embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples, without contradiction. Additionally, it should be noted that in this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0121] As those skilled in the art will understand, although the steps of the methods in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order unless the context clearly indicates otherwise. Additional or alternatively, multiple steps may be combined into a single step, and / or a single step may be broken down into multiple steps. Furthermore, other method steps may be inserted between steps. Inserted steps may represent improvements to the method described herein, or may be unrelated to the method. Moreover, a given step may not be fully completed before the next step begins.

[0122] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A light-emitting substrate, comprising: The substrate includes a plurality of light-emitting regions arranged in an array, each of the plurality of light-emitting regions including a driving circuit and at least one light-emitting unit connected to the driving circuit; A first conductive portion is located on the substrate and connected to the driving circuit and the at least one light-emitting unit in each light-emitting area; as well as The second conductive portion is located on the substrate and includes multiple pads. Wherein, the first conductive part and the second conductive part are located in the same layer, and The plurality of light-emitting regions are arranged in M ​​rows along a first direction and in N columns along a second direction intersecting the first direction, where M and N are both positive integers greater than or equal to 1. Each driving circuit includes a plurality of terminals arranged in an array, including address terminals, relay terminals, and power terminals. The driving circuits in each column of light-emitting regions are cascaded sequentially. The address terminal of the i-th stage driving circuit is located on the side of the i-th stage driving circuit closer to the (i-1)-th stage driving circuit, and the relay terminal of the i-th stage driving circuit is located on the side of the i-th stage driving circuit closer to the (i+1)-th stage driving circuit, where 1 < i < M and i is a positive integer. The address terminal is configured to receive address signals, the relay terminal is configured to output relay signals, and the power terminal is configured to receive power supply voltage signals.

2. The light-emitting substrate according to claim 1, wherein, The first conductive portion includes N driving voltage signal lines and N common voltage signal lines extending along the first direction. Each column of light-emitting areas includes one driving voltage signal line and one common voltage signal line. Within each column of light-emitting areas, the driving voltage signal line is connected to the first terminal of each light-emitting unit within that column of light-emitting areas, and the common voltage signal line is connected to each driving circuit within that column of light-emitting areas. Within each column of light-emitting areas, the driving voltage signal line, the light-emitting unit, the driving circuit, and the common voltage signal line are arranged sequentially along the second direction.

3. The light-emitting substrate according to claim 2, wherein, The driving voltage signal line, the light-emitting unit, the driving circuit, and the orthogonal projection of the common voltage signal line onto the substrate do not overlap with each other.

4. The light-emitting substrate according to claim 2, wherein, The plurality of terminals are arranged in at least two columns along the second direction. The plurality of terminals also includes at least one output terminal and at least one common voltage terminal, wherein the at least one output terminal and the at least one common voltage terminal are located in different columns of the plurality of terminals. In each column of light-emitting areas, at least one output terminal of each driving circuit is connected to the second end of at least one light-emitting unit connected to the driving circuit, and at least one common voltage terminal of each driving circuit is connected to the common voltage signal line in the column of light-emitting areas.

5. The light-emitting substrate according to claim 2, wherein, The extension direction of the first conductive part is parallel to the cascading direction of the driving circuit.

6. The light-emitting substrate according to claim 2, wherein, The multiple terminals of the driving circuit are arranged in a first column and a second column along the second direction. In each column of light-emitting area, the first column of terminals of the driving circuit is located on the side of the driving circuit adjacent to the driving voltage signal line, and the second column of terminals of the driving circuit is located on the side of the driving circuit adjacent to the common voltage signal line.

7. The light-emitting substrate according to claim 6, wherein, The first conductive portion further includes N power signal lines, with each column of light-emitting areas including one power signal line. Each power signal line includes a main body and a first connecting portion, and the main body of the power signal line extends along the first direction. In each column of light-emitting area, the power signal line is connected to the power terminal of each driving circuit in that column of light-emitting area through the first connection portion, and the orthographic projection of the first column terminal on the substrate and the orthographic projection of the second column terminal on the substrate are respectively located on both sides of the orthographic projection of the power signal line on the substrate.

8. The light-emitting substrate according to claim 7, wherein, The first conductive part further includes N address signal lines extending along the first direction. Each column of light-emitting area includes one address signal line. In each column of light-emitting area, the address signal line is connected to the address terminal of the first-stage driving circuit.

9. The light-emitting substrate according to claim 8, wherein, The first conductive portion further includes cascaded traces extending along the first direction, the cascaded traces being located between two adjacent cascaded driving circuits in each column of light-emitting areas, and the relay terminal of the i-th stage driving circuit being connected to the address terminal of the (i+1)-th stage driving circuit via the cascaded traces.

10. The light-emitting substrate according to claim 9, wherein, The first conductive portion further includes N feedback signal lines extending along the first direction. Each column of light-emitting areas includes one feedback signal line. Within each column of light-emitting areas, the feedback signal line is connected to the relay terminal of the last stage driving circuit, and the feedback signal line is at least partially located on the side of the common voltage signal line in that column of light-emitting areas away from the driving circuit.

11. The light-emitting substrate according to claim 10, wherein, The orthogonal projections of the drive voltage signal line, the addressing signal line, the cascaded trace, the power signal line, the common voltage signal line, and the feedback signal line onto the substrate do not overlap.

12. The light-emitting substrate according to claim 7, wherein, The plurality of terminals of the drive circuit also include a common voltage terminal and an output terminal. The first column of terminals includes the output terminal and the address terminal, and the second column of terminals includes the common voltage terminal and the power supply terminal.

13. The light-emitting substrate according to claim 12, wherein, The output terminal and the relay terminal of the driving circuit are the same terminal. The driving circuit is configured to output a relay signal through the output terminal during a first time period as the address signal of the next-level driving circuit cascaded with the driving circuit, and to provide a driving signal to the at least one light-emitting unit connected to the driving circuit through the output terminal during a second time period.

14. The light-emitting substrate according to claim 7, wherein, The plurality of terminals of the drive circuit also include data terminals, which are located in different columns of the plurality of terminals as the power supply terminals.

15. The light-emitting substrate according to claim 14, wherein, The driving circuit's plurality of terminals further includes output terminals and common voltage terminals, wherein there are multiple output terminals and at least one common voltage terminal. The first column of terminals includes the power supply terminal and a plurality of the output terminals, and the second column of terminals includes the address terminal, the relay terminal, the data terminal, and at least one of the common voltage terminals.

16. The light-emitting substrate according to claim 15, wherein, The first conductive portion further includes N data driving signal lines. Each column of light-emitting areas includes one data driving signal line. Each data driving signal line includes a main body and a second connecting portion. The main body of the data driving signal line extends along the first direction. In each column of light-emitting area, the data driving signal line is connected to the data terminal of each driving circuit in that column of light-emitting area through the second connection portion, and the orthographic projection of the first column terminal on the substrate and the orthographic projection of the second column terminal on the substrate are respectively located on both sides of the orthographic projection of the data driving signal line on the substrate, and the orthographic projection of the data driving signal line on the substrate does not overlap with the orthographic projection of the power signal line on the substrate.

17. The light-emitting substrate according to claim 15, wherein, The plurality of output terminals of the driving circuit are connected one-to-one with the second terminals of the plurality of light-emitting units connected to the driving circuit. The driving circuit is configured to output a relay signal through the relay terminal during a first time period as the address signal of the next-level driving circuit cascaded with the driving circuit, and to provide driving signals to the plurality of light-emitting units through the plurality of output terminals during a second time period.

18. The light-emitting substrate according to any one of claims 2-11, wherein, The spacing between the driving voltage signal line and other adjacent signal lines is greater than or equal to 0.2 mm.

19. The light-emitting substrate according to any one of claims 2-11, further comprising a plurality of flexible circuit boards and a fan-out region. in, Each signal line of the first conductive portion includes a straight portion and a bent portion. The bent portion of each signal line is located within the fan-out area, and each signal line is connected to the plurality of flexible circuit boards through its bent portion. In this case, the width of the bent portion of each signal line along the second direction is less than the width of the adjacent two columns of light-emitting areas along the second direction.

20. The light-emitting substrate according to claim 19, wherein, The angle between the straight portion and the bent portion of each signal line is 80° to 100°.

21. The light-emitting substrate according to any one of claims 2-11, wherein, The materials of the first conductive part and the second conductive part include copper.

22. The light-emitting substrate according to any one of claims 2-11, wherein, Each light-emitting unit includes multiple light-emitting elements connected to each other, each of which includes a sub-millimeter light-emitting diode or a micro light-emitting diode.

23. The light-emitting substrate according to any one of claims 2-11, further comprising a shielding ring, wherein, The shielding ring surrounds the periphery of the plurality of light-emitting areas, and the electrical signal received by the shielding ring is the same as the electrical signal received by the common voltage signal line.

24. The light-emitting substrate according to any one of claims 2-11, further comprising a buffer layer and an insulating layer, wherein, The buffer layer is located between the layer containing the first conductive portion and the second conductive portion and the substrate. The insulating layer is located on the side of the layer containing the first conductive portion and the second conductive portion away from the substrate.

25. A backlight source comprising a light-emitting substrate according to any one of claims 1-24.

26. A display device comprising a light-emitting substrate according to any one of claims 1-24.

27. A method for manufacturing a light-emitting substrate, comprising: Provide substrate; A conductive layer is formed on the substrate, and the conductive layer is patterned to simultaneously form a first conductive portion and a second conductive portion including multiple pads; as well as Multiple driving circuits and multiple light-emitting units are mounted on the substrate to form multiple light-emitting regions arranged in an array. Each of the multiple light-emitting regions includes a driving circuit and at least one light-emitting unit connected to the driving circuit. Wherein, the first conductive part is connected to the driving circuit and the at least one light-emitting unit in each light-emitting area, and The plurality of light-emitting regions are arranged in M ​​rows along a first direction and in N columns along a second direction intersecting the first direction, where M and N are both positive integers greater than or equal to 1. Each driving circuit includes a plurality of terminals arranged in an array, including address terminals, relay terminals, and power terminals. The driving circuits in each column of light-emitting regions are cascaded sequentially. The address terminal of the i-th stage driving circuit is located on the side of the i-th stage driving circuit closer to the (i-1)-th stage driving circuit, and the relay terminal of the i-th stage driving circuit is located on the side of the i-th stage driving circuit closer to the (i+1)-th stage driving circuit, where 1 < i < M and i is a positive integer. The address terminal is configured to receive address signals, the relay terminal is configured to output relay signals, and the power terminal is configured to receive power supply voltage signals.

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