A single-photon avalanche diode quenching and reset circuit with fast response

Abstract

The present invention provides a single-photon avalanche diode quenching and reset circuit with fast response, including an SPAD, a load resistor, an NMOS transistor M N2 , an avalanche detection inverter, a first PMOS transistor M P1 , a second PMOS transistor M P2 , a third PMOS transistor M P3 , a fourth PMOS transistor M P4 , a fifth PMOS transistor M P5 , a quenching signal level shifter, a reset signal level shifter, a delay module, a monostable circuit, and a low-voltage branch shutdown module. The present invention provides a single-photon avalanche diode quenching and reset circuit with fast response, which solves the problem that the existing fast-response active quenching and reset circuit cannot simultaneously meet the requirement of the high additional bias voltage required by a high-sensitivity SPAD and maintain the fast-response characteristic.

Description

Technical Field

[0001] The present invention relates to the technical field of optical signal receiving circuits, and more specifically, to a single-photon avalanche diode quenching and resetting circuit with fast response. Background Art

[0002] Single-photon avalanche diodes (SPADs) have important potential applications in fields such as medical imaging, lidar, and optical communication. This is because SPADs operating in Geiger mode can generate large current pulses from weak optical signals at the single-photon level, exhibiting very high photoelectric conversion gain. To ensure its stable operation in Geiger mode, a quenching circuit is required to quench the triggered SPAD avalanche current, and a resetting circuit is needed to reset the SPAD to its initial bias state to detect the next photon event.

[0003] The passive quenching and resetting circuit connects a large resistor in series to one end of the SPAD. However, the relatively slow quenching reaction speed and very long reset time limit its application in high-speed detection systems. The active quenching and resetting circuit actively charges and discharges the node where the SPAD is connected to the front-end circuit, thereby effectively shortening the dead time. However, the reduction of the dead time is likely to cause an increase in the probability of afterpulses. In addition, the time interval between the start and end of the SPAD avalanche current has a strong correlation with the amount of avalanche charge generated. The shorter the response time of the front-end quenching circuit to the avalanche current, the more beneficial it is to reduce the probability of afterpulses. Therefore, it is a major development trend to adopt an active quenching and resetting circuit in the SPAD front-end circuit and minimize the quenching response time.

[0004] The active quenching and resetting circuit with fast response usually uses an inverter or MOS transistor powered by a logic module to detect the avalanche current, because the detection threshold of the detection module is directly related to the supply voltage. On the other hand, a higher SPAD photon detection probability requires a larger additional bias voltage. However, the swing of the quenching signal is limited by the low supply voltage, and the output voltage of the quenching switch MOS driven by it can only be limited to a maximum of the supply voltage of the logic module. With the reduction of the CMOS process technology, the supply voltage of the logic module further decreases, and the quenching voltage amplitude of the existing fast-response active quenching and resetting circuit for SPAD also decreases accordingly, unable to meet the requirements of the high additional bias voltage required by high-sensitivity SPADs and maintain the fast-response characteristics at the same time. Summary of the Invention

[0005] In order to overcome the technical defect that the existing fast-response active quenching and resetting circuit cannot meet the requirements of the high additional bias voltage required by high-sensitivity SPADs and maintain the fast-response characteristics at the same time, the present invention provides a single-photon avalanche diode quenching and resetting circuit with fast response.

[0006] To solve the above technical problems, the technical solution of the present invention is as follows:

[0007] A single-photon avalanche diode quenching and reset circuit with fast response, comprising an SPAD, a load resistor, an NMOS transistor M N2 , an avalanche detection inverter, a first PMOS transistor M P1 , a second PMOS transistor M P2 , a third PMOS transistor M P3 , a fourth PMOS transistor M P4 , a fifth PMOS transistor M P5 , a quenching signal level shifter, a reset signal level shifter, a delay module, a monostable circuit, and a low-voltage branch shutdown module;

[0008] The cathode of the SPAD is connected to an externally input reverse bias voltage, the anode is grounded via the load resistor, and the anode is also respectively connected to the input end of the avalanche detection inverter, the drain of the NMOS transistor M N2 , the drain of the second PMOS transistor M P2 , and the drain of the fourth PMOS transistor M P4 ; the output end of the avalanche detection inverter is respectively connected to the input end of the delay module and the gate of the second PMOS transistor M P2 , and is connected to the gate of the fourth PMOS transistor M P4 via the quenching signal level shifter; the first output end of the delay module is connected to the input end of the monostable circuit; the output end of the monostable circuit is connected to the input end of the low-voltage branch shutdown module, and is respectively connected to the gate of the NMOS transistor M N2 and the gate of the third PMOS transistor M P3 via the reset signal level shifter; the source of the first PMOS transistor M P1 is connected to an externally input low power supply voltage, the drain is connected to the source of the second PMOS transistor M P2 , and the gate is connected to the first output end of the low-voltage branch shutdown module; the source of the third PMOS transistor M P3 is connected to an externally input high power supply voltage, and the drain is connected to the source of the fourth PMOS transistor M P4 ; the source of the fifth PMOS transistor M P5 is connected to the low power supply voltage, the drain is connected to the input end of the delay module, and the gate is connected to the second output end of the low-voltage branch shutdown module; the third output end of the low-voltage branch shutdown module is used as the output end of the single-photon avalanche diode quenching and reset circuit.

[0009] In the above solution, when the avalanche detection inverter detects an avalanche current, the first step is to quickly turn on the circuit composed of the first PMOS transistor M P1 , the second PMOS transistor M P2The low - power - supply - voltage quenching branch composed of... performs low - voltage quenching. In the second step, after the quenching signal level shifter boosts the voltage, the high - power - supply - voltage quenching branch composed of the third PMOS transistor M P3 and the fourth PMOS transistor M P4 is turned on and the low - power - supply - voltage quenching branch is disconnected to perform high - voltage quenching, ultimately achieving compatibility with the requirement for a large additional bias voltage of the SPAD while ensuring a fast quenching response speed.

[0010] Preferably, the low - voltage branch closing module includes an inverter and a NAND gate;

[0011] The input terminal of the inverter serves as the input terminal of the low - voltage branch closing module and receives the output terminal of the monostable circuit. The output terminal is respectively connected to the first input terminal of the NAND gate, serves as the first output terminal of the low - voltage branch closing module and is connected to the gate of the first PMOS transistor M P1 , and serves as the third output terminal of the low - voltage branch closing module. The output terminal of the NAND gate serves as the second output terminal of the low - voltage branch closing module and is connected to the gate of the fifth PMOS transistor M P5 , and the second input terminal is connected to the second output terminal of the delay module.

[0012] Preferably, the load resistor is the NMOS transistor M N1 ; the drain of the NMOS transistor M N1 is connected to the anode of the SPAD, the source is grounded, and the gate is connected to the externally input DC voltage Vb.

[0013] Preferably, the avalanche detection inverter is powered by a low - power - supply voltage, has a low flip - flop threshold, and is used to convert the avalanche signal into a digital negative pulse output.

[0014] Preferably, the delay module is a non - inverting delay module.

[0015] Preferably, in the initial state, the anode of the SPAD is connected to the ground via the NMOS transistor M N1 , the second PMOS transistor M P2 , the fourth PMOS transistor M P4 and the NMOS transistor M N2 remain off, and the first PMOS transistor M P1 and the fifth PMOS transistor M P5 remain on.

[0016] Preferably, the quenching process of the single - photon avalanche diode quenching and reset circuit includes a low - voltage quenching stage and a high - voltage quenching stage.

[0017] Preferably, the low - voltage quenching stage is specifically: when the optical signal excites the SPAD and causes it to avalanche breakdown, the SPAD outputs a large - current pulse via the NMOS transistor M N1Converted into a voltage pulse, the SPAD anode level starts to rise. The avalanche signal detection inverter converts the avalanche signal into a digital negative pulse output, that is, a low-voltage quenching signal. The low-voltage quenching signal directly turns on the second PMOS transistor M P2 , at this time the first PMOS transistor M P1 , the second PMOS transistor M P2 are both turned on to form a low-power supply voltage quenching branch, and rapid low-voltage quenching is performed to accelerate the pulling up of the SPAD anode potential.

[0018] Preferably, the high-voltage quenching stage is specifically: after accelerating the pulling up of the SPAD anode potential in the low-voltage quenching stage, the output of the avalanche signal detection inverter is boosted by a quenching signal level shifter, and after an unavoidable delay, the fourth PMOS transistor M P4 is turned on. At this time, the third PMOS transistor M P3 , the fourth PMOS transistor M P4 are both turned on to form a high-power supply voltage quenching branch, and the low-power supply voltage quenching branch is disconnected to perform high-voltage quenching.

[0019] Preferably, the monostable circuit is a falling-edge triggered monostable circuit, and its output positive pulse is a reset signal.

[0020] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0021] The present invention provides a single-photon avalanche diode quenching and reset circuit with fast response. When the avalanche detection inverter detects an avalanche current, the first step is to quickly turn on the low-power supply voltage quenching branch composed of the first PMOS transistor M P1 , the second PMOS transistor M P2 to perform low-voltage quenching. The second step is to turn on the high-power supply voltage quenching branch composed of the third PMOS transistor M P3 , the fourth PMOS transistor M P4 after boosting by the quenching signal level shifter and disconnect the low-power supply voltage quenching branch to perform high-voltage quenching, ultimately achieving compatibility with the requirement for a large additional bias voltage of the SPAD while ensuring a fast quenching response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is the circuit schematic diagram of one embodiment of the present invention;

[0023] Figure 2 is the circuit schematic diagram of another embodiment of the present invention;

[0024] Figure 3 is the node transient voltage schematic diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The accompanying drawings are only for illustrative purposes and should not be construed as limiting the present patent;

[0026] To better illustrate this embodiment, some components in the accompanying drawings are omitted, enlarged or reduced, which does not represent the size of the actual product;

[0027] For those skilled in the art, it is understandable that some well-known structures and their descriptions in the accompanying drawings may be omitted.

[0028] The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0029] Embodiment 1

[0030] As Figure 1 shown, a single-photon avalanche diode quenching and reset circuit with fast response includes an SPAD, a load resistor, an NMOS transistor M N2 , an avalanche detection inverter, a first PMOS transistor M P1 , a second PMOS transistor M P2 , a third PMOS transistor M P3 , a fourth PMOS transistor M P4 , a fifth PMOS transistor M P5 , a quenching signal level shifter, a reset signal level shifter, a delay module, a monostable circuit, and a low-voltage branch shutdown module;

[0031] The cathode of the SPAD is connected to an externally input reverse bias voltage, the anode is grounded via the load resistor, and the anode is also respectively connected to the input terminal of the avalanche detection inverter, the drain of the NMOS transistor M N2 , the drain of the second PMOS transistor M P2 , and the drain of the fourth PMOS transistor M P4 ; the output terminal of the avalanche detection inverter is respectively connected to the input terminal of the delay module and the gate of the second PMOS transistor M P2 , and is connected to the gate of the fourth PMOS transistor M P4 via the quenching signal level shifter; the first output terminal of the delay module is connected to the input terminal of the monostable circuit; the output terminal of the monostable circuit is connected to the input terminal of the low-voltage branch shutdown module, and is respectively connected to the gate of the NMOS transistor M N2 and the gate of the third PMOS transistor M P3 via the reset signal level shifter; the source of the first PMOS transistor M P1 is connected to an externally input low power supply voltage, the drain is connected to the source of the second PMOS transistor M P2 , and the gate is connected to the first output terminal of the low-voltage branch shutdown module; the source of the third PMOS transistor M P3 is connected to an externally input high power supply voltage, the drain is connected to the source of the fourth PMOS transistor M P4the source electrode of; the fifth PMOS transistor M P5 The source electrode of is connected to the low power supply voltage, the drain electrode is connected to the input end of the delay module, and the gate electrode is connected to the second output end of the low-voltage branch closing module; the third output end of the low-voltage branch closing module serves as the output end of the single-photon avalanche diode quenching and reset circuit.

[0032] In the specific implementation process, when the avalanche detection inverter detects the avalanche current, the first step is to quickly turn on the low power supply voltage quenching branch composed of the first PMOS transistor M P1 and the second PMOS transistor M P2 for low-voltage quenching. The second step is to turn on the high power supply voltage quenching branch composed of the third PMOS transistor M P3 and the fourth PMOS transistor M P4 after boosting through the quenching signal level shifter, and disconnect the low power supply voltage quenching branch for high-voltage quenching, ultimately achieving compatibility with the requirement for a large additional bias voltage of the SPAD while ensuring a fast quenching response speed.

[0033] Embodiment 2

[0034] As Figures 2-3 shown, a single-photon avalanche diode quenching and reset circuit with fast response includes an SPAD, a load resistor, an NMOS transistor M N2 , an avalanche detection inverter, a first PMOS transistor M P1 , a second PMOS transistor M P2 , a third PMOS transistor M P3 , a fourth PMOS transistor M P4 , a fifth PMOS transistor M P5 , a quenching signal level shifter, a reset signal level shifter, a delay module, a monostable circuit, and a low-voltage branch closing module;

[0035] The cathode of the SPAD is connected to the externally input reverse bias voltage, the anode is grounded via the load resistor, and the anode is also respectively connected to the input end of the avalanche detection inverter, the drain electrode of the NMOS transistor M N2 , the drain electrode of the second PMOS transistor M P2 , and the drain electrode of the fourth PMOS transistor M P4 ; the output end of the avalanche detection inverter is respectively connected to the input end of the delay module and the gate electrode of the second PMOS transistor M P2 , and is connected to the gate electrode of the fourth PMOS transistor M P4 via the quenching signal level shifter; the first output end of the delay module is connected to the input end of the monostable circuit; the output end of the monostable circuit is connected to the input end of the low-voltage branch closing module, and is respectively connected to the gate electrode of the NMOS transistor M N2 and the gate electrode of the third PMOS transistor M P3 via the reset signal level shifter.The gate of; the first PMOS transistor M P1 The source of is connected to the low power supply voltage input externally, and the drain is connected to the second PMOS transistor M P2 The source of, and the gate is connected to the first output terminal of the low-voltage branch closing module; the third PMOS transistor M P3 The source of is connected to the high power supply voltage input externally, and the drain is connected to the fourth PMOS transistor M P4 The source of; the fifth PMOS transistor M P5 The source of is connected to the low power supply voltage, the drain is connected to the input terminal of the delay module, and the gate is connected to the second output terminal of the low-voltage branch closing module; the third output terminal of the low-voltage branch closing module serves as the output terminal of the single-photon avalanche diode quenching and reset circuit.

[0036] More specifically, the low-voltage branch closing module includes an inverter and a NAND gate;

[0037] The input terminal of the inverter serves as the input terminal of the low-voltage branch closing module and is connected to the output terminal of the monostable circuit. The output terminal is respectively connected to the first input terminal of the NAND gate, serves as the first output terminal of the low-voltage branch closing module and is connected to the gate of the first PMOS transistor M P1 The gate of, and serves as the third output terminal of the low-voltage branch closing module; the output terminal of the NAND gate serves as the second output terminal of the low-voltage branch closing module and is connected to the gate of the fifth PMOS transistor M P5 The gate of, and the second input terminal is connected to the second output terminal of the delay module.

[0038] Embodiment 3

[0039] A single-photon avalanche diode quenching and reset circuit with fast response, including an SPAD, a load resistor, an NMOS transistor M N2 , an avalanche detection inverter, a first PMOS transistor M P1 , a second PMOS transistor M P2 , a third PMOS transistor M P3 , a fourth PMOS transistor M P4 , a fifth PMOS transistor M P5 , a quenching signal level shifter, a reset signal level shifter, a delay module, a monostable circuit and a low-voltage branch closing module;

[0040] The cathode of the SPAD is connected to the reverse bias voltage input externally, the anode is grounded via the load resistor, and the anode is also respectively connected to the input terminal of the avalanche detection inverter, the drain of the NMOS transistor M N2 , the drain of the second PMOS transistor M P2 , and the drain of the fourth PMOS transistor M P4 ; the output terminal of the avalanche detection inverter is respectively connected to the input terminal of the delay module and the gate of the second PMOS transistor M P2 , and is connected to the fourth PMOS transistor M via the quenching signal level shifterP4 The gate; the first output terminal of the delay module is connected to the input terminal of the monostable circuit; the output terminal of the monostable circuit is connected to the input terminal of the low-voltage branch closing module, and is respectively connected to the gate of the NMOS transistor M N2 via the reset signal level shifter and the gate of the third PMOS transistor M P3 ; the source of the first PMOS transistor M P1 is connected to the externally input low power supply voltage, the drain is connected to the source of the second PMOS transistor M P2 ; the gate is connected to the first output terminal of the low-voltage branch closing module; the source of the third PMOS transistor M P3 is connected to the externally input high power supply voltage, the drain is connected to the source of the fourth PMOS transistor M P4 ; the source of the fifth PMOS transistor M P5 is connected to the low power supply voltage, the drain is connected to the input terminal of the delay module, and the gate is connected to the second output terminal of the low-voltage branch closing module; the third output terminal of the low-voltage branch closing module serves as the output terminal of the single-photon avalanche diode quenching and reset circuit.

[0041] More specifically, the low-voltage branch closing module includes an inverter and a NAND gate;

[0042] The input terminal of the inverter serves as the input terminal of the low-voltage branch closing module and is connected to the output terminal of the monostable circuit, and the output terminal is respectively connected to the first input terminal of the NAND gate, serves as the first output terminal of the low-voltage branch closing module and is connected to the gate of the first PMOS transistor M P1 and serves as the third output terminal of the low-voltage branch closing module; the output terminal of the NAND gate serves as the second output terminal of the low-voltage branch closing module and is connected to the gate of the fifth PMOS transistor M P5 , and the second input terminal is connected to the second output terminal of the delay module.

[0043] More specifically, the load resistor is the NMOS transistor M N1 ; the drain of the NMOS transistor M N1 is connected to the anode of the SPAD, the source is grounded, and the gate is connected to the externally input DC voltage Vb.

[0044] More specifically, the avalanche detection inverter is powered by a low power supply voltage, has a low switching threshold, and is used to convert the avalanche signal into a digital negative pulse output.

[0045] More specifically, the delay module is a non-inverting delay module.

[0046] In the specific implementation process, the non-inverting delay module can set different delays for the rising and falling edges.

[0047] Embodiment 4

[0048] A single-photon avalanche diode quenching and reset circuit with fast response, including an SPAD, a load resistor, an NMOS transistor M N2 , an avalanche detection inverter, a first PMOS transistor M P1 , a second PMOS transistor M P2 , a third PMOS transistor M P3 , a fourth PMOS transistor M P4 , a fifth PMOS transistor M P5 , a quenching signal level shifter, a reset signal level shifter, a delay module, a monostable circuit, and a low-voltage branch shutdown module;

[0049] The cathode of the SPAD is connected to an externally input reverse bias voltage, the anode is grounded via the load resistor, and the anode is also respectively connected to the input end of the avalanche detection inverter, the drain of the NMOS transistor M N2 , the drain of the second PMOS transistor M P2 , and the drain of the fourth PMOS transistor M P4 ; The output end of the avalanche detection inverter is respectively connected to the input end of the delay module and the gate of the second PMOS transistor M P2 , and is connected to the gate of the fourth PMOS transistor M P4 via the quenching signal level shifter; The first output end of the delay module is connected to the input end of the monostable circuit; The output end of the monostable circuit is connected to the input end of the low-voltage branch shutdown module, and is respectively connected to the gate of the NMOS transistor M N2 and the gate of the third PMOS transistor M P3 via the reset signal level shifter; The source of the first PMOS transistor M P1 is connected to an externally input low power supply voltage, the drain is connected to the source of the second PMOS transistor M P2 , and the gate is connected to the first output end of the low-voltage branch shutdown module; The source of the third PMOS transistor M P3 is connected to an externally input high power supply voltage, and the drain is connected to the source of the fourth PMOS transistor M P4 ; The source of the fifth PMOS transistor M P5 is connected to the low power supply voltage, the drain is connected to the input end of the delay module, and the gate is connected to the second output end of the low-voltage branch shutdown module; The third output end of the low-voltage branch shutdown module is used as the output end of the single-photon avalanche diode quenching and reset circuit.

[0050] More specifically, the low-voltage branch shutdown module includes an inverter and a NAND gate;

[0051] The input end of the inverter is used as the input end of the low-voltage branch shutdown module to connect to the output end of the monostable circuit, the output end is respectively connected to the first input end of the NAND gate, and is used as the first output end of the low-voltage branch shutdown module to connect to the first PMOS transistor M P1The gate, as the third output terminal of the low-voltage branch closing module; the output terminal of the NAND gate is used as the second output terminal of the low-voltage branch closing module and is connected to the gate of the fifth PMOS transistor M P5 The second input terminal is connected to the second output terminal of the delay module.

[0052] More specifically, the load resistor is the NMOS transistor M N1 ; the drain of the NMOS transistor M N1 is connected to the anode of the SPAD, the source is grounded, and the gate is connected to the externally input DC voltage Vb.

[0053] More specifically, the avalanche detection inverter is powered by a low supply voltage and has a low switching threshold, and is used to convert the avalanche signal into a digital negative pulse output.

[0054] More specifically, the delay module is a non-inverting delay module.

[0055] In the specific implementation process, the non-inverting delay module can set different delays for the rising and falling edges.

[0056] More specifically, in the initial state, the anode of the SPAD is connected to the ground via the NMOS transistor M N1 , the second PMOS transistor M P2 , the fourth PMOS transistor M P4 and the NMOS transistor M N2 remain off, and the first PMOS transistor M P1 and the fifth PMOS transistor M P5 remain on.

[0057] More specifically, the quenching process of the single-photon avalanche diode quenching and reset circuit includes a low-voltage quenching stage and a high-voltage quenching stage.

[0058] More specifically, the low-voltage quenching stage is specifically as follows: when the optical signal excites the SPAD and causes it to avalanche breakdown, the SPAD outputs a large current pulse, which is converted into a voltage pulse via the NMOS transistor M N1 , the anode level of the SPAD begins to rise, and the avalanche signal detection inverter converts the avalanche signal into a digital negative pulse output, that is, the low-voltage quenching signal. The low-voltage quenching signal directly turns on the second PMOS transistor M P2 . At this time, the first PMOS transistor M P1 and the second PMOS transistor M P2 are both turned on to form a low-supply-voltage quenching branch, and rapid low-voltage quenching is performed to accelerate the pulling up of the SPAD anode potential.

[0059] More specifically, the high-voltage quenching stage is specifically as follows: after accelerating the pulling up of the SPAD anode potential in the low-voltage quenching stage, the output of the avalanche signal detection inverter is boosted by the quenching signal level shifter, and the fourth PMOS transistor M is turned on after an unavoidable delayP4 , at this time, the third PMOS transistor M P3 and the fourth PMOS transistor M P4 are both turned on to form a high power supply voltage quenching branch, and the low power supply voltage quenching branch is disconnected for high voltage quenching.

[0060] More specifically, the monostable circuit is a falling edge triggered monostable circuit, and the positive pulse output by it is a reset signal.

[0061] In the specific implementation process, the SPAD with a high reverse bias voltage applied to the cathode is biased in the Geiger mode. The anode of the SPAD is connected to a load resistor (NMOS transistor M N1 ) to achieve the conversion of current to voltage; the avalanche detection inverter (composed of high breakdown voltage transistors) powered by the low power supply voltage has a very low detection threshold, and it converts the avalanche signal into a digital negative pulse output, that is, the quenching signal (low voltage); the low power supply voltage quenching branch composed of the first PMOS transistor M P1 and the second PMOS transistor M P2 is controlled by the quenching signal (low voltage). The quenching signal (low voltage) first turns on the second PMOS transistor M P2 (at this time, the first PMOS transistor M P1 remains on) for rapid quenching, pulling up the anode potential of the SPAD and reducing the voltage across the SPAD; after the quenching signal level shifter boosts the voltage and an inevitable delay, the quenching signal (high voltage) turns on the high power supply voltage quenching branch composed of the third PMOS transistor M P3 and the fourth PMOS transistor M P4 and disconnects the low power supply voltage quenching branch after a preset short delay, that is, turns off the first PMOS transistor M P1 , achieving a two-step active quenching effect in the case of quickly responding to the avalanche signal. Both the quenching signal level shifter and the reset signal level shifter are used to boost the digital pulse signal with a low power supply voltage swing to a pulse with a high power supply voltage swing, but they will introduce inevitable delays themselves. The delay module is used to delay the quenching signal for a period and then output it to the falling edge triggered monostable circuit. The positive pulse generated by the monostable circuit is used to reset the anode of the SPAD and turn off the low power supply voltage quenching branch and the high power supply voltage quenching branch. After the intermediate node of the delay module is NANDed with the reset signal that has not been boosted (i.e., the output signal of the monostable circuit) through the low voltage branch closing module, the low voltage branch closing signal is output to the gate of the first PMOS transistor M P1 to ensure that the first PMOS transistor M P1 is turned off before the anode potential of the SPAD is higher than the low power supply voltage during the quenching process and is turned off during the reset process to prevent short circuits between the high and low power supplies and between the power supply and ground.

[0062] In the initial state, the anode of the SPAD passes through the NMOS transistor MN1 Connected to the ground, the quenching signal and the reset signal are both inoperative, and the corresponding second PMOS transistor M P2 , the fourth PMOS transistor M P4 and the NMOS transistor M N2 remain off, that is, the low-power-voltage quenching branch, the high-power-voltage quenching branch, and the reset branch are all off. However, the first PMOS transistor M P1 and the third PMOS transistor M P3 on the quenching branch remain on. Their function is to cut off the quenching branch with higher priority when the reset signal or the low-voltage branch off signal starts to work, ensuring no short circuit during the reset or high-voltage quenching process. When the optical signal excites the SPAD and causes it to avalanche breakdown, the SPAD outputs a large current pulse, which is converted into a voltage pulse via the NMOS transistor M N1 , and the anode level of the SPAD starts to rise. This stage is called the passive quenching stage, and the node voltage rise is provided by the SPAD avalanche current. This stage needs to be switched to active quenching as soon as possible to reduce the SPAD avalanche charge amount and thereby reduce the probability of afterpulses. The avalanche signal detection inverter powered by the low power voltage is set at a low flip threshold by adjusting the width-to-length ratios of the PMOS and NMOS transistors that make it up; it converts the avalanche signal into a digital negative pulse output, that is, the low-voltage quenching signal. The low-voltage quenching signal, that is, the quenching signal (low voltage), directly turns on the second PMOS transistor M P2 (at this time, the first PMOS transistor M P1 still remains on), quickly opens the low-power-voltage quenching branch, performs the first step of rapid quenching, and accelerates the pull-up of the SPAD anode potential; after the quenching signal level shifter boosts the voltage, the high-power-voltage quenching branch is turned on after an unavoidable delay, that is, the fourth PMOS transistor M P4 is turned on. This process is the second step of high-voltage quenching. At the same time, the quenching signal (low voltage) also serves as an input signal to the reset signal generation module. It is output to the next-stage monostable circuit after a delay for setting the quenching hold duration through a delay module with adjustable delay. One of the forward intermediate nodes with a short delay in the delay module is also used to generate the low-voltage branch off signal for the low-voltage branch off module. Because it takes a certain amount of time for the high-power-voltage quenching branch to rise from being turned on to the node potential being higher than the low power voltage, a short period of time needs to be reserved. The positive pulse output by the falling-edge-triggered monostable circuit is the reset signal (low voltage). After it is inverted, it serves as another input terminal of the low-voltage branch off module, ensuring that the low-power-voltage quenching branch remains off until the end of the reset process during the reset process. The reset signal (low voltage) also acts on the fifth PMOS transistor M P5, actively charging the quenching signal (low voltage) node accelerates the slow process that originally required resetting the SPAD anode potential and then driving the PMOS in the avalanche inverter to turn off the quenching signal (low voltage). The reset signal (low voltage) is boosted by the reset signal level shifter and then the NMOS transistor M is turned on. N2 , that is, the reset branch is turned on and the high power supply voltage quenching branch is turned off. After the reset process is completed, the SPAD anode terminal is set to ground and restored to the initial bias state to detect the next photon event.

[0063] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limiting the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A single-photon avalanche diode quenching and reset circuit with fast response, characterized in that Including a SPAD, a load resistor, and NMOS transistor M N2 , an avalanche detection inverter, a first PMOS transistor M P1 , a second PMOS transistor M P2 , a third PMOS transistor M P3 , a fourth PMOS transistor M P4 , a fifth PMOS transistor M P5 , a quenching signal level shifter, a reset signal level shifter, a delay module, a monostable circuit, and a low voltage branch shutdown module; The cathode of the SPAD is connected to an externally input reverse bias voltage, the anode is grounded via a load resistor, and the anode is also connected to the input terminal of an avalanche detection inverter, the drain of NMOS transistor M N2 , the drain of the second PMOS transistor M P2 , and the drain of the fourth PMOS transistor M P4 ; The source of M N2 is grounded; The output terminal of the avalanche detection inverter is connected to the input terminal of the delay module and the gate of the second PMOS transistor M P2 , and is connected to the gate of the fourth PMOS transistor M P4 via a quenching signal level shifter; The first output terminal of the delay module is connected to the input terminal of a monostable circuit; The output terminal of the monostable circuit is connected to the input terminal of a low-voltage branch shutdown module, and is connected to the gate of NMOS transistor M N2 and the gate of the third PMOS transistor M P3 via a reset signal level shifter; The source of the first PMOS transistor M P1 is connected to an externally input low power supply voltage, the drain is connected to the source of the second PMOS transistor M P2 , and the gate is connected to the first output terminal of the low-voltage branch shutdown module; The source of the third PMOS transistor M P3 is connected to an externally input high power supply voltage, the drain is connected to the source of the fourth PMOS transistor M P4 ; The source of the fifth PMOS transistor M P5 is connected to the low power supply voltage, the drain is connected to the input terminal of the delay module, and the gate is connected to the second output terminal of the low-voltage branch shutdown module; The third output terminal of the low-voltage branch shutdown module serves as the output terminal of the single-photon avalanche diode quenching and reset circuit; The low-voltage branch closing module includes an inverter and a NAND gate; The input terminal of the inverter serves as the input terminal of the low-voltage branch closing module and receives the output terminal of the one-shot circuit. The output terminal is respectively connected to the first input terminal of the NAND gate. The second output terminal of the low-voltage branch closing module is connected to the gate of the fifth PMOS transistor M P5 ; The third output terminal of the low-voltage branch closing module. The output terminal of the NAND gate serves as the first output terminal of the low-voltage branch closing module and is connected to the gate of the first PMOS transistor M P1 . The second input terminal of the NAND gate is connected to the second output terminal of the delay module.

2. The quenching and reset circuit of a single-photon avalanche diode with fast response according to claim 1, characterized in that, The load resistor is NMOS transistor M N1 ; The drain of the NMOS transistor M N1 is connected to the anode of the SPAD, the source is grounded, and the gate is connected to the externally input DC voltage Vb.

3. A quenching and reset circuit for a single-photon avalanche diode with fast response according to claim 1, characterized in that The avalanche detection inverter is powered by a low supply voltage, has a low switching threshold, and is used to convert the avalanche signal into a digital negative pulse output.

4. A quenching and reset circuit for a single-photon avalanche diode with fast response according to claim 1, characterized in that, The delay module is a non-inverting delay module.

5. A quenching and reset circuit for a single-photon avalanche diode with fast response according to claim 2, characterized in that In the initial state, the anode of the SPAD is connected to the ground via the NMOS transistor M N1 , the second PMOS transistor M P2 , the fourth PMOS transistor M P4 and the NMOS transistor M N2 are kept off, and the first PMOS transistor M P1 and the fifth PMOS transistor M P5 are kept on.

6. A quenching and reset circuit for a single-photon avalanche diode with fast response according to claim 5, characterized in that, The quenching process of the single-photon avalanche diode quenching and reset circuit includes a low-voltage quenching stage and a high-voltage quenching stage.

7. A quenching and reset circuit for a single-photon avalanche diode with fast response according to claim 6, characterized in that, The low-voltage quenching stage is specifically as follows: When the optical signal excites the SPAD and causes it to avalanche breakdown, the large current pulse output by the SPAD is converted into a voltage pulse via the NMOS transistor M N1 The anode level of the SPAD begins to rise. The avalanche signal is converted into a digital negative pulse output by the avalanche signal detection inverter, that is, the low-voltage quenching signal. The low-voltage quenching signal directly turns on the second PMOS transistor M P2 At this time, the first PMOS transistor M P1 and the second PMOS transistor M P2 are both turned on to form a low-power-supply-voltage quenching branch, and low-voltage quenching is carried out quickly to accelerate the pulling up of the SPAD anode potential.

8. A quenching and reset circuit for a single-photon avalanche diode with fast response according to claim 7, characterized in that, The specific high-voltage quenching stage is as follows: after accelerating and pulling up the SPAD anode potential in the low-voltage quenching stage, the output of the avalanche signal detection inverter is boosted by the quenching signal level shifter, and the fourth PMOS transistor M is turned on after an unavoidable delay. P4 At this time, the third PMOS transistor M P3 , the fourth PMOS transistor M P4 are both turned on to form a high power supply voltage quenching branch, and the low power supply voltage quenching branch is disconnected to perform high-voltage quenching.

9. A quenching and reset circuit for a single-photon avalanche diode with fast response according to claim 1, characterized in that, The monostable circuit is a falling-edge triggered monostable circuit, and the positive pulse output by it is the reset signal.

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