Random source circuit for random computing and configuration optimization method thereof

Abstract

A random source circuit for random computing and a configuration optimization method thereof, wherein the random source is generated by m linear feedback shift registers for m n-bit random binary numbers; the bits of the random binary numbers generated by the linear feedback shift registers are rearranged by m+1 n-bit rearrangement elements; the bits generated by the rearrangement elements are selected by 2m bit selection elements and combined to generate m new n-bit random binary numbers as the final random source output. The present application is optimized for any random computing circuit, and on the basis of maintaining high computing accuracy, the hardware overhead is greatly reduced, realizing high computing accuracy and low hardware overhead, achieving efficient random source design; no longer limited to random computing circuits for implementing single-variable functions, with wide application potential.

Description

Technical Field

[0001] This invention relates to the field of digital circuit design technology, and more specifically to a random source circuit for random computation and its configuration optimization method. Background Technology

[0002] As a novel computing technology, random computation offers advantages such as low hardware overhead and high fault tolerance. It uses random bitstreams to encode data and performs calculations based on these random bitstreams using traditional digital circuits. A random computation circuit (hereinafter referred to as a random circuit) consists of a random sequence generator and a core random computation circuit, such as... Figure 1 As shown in the diagram. The random sequence generator converts the input binary number into a random bit stream. The core circuit of the random computation performs calculations based on the obtained random bit stream to achieve the final function. Generally, to generate m independent random bit streams, random computation uses m independent random sequence generators to form a random sequence generator, such as... Figure 1 As shown, each random sequence generator consists of a random source and a comparator. The random source generates a random binary number, and the comparator compares the input binary number with the random binary number generated by the random source to produce a 0 / 1 bit. Therefore, in the traditional method, m independent random sources are needed to generate m independent random bit streams. While this is beneficial for achieving high computational accuracy, it generally results in significant hardware overhead for the random sources, and consequently, substantial hardware overhead for the random circuitry. Figure 2 The two-input random multiplier shown uses two independent Sobol sequence generators as random sources. The random sources account for 95.7% of the total area, resulting in an excessively large overall circuit area and low practical value. Figure 3 It is a bit rearrangement element. Figure 4 It is a bit selection element. Bit rearrangement elements and bit selection elements are components used in random circuit design. Summary of the Invention

[0003] This invention addresses the problems in generating random binary numbers in traditional random circuits by making technical improvements to the design and configuration optimization methods of random sources, providing a highly efficient random source circuit with high computational accuracy and low hardware overhead.

[0004] To achieve the above object, the technical scheme of the present application is a high-efficiency random source circuit with high calculation accuracy and low hardware cost, which comprises m n-bit linear feedback shift registers for generating m n-bit random binary numbers; (m+1) n-bit rearrangement elements for rearranging the bits of the random binary numbers generated by the linear feedback shift registers, wherein the first two rearrangement elements act on the output of the first linear feedback shift register, and the last (m-1) rearrangement elements act on the output of the last (m-1) linear feedback shift registers; 2m bit selection elements for selecting the bits output by the rearrangement elements and combining to generate m new n-bit random binary numbers, wherein the first (m+1) bit selection elements act on the output of the first rearrangement element, and the last (m-1) bit selection elements act on the output of the last (m-1) rearrangement elements. Specifically, assuming that the n output bits of the first bit rearrangement element are divided into m segments, wherein the first segments each have bits, and the last segments each have bits. For the i-th bit selection element, when 1≤i≤m, it selects the bits in the i-th segment of the output of the first bit rearrangement element as the first or highest bit of the new i-th random binary number; when , the i-th bit selection element selects the first bits of the output of the (i-m)th rearrangement element as the last bits of the new (i-m)th random binary number; when , the i-th bit selection element selects the first bits of the output of the (i-m)th rearrangement element as the last bits of the new (i-m)th random binary number. The comparator compares based on the new n-bit random binary numbers and outputs 0 / 1 bits, and the random calculation core circuit calculates based on the random bit stream and outputs the final calculation result.

[0005] Preferably, the high-efficiency random source circuit with high calculation accuracy and low hardware cost comprises three 8-bit linear feedback shift registers to generate three 8-bit random binary numbers; four 8-bit rearrangement elements to rearrange the bits of the random binary numbers generated by the linear feedback shift registers, wherein the first two 8-bit rearrangement elements act on the output of the first linear feedback shift register, and the third and fourth 8-bit rearrangement elements act on the outputs of the second and third linear feedback shift registers, respectively; and six bit selection elements to select the output bits of the 8-bit rearrangement elements, wherein the first three bit selection elements act on the output of the first 8-bit rearrangement element, and the fourth, fifth and sixth bit selection elements act on the outputs of the second, third and fourth 8-bit rearrangement elements, respectively. Specifically, the eight output bits of the first 8-bit rearrangement element are divided into three segments, the first two segments have three bits, and the last segment has two bits; the first, second and third bit selection elements select the bits in the first, second and third segments of the output of the first 8-bit rearrangement element as the three highest bits of a new first random binary number, the three highest bits of a new second random binary number and the two highest bits of a new third random binary number, respectively; the fourth and fifth bit selection elements select the first five bits of the outputs of the second and third 8-bit rearrangement elements as the last five bits of the new first random binary number and the last five bits of the new second random binary number, respectively; and the sixth bit selection element selects the first six bits of the output of the fourth 8-bit rearrangement element as the last six bits of the new third random binary number. The comparator compares the new 8-bit random binary numbers and outputs 0 / 1 bits, and the random calculation core circuit calculates and outputs a final calculation result based on the random bit stream.

[0006] Another object of the present application is to provide a configuration and optimization method of a high-efficiency random source circuit with high calculation accuracy and low hardware cost.

[0007] To achieve the above object, the present application adopts a configuration and optimization method of a high-efficiency random source circuit with high calculation accuracy and low hardware cost. The assumptions used by the configuration and optimization method of the high-efficiency random source circuit with high calculation accuracy and low hardware cost are as follows: it is assumed that m linear feedback shift registers have the same feedback polynomial; it is assumed that the initial value of the i-th linear feedback shift register is S i ; and a reference linear feedback shift register is also considered, which has the same feedback polynomial but an initial value of 1, and it is assumed that the reference linear feedback shift register outputs S i at time T(S i; assume that the number of possible feedback polynomials is f for an n-bit LFSR; assume that the signal is transferred from the 1st D flip-flop to the nth D flip-flop for an n-bit LFSR; assume that, in the high-computational-accuracy, low-hardware-overhead efficient random source circuit optimization method, m LFSRs are implemented using h consecutive D flip-flop sequences, the ith D flip-flop sequence contains q i D flip-flops; assume that u, t d , and t b are designer-defined parameters, where u is the upper limit of the exploration space, generally ranging from [1, 2 n -1], t d and t b are the upper limits of the search number of the configuration method, greater than or equal to 1.

[0008] The high-computational-accuracy, low-hardware-overhead efficient random source circuit configuration optimization method optimizes the configuration and implementation of the m LFSRs and the (m+1) bit rearrangement elements of the high-computational-accuracy, low-hardware-overhead efficient random source circuit based on the assumptions, so that the computational accuracy of the high-computational-accuracy, low-hardware-overhead efficient random source circuit is improved and the hardware overhead is reduced.

[0009] Preferably, the high-computational-accuracy, low-hardware-overhead efficient random source circuit configuration method is a cyclic configuration method, comprising the following steps:

[0010] S1, assuming that the minimum computational error MAE min is positive infinity, and the optimal configuration C * is empty;

[0011] S2, assigning i = 1;

[0012] S3, selecting the ith possible feedback polynomial configuration m LFSRs;

[0013] S4, selecting the initial value S1 of the first LFSR, so that T(S1) = u is satisfied;

[0014] S5, assigning j = 1;

[0015] S6, randomly selecting the initial values S i of the remaining (m-1) LFSRs, so that 1≤T(S i )≤u is satisfied;

[0016] S7, assigning k = 1;

[0017] S8, randomly selecting the configuration of the (m+1) bit rearrangement elements;

[0018] S9, based on the above configuration, simulate the calculation error MAE of the circuit; if MAE < MAE min , update the optimal configuration C * for the current configuration mode, update the lowest calculation error MAE min for MAE; k = k + 1;

[0019] S10, if k≤t b , jump to S8, otherwise proceed to the next step;

[0020] S11, j = j + 1;

[0021] S12, if j≤t d , jump to S6, otherwise proceed to the next step;

[0022] S13, i = i + 1;

[0023] S14, if i≤f, jump to S3, otherwise end the overall process and obtain the final element optimal configuration mode C * ;

[0024] Preferably, the above-mentioned high-computing-accuracy, low-hardware-overhead and high-efficiency random source circuit optimization method is a loop optimization method, comprising the following steps:

[0025] P1, sort the set (T(S1), …, T(S m )) from large to small to obtain a new set (T(S r1 ), …, T(S rm ));

[0026] P2, independently implement the r1th linear feedback shift register;

[0027] P3, assign i = 1;

[0028] P4, if d = T(S ri )-T(S ri+1 )≤n, insert d D flip-flops after the rith linear feedback shift register to implement the (ri+1)th linear feedback shift register, otherwise independently implement the (ri+1)th linear feedback shift register;

[0029] P5, i = i + 1;

[0030] P6, if i≤m-1, jump to P4, otherwise obtain h consecutive D flip-flop sequences to implement m linear feedback shift registers, and proceed to the next step;

[0031] P7, assign j = 1;

[0032] P8, assign k = qj where q j is the number of D-flip-flops in the jth D-flip-flop sequence;

[0033] P9, for the kth D-flip-flop in the jth D-flip-flop sequence, if it is not selected by the bit selection element and is not an input of the XOR gate, delete this D-flip-flop, and go to the next step, otherwise jump to P12;

[0034] P10, k=k-1;

[0035] P11, if k≥1, jump to P9, otherwise go to the next step;

[0036] P12, j=j+1;

[0037] P13, if j≤h, jump to P8, otherwise end the whole process, and obtain the optimized implementation of the final random source design.

[0038] Compared with the prior art, the beneficial effects of the present application are that the general optimization is carried out for any random calculation circuit, the great reduction of the circuit hardware overhead is realized under the condition of ensuring the high accuracy performance, and the present application is not limited to the random calculation circuit for realizing the single variable function, and has wide application potential. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 is a schematic diagram of a random circuit.

[0040] Figure 2 is a schematic diagram of a two-input random multiplier.

[0041] Figure 3 is a schematic diagram of a bit rearrangement element.

[0042] Figure 4 is a schematic diagram of a bit selection element.

[0043] Figure 5 is a schematic diagram of a random calculation random source circuit embodiment of the present application.

[0044] Figure 6 is a schematic diagram of a three-input random multiplier realized based on a traditional random source design.

[0045] Figure 7 is a schematic diagram of a three-input random multiplier realized based on the random calculation random source circuit embodiment of the present application. DETAILED DESCRIPTION

[0046] The present application will be further described below in combination with embodiments and with reference to the accompanying drawings, but the protection scope of the present application should not be limited thereby.

[0047] Example 1

[0048] The purpose of the embodiment of the high-efficiency random source circuit with high calculation accuracy and low hardware cost is to overcome the problem of large design cost of the traditional random source. By reasonably using the linear feedback shift register, the bit rearrangement element and the bit selection element, high accuracy of the random circuit is realized, and optimization space is created for further reducing the hardware cost.

[0049] Figure 5 The figure is a schematic diagram of the random source circuit for random calculation according to the embodiment of the present application. As shown in the figure, the random source circuit for random calculation comprises m n-bit linear feedback shift registers, (m+1) n-bit rearrangement elements, and 2m bit selection elements, wherein the bit rearrangement element and the bit selection element do not generate hardware cost. The working principle is as follows:

[0050] 1) m n-bit random binary numbers are generated by the m n-bit linear feedback shift registers;

[0051] 2) The bits of the random binary numbers generated by the linear feedback shift registers are rearranged by the (m+1) n-bit rearrangement elements, wherein the first two rearrangement elements act on the output of the first linear feedback shift register, and the last (m-1) rearrangement elements act on the output of the last (m-1) linear feedback shift registers;

[0052] 3) The bits output by the rearrangement elements are selected and combined to generate m new n-bit random binary numbers by the 2m bit selection elements, wherein the first (m+1) bit selection elements act on the output of the first rearrangement element, and the last (m-1) bit selection elements act on the output of the last (m-1) rearrangement elements. Specifically, assuming that the n output bits of the first bit rearrangement element are divided into m segments, wherein the first segment has bits, and the last segment has bits. For the i-th bit selection element, when 1≤i≤m, the bits in the i-th segment of the output of the first bit rearrangement element are selected as the first or highest bit of the new i-th random binary number; when , the i-th bit selection element selects the first bits of the output of the (i-m)th rearrangement element as the last lowest bit of the new (i-m)th random binary number; when , the i-th bit selection element selects the first bits of the output of the (i-m)th rearrangement element as the last the lowest bit position;

[0053] The embodiment of the application is a configuration optimization method of a high-efficiency random source circuit with high calculation accuracy and low hardware cost, which is used for reasonably configuring a feedback polynomial and an initial value of a linear feedback shift register and an n-bit rearrangement element, and further optimizing an implementation mode of the random source. The related assumptions are as follows:

[0054] 1) It is assumed that m linear feedback shift registers have the same feedback polynomial;

[0055] 2) It is assumed that an initial value of the i-th linear feedback shift register is S i ;

[0056] 3) It is assumed that a linear feedback shift register with the same feedback polynomial and an initial value of 1 outputs S i at T(S i );

[0057] 4) It is assumed that for an n-bit linear feedback shift register, the number of possible feedback polynomials is f;

[0058] 5) It is assumed that for an n-bit linear feedback shift register, a signal is transferred from the first D flip-flop to the n-th D flip-flop;

[0059] 6) It is assumed that in the high-efficiency random source circuit optimization method with high calculation accuracy and low hardware cost, m linear feedback shift registers are finally implemented by using h continuous D flip-flop sequences, and the i-th D flip-flop sequence includes q i D flip-flops;

[0060] 7) It is assumed that u, t d , and t b are designer-defined parameters, in which u is an upper limit of an exploration space, generally ranging from 1 to 2 n -1, t d and t b are upper limits of the number of search times of the configuration method, and are greater than or equal to 1.

[0061] The embodiment of the application is a configuration method of a high-efficiency random source circuit with high calculation accuracy and low hardware cost, which is a cyclic configuration method, and the specific steps are as follows:

[0062] 1) It is assumed that the minimum calculation error MAE min is positive infinity, and the optimal configuration C * is empty;

[0063] 2) The value of i is set to 1;

[0064] 3) The i-th possible feedback polynomial is selected to configure m linear feedback shift registers;

[0065] 4) Select the initial value S1 of the first linear feedback shift register so that it satisfies T(S1)=u;

[0066] 5) Assign the value j = 1;

[0067] 6) Randomly select the initial values ​​S for the remaining (m-1) linear feedback shift registers. i Make it satisfy 1≤T(S) i )≤u,;

[0068] 7) Assign the value k = 1;

[0069] 8) Randomly select (m+1) bits for reordering the configuration;

[0070] 9) Based on the above configuration, simulate the circuit's computational error (MAE); if the MAE... <MAE min Update the optimal configuration C * Update the minimum calculation error (MAE) for the current configuration. min For MAE; k = k + 1;

[0071] 10) If k≤t b If you are not in a position to proceed to step 8, proceed to the next step.

[0072] 11) j = j + 1;

[0073] 12) If j≤t d If you are not already in the correct position, proceed to step 6; otherwise, proceed to the next step.

[0074] 13) i = i + 1;

[0075] 14) If i≤f, jump to 3), otherwise end the overall process and obtain the final optimal component configuration C. * ;

[0076] This embodiment presents an optimization method for a highly efficient random source circuit with high computational accuracy and low hardware overhead. This method is a loop optimization method, and the specific steps are as follows:

[0077] 1) For the set (T(S1), ..., T(S...)... m Sort the data from largest to smallest to obtain a new set (T(S)). r1 ),…,T(S rm ));

[0078] 2) Independently implement the r1-th linear feedback shift register;

[0079] 3) Assign the value i = 1;

[0080] 4) If d = T(S) ri )-T(S ri+1) < n, insert d D flip-flops after the rihlinear feedback shift register to realize the (ri+1)th linear feedback shift register, or realize the (ri+1)th linear feedback shift register independently;

[0081] 5) i = i + 1;

[0082] 6) If i < m - 1, jump to 4), otherwise obtain h consecutive D flip-flop sequences to realize m linear feedback shift registers, and proceed to the next step;

[0083] 7) Assign j = 1;

[0084] 8) Assign k = q j , where q j is the number of D flip-flops in the jth D flip-flop sequence;

[0085] 9) For the kth D flip-flop in the jth D flip-flop sequence, if it is not selected by a bit selection element and is not an input of an XOR gate, delete the D flip-flop, and proceed to the next step, otherwise jump to 12);

[0086] 10) k = k - 1;

[0087] 11) If k > 1, jump to 9), otherwise proceed to the next step;

[0088] 12) j = j + 1;

[0089] 13) If j < h, jump to 8), otherwise end the overall process and obtain the optimized implementation of the final random source design;

[0090] Example 2

[0091] Figure 6 is a schematic diagram of a three-input random multiplier implemented based on a traditional random source design. As shown in Figure 6 , the random computing core circuit is composed of a three-input AND gate; n = 8; to generate 3 independent random bit streams, it needs 3 independent 8-bit random sources and 3 comparators. A Sobol sequence generator is used as a random source. The three-input random multiplier implemented based on the traditional random source design uses 3 randomly selected independent 8-bit Sobol sequence generators as random sources, and the 3 Sobol sequence generators generate 3 random binary numbers in one clock; 3 comparators compare the generated random binary numbers with the input binary numbers, and if the random binary number is less than the input binary number, output 1, otherwise output 0, thus generating a random bit stream inputting the subsequent random computing core circuit, i.e. the three-input AND gate; after 256 clocks, the number of 1s in the output random bit stream is divided by 256, and the calculation result of the three-input multiplier implemented based on the traditional random source design is obtained.

[0092] Figure 7 is a schematic diagram of a three-input random multiplier realized based on the high-efficiency random source circuit of the application. As shown in Figure 7 , three 8-bit linear feedback shift registers, four 8-bit rearrangement elements and six bit selection elements are applied to form three random sources. The three 8-bit linear feedback shift registers generate three random binary numbers in one clock, the four 8-bit rearrangement elements rearrange the generated binary numbers, and the six bit selection elements select the output bits of the rearrangement elements to generate new random binary numbers; the three comparators compare the generated new random binary numbers with the input binary numbers, and if the random binary numbers are smaller than the input binary numbers, output 1, otherwise output 0, thus generating a random bit stream inputting a subsequent random calculation core circuit, i.e. a three-input AND gate; after 255 clocks, the number of 1s in the output random bit stream is divided by 256, and thus the calculation result of the three-input multiplier is obtained.

[0093] In terms of calculation accuracy, the circuit realized in the embodiment has an average absolute error of 0.0033 under the configuration of the configuration method. Based on the same time configuration Figure 6 of the traditional design shown in the figure, the corresponding average error is 0.0027. Obviously, the calculation accuracies of the two designs are very similar. In terms of hardware overhead, under the optimization of the optimization method, the random sequence generator area of the circuit realized in the embodiment is 152.04 square microns, which is much smaller than the random sequence generator area of 1921.59 square microns of the traditional design, and the area is reduced by 92%. The standard cell library used here is Nangate Standard 45nm CellLibrary【 https: / / si2.org / open-cell-library / .

[0094] As can be seen from the above, through the reasonable configuration and optimization design of the embodiment, the hardware overhead of the random circuit is greatly reduced on the basis of maintaining high calculation accuracy, realizing high calculation accuracy and low hardware overhead, and achieving high-efficiency random source design. Compared with the traditional design, the application has strong application effect and application prospect.

[0095] Those skilled in the art can understand that all or part of the steps of the above embodiments can be completed by hardware, or by a program instructing relevant hardware to complete, and the program can be stored in any computer readable storage medium, wherein the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0096] The above merely describes the preferred embodiments of the present application, and it should be pointed out that, for those skilled in the art, several improvements and supplements can be made without departing from the principles of the present application, and these improvements and supplements should also be considered as the protection scope of the present application.

Claims

1. A random source circuit for random computation, characterized in that, include: m n-bit linear feedback shift registers are used to generate m n-bit random binary numbers; (m+1) n-bit rearrangement elements are used to rearrange the bits of the random binary number generated by the linear feedback shift register. The first two rearrangement elements are applied to the output of the first linear feedback shift register, and the last (m-1) rearrangement elements are applied to the outputs of the last (m-1) linear feedback shift registers respectively. 2m bit selection elements are used to select bits from the output of the rearrangement elements and combine them to generate m new n-bit random binary numbers. The first (m+1) bit selection elements all act on the output of the first rearrangement element, and the last (m-1) bit selection elements act on the outputs of the last (m-1) rearrangement elements respectively. Specifically, assume that the n output bits of the first bit rearrangement element are divided into m segments, where the first... Each section has bits, then Each section has For the i-th bit selection element, when 1 ≤ i ≤ m, it selects the bits in the i-th segment of the output of the first bit rearrangement element as the first bit of the new i-th random binary number. or The highest bit; when At that time, the i-th bit selection element selects the first bit of the output of the (im)-th rearrangement element. The bits are used as the last bit of the new (im)th random binary number. The lowest bit; when At that time, the i-th bit selection element selects the first bit of the output of the (im)-th rearrangement element. The bits are used as the last bit of the new (im)th random binary number. The lowest bit.

2. The random source circuit for random calculation according to claim 1, characterized in that: Let m = 3 and n = 8. Then, three 8-bit linear feedback shift registers generate three 8-bit random binary numbers. Four 8-bit rearrangement elements rearrange the bits of the random binary numbers generated by the linear feedback shift registers, with the first two rearrangement elements acting on the output of the first linear feedback shift register, and the third and fourth rearrangement elements acting on the outputs of the second and third linear feedback shift registers, respectively. Six bit selection elements select the output bits of the bit rearrangement elements, with the first three bit selection elements acting on the output of the first bit rearrangement element, and the fourth, fifth, and sixth bit selection elements acting on the outputs of the second, third, and fourth bit rearrangement elements, respectively. Specifically, the eight output bits of the first bit rearrangement element are... The number is divided into 3 segments, with the first two segments having 3 bits each and the last segment having 2 bits each. The first, second, and third bit selection elements select bits from the first, second, and third segments output by the first bit rearrangement element, respectively, as the 3 highest bits of the new first random binary number, the 3 highest bits of the new second random binary number, and the 2 highest bits of the new third random binary number. The fourth and fifth bit selection elements select the first 5 bits output by the second and third bit rearrangement elements, respectively, as the last 5 bits of the new first random binary number and the last 5 bits of the new second random binary number. The sixth bit selection element selects the first 6 bits output by the fourth bit rearrangement element as the last 6 bits of the new third random binary number.

3. A method for optimizing the configuration of a stochastic source circuit based on random computation, characterized in that: Assume that m linear feedback shift registers have the same feedback polynomial; assume that the initial value of the i-th linear feedback shift register is S. i Consider another reference linear feedback shift register, which has the same feedback polynomial but is initialized to 1. Assume the reference linear feedback shift register is in T(S i Output S at time ) i Assume that for an n-bit linear feedback shift register, the number of possible feedback polynomials is f; assume that for an n-bit linear feedback shift register, the signal is transferred from the 1st D flip-flop to the nth D flip-flop; assume that in the random source circuit and its configuration optimization method of the random computation, m linear feedback shift registers are implemented using h consecutive D flip-flop sequences, and the i-th D flip-flop sequence contains q i A D flip-flop; assuming u, t d t b The designer defines the parameters, where u is the upper limit of the exploration space, typically ranging from [1, 2]. n -1],t d and t b To configure the upper limit of the number of search attempts, which is greater than or equal to 1, the configuration and implementation of m linear feedback shift registers and (m+1) bit rearrangement elements of the random source circuit design for random computation described in claim 1 or claim 2 are optimized based on the assumption, so that the computational accuracy of the efficient random source design is improved and the hardware overhead is reduced.

4. The configuration optimization method for randomly calculated random source circuits according to claim 3, wherein the configuration method is a cyclic configuration method, comprising the following steps: S1, Assuming the lowest calculation error MAE min If the value is positive infinity, the optimal configuration is C. * Empty; S2, assign i = 1; S3. Select the i-th possible feedback polynomial to configure m linear feedback shift registers; S4. Select the initial value S1 of the first linear feedback shift register so that it satisfies T(S1)=u; S5, assign j = 1; S6. Randomly select the initial values ​​S of the remaining (m-1) linear feedback shift registers. i Make it satisfy 1≤T(S) i )≤u; S7, assign k = 1; S8. Randomly select the configuration of (m+1) bit rearrangement elements; S9. Based on the above configuration, simulate the circuit's calculation error MAE; if MAE <MAE min Update the optimal configuration C * Update MAE for the current configuration. min For MAE; k = k + 1; S10. If k≤t b Otherwise, proceed to the next step. S11, j = j + 1; S12, if j≤t d Otherwise, proceed to the next step. S13, i = i + 1; S14. If i ≤ f, jump to S3; otherwise, end the overall process and obtain the final optimal component configuration C. * .

5. The method for optimizing the configuration of a randomly calculated random source circuit according to claim 3, wherein the method is a cyclic optimization method, comprising the following steps: P1. For the set (T(S1), ..., T(S1), ..., T(S1)... m Sort the data from largest to smallest to obtain a new set (T(S)). r1 ),…,T(S rm )); P2, independently implement the r1th linear feedback shift register; P3, assign i = 1; P4, If d = T(S) ri )-T(S ri+1 If n ≤ n, insert d D flip-flops after the ri-th linear feedback shift register to implement the (ri+1)-th linear feedback shift register; otherwise, implement the (ri+1)-th linear feedback shift register independently. P5, i = i + 1; P6. If i≤m-1, jump to P4; otherwise, obtain h consecutive D flip-flop sequences to implement m linear feedback shift registers, and proceed to the next step. P7, assign j = 1; P8, Assigning k = q j , where q j The number of D flip-flops in the j-th D flip-flop sequence; P9. For the k-th D flip-flop in the j-th D flip-flop sequence, if it is not selected by the bit selection element and is not used as the input of the XOR gate, delete this D flip-flop and proceed to the next step; otherwise, jump to P12. P10, k = k-1; P11. If k≥1, jump to P9; otherwise, proceed to the next step. P12, j = j + 1; P13. If j≤h, jump to P8; otherwise, end the overall process and obtain the optimized implementation of the final random source design.

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