Image-text layout method, image-text layout device, computer device, and storage medium

Abstract

This disclosure relates to a graphic layout method, graphic layout processor, computer device, and storage medium. The graphic layout method includes: parsing the topological relationships of all graphic elements in the current layer stack of a design drawing to be processed, wherein the current layer stack includes multiple layers, and each layer includes multiple graphic elements; determining the current logical block corresponding to each graphic element in the current layer stack according to the topological relationships; and determining the size and position of each graphic element in the current layer stack based on the topological relationships and the current logical block corresponding to each graphic element. This disclosure can decompose complex design layers into independent design units, each unit having the ability to calculate its own size and position. Therefore, this disclosure can achieve efficient and intelligent layout.

Description

Technical Field

[0001] This disclosure relates to the field of graphic design, and in particular to a graphic layout method, graphic layout device, computer device, and storage medium that integrates image information. Background Technology

[0002] In the process of intelligent graphic design, the intelligent layout of all graphic elements is a very important part of the entire intelligent design system.

[0003] The related technologies utilize manually configured templates that are then modified. They employ simple, responsive line-wrapping text and graphics to adapt to various size variations. Summary of the Invention

[0004] The inventors noted that the template layout schemes of related technologies require manual editing, lack intelligent layout capabilities, and are inefficient.

[0005] In view of at least one of the above technical problems, this disclosure provides a graphic layout method, graphic layout tool, computer device and storage medium that integrates image information, making the overall layout design style richer and laying an important foundation for the entire intelligent design system.

[0006] According to one aspect of this disclosure, a method for typesetting text and images is provided, comprising:

[0007] The topological relationships of all elements in the current layer stack of the design drawing to be processed are parsed. The current layer stack includes multiple layers, and each layer includes multiple elements.

[0008] Based on the aforementioned topological relationships, determine the current logical block corresponding to each primitive in the current layer stack;

[0009] Based on the topological relationship and the current logic block corresponding to each element in the current layer stack, determine the size and position of each element in the current layer stack.

[0010] In some embodiments of this disclosure, the topological relationships of all elements in the current layer stack of the design drawing to be processed are analyzed, including:

[0011] Classify and divide multiple layers in the current layer stack into queues, and determine the queue type corresponding to each layer;

[0012] Create a topological relationship diagram for all elements in all layers;

[0013] Determine the node type, node relationships, and node attributes for all graphical elements.

[0014] In some embodiments of this disclosure, determining the node relationships of all primitives includes:

[0015] Determine the relationships between elements in different layers;

[0016] Determine the node relationships between primitives on the same layer, wherein the node relationships between primitives on the same layer include at least one of intersecting, adjacent, blocking, and surrounding.

[0017] In some embodiments of this disclosure, determining the node relationships between primitives in the same layer includes:

[0018] Group multiple elements on the same layer into the same group.

[0019] In some embodiments of this disclosure, determining the current logical block corresponding to each primitive in the current layer stack according to the topological relationship includes:

[0020] A node scanner is used to perform a global scan of the entire topology graph, and all logical blocks in the queue that meet the conditions are determined based on the scanner.

[0021] For each primitive, the logic block with the highest selection probability is selected as the current logic block according to the topology matrix environment selector.

[0022] In some embodiments of this disclosure, determining the size and position of each element in the current layer stack based on the topological relationship and the current logic block corresponding to each element in the current layer stack includes:

[0023] Based on the variable extraction logic in the current logic block, obtain all environment variable parameters from the environment;

[0024] The environmental variable parameters are fed into the parameter mapping network to calculate the size and position of the current logical block;

[0025] Add the primitive corresponding to the current logic block to the current layer stack, and perform the calculation of the next primitive until all queues have been calculated.

[0026] In some embodiments of this disclosure, selecting the logic block with the highest selection probability as the current logic block according to the topology matrix environment selector includes:

[0027] A symbol rule filter is used to scan and judge individual nodes and node groups;

[0028] The selection probability of each logic block is determined based on the decomposition vector of the primitive relationship matrix and the primitive size information vector.

[0029] Select the logic block with the highest probability of being selected as the current logic block.

[0030] In some embodiments of this disclosure, the step of inputting environmental variable parameters into a parameter mapping network to calculate the size and position of the current logical block includes:

[0031] Get the shape parameters of the primitive itself;

[0032] The position and size parameters of the current logic block are determined based on the environment variable parameters and the shape parameters of the primitive itself.

[0033] In some embodiments of this disclosure, the graphic layout method further includes:

[0034] A pre-designed integrated layout structure comprising multiple first-type logic blocks and multiple second-type logic blocks;

[0035] Based on the requirements, select the appropriate number of first-type and second-type logic blocks, as well as the corresponding position and size parameters of the logic blocks, to generate the required layout structure.

[0036] In some embodiments of this disclosure, the graphic layout method further includes:

[0037] The maximum width range of each line of text is determined by the graphic boundaries on both sides of the graphic element.

[0038] In some embodiments of this disclosure, the graphic layout method further includes:

[0039] Limit the maximum and minimum height of each title in the graphic element, and limit the maximum and minimum height of all titles in the graphic element.

[0040] In some embodiments of this disclosure, the graphic layout method further includes:

[0041] Multiple grid layout styles can be achieved by using a nested method of hierarchical grouping and area division.

[0042] According to another aspect of this disclosure, a text layout tool is provided, comprising:

[0043] The topology parsing module is used to parse the topology relationships of all elements in the current layer stack of the design drawing to be processed. The current layer stack includes multiple layers, and each layer includes multiple elements.

[0044] The logic block determination module is used to determine the current logic block corresponding to each primitive in the current layer stack according to the topological relationship.

[0045] The size and position determination module is used to determine the size and position of each graphic element in the current layer stack based on the topological relationship and the current logic block corresponding to each graphic element in the current layer stack.

[0046] According to another aspect of this disclosure, a computer apparatus is provided, comprising:

[0047] Memory, used to store instructions;

[0048] A processor is configured to execute the instructions, causing the computer device to perform operations implementing the graphic layout method as described in any of the above embodiments.

[0049] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided, wherein the non-transitory computer-readable storage medium stores computer instructions that, when executed by a processor, implement the graphic layout method as described in any of the above embodiments.

[0050] According to another aspect of this disclosure, a computer program product is provided, including a computer program and / or instructions, wherein when the computer program and / or instructions are executed by a processor, they implement the steps of the graphic layout method as described in any of the above embodiments.

[0051] This disclosure can decompose complex design layers into independent design units, each of which has the ability to calculate its own size and position. Therefore, this disclosure enables efficient and intelligent typesetting. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 These are schematic diagrams illustrating some embodiments of the text and image layout method disclosed herein.

[0054] Figure 2 These are schematic diagrams illustrating other embodiments of the text and image layout method disclosed herein.

[0055] Figure 3 This is a schematic diagram illustrating the relationship between elements in different layers in some embodiments of this disclosure.

[0056] Figure 4 This is a schematic diagram illustrating the relationship between layer elements in some embodiments of this disclosure.

[0057] Figure 5 This is a schematic diagram of the topological relationships established for the primitives of all layers in some embodiments of this disclosure.

[0058] Figure 6 This is a schematic diagram showing the node types, node relationships, and node attributes of all graphic elements in some embodiments of this disclosure.

[0059] Figure 7 This is a schematic diagram of queue types in some embodiments of this disclosure.

[0060] Figure 8 This is a schematic diagram illustrating the encoding of the topological relationships of all primitives in some embodiments of this disclosure.

[0061] Figure 9 This is a schematic diagram of a primitive environment network in some embodiments of this disclosure.

[0062] Figure 10 This is a schematic diagram showing the relative position variables and size variables of graphic elements in the whole picture in some embodiments of this disclosure.

[0063] Figure 11 This is a schematic diagram of the environmental network structure in some embodiments of this disclosure.

[0064] Figure 12 This is a schematic diagram of the main layout of the left and right structures in some embodiments of this disclosure.

[0065] Figure 13 This is a schematic diagram of the main layout of the upper and lower structures in some embodiments of this disclosure.

[0066] Figure 14 This is a schematic diagram of the integrated main layout in some embodiments of this disclosure.

[0067] Figure 15 This is a schematic diagram illustrating the title height limitation in some embodiments of this disclosure.

[0068] Figure 16 This is a schematic diagram of a search tree in some embodiments of this disclosure.

[0069] Figure 17 This is a schematic diagram illustrating the title width limitation in some embodiments of this disclosure.

[0070] Figure 18 This is a schematic diagram illustrating the title width limitation in some other embodiments of this disclosure.

[0071] Figure 19 This is a schematic diagram of the layered and grouped structure in some embodiments of this disclosure.

[0072] Figure 20 This is a schematic diagram of the region division method in some embodiments of this disclosure.

[0073] Figure 21 This is a schematic diagram of nested division of the three regions in some embodiments of this disclosure.

[0074] Figure 22 These are schematic diagrams of some embodiments of the text layout device disclosed herein.

[0075] Figure 23 This is a schematic diagram of the structure of some embodiments of the computer device disclosed herein. Detailed Implementation

[0076] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0077] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0078] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0079] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0080] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0081] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0082] The inventors noted that in the intelligent graphic design process, the intelligent layout of all graphic elements is a crucial step in the entire intelligent design system. Given specified text titles, product and other item image dimensions, and person image dimensions, the system can intelligently generate diverse, layered, complete, and dimensionally accurate layouts with a single click. Furthermore, the intelligently synthesized layouts must conform to graphic design typography standards, such as principles of proximity, contrast, and balance.

[0083] The inventors noted that related responsive layout methods are limited to a single pattern, offering only simple line breaks and lacking the ability to generalize various styles of title images under different design principles such as size contrast. Their research revealed a lack of practical and intelligent layout tools in the field of smart design.

[0084] In view of at least one of the above technical problems, this disclosure requires an intelligent typesetting design algorithm that can calculate the size and position coordinates of each material element, so that the typesetting effect achieves a layout design with human visual aesthetics. The algorithm design of this disclosure can greatly reduce the typesetting time of designers, improve design efficiency, and increase the generalization space of layout design, playing a very important role in the entire graphic design work.

[0085] The present disclosure will now be described through specific embodiments.

[0086] Figure 1 This is a schematic diagram of some embodiments of the text and image layout method of this disclosure. Preferably, this embodiment can be executed by a text and image layout device or the computer device of this disclosure. The method may include at least one of steps 11-12, wherein:

[0087] Step 11: parse the topological relationships of all elements in the current layer stack of the design drawing to be processed. The current layer stack includes multiple layers, and each layer includes multiple elements.

[0088] In some embodiments of this disclosure, step 11 may include at least one of steps 111-113, wherein:

[0089] Step 111: Classify and divide the multiple layers in the current layer stack into queues, and determine the queue type corresponding to each layer.

[0090] Step 112: Create a topological relationship diagram for all layers of primitives.

[0091] Step 113: Determine the node type, node relationship, and node attributes of all graphic elements.

[0092] In some embodiments of this disclosure, step 113, the step of determining the node relationships of all graphic elements, may include: determining the relationships between graphic elements in different layers; determining the node relationships between graphic elements in the same layer, wherein the node relationships between graphic elements in the same layer include at least one of intersection, adjacency, obstruction, and surrounding.

[0093] In some embodiments of this disclosure, determining the node relationships between elements in the same layer may include: grouping multiple elements in the same layer into the same group.

[0094] Step 12: Determine the current logic block corresponding to each primitive in the current layer stack according to the topological relationship.

[0095] In some embodiments of this disclosure, step 12 may include at least one of steps 121-122, wherein:

[0096] Step 121: Use a node scanner to perform a global scan of the entire topology graph and determine all logical blocks in the queue that meet the conditions based on the scanner.

[0097] Step 122: For each primitive, select the logical block with the highest selection probability as the current logical block according to the topology matrix environment selector.

[0098] Step 13: Determine the size and position of each logical block based on the topological relationship and the current logical block corresponding to each primitive in the current layer stack.

[0099] In some embodiments of this disclosure, step 13 may include at least one of steps 131-133, wherein:

[0100] Step 131: Based on the variable extraction logic in the current logic block, obtain all environment variable parameters from the environment.

[0101] Step 132: Input the environment variable parameters into the parameter mapping network to calculate the size and position of the current logic block.

[0102] Step 133: Add the primitive corresponding to the current logic block to the current layer stack, and perform the next logic block calculation (i.e., perform the calculation of the next primitive) until all queues have been calculated.

[0103] The graphic layout method of the above embodiments of this disclosure is an intelligent layout design method. It can calculate the size and position coordinates of each material element, so that the layout effect can achieve a layout design with human visual aesthetics as much as possible. The algorithm design of the above embodiments of this disclosure can greatly reduce the layout time of designers, improve design efficiency, and increase the generalization space of layout design, playing a very important role in the entire graphic design work.

[0104] The embodiments of this disclosure can decompose complex design layers into independent graphic elements. For each graphic element, a corresponding logical block is selected. For each graphic element, its size and position can be determined based on the environment variable parameters of the corresponding logical block. Thus, this disclosure can achieve efficient and intelligent typesetting.

[0105] Figure 2 These are schematic diagrams illustrating other embodiments of the text and image layout method of this disclosure. Preferably, this embodiment can be executed by a text and image layout device or the computer device of this disclosure. Figure 2 The intelligent layout design framework for the logic blocks disclosed in this paper is also provided.

[0106] like Figure 2 As shown, Figure 2The text and image layout method of the embodiment may include: first, parsing the topological relationship of all primitives in the current layer stack (empty during the first parsing); then, describing the topological relationship using a graph data structure; determining the required logical block queue type (including background queue, main body queue, decoration queue, and embellishment queue) based on queue selection; then, using a node scanner to perform a global scan of the entire topological relationship graph; determining all logical blocks in the queue that meet the conditions based on the scanner; then, selecting the logical block with the highest selection probability as the current rendering logic based on the topology matrix environment selector; after determining the current logical block, obtaining all variable parameters from the environment based on the variable extraction logic in the logical block; then, substituting these parameters into the parameter mapping network to calculate the size and position of the primitive; and adding this primitive to the current layer stack for the next logical block calculation, until all queue calculations are completed and all calculation logic ends.

[0107] Specifically, Figure 2 The text and image layout method of the embodiment may include at least one of steps 20-24, wherein:

[0108] Step 20: parse the topological relationships of all elements in the current layer stack of the design drawing to be processed. The current layer stack includes multiple layers, and each layer includes multiple elements.

[0109] In some embodiments of this disclosure, step 20 may include at least one of steps 201-204, wherein:

[0110] Step 201: Determine the relationship between the elements in different layers.

[0111] In some embodiments of this disclosure, the selection of a logic block in each logic block queue needs to be determined based on the current layer environment relationship. The current environment is a description of the size of all environment primitives and their relative positions.

[0112] Figure 3 This is a schematic diagram illustrating the relationship between primitives in different layers in some embodiments of this disclosure. According to the z-axis ( Figure 3 The middle section represents the horizontal direction from left to right. The relationship between different layers of primitives is as follows: Figure 3 As shown, the inner primitives act as the parent primitives of the upper primitives. Figure 3 As shown, layer 1 is the parent of layer 2, and layer 2 is the parent of layer 3.

[0113] Step 202: Determine the node relationships between elements in the same layer, wherein the node relationships between elements in the same layer include at least one of the following relationships: intersecting, adjacent, blocking (separating), and surrounding (encircling).

[0114] Figure 4 This is a schematic diagram illustrating the relationship between elements on the same layer in some embodiments of this disclosure. For example... Figure 4 As shown, primitives a and c are intersecting, primitives b and d are adjacent, primitives e and f are surrounding each other, and primitives b and e are separated.

[0115] Step 203: Create a topological relationship diagram for all layers of primitives.

[0116] In some embodiments of this disclosure, step 203 may include: establishing a topological relationship graph for the primitives of all layers, using the representation of graph data structures. Figure 5 This is a schematic diagram of the topological relationships established for the primitives of all layers in some embodiments of this disclosure. For example... Figure 5 As shown, the hierarchy and relative positions of all graphs in a layer can be expressed through the graph data structure. Multiple primitives in a certain layer may be assigned to a group, and therefore are marked as a group in the graph relationship. For example... Figure 5 As shown, the relationship diagrams for Layer 1 and Layer 2 are given. The relationship diagram for Layer 1 includes Group 1, which includes primitives p and c; the relationship diagram for Layer 2 includes Group 2, which includes primitives b and c.

[0117] Step 204: Determine the node type, node relationship, and node attributes of all graphic elements.

[0118] Figure 6 This is a schematic diagram illustrating the node types, node relationships, and node attributes of all graphical elements in some embodiments of this disclosure. For example... Figure 6 As shown, the node types of all graphic elements can include background, title, uploaded image, decorative image, embellishment image, etc.; the node relationships of graphic elements can include intersecting, adjacent, blocking, surrounding, etc.; the node attributes of graphic elements can include rectangular, non-rectangular, area, etc.; the parent relationship can include single parent, multiple parent, etc.

[0119] The above embodiments of this disclosure propose a method for describing the topological relationships of layers.

[0120] Step 21, Queue Selection and Termination Judgment. Multiple layers in the current layer stack are categorized and divided into queues, determining the queue type for each layer.

[0121] In some embodiments of this disclosure, since a typical design drawing includes multiple layers, step 201 may include: using a queue selector to classify and divide the layers in the current layer stack into queues.

[0122] Figure 7 This is a schematic diagram illustrating queue types in some embodiments of this disclosure. For example... Figure 7As shown, queues in this disclosure are classified into four types: background queue, main logic queue, decoration logic queue, and embellishment logic queue. The background queue m includes background logic block 1, background logic block 2, ..., background logic block n; the main logic queue n includes main logic block 1, main logic block 2, ..., main logic block n; the decoration logic queue j includes decoration logic block 1, decoration logic block 2, ..., decoration logic block n; and the embellishment logic queue k includes embellishment logic block 1, embellishment logic block 2, ..., embellishment logic block n.

[0123] This disclosure selects logic blocks from the queues for design at each step. Once all logic blocks in all queues have been designed, the overall image layout design is achieved. The selection of logic blocks from all queues is as follows: Figure 7 As shown.

[0124] The embodiments described above implement a method for generalizing the selection of multi-level queues based on logical blocks.

[0125] Step 22, Logic block selector design.

[0126] In some embodiments of this disclosure, step 22 may include: after establishing the topology graph of the layer, scanning the environmental topology of all nodes to provide a basis for the selection of logical blocks. The selection of logical blocks is first filtered by a symbol rule system, and then a network learning machine is used to create a selection probability for each logical block and perform polling selection.

[0127] In some embodiments of this disclosure, step 22 may include steps 221 and 222, wherein:

[0128] Step 221: Use a symbol rule filter to scan and judge individual nodes and node groups.

[0129] In some embodiments of this disclosure, certain specific rules need to be described by a specific symbol rule system. For example, the following symbol rules are used to determine and select the background button for modifying the design of a pre-typed text.

[0130] In some embodiments of this disclosure, the single-node condition set is:

[0131] Type(curNode) = Text / / The currently traversed node is a text node.

[0132] Parent(curNode).Type = background / / The parent node of the current node is the background node.

[0133] In some other embodiments of this disclosure, in addition to judging individual nodes, it is also necessary to scan and judge node groups, as shown below.

[0134] Group node condition set:

[0135] Type(current group) = subject / / The group is the subject

[0136] Type(Parnet(body)) = Background

[0137] Step 222: The environment decision network selector determines the selection probability of each logical block based on the decomposition vector of the primitive relationship matrix and the primitive size information vector; based on the topology matrix, the environment selector selects the logical block with the highest selection probability as the current logical block.

[0138] To enhance the generalization ability of the selector, after filtering by symbolic rules, an environment judgment network is used for further selection probability allocation. A key step in building the environment network is to convert the current environment topology graph into a feature vector, providing a fixed-dimensional vector as input to the environment judgment network. This disclosure establishes a primitive relationship matrix for all primitives, then performs matrix decomposition to generate vectors, and finally merges the size information of the primitives to generate the input vector for the environment network. The primitive relationship matrix is ​​as follows: Figure 8 As shown.

[0139] In some embodiments of this disclosure, step 222 may include at least one of steps 2221-2223, wherein:

[0140] Step 2221: Encode the topological relationships of all primitives.

[0141] In some embodiments of this disclosure, 1 can be designated as parent relationship, 2 as adjacent, 3 as intersecting, 4 as separated, 5 as surrounding, and 6 as child relationship. This allows the topological relationships of all primitives parsed in step 21 to be established as follows: Figure 8 The primitive relationship matrix shown. Figure 8 This is a schematic diagram illustrating the encoding of the topological relationships of all primitives in some embodiments of this disclosure.

[0142] Step 2222: Decompose the primitive relation matrix to obtain the decomposed vector of the primitive relation matrix.

[0143] like Figure 8 The topological relation matrix shown is a two-dimensional tensor. Therefore, the topological relation matrix can be decomposed according to formula (1) to obtain two vectors, L and F.

[0144] M = L * F (1)

[0145] The above embodiments of this disclosure implement a method for extracting feature vectors from an environment layer.

[0146] Step 2223: Obtain the vector of primitive size information.

[0147] In some embodiments of this disclosure, in addition to positional relationships, the area of ​​the primitives is also an important component of environmental features. The area components of all primitives can be obtained by the ratio of the area of ​​each primitive to the total area according to formula (2).

[0148]

[0149] Step 2224: Input the decomposition vector of the primitive relationship matrix and the primitive size information vector into the primitive environment network to determine the selection probability of each logical block; select the logical block with the highest selection probability as the current logical block.

[0150] Figure 9 This is a schematic diagram of a primitive environment network in some embodiments of this disclosure. For example... Figure 9 As shown, the input vector of the primitive environment network is generated by merging the relation matrix decomposition vector and the primitive size information vector.

[0151] The output of the primitive environment network is the probability of selecting each logical block in each queue. When actually selecting logical blocks, the selection probability of each logical block is used for polling. Since rule filtering has been performed in the previous step, this disclosure recalculates the selection probability of all selected primitives according to formula (3).

[0152]

[0153] The embodiments described above can improve the generalization ability of the design by using a polling method to ensure that each logic block has the possibility of being selected.

[0154] The above embodiments of this disclosure implement a method for logical block judgment and selection of an environment layer.

[0155] Step 23: Use a variable extractor to extract variables from the environment and then logically map them into environment variable parameters.

[0156] In some embodiments of this disclosure, to calculate the size and position parameters of a graphic element, it is first necessary to extract environment variables, and then map the environment parameters out using logical symbols based on the environment variables.

[0157] The following example illustrates how to add a decorative background image to a title text group.

[0158] In some embodiments of this disclosure, single-node environment extraction can be performed via (4) and (5).

[0159] Rect a = Parent(current group).Rect / / parent node region (4)

[0160] Rect b = current group.Rect current group region(5)

[0161] In formulas (4) and (5): Rect a and Rect b are the coordinates of the top left corner and the length and width parameters of the primitive rectangle. Parent is the parent layer of the layer topology diagram in 2.3.2. Here, the example illustrates a simple case of a background image and a text title. After establishing the topology diagram, parent is the rect of the background image, and b is the rect of the text title.

[0162] In some embodiments of this disclosure, the environment parameters of the logic block can be obtained through symbol mapping logic, which represent the maximum size range of the text decoration background primitives via formulas (6) and (7).

[0163] minW = bw, maxW = aw (6)

[0164] minH = bh, maxH = aH (7)

[0165] In formulas (6) and (7), bw is the width of the title text and aw is the width of the background. Add a background image element to the text title. The size of this element should be larger than the size of the title text but smaller than the size of the background. This expresses the range of the size selection for the background image. The specific size can be specified based on experience or generalized through the training network disclosed in this publication.

[0166] Step 24: Use network mapping to determine the position and size of each primitive.

[0167] Figure 10 This is a schematic diagram illustrating the relative position variables and size variables of graphic elements within the overall drawing in some embodiments of this disclosure. For example... Figure 10 As shown, the position of a graphic element within the graphic element layout area is determined by the distances a, b, c, and d of the graphic element from the upper boundary, left boundary, lower boundary, and right boundary of the layout area, and its size is determined by the length e and width f of the graphic element. Figure 10 The variables in the text are not absolute quantities, but are calculated proportionally based on the width and height of the entire image.

[0168] In some embodiments of this disclosure, step 24 may include: the determination of the size and position parameters of the graphic element is determined by two parts, environmental parameter variables and the shape parameters of the graphic element itself, wherein the environmental parameter variables are extracted by the logical expression in step 23; and the shape parameters of the graphic element itself are extracted by the perceptual hash algorithm.

[0169] In some embodiments of this disclosure, the step of extracting primitive shapes using the perceptual hash algorithm may include at least one of steps (1)-(5), wherein:

[0170] (1) Reduce the image size to 8x8 pixels, a total of 64 pixels. This step is to remove the differences in image size and aspect ratio, and only retain basic information such as structure and brightness.

[0171] (2) Convert to grayscale image, convert to 64-level grayscale image.

[0172] (3) Calculate the average gray level. Calculate the average gray level of all pixels in the image.

[0173] (4) Compare the grayscale of the pixels. Compare the grayscale of each pixel with the average value. If it is greater than or equal to the average value, record it as 1; if it is less than the average value, record it as 0.

[0174] (5) Calculate the hash value. Combine the comparison results from the previous step to form a 64-bit binary integer, which is the fingerprint of this image.

[0175] Figure 11 This is a schematic diagram of the environmental network structure in some embodiments of this disclosure. For example... Figure 11 As shown, the input layer of the environment network structure is a combination of environment parameters and the shape parameters of the primitives themselves. The position and size parameters of the primitives are obtained through mapping in the hidden layer.

[0176] The above embodiments of this disclosure implement a method for intelligently calculating the position and size of primitives through environmental parameter network mapping.

[0177] Figures 1-11 This disclosure introduces the overall typesetting framework system design. Furthermore, this disclosure designs several specific main typesetting logic blocks. The position and size calculations of these logic blocks can be performed independently of the environment training network, and can be calculated according to their own special generalization algorithms.

[0178] First, the design of the main integrated layout logic block.

[0179] In some embodiments of this disclosure, the design of the main body typically includes the layout of the title, text paragraphs, uploaded images of people, products, or items, while other decorative elements are adjusted automatically according to the layout of the main body.

[0180] In some embodiments of this disclosure, the graphic layout method may further include: pre-designing an integrated layout structure comprising multiple first-type logic blocks and multiple second-type logic blocks; and, according to requirements, selecting a corresponding number of first-type logic blocks and second-type logic blocks, as well as the position and size parameters of the corresponding logic blocks, to generate the required layout structure.

[0181] In some embodiments of this disclosure, the first type of logic block and the second type of logic block are logic blocks of different types. The type of logic block can be a title, text paragraph, uploaded image of a person, product image, or item image, etc.

[0182] Figure 12 This is a schematic diagram of the main layout of the left and right structures in some embodiments of this disclosure. Figure 13 This is a schematic diagram of the main layout of the upper and lower structures in some embodiments of this disclosure.

[0183] Combining different numbers of text titles with product images facing different directions can produce various results. Therefore, the above embodiments of this disclosure address, for example... Figure 12 and Figure 13 The layout structure is integrated together, and various combined layouts can be created by simply inputting different variables, transforming layout design into a data-driven approach and enhancing the generalization control of the design.

[0184] Figure 14 This is a schematic diagram of the integrated main layout in some embodiments of this disclosure. Figure 12 and Figure 13 The layout structure can be selected Figure 14 The variables in the code are implemented, and various combined layouts can be created. For example... Figure 14 As shown, for Figure 14 Selective input of various variables can generalize to create layout designs with arbitrary combinations of line headings and images. For example, selecting variables p, b, s, q, r, a, e, f, g, c, and d creates a layout structure design based on... Figure 14 The layout structure consists of the image logic block, the first title logic block, and the second title logic block on the left side of the page.

[0185] The above embodiments of this disclosure implement a method for integrated layout of main logic blocks.

[0186] Second, the design of the main body layout title generalizer.

[0187] In some embodiments of this disclosure, the graphic layout method may further include: limiting the maximum height and minimum height of each title in the graphic element, and limiting the maximum height and minimum height of all titles in the graphic element.

[0188] In order to generalize the multi-line headings into a variety of contrasting design styles, the above embodiments of this disclosure generalize the height of multiple headings and limit the total height of multiple headings.

[0189] Figure 15 This is a schematic diagram illustrating the title height limitation in some embodiments of this disclosure. For example... Figure 15As shown, inequality equations are established for the variables e, f, g, h, i, z, aa to constrain and control them as shown in formula (8). Each title is given a maximum and minimum height limit, and the total height of all titles is also given a maximum and minimum limit.

[0190]

[0191] To resolve the above inequality, this disclosure uses a search tree method to traverse all cases and obtain a solution that satisfies the above conditions, such as... Figure 16 As shown, Figure 16 This is a schematic diagram of the search tree in some embodiments of this disclosure. When a combination solution is too small, the cases to its left are pruned; similarly, when a combination solution is too large, the cases to its right are pruned to improve search efficiency.

[0192] The above limits the height of the text. To ensure the neatness of the text group, the width of the text is also limited. When the text title is too long, it needs to be wrapped. In graphic design, text needs to be aligned as much as possible. Therefore, when the text length reaches the maximum boundary, the text is wrapped. When the text length is less than the minimum width, the spacing of the text title is increased to increase the text length and achieve the alignment effect. Figure 17 As shown. Figure 17 This is a schematic diagram illustrating the title width limitation in some embodiments of this disclosure.

[0193] In some embodiments of this disclosure, the graphic layout method may further include: determining the maximum width range of each line of text by using the graphic boundaries on both sides of the graphic element.

[0194] In some embodiments of this disclosure, in many cases of mixed text and images, the images may have irregular boundaries that are not non-rectangular. In such cases, the size of the generalized text title is searched sequentially from top to bottom according to the top case, such as... Figure 18 As shown, Figure 18 This is a schematic diagram illustrating the title width limitation in some other embodiments of this disclosure.

[0195] like Figure 18 As shown, the width of text wrapping is determined by the graphic boundaries on both sides, not as... Figure 17 The fixed rectangle width shown needs to be determined by the graphic boundary when performing the previous line break traversal.

[0196] The above embodiments of this disclosure implement the logic of generalizing the main title style inequality constraint.

[0197] Third, the generalized logic block for the main grid layout.

[0198] In some embodiments of this disclosure, the graphic layout method may further include: using a layered grouping and nested area division method to achieve various grid layout styles.

[0199] In many graphic design layouts, there are grid layout types. In order to achieve the diversity of grid layouts, this disclosure uses a method of nested area division with hierarchical grouping to achieve a variety of grid layout styles. Figure 19 This is a schematic diagram of the layered and grouped structure in some embodiments of this disclosure. For example... Figure 19 As shown, each of the layers 1, 2, ..., n contains n groups, namely, group 1, group 2, ..., group n.

[0200] In some embodiments of this disclosure, the main grid layout can be partitioned using a partitioning algorithm. There are two, three, or four partitioning methods based on the region division. Two regions can be divided vertically or horizontally, while four regions are divided into four parts. Figure 20 This is a schematic diagram of the region division method in some embodiments of this disclosure.

[0201] S1·k=(wx)y

[0202] S2·k=(wx).(hy) (9)

[0203] S3·k=xh

[0204] In formula (9), S1, S3, and S3 correspond to Figure 20 The estimated areas of the three text blocks in the upper left region division diagram are calculated based on the length of the text paragraph and the size of each individual character. Then, the value of the center point (x, y) is estimated. Figure 20 The top left region division diagram, with the top left corner of the diagram being the origin (0, 0).

[0205] This invention can be derived from equation (9) using formula 3. Figure 20 The coordinates of (x, y) in the upper left region division diagram. Similarly, the coordinates of (x, y) for the other three 3-partition cases can also be calculated using a formula similar to formula (9).

[0206] After dividing each layer into regions, the next layer of nested division begins. Figure 21 This is a schematic diagram illustrating the nested division of the three regions in some embodiments of this disclosure. For example... Figure 21 As shown, the bottom layer uses Figure 20 The upper left region division diagram; then in region S1, the following is used... Figure 20The area division diagram in the lower left corner can be used to determine the area allocation method for the next layer. In the above embodiments of this disclosure, after all areas are divided, all text is filled into the corresponding areas. If it is multi-line text, the text generalization method described above can be used to achieve various styles of text size.

[0207] The embodiments disclosed above implement the generalized logic of graphic grid layout.

[0208] Based on the graphic layout method provided in the above embodiments of this disclosure, a complete intelligent design framework system based on queue logic block generalization processing is established. The complex layout design process is decomposed into multiple logic block processing steps. Generalization is performed by selecting the selection probability of multiple steps, making the entire layout design style richer and laying an important foundation for the entire intelligent design system.

[0209] Figure 22 These are schematic diagrams illustrating some embodiments of the text and image layout device disclosed herein. For example... Figure 22 As shown, the graphic layout tool disclosed herein may include a topology parsing module 110, a logic block determination module 130, and a size and position determination module 120, wherein:

[0210] The topology parsing module 110 is used to parse the topology relationships of all elements in the current layer stack of the design drawing to be processed. The current layer stack includes multiple layers, and each layer includes multiple elements.

[0211] In some embodiments of this disclosure, the topology relation parsing module 110 can be used to classify and divide multiple layers in the current layer stack into queues, determine the queue type corresponding to each layer, establish a topology relation graph for the elements of all layers, and determine the node type, node relationship, and node attribute of all elements.

[0212] In some embodiments of this disclosure, the topology relationship parsing module 110, after determining the node relationships of all elements, can be used to determine the relationships between elements in different layers; and to determine the node relationships between elements in the same layer, wherein the node relationships between elements in the same layer include at least one of intersection, adjacency, obstruction, and surrounding.

[0213] In some embodiments of this disclosure, the topology relationship parsing module 110, when determining the node relationship between elements in the same layer, can be used to group multiple elements in the same layer into the same group.

[0214] The logic block determination module 130 is used to determine the current logic block corresponding to each primitive in the current layer stack according to the topological relationship.

[0215] In some embodiments of this disclosure, the logic block determination module 130 can be used to perform a global scan of the entire topology graph using a node scanner, and determine all the logic blocks in the queue that meet the conditions according to the scanner; for each graph element, the logic block with the highest selection probability is selected as the current logic block according to the topology matrix environment selector.

[0216] In some embodiments of this disclosure, when the logic block determination module 130 selects the logic block with the highest selection probability as the current logic block according to the topology matrix environment selector, it can be used to scan and judge individual nodes and node groups using a symbol rule filter; determine the selection probability of each logic block according to the decomposition vector of the primitive relationship matrix and the primitive size information vector; and select the logic block with the highest selection probability as the current logic block.

[0217] The size and position determination module 120 is used to determine the size and position of each graphic element in the current layer stack based on the topological relationship and the current logic block corresponding to each graphic element in the current layer stack.

[0218] In some embodiments of this disclosure, the size and position determination module 120 can be used to extract logic based on the variables in the current logic block, obtain all environment variable parameters from the environment; input the environment variable parameters into the parameter mapping network to calculate the size and position of the logic block; add the primitive corresponding to the current logic block to the current layer stack, and perform the next logic block calculation until all queue calculations are completed.

[0219] In some embodiments of this disclosure, the size and position determination module 120 can be used to obtain the shape parameters of the primitive itself when the environmental variable parameters are brought into the parameter mapping network to calculate the size and position of the logic block; and to determine the position and size parameters of the primitive based on the environmental variable parameters and the shape parameters of the primitive itself.

[0220] In some embodiments of this disclosure, the graphic layout tool can also be used to pre-design an integrated layout structure including multiple first-type logic blocks and multiple second-type logic blocks; according to requirements, select the appropriate number of first-type logic blocks and second-type logic blocks, as well as the position and size parameters of the corresponding logic blocks, to generate the required layout structure.

[0221] In some embodiments of this disclosure, the graphic layout tool can also be used to determine the maximum width range of each line of text by using the graphic boundaries on both sides of the graphic element.

[0222] In some embodiments of this disclosure, the graphic layout tool can also be used to limit the maximum and minimum height limits of each title in the graphic element, and to limit the maximum and minimum height limits of all titles in the graphic element.

[0223] In some embodiments of this disclosure, the graphic layout tool can also be used to implement various grid layout styles by using a hierarchical grouping and nested area division method.

[0224] In some embodiments of this disclosure, the graphic layout tool can also be used to perform any of the above embodiments (e.g., Figures 1-21 The operation of the graphic layout method described in any embodiment.

[0225] To address the shortcomings of related technologies, the present invention proposes an intelligent graphic layout tool. By using the concept of logical blocks, complex design layers can be decomposed into independent design units. Each unit has the ability to self-select type and self-calculate size and position based on the environment. These independent design units are named logical blocks. Logical blocks are selected sequentially in multiple queues according to their selection probability for multi-level generalization, ultimately creating a layout design effect with rich structural hierarchy.

[0226] Figure 23 This is a schematic diagram illustrating the structure of some embodiments of the computer device disclosed herein. For example... Figure 23 As shown, the computer device includes a memory 210 and a processor 220.

[0227] Memory 210 is used to store instructions, and processor 220 is coupled to memory 210. Processor 220 is configured to execute instructions stored in memory as described in any of the above embodiments (e.g., Figures 1-21 The graphic layout method described in any embodiment.

[0228] like Figure 23 As shown, the computer device also includes a communication interface 230 for exchanging information with other devices. Additionally, the computer device includes a bus 240, through which the processor 220, communication interface 230, and memory 210 communicate with each other.

[0229] The memory 210 may include high-speed RAM, and may also include non-volatile memory, such as at least one disk storage device. The memory 210 may also be a memory array. The memory 210 may also be divided into blocks, and the blocks may be combined into virtual volumes according to certain rules.

[0230] Furthermore, processor 220 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present disclosure.

[0231] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided, wherein the non-transitory computer-readable storage medium stores computer instructions that, when executed by a processor, implement any of the embodiments described above (e.g., Figures 1-21 The graphic layout method described in any embodiment.

[0232] According to another aspect of this disclosure, a computer program product is provided, comprising a computer program and / or computer instructions and / or computer program instructions, wherein the computer program and / or computer instructions and / or computer program instructions, when executed by a processor, implement any of the embodiments described above (e.g., Figures 1-21 The steps of the graphic layout method described in any embodiment.

[0233] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, apparatus, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable non-transitory storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0234] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0235] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0236] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0237] The graphic layout device described above can be implemented as a general-purpose processor, programmable logic controller (PLC), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component or any suitable combination thereof for performing the functions described herein.

[0238] This concludes the detailed description of the present disclosure. To avoid obscuring the concept of the disclosure, some details known in the art have not been described. Those skilled in the art will fully understand how to implement the technical solutions disclosed herein based on the above description.

[0239] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program instructing the relevant hardware to implement them. The program can be stored in a non-transitory computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0240] The description in this disclosure is provided for illustrative and descriptive purposes only and is not intended to be exhaustive or to limit the disclosure to its forms. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to better illustrate the principles and practical application of this disclosure and to enable those skilled in the art to understand this disclosure and to design various embodiments with various modifications suitable for a particular purpose.

Claims

1. A method of typesetting, characterized by, The method comprises the following steps: analyzing the topological relationship of all primitives in the current layer stack of the design drawing to be processed, wherein the current layer stack comprises a plurality of layers, and each layer comprises a plurality of primitives; determining the current logical block corresponding to each primitive in the current layer stack according to the topological relationship, wherein the determination of the current logical block corresponding to each primitive in the current layer stack according to the topological relationship comprises: using a node scanner to perform global scanning on the entire topological relationship graph, and determining all logical blocks meeting the conditions in the queue according to the scanner; for each primitive, selecting the logical block with the maximum selection probability as the current logical block according to a topological matrix environment selector; determining the size and position of each primitive in the current layer stack according to the topological relationship and the current logical block corresponding to each primitive in the current layer stack, wherein the determination of the size and position of each primitive in the current layer stack according to the topological relationship and the current logical block corresponding to each primitive in the current layer stack comprises: extracting the logic in the current logical block according to the variable, obtaining all environmental variable parameters from the environment; bringing the environmental variable parameters into a parameter mapping network to calculate the size and position of the current logical block; adding the primitive corresponding to the current logical block to the current layer stack to calculate the next primitive until all queues are calculated.

2. The typesetting method of claim 1, wherein The analysis of the topological relationship of all primitives in the current layer stack of the design drawing to be processed comprises: classifying the plurality of layers in the current layer stack and dividing the queues to determine the queue type corresponding to each layer; establishing a topological relationship graph for the primitives of all layers; determining the node type, node relationship and node attribute of all primitives.

3. The typesetting method of claim 2, wherein The determination of the node relationship of all primitives comprises: determining the relationship between the primitives of different layers; determining the node relationship between the primitives of the same layer, wherein the node relationship between the primitives of the same layer comprises at least one of intersection, adjacency, blocking and surrounding.

4. The typesetting method of claim 3, wherein The determination of the node relationship between the primitives of the same layer comprises: dividing the plurality of primitives of the same layer into the same group.

5. The typesetting method according to any one of claims 1 to 4, wherein, The selection of the logical block with the maximum selection probability as the current logical block according to the topological matrix environment selector comprises: adopting a symbol rule filter to scan and judge the single node and node group; determining the selection probability of each logical block according to the decomposition vector of the primitive relationship matrix and the primitive size information vector; selecting the logical block with the maximum selection probability as the current logical block.

6. The typesetting method according to any one of claims 1 to 4, wherein, The calculation of the size and position of the current logical block by bringing the environmental variable parameters into the parameter mapping network comprises: obtaining the shape parameters of the primitive itself; determining the position and size parameters of the current logical block according to the environmental variable parameters and the shape parameters of the primitive itself.

7. The typesetting method according to any one of claims 1 to 4, wherein, Further comprising: pre-designing an integrated layout structure comprising a plurality of first-type logical blocks and a plurality of second-type logical blocks; selecting a corresponding number of first-type logical blocks and second-type logical blocks and corresponding position and size parameters of the logical blocks according to the requirements to generate the required layout structure.

8. The typesetting method according to any one of claims 1 to 4, wherein, Further comprising: determining the maximum width range of each line of text through the graphic boundary on both sides of the primitive; and / or, limiting the maximum height limit and minimum height limit of each title in the primitive, and limiting the maximum height limit and minimum height limit of all titles in the primitive.

9. The typesetting method according to any one of claims 1 to 4, wherein, Also included are: Using hierarchical grouping area division nesting mode, realize a variety of grid layout style.

10. A page composition device characterized by comprising: Included are: A topology relationship analysis module is configured to analyze topology relationships of all graph elements in a current layer stack of a design graph to be processed, wherein the current layer stack includes a plurality of layers, and each layer includes a plurality of graph elements; A logical block determination module is configured to determine, according to the topology relationships, a current logical block corresponding to each graph element in the current layer stack; A size and position determination module is configured to determine, according to the topology relationships and the current logical block corresponding to each graph element in the current layer stack, a size and position of each graph element in the current layer stack; The logical block determination module is configured to perform global scanning on the entire topology relationship graph using a node scanner, and determine all logical blocks meeting a condition in a scanner determination queue according to the scanner; for each graph element, a topology matrix environment selector is used to select a logical block with a maximum selection probability as the current logical block; The size and position determination module is configured to extract a logic according to a variable in the current logical block, obtain all environment variable parameters from an environment, and calculate the size and position of the current logical block by bringing the environment variable parameters into a parameter mapping network; the current logical block corresponding to the graph element is added to the current layer stack, and a next graph element is calculated until all queues are calculated.

11. A computer apparatus, comprising: Included are: A memory is configured to store instructions; A processor is configured to execute the instructions, so that the computer device implements the graphic text layout method according to any one of claims 1-9.

12. A non-transitory computer-readable storage medium, comprising: The non-transitory computer readable storage medium stores computer instructions, and the instructions are executed by the processor to implement the graphic text layout method according to any one of claims 1-9.

13. A computer program product comprising computer programs and / or instructions, characterized in that, The computer program and / or instructions are executed by the processor to implement the graphic text layout method according to any one of claims 1-9.

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