Display substrate, display and display substrate driving method

Abstract

The embodiments of the present application provide a display substrate, a display and a display substrate driving method. The display substrate includes: a first type of pixel row, a second type of pixel row, a first driving circuit, a second driving circuit, and at least one type of data signal source; a first GOA circuit is used to provide a start signal of a first frequency for the first type of pixel row; a second GOA circuit is used to provide a start signal of a second frequency for the second type of pixel row; at least one type of data signal source is used to provide data signals for the data signal circuits of the first type of pixel row and the second type of pixel row. The first type of pixel row can refresh the screen at a first frequency, and the second type of pixel row can refresh the screen at a second frequency, thereby achieving pixels in the same display substrate being refreshed at different refresh frequencies, which can reduce display power consumption and thus increase the standby time of the display product.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate, a display, and a display substrate driving method. Background Art

[0002] With the rapid development of semiconductor technology, AMOLED (Active-matrix organic light-emitting diode) display screens are used in various industries, such as mobile phones, bracelets, watches, car displays, laptops, TVs, etc. Refresh rate is an important parameter in the display screen. The refresh rate refers to the number of images displayed on the display screen per second. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a display substrate, a display and a display substrate driving method. The specific technical solutions are as follows:

[0004] In a first aspect, an embodiment of the present application provides a display substrate, including:

[0005] A first type of pixel row, a second type of pixel row, a first driving circuit, a second driving circuit, and at least one type of data signal source;

[0006] The first driving circuit is used to provide a start signal of a first frequency for the first type of pixel row; the second driving circuit is used to provide a start signal of a second frequency for the second type of pixel row;

[0007] The at least one type of data signal source is used to provide data signals for the data signal lines of the first type of pixel rows and the second type of pixel rows.

[0008] In a possible implementation, the first type of pixel rows constitute a first display area of ​​the display substrate, the second type of pixel rows constitute a second display area of ​​the display substrate, and the display area of ​​the display substrate includes the first display area and the second display area.

[0009] In a possible implementation manner, a display area composed of the first type of pixel rows and a display area composed of the second type of pixel rows are arranged overlappingly in the display substrate.

[0010] In a possible implementation, the at least one type of data signal source includes a first type of data signal source; the first type of data signal source is connected to the data signal line of the first type of pixel row through a first type of switch, and the first type of data signal source is also connected to the data signal line of the second type of pixel row through a second type of switch;

[0011] The display substrate also includes: a first control circuit and a second control circuit; the first control circuit is connected to the gate of the first type of switch; the second control circuit is connected to the gate of the second type of switch; wherein the first type of switch is used to control the on-off of the data signal circuit of the first type of pixel row, and the second type of switch is used to control the on-off of the data signal circuit of the second type of pixel row.

[0012] In a possible implementation manner, when the first-category pixel row and the second-category pixel row are refreshed at the same frequency, the duration of the time period corresponding to each image frame is the same;

[0013] For the time period corresponding to each image frame, the time period includes a first stage and a second stage; in the first stage of the time period, the first control circuit inputs a first voltage signal, the first type of switch is turned on, the first drive circuit inputs a start signal, the second control circuit inputs a second voltage signal, the second type of switch is turned off, and the second drive circuit does not input a start signal; in the second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is turned off, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is turned on, and the second drive circuit inputs a start signal.

[0014] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are different, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the duration of the time period corresponding to the second-category image frames is the same as the duration of the second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0015] For each time period corresponding to the first type of image frame, in a first stage of the time period, the first control circuit inputs a first voltage signal, the first type of switch is turned on, the first drive circuit inputs a start signal, the second control circuit inputs a second voltage signal, the second type of switch is turned off, and the second drive circuit does not input a start signal; in a second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is turned off, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is turned on, and the second drive circuit inputs a start signal;

[0016] For the time period corresponding to each frame of the second type of image frame, within the time period, the first control circuit inputs a second voltage signal, the first type of switch is disconnected, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is opened, and the second drive circuit inputs a start signal.

[0017] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the duration of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0018] For each time period corresponding to the first type of image frame, in a first stage of the time period, the first control circuit inputs a first voltage signal, the first type of switch is turned on, the first drive circuit inputs a start signal, the second control circuit inputs a second voltage signal, the second type of switch is turned off, and the second drive circuit does not input a start signal; in a second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is turned off, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is turned on, and the second drive circuit inputs a start signal;

[0019] For the time period corresponding to each frame of the second type of image frame, within the time period, the first control circuit inputs a second voltage signal, the first type of switch is disconnected, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is opened, and the second drive circuit inputs a start signal.

[0020] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the time period corresponding to the second-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0021] For each time period corresponding to the first type of image frame, in a first stage of the time period, the first control circuit inputs a first voltage signal, the first type of switch is turned on, the first drive circuit inputs a start signal, the second control circuit inputs a second voltage signal, the second type of switch is turned off, and the second drive circuit does not input a start signal; in a second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is turned off, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is turned on, and the second drive circuit inputs a start signal;

[0022] For each time period corresponding to the second type of image frame, in the first stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is disconnected, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is opened, and the second drive circuit does not input a start signal; in the second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is disconnected, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is opened, and the second drive circuit inputs a start signal.

[0023] In one possible embodiment, the at least one type of data signal source includes a first type of data signal source; the display substrate also includes a third control circuit, the third control circuit is connected to the gate of a third type of switch, the third type of switch is connected between the data signal circuit of the first type of pixel row and the data signal circuit of the second type of pixel row, and the first type of data signal source is connected to the data signal circuit of the second type of pixel row.

[0024] In a possible implementation manner, when the first-category pixel row and the second-category pixel row are refreshed at the same frequency, the duration of the time period corresponding to each image frame is the same;

[0025] For the time period corresponding to each image frame, the time period includes a first stage and a second stage; in the first stage of the time period, the third control circuit inputs a first voltage signal, the third type of switch is turned on, the data signal circuit of the first type of pixel row is connected with the data signal circuit of the second type of pixel row, the first drive circuit inputs a start signal, and the second drive circuit does not input a start signal; in the second stage of the time period, the third control circuit inputs a second voltage signal, the third type of switch is turned off, the data signal circuit of the first type of pixel row is disconnected from the data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal.

[0026] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are different, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the duration of the time period corresponding to the second-category image frames is the same as the duration of the second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0027] For each period corresponding to the first type of image frame, in the first stage of the period, the third control circuit inputs a first voltage signal, the third type switch is turned on, the data signal circuit of the first type of pixel row is connected with the data signal circuit of the second type of pixel row, the first drive circuit inputs a start signal, and the second drive circuit does not input a start signal; in the second stage of the period, the third control circuit inputs a second voltage signal, the third type switch is turned off, the data signal circuit of the first type of pixel row is disconnected from the data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal;

[0028] For the time period corresponding to each frame of the second type of image frame, within the time period, the third control circuit inputs a second voltage signal, the third type of switch is disconnected, the data signal circuit of the first type of pixel row is disconnected from the data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal.

[0029] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the duration of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0030] For each period corresponding to the first type of image frame, in the first stage of the period, the third control circuit inputs a first voltage signal, the third type switch is turned on, the data signal circuit of the first type of pixel row is connected with the data signal circuit of the second type of pixel row, the first drive circuit inputs a start signal, and the second drive circuit does not input a start signal; in the second stage of the period, the third control circuit inputs a second voltage signal, the third type switch is turned off, the data signal circuit of the first type of pixel row is disconnected from the data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal;

[0031] For the time period corresponding to each frame of the second type of image frame, within the time period, the third control circuit inputs a second voltage signal, the third type of switch is disconnected, the data signal circuit of the first type of pixel row is disconnected from the data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal.

[0032] In a possible implementation, the at least one type of data signal source includes a second type of data signal source and a third type of data signal source; the second type of data signal source is connected to the data signal line of the first type of pixel row, and the third type of data signal source is connected to the data signal line of the second type of pixel row.

[0033] In a possible implementation manner, when the first-category pixel row and the second-category pixel row are refreshed at the same frequency, the duration of the time period corresponding to each image frame is the same;

[0034] For each time period corresponding to an image frame, the time period includes a first stage and a second stage; in the first stage of the time period, the second type of data signal source outputs a data signal, the first drive circuit inputs a start signal, the third type of data signal source does not output a data signal, and the second drive circuit does not input a start signal; in the second stage of the time period, the second type of data signal source does not output a data signal, the first drive circuit does not input a start signal, the third type of data signal source outputs a data signal, and the second drive circuit inputs a start signal.

[0035] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are different, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the duration of the time period corresponding to the second-category image frames is the same as the duration of the second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0036] For each time period corresponding to the first type of image frame, in the first stage of the time period, the second type of data signal source outputs a data signal, the first driving circuit inputs a start signal, the third type of data signal source does not output a data signal, and the second driving circuit does not input a start signal; in the second stage of the time period, the second type of data signal source does not output a data signal, the first driving circuit does not input a start signal, the third type of data signal source outputs a data signal, and the second driving circuit inputs a start signal;

[0037] For each time period corresponding to the second type image frame, during the time period, the second type data signal source does not output a data signal, the first drive circuit does not input a start signal, the third type data signal source outputs a data signal, and the second drive circuit inputs a start signal.

[0038] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the duration of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0039] For each time period corresponding to the first type of image frame, in the first stage of the time period, the second type of data signal source outputs a data signal, the first driving circuit inputs a start signal, the third type of data signal source does not output a data signal, and the second driving circuit does not input a start signal; in the second stage of the time period, the second type of data signal source does not output a data signal, the first driving circuit does not input a start signal, the third type of data signal source outputs a data signal, and the second driving circuit inputs a start signal;

[0040] For each time period corresponding to the second type image frame, during the time period, the second type data signal source does not output a data signal, the first drive circuit does not input a start signal, the third type data signal source outputs a data signal, and the second drive circuit inputs a start signal.

[0041] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the time period corresponding to the second-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0042] For each time period corresponding to the first type of image frame, in the first stage of the time period, the second type of data signal source outputs a data signal, the first driving circuit inputs a start signal, the third type of data signal source does not output a data signal, and the second driving circuit does not input a start signal; in the second stage of the time period, the second type of data signal source does not output a data signal, the first driving circuit does not input a start signal, the third type of data signal source outputs a data signal, and the second driving circuit inputs a start signal;

[0043] For each time period corresponding to the second type of image frame, in the first stage of the time period, the second type of data signal source does not output a data signal, the first drive circuit does not input a start signal, the third type of data signal source outputs a data signal, and the second drive circuit does not input a start signal; in the second stage of the time period, the second type of data signal source does not output a data signal, the first drive circuit does not input a start signal, the third type of data signal source outputs a data signal, and the second drive circuit inputs a start signal.

[0044] In a second aspect, an embodiment of the present application provides a display screen, comprising any display substrate described in the present application.

[0045] In a third aspect, an embodiment of the present application provides a method for driving a display substrate, which is applied to any display substrate described in the present application, and the method includes:

[0046] Using the first driving circuit to provide a start signal of a first frequency for the first type of pixel rows, and using the at least one type of data signal source to provide a data signal for the data signal circuit of the first type of pixel rows, so as to enable the first type of pixel rows to be refreshed at a first frequency; and

[0047] The second driving circuit is used to provide a start signal of a second frequency for the second type of pixel rows, and the at least one type of data signal source is used to provide a data signal for the data signal circuit of the second type of pixel rows, so as to achieve refreshing of the second type of pixel rows at a second frequency.

[0048] In a possible implementation, the first driving circuit is used to provide a start signal of a first frequency for the first type of pixel rows, and the at least one type of data signal source is used to provide a data signal for the data signal circuit of the first type of pixel rows, so as to enable the first type of pixel rows to be refreshed at a first frequency; and the second driving circuit is used to provide a start signal of a second frequency for the second type of pixel rows, and the at least one type of data signal source is used to provide a data signal for the data signal circuit of the second type of pixel rows, so as to enable the second type of pixel rows to be refreshed at a second frequency, including:

[0049] Using the first driving circuit to provide a start signal of a first frequency to the first type of pixel row, using the first control circuit to control the first type of switch to be turned on, and using the second control circuit to control the second type of switch to be turned off; when the first type of switch is turned on, using the first type of data signal source to provide a data signal to the data signal circuit of the first type of pixel row, so as to enable the first type of pixel row to be refreshed at a first frequency; and

[0050] The second driving circuit is used to provide a start signal of a second frequency for the second type of pixel row, the second control circuit is used to control the second type of switch to be turned on, and the first control circuit is used to control the first type of switch to be turned off; when the second type of switch is turned on, the first type of data signal source is used to provide a data signal to the data signal circuit of the second type of pixel row, so as to achieve refreshing of the second type of pixel row at a second frequency.

[0051] In a possible implementation, the first driving circuit is used to provide a start signal of a first frequency for the first type of pixel rows, and the at least one type of data signal source is used to provide a data signal for the data signal circuit of the first type of pixel rows, so as to enable the first type of pixel rows to be refreshed at a first frequency; and the second driving circuit is used to provide a start signal of a second frequency for the second type of pixel rows, and the at least one type of data signal source is used to provide a data signal for the data signal circuit of the second type of pixel rows, so as to enable the second type of pixel rows to be refreshed at a second frequency, including:

[0052] Using the first driving circuit to provide a start signal of a first frequency to the first type of pixel row, using the third control circuit to control the third type of switch to turn on; when the third type of switch is turned on, using the first type of data signal source to provide a data signal to the data signal circuit of the first type of pixel row, so as to enable the first type of pixel row to be refreshed at a first frequency; and

[0053] The second driving circuit is used to provide a start signal of a second frequency for the second type of pixel row, the third control circuit is used to control the third type of switch to be closed, and the first type of data signal source is used to provide a data signal for the data signal circuit of the second type of pixel row, so as to achieve refreshing of the second type of pixel row at a second frequency.

[0054] Beneficial effects of the embodiments of the present application:

[0055] The display substrate, display and display substrate driving method provided in the embodiments of the present application can refresh the screen of the first type of pixel row at a first frequency, and refresh the screen of the second type of pixel row at a second frequency, thereby achieving pixels in the same display substrate being refreshed with different refresh frequencies.

[0056] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0058] Figure 1a A schematic diagram of a high frame rate game screen in the related art;

[0059] Figure 1b A schematic diagram of a live broadcast scene screen in the related technology;

[0060] Figure 2a This is a first schematic diagram of the display area in the embodiment of the present application;

[0061] Figure 2b A second schematic diagram of the display area in the embodiment of the present application;

[0062] Figure 3 A third schematic diagram of the display area in the embodiment of the present application;

[0063] Figure 4a This is a first schematic diagram of a display substrate in an embodiment of the present application;

[0064] Figure 4b A schematic diagram of the first display area in an embodiment of the present application;

[0065] Figure 5 This is a first schematic diagram of a refresh timing of a display substrate in an embodiment of the present application;

[0066] Figure 6a A second schematic diagram of a refresh timing of a display substrate in an embodiment of the present application;

[0067] Figure 6b A third schematic diagram of a refresh timing of a display substrate in an embodiment of the present application;

[0068] Figure 7 A fourth schematic diagram of a refresh timing of a display substrate in an embodiment of the present application;

[0069] Figure 8 A fifth schematic diagram of a refresh timing of a display substrate in an embodiment of the present application;

[0070] Fig. 9 is a second schematic diagram of a display substrate in an embodiment of the present application;

[0071] Fig.10 A sixth schematic diagram of a refresh timing of a display substrate in an embodiment of the present application;

[0072] Fig.11a A seventh schematic diagram of a refresh timing of a display substrate in an embodiment of the present application;

[0073] Fig.11b This is an eighth schematic diagram of a refresh timing of a display substrate in an embodiment of the present application;

[0074] Fig.12 A ninth schematic diagram of a refresh timing of a display substrate in an embodiment of the present application;

[0075] Fig.13a is a third schematic diagram of a display substrate in an embodiment of the present application;

[0076] Fig.13b This is a fourth schematic diagram of the display substrate in the embodiment of the present application. DETAILED DESCRIPTION

[0077] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0078] With the rapid development of semiconductor technology, AMOLED (Active-matrix organic light-emitting diode) display screens are used in various industries, such as mobile phones, bracelets, watches, car displays, laptops, TVs, etc. However, with the popularity of high-frame rate games, higher requirements are also placed on screen refresh rates. High-refresh and even ultra-high-refresh display screens are gradually required by various industries. However, the refresh rates required for display screens in different situations are different, such as Figure 1a In the high frame rate game screen shown, the game scene screen requires a higher refresh rate, while the game character attribute screen requires a lower refresh rate; for example, Figure 1b In the live broadcast scene shown, the anchor video screen requires a higher refresh rate, while the comment screen requires a lower refresh rate. In view of the above situation, if the display screen adopts a high refresh rate as a whole, it will be accompanied by higher display power consumption, resulting in a reduction in the standby time of the display product.

[0079] In view of this, an embodiment of the present application provides a display substrate, including:

[0080] A first type of pixel row, a second type of pixel row, a first driving circuit, a second driving circuit, and at least one type of Source signal source (data signal source);

[0081] The first driving circuit is used to provide a start signal of a first frequency for the first type of pixel row; the second driving circuit is used to provide a start signal of a second frequency for the second type of pixel row;

[0082] The at least one type of data signal source is used to provide data signals for the Data signal lines of the first type of pixel rows and the second type of pixel rows.

[0083] The first type of pixel row and the second type of pixel row can adopt the same or different manufacturing processes, the first driving circuit provides a GOA (Gate on Array, array substrate row driving circuit) start signal for the first type of pixel row, and the second driving circuit provides a GOA start signal for the second type of pixel row. The first driving circuit can provide a start signal of a first frequency, and the second driving circuit can provide a start signal of a second frequency. Therefore, the first type of pixel row can refresh the screen at the first frequency, and the second type of pixel row can refresh the screen at the second frequency, so that the pixels in the same display substrate are refreshed at different refresh frequencies, which can reduce display power consumption and increase the standby time of the display product.

[0084] The arrangement of the first type of pixel rows and the second type of pixel rows can be designed according to the needs of the actual scene. In a possible implementation, the display area of ​​the display substrate includes a first display area and a second display area, the first type of pixel rows are located in the first display area, and the second type of pixel rows are located in the second display area. The first type of pixel rows constitute the first display area of ​​the display substrate, and the second type of pixel rows constitute the second display area of ​​the display substrate. The positions of the first display area and the second display area in the display substrate can be customized according to actual conditions. In one example, Figure 2a As shown, the first display area is located above the second display area. In one example, Figure 2b As shown, the first display area is located below the second display area.

[0085] In an embodiment of the present application, the display area of ​​the display substrate includes a first display area and a second display area. The first display area and the second display area can be refreshed at different refresh frequencies, which can be suitable for scenarios such as high frame rate games and live broadcasts where the refresh frequency requirements of the upper and lower screens are inconsistent, thereby reducing display power consumption and increasing the standby time of the display product.

[0086] The first type of pixel rows and the second type of pixel rows may also be arranged in an overlapping manner. In a possible implementation, the display area composed of the first type of pixel rows and the display area composed of the second type of pixel rows are arranged in an overlapping manner in the display substrate. In an example, Figure 3 As shown, for the watch display, only the middle time display part requires a higher refresh frequency, while the other parts can use a lower refresh frequency. Therefore, an overlapping arrangement can be adopted to achieve different refresh frequencies for the time display part and other parts, thereby reducing display power consumption and increasing the standby time of the display product.

[0087] At least one type of data signal source may include only one type of data signal source, and the same type of data signal source is used in combination with a switch to provide Data signals to the first type of pixel rows and the second type of pixel rows respectively; at least one type of data signal source may also include two types of data signal sources, and the two types of data signal sources are used to provide Data signals to the first type of pixel rows and the second type of pixel rows respectively.

[0088] In a possible implementation manner, the at least one type of data signal source includes a first type of data signal source; the first type of data signal source is connected to the Data signal line of the first type of pixel row through a first type of switch, and the first type of data signal source is also connected to the Data signal line of the second type of pixel row through a second type of switch;

[0089] The display substrate also includes: a first control circuit and a second control circuit; the first control circuit is connected to the gate of the first type of switch; the second control circuit is connected to the gate of the second type of switch; wherein the first type of switch is used to control the on-off of the Data signal circuit of the first type of pixel row, and the second type of switch is used to control the on-off of the Data signal circuit of the second type of pixel row.

[0090] See also Figure 4a , the display area of ​​the display substrate includes a first display area D1 and a second display area D2, the first type of pixel row is located in the first display area D1, and the second type of pixel row is located in the second display area D2. S1 is a data line of the first type of data signal source, one pixel column in the display substrate corresponds to one first type of data signal source, and the same first type of data signal source corresponds to one pixel column in the display substrate, that is, the first type of data signal source i (the i-th first type of data signal source) corresponds to a pixel column i (the i-th pixel column) in the display substrate. Among them, 1≤i≤N is a positive integer greater than or equal to 1, and N is the total number of columns of the display substrate. For the first type of data signal source i, the data line Si of the first type of data signal source i is connected to the Data signal line of the i-th pixel in each first type of pixel row through the first type of switch. For example, if there are m first type pixel rows, then Si is connected to the Data signal lines of m pixels in D1; in addition, Si is also connected to the Data signal line of the i-th pixel in each second type of pixel row through the second type of switch. For example, if there are n second type pixel rows, then Si is connected to the Data signal line of n pixels in D2; wherein m and n are both positive integers. For example, the data line S1 of the first type of data signal source 1 is connected to the Data signal line S1-1 of the first pixel in the first type of pixel row through the first type of switch, and the data line S1 of the first type of data signal source 1 is also connected to the Data signal line S1-2 of the first pixel in the second type of pixel row through the second type of switch. The first control circuit mux1 is connected to the gate of the first type of switch, the second control circuit mux2 is connected to the gate of the second type of switch, the first drive circuit GOA1 is connected to the first type of pixel row in the first display area D1, and provides the first type of pixel row with a start signal STV1 of a first frequency, and the second drive circuit GOA2 is connected to the second type of pixel row in the first display area D2, and provides the second type of pixel row with a start signal STV2 of a second frequency. It can be understood that the positions of D1 and D2 can be interchanged, which is still within the protection scope of this application.

[0091] STV1 is the GOA start signal provided by the first driving circuit GOA1 to the D1 region, that is, the frequency of STV1 can determine the refresh frequency of the first type of pixel row in D1, and further control the refresh rate of the display substrate. In an example, the pixel driving circuit and the pixel circuit in D1 can be as follows: Figure 4bAs shown, CN is the first scanning control signal, CNB is the second scanning control signal, CLK1, CLK2, CLK3 are three clock signals, VGH_G is a DC high level signal, VGL_G is a DC low level signal, RST is a reset signal, VDD is the positive power supply, VSS is the negative power supply, Data is a data signal, and OUTPUT is the output signal of the pixel driving circuit. STV1 is input to the STV signal input terminal of the first first-class pixel row in D1, and the OUTPUT of the pixel driving circuit of the first first-class pixel row (first-class pixel row 1) outputs a control signal. The gate of the pixel circuit in the first-class pixel row 1 receives the control signal, and the pixel starts to refresh; at the same time, OUTPUT also serves as the STV signal of the pixel driving circuit of the next first-class pixel row (first-class pixel row 2). In addition to being the control signal of the gate of the pixel circuit of this row and the STV signal of the first-class pixel row 3, the OUTPUT of the first-class pixel row 2 also serves as the RST signal of the first-class pixel row 1. The same applies to other first-class pixel rows, which will not be repeated here. It can be seen that each time the first driving circuit provides the start signal STV1, the pixels in D1 are refreshed once. Therefore, when the first driving circuit provides the start signal STV1 at the first frequency, the pixels in D1 are refreshed at the first frequency. Similarly, the second driving circuit drives the pixels in D2 to refresh at the second frequency through the start signal STV2 of the second frequency. The principle is similar and will not be repeated here. Of course, the display substrate can also include multiple display areas and corresponding start signals STV.

[0092] Understandably, Figure 4b The circuit shown is only for the purpose of introducing the principle of pixel refresh, and is not intended to limit the application to only Figure 4b The circuit shown in FIG. 1 can be replaced by a pixel driving circuit and a pixel circuit in the related art by a person skilled in the art. Figure 4b Part or all of the circuits in it are still within the scope of protection of the present application. In one example, the driving circuit may be at least one of P-GOA, N-GOA, and EM-GOA. For example: the driving circuit for driving the P-type switch tube of the pixel circuit in the display area of ​​the display substrate is P-GOA, the driving circuit for driving the N-type switch tube of the pixel circuit in the display area of ​​the display substrate is N-GOA, and the driving circuit for driving the light-emitting control transistor of the pixel circuit in the display area of ​​the display substrate is EM-GOA. Correspondingly, the start signal STV may be one of the P-GOA start signal, the N-GOA start signal, and the EM-GOA start signal.

[0093] In the embodiment of the present application, the GOA control unit is divided into two groups, GOA1 provides the gate signal of the first display area D1, and GOA2 provides the gate signal of the second display area D2. The signals of the same data source are divided into two groups, S1-1 controls the Data signal of the second display area D2, and S1-2 controls the Data signal of the first display area D1. The data signals of the first display area and the second display area are respectively input through mux1 and mux2, that is, the number of the first type of data signal source IC (microelectronic components) is consistent with the number of pixel columns in the display substrate. For example, if the number of pixel columns in the display substrate is W, then W first type data signal sources, W first type switches and W second type switches are required. In the embodiment of the present application, W pixel columns correspond to W first type data signal sources, and there is no need to increase the data of the first type data signal source, which can reduce the cost of the display substrate.

[0094] In the display substrate Figure 4a In the case shown, the first voltage signal and the second voltage signal are signals with opposite high and low levels. The levels of the first voltage signal and the second voltage signal can be set according to actual conditions and are related to the types of the first type of switch and the second type of switch; the refresh time of each pixel row 1H = 1 / (D1 number of pixel rows*D1 refresh frequency+D2 number of pixel rows*refresh frequency).

[0095] In a possible implementation manner, when the first-category pixel row and the second-category pixel row are refreshed at the same frequency, the duration of the time period corresponding to each image frame is the same;

[0096] For the time period corresponding to each image frame, the time period includes a first stage and a second stage; in the first stage of the time period, the first control circuit inputs a first voltage signal, the first type of switch is turned on, the first drive circuit inputs a start signal, the second control circuit inputs a second voltage signal, the second type of switch is turned off, and the second drive circuit does not input a start signal; in the second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is turned off, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is turned on, and the second drive circuit inputs a start signal.

[0097] In an example, taking the first voltage signal as a low level, the second voltage signal as a high level, and the refresh frequency as 60 Hz, the timing of STV1, STV2, mux1, and mux2 and the screen refresh conditions can be as follows: Figure 5As shown, when D1 and D2 are refreshed at the same frequency, for any frame, in the first stage, mux1 inputs a low level and the first type of switch is turned on, D1 is refreshed, mux2 inputs a high level and the second type of switch is turned off, and D2 is not refreshed; in the second stage, mux1 inputs a high level and the first type of switch is turned off, D1 is not refreshed, mux2 inputs a low level and the second type of switch is turned on, and D2 is refreshed; 1H=1 / (D1 pixel row number 1000*60Hz+D2 pixel row number 1000*60Hz)=8.33us.

[0098] In the embodiment of the present application, the display area is divided into D1 and D2, and the two areas are driven by independent driving circuits. When D1 and D2 are refreshed at high frequency (for example, 120Hz, 165Hz, 240Hz, etc.) at the same time, the number of pixel rows in each area is less than the total number of pixel rows in the entire display area, so the data writing time is extended, which is conducive to improving the high-frequency display quality. And when the same type of data signal source is used, the input of the Data signal in D1 and D2 is controlled by two types of switches respectively, which can reduce the mutual influence of the Data signal in the D1 and D2 areas, thereby improving the display quality.

[0099] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are different, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the duration of the time period corresponding to the second-category image frames is the same as the duration of the second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0100] For each time period corresponding to the first type of image frame, in a first stage of the time period, the first control circuit inputs a first voltage signal, the first type of switch is turned on, the first drive circuit inputs a start signal, the second control circuit inputs a second voltage signal, the second type of switch is turned off, and the second drive circuit does not input a start signal; in a second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is turned off, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is turned on, and the second drive circuit inputs a start signal;

[0101] For the time period corresponding to each frame of the second type of image frame, within the time period, the first control circuit inputs a second voltage signal, the first type of switch is disconnected, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is opened, and the second drive circuit inputs a start signal.

[0102] When D1 and D2 are refreshed at different frequencies, in an example, the refresh frequency of D1 is 30Hz and the refresh frequency of D2 is 60Hz, as an example, the timing and screen refresh of STV1, STV2, mux1, mux2 can be as follows Figure 6a As shown, the first type of image frame is an image frame in which both the first type of pixel row and the second type of pixel row are refreshed, that is, the first frame, the third frame, the fifth frame, etc.; the second type of image frame is an image frame in which the first type of pixel row is not refreshed and the second type of pixel row is refreshed, that is, the second frame, the fourth frame, the sixth frame, etc.; the duration of the corresponding period of the second frame is the same as the duration of the second stage in the first frame. For example: the working time of STV1 and STV2 does not overlap (the time for providing low level is staggered), and the working time of mux1 and mux2 does not overlap. In addition, the working time of mux2 is proportional to the frequency of STV2, and the working time of mux1 is proportional to the frequency of STV1, that is, the frequency of STV2 = P*STV1 frequency, then the working time of mux2 = P*mux1 working time, P is a natural number greater than 0.

[0103] For example: the first frame: in the first stage, mux1 inputs a low level, the first switch is turned on, mux2 inputs a high level, the second switch is turned off, D1 is refreshed, D2 is not refreshed, D1 refreshes and enters the second stage, mux1 inputs a high level, the first switch is turned off, mux2 inputs a low level, the second switch is turned on, and D2 starts to refresh; in the second frame, mux1 inputs a high level, the first switch is continuously turned off, the D1 screen remains unchanged, mux2 inputs a low level, the second switch is continuously turned on, and D2 continues to refresh at 60Hz; the third frame: in the first stage, mux1 inputs a low level, the first switch is turned on, mux2 inputs a high level, the second switch is turned off, D1 continues to refresh at 30Hz, the D1 display area is refreshed and enters the second stage, mux1 inputs a high level, the first switch is turned off, mux2 inputs a low level, the second switch is turned on, and D2 starts to refresh; the fourth frame is similar to the second frame, and refreshes are repeated in sequence. In this case, 1H = 1 / (D1 pixel row number 1000*30Hz+D2 pixel row number 1000*60Hz) = 11.11us.

[0104] When D1 and D2 are refreshed at different frequencies, in an example, taking D1 refresh frequency as 1Hz and D2 refresh frequency as 60Hz, the timing and screen refresh of STV1, STV2, mux1, mux2 can be as follows Figure 6bAs shown, the first type of image frame is an image frame in which both the first type of pixel row and the second type of pixel row are refreshed, that is, the first frame, the sixty-first frame, etc.; the second type of image frame is an image frame in which the first type of pixel row is not refreshed and the second type of pixel row is refreshed, that is, the second frame, the third frame, the fourth frame, etc.; the duration of the corresponding period of the second frame is the same as the duration of the second stage in the first frame. First frame: In the first stage, mux1 inputs a low level and the first type of switch is turned on, mux2 inputs a high level and the second type of switch is turned off, D1 is refreshed, and D2 is not refreshed. After D1 is refreshed, it enters the second stage, mux1 inputs a high level and the first type of switch is turned off, mux2 inputs a low level and the second type of switch is turned on, D1 is not refreshed, and D2 is refreshed; from the second frame to the sixtieth frame, mux1 inputs a high level and the first type of switch is continuously turned off, the D1 picture remains unchanged, mux2 inputs a low level and the second type of switch is continuously turned on, and the D2 picture is refreshed; the sixty-first frame is similar to the first frame, and the sixty-second frame to the one hundred and twentieth frame are similar to the second frame, and they are refreshed repeatedly in sequence. In this case, 1H=1 / (number of D1 pixel rows 1000*1Hz+number of D2 pixel rows 1000*60Hz)=16.39us.

[0105] In the embodiment of the present application, pixels in the same display substrate are refreshed using different refresh frequencies, which can reduce display power consumption and thus increase the standby time of the display product; and when the same type of data signal source is used, the input of the Data signal in D1 and D2 is controlled by two types of switches respectively, which can reduce the mutual influence of the Data signal in the D1 and D2 areas, thereby improving the display quality.

[0106] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the duration of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0107] For each time period corresponding to the first type of image frame, in a first stage of the time period, the first control circuit inputs a first voltage signal, the first type of switch is turned on, the first drive circuit inputs a start signal, the second control circuit inputs a second voltage signal, the second type of switch is turned off, and the second drive circuit does not input a start signal; in a second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is turned off, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is turned on, and the second drive circuit inputs a start signal;

[0108] For the time period corresponding to each frame of the second type of image frame, within the time period, the first control circuit inputs a second voltage signal, the first type of switch is disconnected, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is opened, and the second drive circuit inputs a start signal.

[0109] When D1 and D2 are refreshed at different frequencies, in an example, taking D1 refresh frequency as 1Hz and D2 refresh frequency as 60Hz, the timing and screen refresh of STV1, STV2, mux1, mux2 can be as follows Figure 7 As shown, the first type of image frames are image frames in which both the first type of pixel rows and the second type of pixel rows are refreshed, that is, the first frame, the sixty-first frame, etc.; the second type of image frames are image frames in which the first type of pixel rows are not refreshed and the second type of pixel rows are refreshed, that is, the second frame, the third frame, the fourth frame, etc.; the length of the corresponding time period of the second frame is the same as the length of the corresponding time period of the first frame. First frame: In the first stage, mux1 inputs a low level and the first switch is turned on, mux2 inputs a high level and the second switch is turned off, D1 is refreshed, and D2 is not refreshed. After D1 is refreshed, it enters the second stage, mux1 inputs a high level and the first switch is turned off, mux2 inputs a low level and the second switch is turned on, D1 is not refreshed, and D2 is refreshed; From the second frame to the sixtieth frame, in the first stage, mux1 inputs a high level and the first switch is continuously turned off, the D1 screen remains unchanged, mux2 inputs a high level and the second switch is continuously turned off, the D2 screen does not refresh, and in the second stage, mux1 inputs a high level and the first switch is continuously turned off, the D1 screen remains unchanged, mux2 inputs a low level and the second switch is continuously turned on, and the D2 screen is refreshed; The sixty-first frame is similar to the first frame, and the sixty-second frame to the one hundred and twentieth frame are similar to the second frame, and they are refreshed repeatedly in sequence. The corresponding time period of each frame is the same, the first frame: D1 and D2 are written and refreshed in sequence; From the second frame to the sixtieth frame, D1 is not refreshed, and only D2 is written and refreshed in the same time as the first frame. Therefore, the high-frequency writing time of D2 from the second frame to the sixtieth frame is longer, which is conducive to high-frequency refresh. The time period corresponding to each frame is the same. In the first frame, D1 and D2 are written and refreshed in sequence. From the second frame to the sixtieth frame, D1 is not refreshed, and only D2 is written and refreshed within the same time as the first frame. Therefore, the high-frequency writing time of D2 from the second frame to the sixtieth frame is longer, which is conducive to high-frequency refresh.

[0110] In a possible manner, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the time period corresponding to the second-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0111] For each time period corresponding to the first type of image frame, in a first stage of the time period, the first control circuit inputs a first voltage signal, the first type of switch is turned on, the first drive circuit inputs a start signal, the second control circuit inputs a second voltage signal, the second type of switch is turned off, and the second drive circuit does not input a start signal; in a second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is turned off, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is turned on, and the second drive circuit inputs a start signal;

[0112] For each time period corresponding to the second type of image frame, in the first stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is disconnected, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is opened, and the second drive circuit does not input a start signal; in the second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is disconnected, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is opened, and the second drive circuit inputs a start signal.

[0113] When D1 and D2 are refreshed at different frequencies, in an example, taking D1 refresh frequency as 1Hz and D2 refresh frequency as 60Hz, the timing and screen refresh of STV1, STV2, mux1, mux2 can be as follows Figure 8As shown, the first type of image frame is an image frame in which both the first type of pixel row and the second type of pixel row are refreshed, that is, the first frame, the sixty-first frame, etc.; the second type of image frame is an image frame in which the first type of pixel row is not refreshed and the second type of pixel row is refreshed, that is, the second frame, the third frame, the fourth frame, etc.; the duration of the corresponding period of the second frame is the same as the duration of the corresponding period of the first frame. First frame: In the first stage, mux1 inputs a low level and the first type of switch is turned on, mux2 inputs a high level and the second type of switch is turned off, D1 is refreshed, and D2 is not refreshed. After D1 is refreshed, it enters the second stage, mux1 inputs a high level and the first type of switch is turned off, mux2 inputs a low level and the second type of switch is turned on, D1 is not refreshed, and D2 is refreshed; from the second frame to the sixtieth frame, mux1 inputs a high level and the first type of switch is continuously turned off, the D1 picture remains unchanged, mux2 inputs a low level and the second type of switch is continuously turned on, and D2 is refreshed at 60Hz; the sixty-first frame is similar to the first frame, and the sixty-second frame to the one hundred and twentieth frame are similar to the second frame, and they are refreshed repeatedly in sequence. The time period corresponding to each frame is the same. In the first frame: D1 and D2 are written and refreshed in sequence; from the second frame to the sixtieth frame, the D1 display area is not refreshed, and D2 is only written and refreshed in the second stage, and the writing time is kept unchanged.

[0114] In the embodiment of the present application, pixels in the same display substrate are refreshed using different refresh frequencies, which can reduce display power consumption and thus increase the standby time of the display product; and when the same type of data signal source is used, the input of the Data signal in D1 and D2 is controlled by two types of switches respectively, which can reduce the mutual influence of the Data signal in the D1 and D2 areas, thereby improving the display quality.

[0115] In one possible implementation, the at least one type of data signal source includes a first type of data signal source; the display substrate also includes a third control circuit, the third control circuit is connected to the gate of a third type of switch, the third type of switch is connected between the Data signal circuit of the first type of pixel row and the Data signal circuit of the second type of pixel row, and the first type of data signal source is connected to the Data signal circuit of the second type of pixel row.

[0116] See also Fig. 9, the display area of ​​the display substrate includes a first display area D1 and a second display area D2, the first type of pixel row is located in the first display area D1, and the second type of pixel row is located in the second display area D2. sn is the data line of the nth first type of data signal source, sm is the data line of the mth first type of data signal source, one pixel column in the display substrate corresponds to one first type of data signal source, and the same first type of data signal source corresponds to one pixel column in the display substrate, that is, the first type of data signal source i (the i-th first type of data signal source) corresponds to a pixel column i (the i-th pixel column) in the display substrate. For the first type of data signal source i, the data line Si of the first type of data signal source i is connected to the Data signal line of the i-th pixel in the second type of pixel row, and then connected to the Data signal line of the i-th pixel in the second type of pixel row through the third type of switch. The third control circuit mux is connected to the gate of the third type of switch, the first drive circuit GOA1 is connected to the first type of pixel row in the first display area D1, and provides a start signal STV1 of a first frequency to the first type of pixel row, and the second drive circuit GOA2 is connected to the second type of pixel row in the first display area D2, and provides a start signal STV2 of a second frequency to the second type of pixel row.

[0117] In the embodiment of the present application, the GOA control unit is divided into two groups. GOA1 provides the gate signal of the first display area D1, and GOA2 provides the gate signal of the second display area D2. A transistor (third type switch) is added between the Data signal lines of D1 and D2. The transistor controls whether D1 needs to be refreshed, and the gate of the transistor is controlled by the third control circuit mux. When the transistor is turned on, the Data signal line between D1 and D2 is connected, and both D1 and D2 can receive the Data signal from the first type of data signal source; when the transistor is turned off, the Data signal line between D1 and D2 is disconnected, D1 keeps the previous display without refreshing, and D2 is refreshed. The refresh of D1 and D2 at different frequencies is achieved through the third control circuit and the third type of switch, and Figure 4a In comparison, it can reduce one control line and one type of switch, which can reduce production costs.

[0118] In a possible implementation manner, when the first-category pixel row and the second-category pixel row are refreshed at the same frequency, the duration of the time period corresponding to each image frame is the same;

[0119] For the time period corresponding to each image frame, the time period includes a first stage and a second stage; in the first stage of the time period, the third control circuit inputs a first voltage signal, the third type of switch is turned on, the Data signal circuit of the first type of pixel row is connected to the Data signal circuit of the second type of pixel row, the first drive circuit inputs a start signal, and the second drive circuit does not input a start signal; in the second stage of the time period, the third control circuit inputs a second voltage signal, the third type of switch is turned off, the Data signal circuit of the first type of pixel row is disconnected from the Data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal.

[0120] In an example, taking the first voltage signal as a low level, the second voltage signal as a high level, and the refresh frequency as 60 Hz, the timing of STV1, STV2, and mux and the screen refresh can be as follows: Fig.10 As shown, Mux is turned on in the STV2 refresh phase. For any frame, in the first phase, mux inputs a low-level third-type switch to turn on, STV1 inputs a start signal, STV2 does not input a start signal, D1 is refreshed, and D2 is not refreshed; in the second phase, mux inputs a draft-level third-type switch to disconnect, D1 is not refreshed, STV2 inputs a start signal, and D2 is refreshed, 1H = 1 / (D1 pixel row number 1000*60Hz+D2 pixel row number 1000*60Hz) = 8.33us.

[0121] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are different, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the duration of the time period corresponding to the second-category image frames is the same as the duration of the second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0122] For each period corresponding to the first type of image frame, in the first stage of the period, the third control circuit inputs a first voltage signal, the third type switch is turned on, the Data signal circuit of the first type of pixel row is connected to the Data signal circuit of the second type of pixel row, the first drive circuit inputs a start signal, and the second drive circuit does not input a start signal; in the second stage of the period, the third control circuit inputs a second voltage signal, the third type switch is turned off, the Data signal circuit of the first type of pixel row is disconnected from the Data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal;

[0123] For each time period corresponding to the second type of image frame, during the time period, the third control circuit inputs a second voltage signal, the third type of switch is disconnected, the Data signal circuit of the first type of pixel row is disconnected from the Data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal.

[0124] When D1 and D2 are refreshed at different frequencies, in an example, the refresh frequency of D1 is 30Hz and the refresh frequency of D2 is 60Hz, the timing of STV1, STV2, mux and the screen refresh can be as follows Fig.11a As shown, the first type of image frame is an image frame in which both the first type of pixel row and the second type of pixel row are refreshed, that is, the first frame, the third frame, the fifth frame, etc.; the second type of image frame is an image frame in which the first type of pixel row is not refreshed and the second type of pixel row is refreshed, that is, the second frame, the fourth frame, the sixth frame, etc.; the duration of the corresponding period of the second frame is the same as the duration of the second stage in the first frame. First frame: In the first stage, the mux inputs a low level third type switch to open, STV1 inputs a start signal, STV2 does not input a start signal, D1 is refreshed, and D2 is not refreshed; D1 is refreshed and enters the second stage, the mux inputs a high level third type switch to close, D1 is not refreshed, STV2 inputs a start signal, and D2 is refreshed. In the second frame, the mux inputs a high level and the third type switch is continuously closed, the D1 picture remains unchanged, STV1 inputs a start signal, and D2 continues to refresh at 60Hz; in the third frame: in the first stage, the mux inputs a low level and the third type switch is turned on, STV1 inputs a start signal, STV2 does not input a start signal, D1 is refreshed, and D2 is not refreshed; D1 refreshes and enters the second stage after the refresh is completed, the mux inputs a high level and the third type switch is closed, D1 is not refreshed, STV2 inputs a start signal, and D2 is refreshed; the fourth frame is similar to the second frame, and the refresh is repeated in sequence. In this case, 1H = 1 / (D1 pixel row number 1000*30Hz + D2 pixel row number 1000*60Hz) = 11.11us.

[0125] When D1 and D2 are refreshed at different frequencies, in an example, taking D1 refresh frequency as 1Hz and D2 refresh frequency as 60Hz, the timing and screen refresh of STV1, STV2, mux can be as follows Fig.11bAs shown, the first type of image frame is an image frame in which both the first type of pixel row and the second type of pixel row are refreshed, that is, the first frame, the sixty-first frame, etc.; the second type of image frame is an image frame in which the first type of pixel row is not refreshed and the second type of pixel row is refreshed, that is, the second frame, the third frame, the fourth frame, etc.; the duration of the corresponding period of the second frame is the same as the duration of the second stage in the first frame. First frame: mux inputs a low level third type switch to open, STV1 inputs a start signal, STV2 does not input a start signal, D1 is refreshed, and D2 is not refreshed; D1 refreshes and enters the second stage after the refresh is completed, mux inputs a high level third type switch to close, D1 is not refreshed, STV2 inputs a start signal, and D2 is refreshed; from the second frame to the sixtieth frame, mux inputs a high level third type switch to close continuously, the D1 picture remains unchanged, STV1 inputs a start signal, and D2 continues to refresh at 60Hz; the sixty-first frame is similar to the first frame, and the sixty-second frame to the one hundred and twentieth frame are similar to the second frame, and they are refreshed repeatedly in sequence. In this case, 1H=1 / (number of D1 pixel rows 1000*1Hz+number of D2 pixel rows 1000*60Hz)=16.39us.

[0126] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the duration of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0127] For each period corresponding to the first type of image frame, in the first stage of the period, the third control circuit inputs a first voltage signal, the third type switch is turned on, the Data signal circuit of the first type of pixel row is connected to the Data signal circuit of the second type of pixel row, the first drive circuit inputs a start signal, and the second drive circuit does not input a start signal; in the second stage of the period, the third control circuit inputs a second voltage signal, the third type switch is turned off, the Data signal circuit of the first type of pixel row is disconnected from the Data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal;

[0128] For each time period corresponding to the second type of image frame, during the time period, the third control circuit inputs a second voltage signal, the third type of switch is disconnected, the Data signal circuit of the first type of pixel row is disconnected from the Data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal.

[0129] When D1 and D2 are refreshed at different frequencies, in an example, taking D1 refresh frequency as 1Hz and D2 refresh frequency as 60Hz, the timing and screen refresh of STV1, STV2, mux can be as follows Fig.12 As shown, the first type of image frame is an image frame in which both the first type of pixel row and the second type of pixel row are refreshed, that is, the first frame, the sixty-first frame, etc.; the second type of image frame is an image frame in which the first type of pixel row is not refreshed and the second type of pixel row is refreshed, that is, the second frame, the third frame, the fourth frame, etc.; the duration of the corresponding period of the second frame is the same as the duration of the corresponding period of the first frame. First frame: mux inputs a low level third type switch to open, STV1 inputs a start signal, STV2 does not input a start signal, D1 is refreshed, and D2 is not refreshed; D1 refreshes and enters the second stage after the refresh is completed, mux inputs a high level third type switch to close, D1 is not refreshed, STV2 inputs a start signal, and D2 is refreshed; from the second frame to the sixtieth frame, mux inputs a high level third type switch to continue to close, the D1 picture remains unchanged, STV1 inputs a start signal, and D2 continues to refresh at 60Hz; the sixty-first frame is similar to the first frame, and the sixty-second frame to the one hundred and twentieth frame are similar to the second frame, and they are refreshed repeatedly in sequence. The time period corresponding to each frame is the same. In the first frame: D1 and D2 are written and refreshed in sequence. From the second frame to the sixtieth frame, D1 is not refreshed, and only D2 is written and refreshed in the same time as the first frame. Therefore, the high-frequency writing time of D2 from the second frame to the sixtieth frame is longer, which is conducive to high-frequency refresh. The time period corresponding to each frame is the same. In the first frame: D1 and D2 are written and refreshed in sequence. From the second frame to the sixtieth frame, D1 is not refreshed, and only D2 is written and refreshed in the same time as the first frame. Therefore, the high-frequency writing time of D2 from the second frame to the sixtieth frame is longer, which is conducive to high-frequency refresh.

[0130] The following describes the case where the at least one type of data signal source includes two types of data signal sources:

[0131] In a possible implementation, the at least one type of data signal source includes a second type of data signal source and a third type of data signal source; the second type of data signal source is connected to the Data signal line of the first type of pixel row, and the third type of data signal source is connected to the Data signal line of the second type of pixel row.

[0132] The display area of ​​the display substrate includes a first display area D1 and a second display area D2. The first type of pixel row is located in the first display area D1, and the second type of pixel row is located in the second display area D2. One pixel column in D1 corresponds to one second type of data signal source, and similarly one second type of data signal source corresponds to one pixel column in D1, that is, the second type of data signal source i corresponds to the i-th pixel column in D1 one by one; one pixel column in D2 corresponds to one third type of data signal source, and similarly one third type of data signal source corresponds to one pixel column in D2, that is, the third type of data signal source i corresponds to the i-th pixel column in D2 one by one. S2-i is the Data line of the i-th pixel column in D2, S1-i is the Data line of the i-th pixel column in D1, the data line of the i-th second type of data signal source (second type of data signal source i) is connected to S1-i, and the data line of the i-th third type of data signal source (third type of data signal source i) is connected to S2-i. For example, the data line of the third type data signal source 1 is connected to the Data signal line S2-1 of the first pixel column in D2, and the data line of the second type data signal source 1 is connected to the Data signal line S1-1 of the first pixel column in D1. The first driving line GOA1 is connected to the first type of pixel row in the first display area D1, and provides a first frequency start signal STV1 for the first type of pixel row. The second driving line GOA2 is connected to the second type of pixel row in the first display area D2, and provides a second frequency start signal STV2 for the second type of pixel row. In an example, Fig.13a As shown, the second type of data signal source and the third type of data signal source can be located on the same side of the display area (including D1 and D2), and at this time, the length of the pixel column Data signal line S1-1 in D1 corresponding to the data line of the second type of data signal source 1 is greater than the length of the pixel column Data signal line S2-1 in D2 corresponding to the data line of the third type of data signal source 1. In addition, the routing length of STV1 is greater than the routing length of STV2.

[0133] Alternatively, in an example, Fig.13b As shown, the second type of data signal source and the third type of data signal source can be located on both sides (different sides) of the display area. It can be understood that the positions of D1 and D2 can be interchanged, which is still within the protection scope of the present application. Among them, the pixel column Data signal line S1-1 in D1 corresponding to the data line of the second type of data signal source 1, and the pixel column Data signal line S2-1 in D2 corresponding to the data line of the third type of data signal source 1 are both disconnected at the boundary between D1 and D2, saving unnecessary redundant wiring of each pixel column.

[0134] Because D1 and D2 use independent data signal sources and drive circuits respectively, D1 and D2 can be logically regarded as two independent screens. Both of them can use their own data signal sources and drive circuits to complete the refresh of their own areas. Of course, they can also use the screen refresh method when there is only one data signal source.

[0135] In a possible implementation, when the first type of pixel rows and the second type of pixel rows are refreshed at the same frequency, the duration of the time period corresponding to each image frame is the same; for the time period corresponding to each image frame, the time period includes a first stage and a second stage; in the first stage of the time period, the second type of data signal source outputs a Data signal, the first drive circuit inputs a start signal, the third type of data signal source does not output a Data signal, and the second drive circuit does not input a start signal; in the second stage of the time period, the second type of data signal source does not output a Data signal, the first drive circuit does not input a start signal, the third type of data signal source outputs a Data signal, and the second drive circuit inputs a start signal.

[0136] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are different, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the duration of the time period corresponding to the second-category image frames is the same as the duration of the second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0137] For each period corresponding to the first type of image frame, in the first stage of the period, the second type of data signal source outputs a Data signal, the first driving circuit inputs a start signal, the third type of data signal source does not output a Data signal, and the second driving circuit does not input a start signal; in the second stage of the period, the second type of data signal source does not output a Data signal, the first driving circuit does not input a start signal, the third type of data signal source outputs a Data signal, and the second driving circuit inputs a start signal;

[0138] For each time period corresponding to the second type image frame, during the time period, the second type data signal source does not output a Data signal, the first drive circuit does not input a start signal, the third type data signal source outputs a Data signal, and the second drive circuit inputs a start signal.

[0139] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the duration of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0140] For each period corresponding to the first type of image frame, in the first stage of the period, the second type of data signal source outputs a Data signal, the first driving circuit inputs a start signal, the third type of data signal source does not output a Data signal, and the second driving circuit does not input a start signal; in the second stage of the period, the second type of data signal source does not output a Data signal, the first driving circuit does not input a start signal, the third type of data signal source outputs a Data signal, and the second driving circuit inputs a start signal;

[0141] For each time period corresponding to the second type image frame, during the time period, the second type data signal source does not output a Data signal, the first drive circuit does not input a start signal, the third type data signal source outputs a Data signal, and the second drive circuit inputs a start signal.

[0142] In a possible implementation, when the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the time period corresponding to the second-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed;

[0143] For each period corresponding to the first type of image frame, in the first stage of the period, the second type of data signal source outputs a Data signal, the first driving circuit inputs a start signal, the third type of data signal source does not output a Data signal, and the second driving circuit does not input a start signal; in the second stage of the period, the second type of data signal source does not output a Data signal, the first driving circuit does not input a start signal, the third type of data signal source outputs a Data signal, and the second driving circuit inputs a start signal;

[0144] For each time period corresponding to the second type of image frame, in the first stage of the time period, the second type of data signal source does not output the Data signal, the first drive circuit does not input the start signal, the third type of data signal source outputs the Data signal, and the second drive circuit does not input the start signal; in the second stage of the time period, the second type of data signal source does not output the Data signal, the first drive circuit does not input the start signal, the third type of data signal source outputs the Data signal, and the second drive circuit inputs the start signal.

[0145] In addition, an embodiment of the present application provides a display screen, comprising any display substrate described in the present application.

[0146] Then, an embodiment of the present application provides a method for driving a display substrate, which is applied to any display substrate described in the present application, and the method includes:

[0147] Using the first driving circuit to provide a start signal of a first frequency for the first type of pixel rows, and using the at least one type of data signal source to provide a data signal for the data signal circuit of the first type of pixel rows, so as to enable the first type of pixel rows to be refreshed at a first frequency; and

[0148] The second driving circuit is used to provide a start signal of a second frequency for the second type of pixel rows, and the at least one type of data signal source is used to provide a data signal for the data signal circuit of the second type of pixel rows, so as to achieve refreshing of the second type of pixel rows at a second frequency.

[0149] In a possible implementation, the first driving circuit is used to provide a start signal of a first frequency for the first type of pixel rows, and the at least one type of data signal source is used to provide a data signal for the data signal circuit of the first type of pixel rows, so as to enable the first type of pixel rows to be refreshed at a first frequency; and the second driving circuit is used to provide a start signal of a second frequency for the second type of pixel rows, and the at least one type of data signal source is used to provide a data signal for the data signal circuit of the second type of pixel rows, so as to enable the second type of pixel rows to be refreshed at a second frequency, including:

[0150] Using the first driving circuit to provide a start signal of a first frequency to the first type of pixel row, using the first control circuit to control the first type of switch to be turned on, and using the second control circuit to control the second type of switch to be turned off; when the first type of switch is turned on, using the first type of data signal source to provide a data signal to the data signal circuit of the first type of pixel row, so as to enable the first type of pixel row to be refreshed at a first frequency; and

[0151] The second driving circuit is used to provide a start signal of a second frequency for the second type of pixel row, the second control circuit is used to control the second type of switch to be turned on, and the first control circuit is used to control the first type of switch to be turned off; when the second type of switch is turned on, the first type of data signal source is used to provide a data signal to the data signal circuit of the second type of pixel row, so as to achieve refreshing of the second type of pixel row at a second frequency.

[0152] In a possible implementation, the first driving circuit is used to provide a start signal of a first frequency for the first type of pixel rows, and the at least one type of data signal source is used to provide a data signal for the data signal circuit of the first type of pixel rows, so as to enable the first type of pixel rows to be refreshed at a first frequency; and the second driving circuit is used to provide a start signal of a second frequency for the second type of pixel rows, and the at least one type of data signal source is used to provide a data signal for the data signal circuit of the second type of pixel rows, so as to enable the second type of pixel rows to be refreshed at a second frequency, including:

[0153] Using the first driving circuit to provide a start signal of a first frequency to the first type of pixel row, using the third control circuit to control the third type of switch to turn on; when the third type of switch is turned on, using the first type of data signal source to provide a data signal to the data signal circuit of the first type of pixel row, so as to enable the first type of pixel row to be refreshed at a first frequency; and

[0154] The second driving circuit is used to provide a start signal of a second frequency for the second type of pixel row, the third control circuit is used to control the third type of switch to be closed, and the first type of data signal source is used to provide a data signal for the data signal circuit of the second type of pixel row, so as to achieve refreshing of the second type of pixel row at a second frequency.

[0155] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0156] Each embodiment in this specification is described in a related manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referenced to each other.

[0157] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A display substrate, characterized in that: include: A first type of pixel row, a second type of pixel row, a first driving circuit, a second driving circuit, and at least one type of data signal source; The first driving circuit is used to provide a start signal of a first frequency for the first type of pixel row; The second driving circuit is used to provide a start signal of a second frequency for the second type of pixel rows; The at least one type of data signal source is used to provide data signals for the data signal lines of the first type of pixel rows and the second type of pixel rows; The first type of pixel rows constitute a first display area of ​​the display substrate, the second type of pixel rows constitute a second display area of ​​the display substrate, and the display area of ​​the display substrate includes the first display area and the second display area; The at least one type of data signal source includes a first type of data signal source; the first type of data signal source is connected to the data signal line of the first type of pixel row through a first type of switch, and the first type of data signal source is also connected to the data signal line of the second type of pixel row through a second type of switch; The display substrate further includes a first control circuit, a second control circuit and a third control circuit, wherein the first control circuit is connected to the gate of the first type of switch; The second control circuit is connected to the gate of the second type of switch; wherein the first type of switch is used to control the on and off of the data signal circuit of the first type of pixel row, and the second type of switch is used to control the on and off of the data signal circuit of the second type of pixel row, and the third control circuit is connected to the gate of the third type of switch, and the third type of switch is connected between the data signal circuit of the first type of pixel row and the data signal circuit of the second type of pixel row.

2. The display substrate according to claim 1, characterized in that: The display area formed by the first type of pixel rows and the display area formed by the second type of pixel rows are overlapped and arranged in the display substrate.

3. The display substrate according to claim 1, characterized in that: When the first type of pixel rows and the second type of pixel rows are refreshed at the same frequency, the duration of the time period corresponding to each image frame is the same; For each time period corresponding to an image frame, the time period includes a first stage and a second stage; in the first stage of the time period, the first control circuit inputs a first voltage signal, the first type of switch is turned on, the first drive circuit inputs a start signal, the second control circuit inputs a second voltage signal, the second type of switch is turned off, and the second drive circuit does not input a start signal; In the second stage of this period, the first control circuit inputs a second voltage signal, the first type switch is disconnected, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type switch is opened, and the second drive circuit inputs a start signal.

4. The display substrate according to claim 1, characterized in that: In the case where the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are different, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the duration of the time period corresponding to the second-category image frames is the same as the duration of the second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed; For each time period corresponding to the first type of image frame, in a first stage of the time period, the first control circuit inputs a first voltage signal, the first type of switch is turned on, the first drive circuit inputs a start signal, the second control circuit inputs a second voltage signal, the second type of switch is turned off, and the second drive circuit does not input a start signal; in a second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is turned off, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is turned on, and the second drive circuit inputs a start signal; For the time period corresponding to each frame of the second type of image frame, within the time period, the first control circuit inputs a second voltage signal, the first type of switch is disconnected, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is opened, and the second drive circuit inputs a start signal.

5. The display substrate according to claim 1, characterized in that: In the case where the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames where both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames where the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed; For each time period corresponding to the first type of image frame, in a first stage of the time period, the first control circuit inputs a first voltage signal, the first type of switch is turned on, the first drive circuit inputs a start signal, the second control circuit inputs a second voltage signal, the second type of switch is turned off, and the second drive circuit does not input a start signal; in a second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is turned off, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is turned on, and the second drive circuit inputs a start signal; For the time period corresponding to each frame of the second type of image frame, within the time period, the first control circuit inputs a second voltage signal, the first type of switch is disconnected, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is opened, and the second drive circuit inputs a start signal.

6. The display substrate according to claim 1, characterized in that: In the case where the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the time period corresponding to the second-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames where both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames where the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed; For each time period corresponding to the first type of image frame, in a first stage of the time period, the first control circuit inputs a first voltage signal, the first type of switch is turned on, the first drive circuit inputs a start signal, the second control circuit inputs a second voltage signal, the second type of switch is turned off, and the second drive circuit does not input a start signal; in a second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is turned off, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is turned on, and the second drive circuit inputs a start signal; For each time period corresponding to the second type of image frame, in the first stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is disconnected, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is opened, and the second drive circuit does not input a start signal; in the second stage of the time period, the first control circuit inputs a second voltage signal, the first type of switch is disconnected, the first drive circuit does not input a start signal, the second control circuit inputs a first voltage signal, the second type of switch is opened, and the second drive circuit inputs a start signal.

7. The display substrate according to claim 1, characterized in that: When the first type of pixel rows and the second type of pixel rows are refreshed at the same frequency, the duration of the time period corresponding to each image frame is the same; For each period corresponding to an image frame, the period includes a first stage and a second stage; in the first stage of the period, the third control circuit inputs a first voltage signal, the third type of switch is turned on, the data signal circuit of the first type of pixel row is connected to the data signal circuit of the second type of pixel row, the first drive circuit inputs a start signal, and the second drive circuit does not input a start signal; In the second stage of this period, the third control circuit inputs a second voltage signal, the third type of switch is disconnected, the data signal circuit of the first type of pixel row is disconnected from the data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal.

8. The display substrate according to claim 1, characterized in that: In the case where the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are different, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the duration of the time period corresponding to the second-category image frames is the same as the duration of the second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed; For each period corresponding to the first type of image frame, in the first stage of the period, the third control circuit inputs a first voltage signal, the third type switch is turned on, the data signal circuit of the first type of pixel row is connected with the data signal circuit of the second type of pixel row, the first drive circuit inputs a start signal, and the second drive circuit does not input a start signal; in the second stage of the period, the third control circuit inputs a second voltage signal, the third type switch is turned off, the data signal circuit of the first type of pixel row is disconnected from the data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal; For the time period corresponding to each frame of the second type of image frame, within the time period, the third control circuit inputs a second voltage signal, the third type of switch is disconnected, the data signal circuit of the first type of pixel row is disconnected from the data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal.

9. The display substrate according to claim 1, characterized in that: In the case where the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames where both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames where the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed; For each period corresponding to the first type of image frame, in the first stage of the period, the third control circuit inputs a first voltage signal, the third type switch is turned on, the data signal circuit of the first type of pixel row is connected with the data signal circuit of the second type of pixel row, the first drive circuit inputs a start signal, and the second drive circuit does not input a start signal; in the second stage of the period, the third control circuit inputs a second voltage signal, the third type switch is turned off, the data signal circuit of the first type of pixel row is disconnected from the data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal; For the time period corresponding to each frame of the second type of image frame, within the time period, the third control circuit inputs a second voltage signal, the third type of switch is disconnected, the data signal circuit of the first type of pixel row is disconnected from the data signal circuit of the second type of pixel row, the first drive circuit does not input a start signal, and the second drive circuit inputs a start signal.

10. The display substrate according to claim 1, characterized in that: The at least one type of data signal source includes a second type of data signal source and a third type of data signal source; the second type of data signal source is connected to the data signal line of the first type of pixel row, and the third type of data signal source is connected to the data signal line of the second type of pixel row.

11. The display substrate according to claim 10, characterized in that: When the first type of pixel rows and the second type of pixel rows are refreshed at the same frequency, the duration of the time period corresponding to each image frame is the same; For each time period corresponding to an image frame, the time period includes a first stage and a second stage; in the first stage of the time period, the second type of data signal source outputs a data signal, the first driving circuit inputs a start signal, the third type of data signal source does not output a data signal, and the second driving circuit does not input a start signal; In the second stage of this period, the second type of data signal source does not output a data signal, the first driving circuit does not input a start signal, the third type of data signal source outputs a data signal, and the second driving circuit inputs a start signal.

12. The display substrate according to claim 10, characterized in that: In the case where the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are different, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the duration of the time period corresponding to the second-category image frames is the same as the duration of the second stage; wherein the first-category image frames are image frames in which both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames in which the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed; For each time period corresponding to the first type of image frame, in the first stage of the time period, the second type of data signal source outputs a data signal, the first driving circuit inputs a start signal, the third type of data signal source does not output a data signal, and the second driving circuit does not input a start signal; in the second stage of the time period, the second type of data signal source does not output a data signal, the first driving circuit does not input a start signal, the third type of data signal source outputs a data signal, and the second driving circuit inputs a start signal; For each time period corresponding to the second type image frame, during the time period, the second type data signal source does not output a data signal, the first drive circuit does not input a start signal, the third type data signal source outputs a data signal, and the second drive circuit inputs a start signal.

13. The display substrate according to claim 10, characterized in that: In the case where the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames where both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames where the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed; For each time period corresponding to the first type of image frame, in the first stage of the time period, the second type of data signal source outputs a data signal, the first driving circuit inputs a start signal, the third type of data signal source does not output a data signal, and the second driving circuit does not input a start signal; in the second stage of the time period, the second type of data signal source does not output a data signal, the first driving circuit does not input a start signal, the third type of data signal source outputs a data signal, and the second driving circuit inputs a start signal; For each time period corresponding to the second type image frame, during the time period, the second type data signal source does not output a data signal, the first drive circuit does not input a start signal, the third type data signal source outputs a data signal, and the second drive circuit inputs a start signal.

14. The display substrate according to claim 10, characterized in that: In the case where the refresh frequency of the first-category pixel rows is lower than the refresh frequency of the second-category pixel rows, and the durations of the time periods corresponding to the first-category image frames and the second-category image frames are the same, the time period corresponding to the first-category image frames includes a first stage and a second stage, and the time period corresponding to the second-category image frames includes a first stage and a second stage; wherein the first-category image frames are image frames where both the first-category pixel rows and the second-category pixel rows are refreshed, and the second-category image frames are image frames where the first-category pixel rows are not refreshed and the second-category pixel rows are refreshed; For each time period corresponding to the first type of image frame, in the first stage of the time period, the second type of data signal source outputs a data signal, the first driving circuit inputs a start signal, the third type of data signal source does not output a data signal, and the second driving circuit does not input a start signal; in the second stage of the time period, the second type of data signal source does not output a data signal, the first driving circuit does not input a start signal, the third type of data signal source outputs a data signal, and the second driving circuit inputs a start signal; For each time period corresponding to the second type of image frame, in the first stage of the time period, the second type of data signal source does not output a data signal, the first drive circuit does not input a start signal, the third type of data signal source outputs a data signal, and the second drive circuit does not input a start signal; in the second stage of the time period, the second type of data signal source does not output a data signal, the first drive circuit does not input a start signal, the third type of data signal source outputs a data signal, and the second drive circuit inputs a start signal.

15. A display screen, characterized in that: Comprising the display substrate described in any one of claims 1-14.

16. A method for driving a display substrate, characterized in that: Applied to the display substrate according to any one of claims 1 to 14, the method comprising: Using the first driving circuit to provide a start signal of a first frequency for the first type of pixel rows, and using the at least one type of data signal source to provide a data signal for the data signal circuit of the first type of pixel rows, so as to enable the first type of pixel rows to be refreshed at a first frequency; and The second driving circuit is used to provide a start signal of a second frequency for the second type of pixel rows, and the at least one type of data signal source is used to provide a data signal for the data signal circuit of the second type of pixel rows, so as to achieve refreshing of the second type of pixel rows at a second frequency.

17. The method according to claim 16, characterized in that The method comprises: using the first driving circuit to provide a start signal of a first frequency for the first type of pixel rows, and using the at least one type of data signal source to provide a data signal for the data signal circuit of the first type of pixel rows, so as to enable the first type of pixel rows to be refreshed at a first frequency; and using the second driving circuit to provide a start signal of a second frequency for the second type of pixel rows, and using the at least one type of data signal source to provide a data signal for the data signal circuit of the second type of pixel rows, so as to enable the second type of pixel rows to be refreshed at a second frequency, including: Using the first driving circuit to provide a start signal of a first frequency to the first type of pixel row, using the first control circuit to control the first type of switch to be turned on, and using the second control circuit to control the second type of switch to be turned off; when the first type of switch is turned on, using the first type of data signal source to provide a data signal to the data signal circuit of the first type of pixel row, so as to enable the first type of pixel row to be refreshed at a first frequency; and The second driving circuit is used to provide a start signal of a second frequency for the second type of pixel row, the second control circuit is used to control the second type of switch to be turned on, and the first control circuit is used to control the first type of switch to be turned off; when the second type of switch is turned on, the first type of data signal source is used to provide a data signal to the data signal circuit of the second type of pixel row, so as to achieve refreshing of the second type of pixel row at a second frequency.

18. The method according to claim 16, characterized in that The method comprises: using the first driving circuit to provide a start signal of a first frequency for the first type of pixel rows, and using the at least one type of data signal source to provide a data signal for the data signal circuit of the first type of pixel rows, so as to enable the first type of pixel rows to be refreshed at a first frequency; and using the second driving circuit to provide a start signal of a second frequency for the second type of pixel rows, and using the at least one type of data signal source to provide a data signal for the data signal circuit of the second type of pixel rows, so as to enable the second type of pixel rows to be refreshed at a second frequency, including: Using the first driving circuit to provide a start signal of a first frequency to the first type of pixel row, using the third control circuit to control the third type of switch to turn on; when the third type of switch is turned on, using the first type of data signal source to provide a data signal to the data signal circuit of the first type of pixel row, so as to enable the first type of pixel row to be refreshed at a first frequency; and The second driving circuit is used to provide a start signal of a second frequency for the second type of pixel row, the third control circuit is used to control the third type of switch to be closed, and the first type of data signal source is used to provide a data signal for the data signal circuit of the second type of pixel row, so as to achieve refreshing of the second type of pixel row at a second frequency.

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