A heat dissipation structure and fabrication method for a three-dimensional stacked chip packaging substrate

Abstract

This invention discloses a heat dissipation structure and fabrication method for a three-dimensional stacked chip packaging substrate, comprising: a top bare chip, an intermediate bare chip, and a bottom bare chip. One end face of the bottom bare chip is bonded to the intermediate bare chip, and the other end face of the intermediate bare chip is bonded to the top bare chip. A flip chip is bonded to the other end face of the bottom bare chip. The flip chip is bonded to one end face of the packaging substrate. Wire bonding signal lines are bonded to the top bare chip and the packaging substrate. A first wire bonding ground line is bonded to the intermediate bare chip and the packaging substrate. A grounding heat dissipation solder pad is disposed on the packaging substrate. A grounding heat sink is connected to the grounding heat dissipation solder pad. The grounding heat sink is connected to the top bare chip and the intermediate bare chip via a second wire bonding ground line. The beneficial effects of this invention are: the grounding heat dissipation solder pad concentrates the heat of all chips, which not only improves the heat dissipation efficiency of the three-dimensional stacked packaging but also reduces the heat dissipation space.

Description

Technical Field

[0001] This invention relates to the field of semiconductor heat dissipation technology, specifically to a heat dissipation structure for a three-dimensional stacked chip packaging substrate and its fabrication method. Background Technology

[0002] With technological advancements and improvements in chip manufacturing processes, electronic products are increasingly moving towards higher integration and miniaturization. Improved chip manufacturing processes mean that more transistors can be integrated within the same area, leading to increased chip performance but also higher power consumption. Simultaneously, due to electron migration and quantum tunneling effects, chip manufacturing processes are approaching physical limitations, making chip miniaturization increasingly difficult. Against this backdrop, engineers have developed multi-chip 3D stacking technology, which involves stacking chips with different functions in layers along the Z-axis of a packaging substrate. The chips are connected to the substrate using wire bonding or flip-chip technology. The 3D stacking of different functional chips means a concentration of power consumption and heat. Effectively dissipating this concentrated heat becomes a design challenge for 3D stacked chips. In nature, heat transfer occurs through convection, conduction, and thermal radiation. Inside the package, heat is transferred via conduction, while outside the chip, heat dissipation is primarily achieved through the addition of heat sinks, heat pipes, or cooling fans.

[0003] However, existing technologies have the following drawbacks: While internal interposers can be added between different chip layers to increase heat dissipation within a 3D stacked chip package, their use only applies to Flip Chip technology. When multiple chip layers are stacked, the heat dissipation of the upper chip remains poor. Externally, adding heat sinks, heat pipes, or cooling fans requires specific space and a dedicated heat dissipation channel. Without external heat dissipation devices, the device's heat dissipation performance is significantly reduced. Furthermore, with external heat dissipation devices, the heat sink or cooling fan becomes a dipole antenna, and common-mode radiated current radiates into free space, worsening the device's EMC. Summary of the Invention

[0004] The technical problems to be solved by this invention are: insufficient heat dissipation efficiency of conventional three-dimensional stacked packaging; insufficient space due to the addition of a cooling fan for heat dissipation at the top of conventional three-dimensional stacked packaging; and spatial radiation problems caused by common-mode coupling when adding a cooling fan. The purpose of this invention is to provide a heat dissipation structure for a three-dimensional stacked chip packaging substrate and its manufacturing method, which solves the problem of rapid heat dissipation of three-dimensional stacked chips.

[0005] This invention is achieved through the following technical solution:

[0006] A heat dissipation structure for a three-dimensional stacked chip packaging substrate includes:

[0007] Top-level bare chip;

[0008] intermediate layer bare chip;

[0009] The bottom bare chip has one end face attached to the middle layer bare chip, the other end face of the middle layer bare chip is attached to the top bare chip, and a flip chip is attached to the other end face of the bottom bare chip.

[0010] A packaging substrate, one end face of which is attached to the flip chip, a wire bond signal line is bonded to the top bare chip and the packaging substrate, and a first wire bond ground line is bonded to the middle layer bare chip and the packaging substrate.

[0011] A grounding heat dissipation solder strip is used to transfer heat from the bare chip to the outside of the packaging substrate. The grounding heat dissipation solder strip is disposed on the packaging substrate.

[0012] A grounding heat sink is used to conduct heat generated by the bare chip. The grounding heat sink is connected to the grounding heat sink solder strip and is connected to the top layer bare chip and the middle layer bare chip through a second lead bonding ground wire.

[0013] The wire bonding signal line and the first wire bonding ground line are directly bonded to the grounding heat sink, or the wire bonding signal line and the first wire bonding ground line are bonded to the grounding heat sink through the second wire bonding ground line.

[0014] The other end of the packaging substrate is connected to a BGA solder ball, and the lower end of the BGA solder ball is connected to the printed circuit board.

[0015] The BGA solder balls are arranged in a rectangular array between the packaging substrate and the printed circuit board.

[0016] The rectangular array of grounding heat dissipation solder strips is distributed on the packaging substrate, and the grounding heat dissipation solder strips are parallel to the outer contour edge of the packaging substrate.

[0017] The packaging substrate has buried copper vias, and the grounding heat dissipation solder strip is soldered to the BGA solder ball through the buried copper vias. The BGA solder ball is soldered to the printed circuit board.

[0018] The upper end of the grounding heat sink has a flat grounding bonding wire strip, which is directly bonded to the lead bonding signal line and the first lead bonding ground line, or the flat grounding bonding wire strip is bonded to the lead bonding signal line and the first lead bonding ground line through the second lead bonding ground line.

[0019] The flat grounding solder strip is parallel to the packaging substrate or printed circuit board.

[0020] A method for fabricating a heat dissipation structure for a three-dimensional stacked chip packaging substrate includes the following steps:

[0021] Step 1): Create a series of buried copper vias near the outer contour edge of the packaging substrate, solder BGA solder balls to the lower end of the buried copper vias, and solder the lower end of the BGA solder balls to the printed circuit board.

[0022] Step 2): Connect the grounding heat dissipation strip to the grounding heat sink using a bonding method;

[0023] Step 3): The second wire bonding ground wire is bonded to the top bare chip and the middle bare chip. The second wire bonding ground wire (14) is also bonded to the ground heat sink. The wire bonding signal wire is bonded to the top bare chip and the packaging substrate. The first wire bonding ground wire is bonded to the middle bare chip and the packaging substrate.

[0024] Step 4): Bond the grounding heat sink to the package substrate;

[0025] Step 5): Pass the grounding heat dissipation strip through the buried copper through-hole and solder it to the printed circuit board. Connect the grounding heat dissipation strip to the thermal conductive material and connect it to the outside of the packaging substrate through the thermal conductive material.

[0026] Step 6): Package and test all chips on the packaging substrate.

[0027] In step 4), the grounding heat sink is made of silver-plated copper sheet material, and the grounding heat sink is bonded to the grounding heat sink strip on the packaging substrate.

[0028] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0029] 1. The grounding heat dissipation solder strip of the present invention is the convergence point of heat from all chips. The grounding heat dissipation solder strip converges the heat from all chips, namely the top bare chip, the middle bare chip, the bottom bare chip, the flip chip and the printed circuit board, which improves the heat dissipation efficiency of the three-dimensional stacked package. The heat dissipation using the grounding heat sink and the package substrate eliminates the space shortage problem caused by the addition of a cooling fan for heat dissipation at the top of the three-dimensional stacked package. Since no cooling fan is added, there is no spatial radiation problem caused by common-mode coupling of the cooling fan. The present invention not only improves the heat dissipation efficiency of the three-dimensional stacked package, but also reduces the heat dissipation space.

[0030] 2. The three-dimensional stacked package of the present invention has a highly efficient heat dissipation channel inside, and all the stacked chips are connected to the heat dissipation channel. Through the channel, most of the heat is efficiently conducted to the outside of the package, thereby improving the heat dissipation efficiency of the package. Specifically, the heat dissipation channel transfers the heat of the top layer bare chip and the middle layer bare chip to the ground heat sink. The ground heat sink transfers the heat of the top layer bare chip and the middle layer bare chip to the ground heat sink. The heat of the top layer bare chip and the middle layer bare chip is then transferred to the package substrate through the wire bonding signal line and the first wire bonding ground line, respectively. The package substrate then transfers the heat to the ground heat sink. The heat of the bottom layer bare chip and the flip chip is transferred to the ground heat sink through the package substrate. The heat of the printed circuit board is directly transferred to the ground heat sink. Finally, the ground heat sink transfers the heat of all the chips to the outside of the package substrate through the thermally conductive material.

[0031] 3. This invention adds a large-area grounding heat dissipation strip around the outer edge of a conventional packaging substrate, improving heat dissipation efficiency. The bonding wire length between the wire-bonded signal line and the first wire-bonded ground line is shortened by connecting the second wire-bonded ground line to the grounding heat sink. Buried copper vias are designed between the grounding heat dissipation solder pad and the BGA solder balls on the packaging substrate to increase the thermal conductivity of the grounding heat dissipation solder pad. The buried copper vias in the corresponding areas of the printed circuit board can be achieved by slotting and filling copper, designing large-area heat dissipation buried copper vias, or increasing the copper foil thickness within the buried copper vias, to quickly conduct heat from the chip to the outside of the packaging substrate.

[0032] 4. In this invention, both the top-layer bare chip and the middle-layer bare chip transfer heat to the grounded heat sink via the second wire bonding ground line; the top-layer bare chip and the middle-layer bare chip also transfer heat to the grounded heat sink via the wire bonding signal line and the first wire bonding ground line, respectively; the heat from the top-layer bare chip and the middle-layer bare chip can also be transferred to the grounded heat sink via the wire bonding signal line and the first wire bonding ground line, respectively, and then via the packaging substrate to the grounded heat sink solder strip. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0034] Figure 1 This is a side view of the three-dimensional stacked package of the present invention without heat sinks;

[0035] Figure 2 This is a top view of the three-dimensional stacked package of the present invention without heat sinks;

[0036] Figure 3 Side view of the three-dimensional stacked package of the present invention with heat sink added;

[0037] Figure 4 Top view of the invention with a grounded heat sink added;

[0038] Figure 5 A top view of the three-dimensional stacked package for adding heat sinks to this invention.

[0039] The attached diagram shows the markings and corresponding component names:

[0040] 1. Top layer bare chip, 2. Middle layer bare chip, 3. Bottom layer bare chip, 4. Flip chip, 5. Wire bond signal line, 6. First wire bond ground line, 7. Package substrate, 8. BGA solder ball, 9. Printed circuit board, 10. Package substrate power ring, 11. Grounding heat dissipation solder strip, 12. Grounding heat sink, 13. Buried copper via, 14. Second wire bond ground line, 15. Flat grounding solder strip. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0042] Example 1

[0043] like Figure 3-5 As shown, this embodiment provides a heat dissipation structure for a three-dimensional stacked chip packaging substrate, including: a top bare chip 1, a middle bare chip 2, and a bottom bare chip 3 (this invention describes a classic three-layer bare chip structure, but this heat dissipation method is also applicable to stacked designs with more than three layers). The upper surface of the bottom bare chip 3 is bonded to the middle bare chip 2, the upper surface of the middle bare chip 2 is bonded to the top bare chip 1, and a flip chip 4 is bonded to the lower surface of the bottom bare chip 3. The flip chip 4 is bonded to the upper surface of the packaging substrate 7, and wire bonding is used to attach the chips. Line 5 is bonded to the top bare chip 1 and the packaging substrate 7. The first lead ground wire 6 is bonded to the middle layer bare chip 2 and the packaging substrate 7. The ground heat dissipation solder ribbon 11 is used to transfer the heat of the bare chip to the outside of the packaging substrate 7. The ground heat dissipation solder ribbon 11 is disposed on the packaging substrate 7. The packaging substrate 7 is provided with buried copper vias 13. The ground heat dissipation solder ribbon 11 is soldered to the printed circuit board 9 through the buried copper vias 13. The ground heat sink 12 is used to conduct the heat generated by the bare chip. The ground heat sink 12 is connected to the ground heat dissipation solder ribbon 11.

[0044] The grounding heat sink 12 is bonded to the top bare chip 1 and the middle bare chip 2 via the second wire bonding ground line 14. The wire bonding signal line 5 and the first wire bonding ground line 6 are directly bonded to the grounding heat sink 12, or the wire bonding signal line 5 and the first wire bonding ground line 6 are bonded to the grounding heat sink 12 via the second wire bonding ground line 14. Both the top bare chip 1 and the middle bare chip 2 transfer heat to the grounding heat sink 12 via the second wire bonding ground line 14. The top bare chip 1 and the middle bare chip 2 then transfer heat to the grounding heat sink 12 via the wire bonding signal line 5 and the first wire bonding ground line 6, respectively. The heat from the top bare chip 1 and the middle bare chip 2 can also be transferred to the grounding heat dissipation solder strip 11 via the wire bonding signal line 5 and the first wire bonding ground line 6, respectively, and then via the packaging substrate 7.

[0045] BGA solder balls 8 are soldered to the lower end face of the packaging substrate 7, that is, BGA solder balls 8 are soldered to the lower end of the buried copper via 13. The BGA solder balls 8 are soldered to the printed circuit board 9. The BGA solder balls 8 are distributed in a rectangular array between the packaging substrate 7 and the printed circuit board 9.

[0046] The grounding heat dissipation solder strips 11 are arranged in a rectangular array on the packaging substrate 7, and the grounding heat dissipation solder strips 11 are parallel to the outer contour edge of the packaging substrate 7.

[0047] The upper end of the grounding heat sink 12 has a flat grounding bonding wire strip 15, which is directly bonded to the lead bonding signal line 5 and the first lead bonding ground line 6, or the flat grounding bonding wire strip 15 is bonded to the lead bonding signal line 5 and the first lead bonding ground line 6 through the second lead bonding ground line 14. The flat grounding bonding wire strip 15 is parallel to the packaging substrate 7 or the printed circuit board 9.

[0048] Example 2

[0049] A method for fabricating a heat dissipation structure for a three-dimensional stacked chip packaging substrate, applied to a heat dissipation structure for a three-dimensional stacked chip packaging substrate in Example 1, includes the following steps:

[0050] Step 1): A series of buried copper vias 13 are formed near the outer contour edge of the package substrate 7. BGA solder balls 8 are soldered to the lower end of the buried copper vias 13. The lower end of the BGA solder balls 8 is soldered to the printed circuit board 9.

[0051] Step 2): Connect the grounding heat dissipation strip 11 to the grounding heat dissipation plate 12 by bonding;

[0052] Step 3): The second wire bonding ground line 14 is bonded to the top bare chip 1 and the middle bare chip 2. The second wire bonding ground line 14 is also bonded to the ground heat sink 12. The wire bonding signal line 5 is bonded to the top bare chip 1 and the packaging substrate 7. The first wire bonding ground line 6 is bonded to the middle bare chip 2 and the packaging substrate 7.

[0053] Step 4): Bond the grounding heat sink 12 to the packaging substrate 7;

[0054] Step 5): Pass the grounding heat dissipation strip 11 through the buried copper through hole 13 and solder it to the printed circuit board 9. Connect the grounding heat dissipation strip 11 to the thermal conductive material and connect it to the outside of the packaging substrate 7 through the thermal conductive material.

[0055] Step 6): Package and test all chips on the packaging substrate 7.

[0056] Specifically, in step 4), the grounding heat sink 12 is made of silver-plated copper sheet material, and the grounding heat sink 12 is bonded to the grounding heat dissipation strip 11 on the packaging substrate 7.

[0057] The buried copper via 13 is formed on the packaging substrate 7. If the hole of the buried copper via 13 is large, a certain amount of copper can be buried in the hole before electroplating to fill it. If the hole of the buried copper via 13 is small, it can be directly electroplated to fill it. The silver-plated copper sheet of the grounding heat sink 12 is bonded to the grounding heat sink strip 11 of the packaging substrate 7. This bonding is atomic and different from ordinary welding, so no filler is required.

[0058] Wire bonding is a process that uses fine metal wires and leverages heat, pressure, and ultrasonic energy to tightly bond the metal wires to the substrate pads, enabling electrical interconnection and information exchange between chips and the substrate. Under ideal controlled conditions, electron sharing or atomic diffusion occurs between the wires and the substrate, resulting in atomic-level bonding between the two metals.

[0059] Example 3

[0060] like Figure 3-5As shown, the packaging substrate 7 has a grounding heat dissipation solder strip 11, which is the convergence point of heat from all the chips. The heat from the top bare chip 1 and the middle bare chip 2 is transferred to the grounding heat sink 12. The grounding heat sink 12 transfers the heat from the top bare chip 1 and the middle bare chip 2 to the grounding heat dissipation solder strip 11. The heat from the top bare chip 1 and the middle bare chip 2 is then transferred to the packaging substrate 7 through the wire bonding signal line 5 and the first wire bonding ground line 6, respectively. The packaging substrate 7 then transfers the heat to the grounding heat dissipation solder strip 11. The bottom bare chip 3 is attached to the flip chip 4, which is also attached to the packaging substrate 7. The heat from the bottom bare chip 3 and the flip chip 4 is transferred to the grounding heat dissipation solder strip 11 through the packaging substrate 7. The grounding heat dissipation solder strip 11 is connected to the printed circuit board 9 by filler. The heat from the printed circuit board 9 is directly transferred to the grounding heat dissipation solder strip 11. Finally, the grounding heat dissipation solder strip 11 transfers the heat from all the chips to the outside of the packaging substrate 7 through the thermally conductive material.

[0061] Example 4

[0062] This invention adds a large-area grounding heat dissipation strip 11 around the outer edge of a conventional packaging substrate 7, improving heat dissipation efficiency. The bonding wire length between the lead-bonded signal line 5 and the first lead-bonded ground line 6 is shortened by bonding the second lead-bonded ground line 14 to the grounding heat sink 12. Buried copper vias 13 are designed between the grounding heat dissipation solder strip 11 and the BGA solder balls 8 on the packaging substrate 7 to increase the thermal conductivity of the grounding heat dissipation solder strip 11. The buried copper vias 13 in the corresponding area of ​​the printed circuit board 9 can be designed by slotting and filling copper, creating a large-area heat dissipation buried copper via 13, or by increasing the copper foil thickness within the buried copper via 13, to quickly conduct the heat from the chip to the outside of the packaging substrate 7.

[0063] Example 5

[0064] The principle of this invention is as follows: The heat conduction problem of the chip can be designed using Fourier's Law. Since there is no air inside the chip after it is encapsulated in plastic, and the thermal conductivity of the encapsulation material is extremely low, the heat conduction of the chip can be considered only along the heat transfer path: chip - second lead bonding ground wire 14 - ground heat sink 12 - ground heat dissipation solder ribbon 11 - BGA solder ball 8 - printed circuit board 9. When the chip is operating stably, a one-dimensional steady-state series thermal conductivity analysis can be used, and the formula is:

[0065]

[0066] illustrate:

[0067] 1.Δt i -Temperature difference between material walls;

[0068] 2.δ i -Thickness of each material;

[0069] 3.λi - Thermal conductivity of each material;

[0070] 4. A - Average thermal conductivity area;

[0071] 5. Q - Heat flux (heat conducted through a unit area per unit time).

[0072] From the formula, we can see that λ i The larger the value of A, the larger the thermal conductivity and the average thermal conductivity area, the smaller the total thermal resistance, the larger the heat flux Q, and the stronger the heat dissipation capacity of the device.

[0073] Example 6

[0074] like Figure 1-2 As shown, this embodiment is relative to Figure 3-5 Compared with the previous embodiment, this embodiment does not have a grounding heat dissipation solder strip 11, a grounding heat sink 12, and a second lead bonding ground wire 14. In this embodiment, the power ring 10 of the packaging substrate is set at the upper end of the packaging substrate 7. The lead bonding signal line 5 and the first lead bonding ground wire 6 pass through the power ring 10 of the packaging substrate for heat dissipation. The bottom bare chip 3 and the flip chip 4 are cooled through the packaging substrate 7. It is not possible to cool all the chips in the same position. Therefore, the heat dissipation efficiency is low.

[0075] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A heat dissipation structure for a three-dimensional stacked chip packaging substrate, characterized in that, include: Top-level bare chip (1); Intermediate layer bare chip (2); Bottom bare chip (3), one end face of which is attached to the intermediate layer bare chip (2), the other end face of the intermediate layer bare chip (2) is attached to the top bare chip (1), and a flip chip (4) is attached to the other end face of the bottom bare chip (3). A packaging substrate (7) is attached to one end face of the flip chip (4), a wire bond signal line (5) is bonded to the top bare chip (1) and the packaging substrate (7), and a first wire bond ground line (6) is bonded to the middle layer bare chip (2) and the packaging substrate (7). A grounding heat dissipation strip (11) is used to transfer the heat of the bare chip to the outside of the packaging substrate (7), and the grounding heat dissipation strip (11) is disposed on the packaging substrate (7); The grounding heat sink (12) is used to conduct heat generated by the bare chip. The grounding heat sink (12) is connected to the grounding heat sink (11). The grounding heat sink (12) is bonded to the top bare chip (1) and the middle bare chip (2) through the second lead bonding ground wire (14). The encapsulation substrate (7) is provided with a buried copper via (13), and the grounding heat dissipation strip (11) is soldered to the BGA solder ball (8) through the buried copper via (13). The BGA solder ball (8) is soldered to the printed circuit board (9).

2. The heat dissipation structure of a three-dimensional stacked chip packaging substrate according to claim 1, characterized in that, The first lead-bonded ground wire (6) is directly bonded to the grounding heat sink (12), or the first lead-bonded ground wire (6) is bonded to the grounding heat sink (12) through the second lead-bonded ground wire (14).

3. The heat dissipation structure of a three-dimensional stacked chip packaging substrate according to claim 1, characterized in that, The other end face of the packaging substrate (7) is connected to a BGA solder ball (8), and the lower end of the BGA solder ball (8) is connected to the printed circuit board (9).

4. The heat dissipation structure of a three-dimensional stacked chip packaging substrate according to claim 3, characterized in that, The BGA solder balls (8) are arranged in a rectangular array between the packaging substrate (7) and the printed circuit board (9).

5. The heat dissipation structure of a three-dimensional stacked chip packaging substrate according to claim 1, characterized in that, The grounding heat dissipation strips (11) are arranged in a rectangular array on the packaging substrate (7), and the grounding heat dissipation strips (11) are parallel to the outer contour edge of the packaging substrate (7).

6. The heat dissipation structure of a three-dimensional stacked chip packaging substrate according to claim 1, characterized in that, The upper end of the grounding heat sink (12) has a flat grounding bonding wire strip (15), which is directly bonded to the first lead bonding ground wire (6), or the flat grounding bonding wire strip (15) is bonded to the first lead bonding ground wire (6) through the second lead bonding ground wire (14).

7. The heat dissipation structure of a three-dimensional stacked chip packaging substrate according to claim 6, characterized in that, The flat grounding solder strip (15) is parallel to the packaging substrate (7) or printed circuit board (9).

8. A method for fabricating a heat dissipation structure for a three-dimensional stacked chip packaging substrate, applied to the heat dissipation structure of the three-dimensional stacked chip packaging substrate described in claims 1-7, characterized in that, Includes the following steps: Step 1): A series of buried copper vias (13) are opened near the outer contour edge of the package substrate (7). BGA solder balls (8) are soldered to the lower end of the buried copper vias (13). The lower end of the BGA solder balls (8) is soldered to the printed circuit board (9). Step 2): Connect the grounding heat dissipation strip (11) to the grounding heat dissipation plate (12) by bonding; Step 3): The second wire bonding ground line (14) is bonded to the top bare chip (1) and the middle bare chip (2). The second wire bonding ground line (14) is also bonded to the ground heat sink (12). The wire bonding signal line (5) is bonded to the top bare chip (1) and the package substrate (7). The first wire bonding ground line (6) is bonded to the middle bare chip (2) and the package substrate (7). Step 4): Bond the grounding heat sink (12) to the packaging substrate (7); Step 5): Pass the grounding heat dissipation strip (11) through the buried copper through hole (13) and solder it to the printed circuit board (9). Connect the grounding heat dissipation strip (11) to the thermal conductive material and connect it to the outside of the packaging substrate (7) through the thermal conductive material. Step 6): Package and test all chips on the packaging substrate (7).

9. A method for fabricating a heat dissipation structure for a three-dimensional stacked chip packaging substrate according to claim 8, characterized in that, In step 4), the grounding heat sink (12) is made of silver-plated copper sheet material, and the grounding heat sink (12) and the grounding heat sink strip (11) on the packaging substrate (7) are bonded together.

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