Method for manufacturing gate oxide layer of sgt semiconductor device

Abstract

The application discloses a manufacturing method of an inter-gate oxide layer of an SGT semiconductor device, which comprises the following steps: step one, defining a gate trench by using a first hard mask layer and etching to form the gate trench; step two, forming a bottom dielectric layer and a shielding gate polysilicon; step three, forming a second inner sidewall on the side of the gate trench on the top of the bottom dielectric layer; step four, etching the bottom dielectric layer at the bottom of the second inner sidewall to expose the top area of the shielding gate polysilicon; step five, oxidizing the shielding gate polysilicon by using a first heat oxidation process and forming an inter-gate oxide layer; step six, removing the first hard mask layer and the second inner sidewall; and step seven, forming a gate dielectric layer and a gate conductive material layer. The thickness of the inter-gate oxide layer can be independent of the thickness of the gate dielectric layer, the thickness of the inter-gate oxide layer can be independently adjusted, a thicker and better-quality inter-gate oxide layer can be ensured, and the process flow is simple and the process difficulty is low.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit manufacturing method, in particular to a manufacturing method of an inter-gate oxide layer of a shield gate trench (SGT) semiconductor device. BACKGROUND

[0002] The most important process in an SGT semiconductor device such as an SGT MOSFET is the isolation process between the shield ploy and the poly gate in the gate trench. The isolation is generally performed by an oxide layer, which is referred to as an inter-poly oxide (IPO). The shield ploy is connected to the source electrode composed of a front metal layer, and is also referred to as a source ploy. The poly gate is connected to the gate electrode composed of a front metal layer. The thickness and stability of the IPO not only affect the isolation effect between the gate electrode and the source electrode, but also affect the input capacitance, and are therefore very important for the SGT process.

[0003] Currently, there are two main IPO manufacturing schemes, namely, a thermal oxidation process for forming an IPO and a high-density plasma (HDP) chemical vapor deposition (CVD) process for depositing an IPO.

[0004] In the thermal oxidation process for forming an IPO, after the source ploy at the bottom is formed, heavy ion implantation is performed to further form defects on the surface of the source ploy. The semiconductor material such as silicon at the side of the gate trench, i.e., the mesa sidewall channel region, remains a good single crystal structure. Then, a thermal oxidation process is performed to form an IPO on the top of the source ploy and a gate oxide layer (GOX) on the side of the gate trench. The defects on the surface of the source ploy are used to make the thickness of the IPO greater than the thickness of the GOX. This process has simple steps, but has a high process difficulty. Moreover, the thickness ratio of the IPO to the GOX is fixed, the thickness adjustment range is small, and this scheme is not suitable for thin gate oxide products. In addition, the top corner of the source ploy is prone to have a weak point of a significantly thin IPO.

[0005] In the HDP CVD process for depositing an IPO, the HDP CVD process is used to form an oxide layer to completely fill the gate trench. Then, the oxide layer is etched back to form an IPO with a desired thickness. In this process, the IPO thickness adjustment range is large and is not affected by the thickness of the GOX. However, the process steps are complicated and the cost is high. Moreover, due to the limitation of the HDP filling capacity, it is difficult to achieve a depth-to-width ratio greater than 3. The IPO thickness depends on the oxide layer etching back, and has a large fluctuation. SUMMARY

[0006] The technical problem solved by the present application is to provide a method for manufacturing an inter-gate oxide layer of an SGT semiconductor device, the thickness of the inter-gate oxide layer can be independent of the thickness of the gate dielectric layer and thus can be independently adjusted, and a thicker and better quality inter-gate oxide layer can be obtained, and the process flow is simple and the process difficulty is low.

[0007] To solve the above technical problem, the present application provides a method for manufacturing an inter-gate oxide layer of an SGT semiconductor device, which comprises the following steps:

[0008] Step one, a first hard mask layer is used to define a gate trench, and then the semiconductor substrate is etched to form a gate trench.

[0009] Step two, a bottom dielectric layer and a shield gate polysilicon are formed in the bottom region of the gate trench; the bottom dielectric layer is isolated between the shield gate polysilicon and the gate trench, the side surface of the gate trench at the top of the bottom dielectric layer is exposed; the first hard mask layer has a material layer different from that of the bottom dielectric layer.

[0010] Step three, a second inner sidewall is formed on the side surface of the gate trench at the top of the bottom dielectric layer, the material of the second inner sidewall is different from that of the bottom dielectric layer, and the thickness of the second inner sidewall is thinner than that of the bottom dielectric layer.

[0011] Step four, the bottom dielectric layer at the bottom of the second inner sidewall is etched with the first hard mask layer and the second inner sidewall as masks, so that the top region of the shield gate polysilicon is exposed above the top surface of the bottom dielectric layer.

[0012] Step five, the shield gate polysilicon is oxidized by a first thermal oxidation process to form an inter-gate oxide layer, and the first thermal oxidation process oxidizes from the side surface and the top surface of the top region of the shield gate polysilicon to increase the thickness of the inter-gate oxide layer.

[0013] Step six, the first hard mask layer and the second inner sidewall are removed.

[0014] Step seven, a gate dielectric layer is formed on the side surface of the gate trench with the inter-gate oxide layer, and a gate conductive material layer is filled in the gate trench.

[0015] Further improvement is that in step one, the semiconductor substrate comprises a silicon substrate.

[0016] Further improvement is that the material of the bottom dielectric layer comprises an oxide layer;

[0017] In step seven, the material of the gate dielectric layer comprises an oxide layer.

[0018] Further improvement is that the material of the gate conductive material layer comprises polysilicon.

[0019] Further improvement is that in step one, the first hard mask layer is a silicon nitride layer or a stack of silicon oxide, silicon nitride or a stack of silicon oxide, silicon nitride and silicon oxide.

[0020] In step three, the material of the second inner sidewall comprises silicon nitride.

[0021] Further improvement is that step two comprises the following sub-steps:

[0022] Step 21, forming the bottom dielectric layer covering the bottom surface and side surface of the gate trench and the surface outside the gate trench.

[0023] Step 22, forming the shield gate polysilicon, which completely fills the gate trench and extends to the surface of the bottom dielectric layer outside the gate trench.

[0024] Step 23, etching back the shield gate polysilicon to remove the shield gate polysilicon outside the gate trench and the shield gate polysilicon inside the gate trench is only located in the bottom region of the gate trench.

[0025] Step 24, etching the bottom dielectric layer so that the bottom dielectric layer is only located in the bottom region of the gate trench.

[0026] Further improvement is that after step 23 and before step 24, further comprising performing amorphous ion implantation to amorphize the lattice of the top region of the shield gate polysilicon.

[0027] Further improvement is that in step four, after the etching of the bottom dielectric layer at the bottom of the second inner sidewall is completed, the side surface of the gate trench in the region where the bottom dielectric layer at the bottom of the second inner sidewall is removed is exposed.

[0028] In step five, the first thermal oxidation process also oxidizes the exposed side surface of the gate trench at the bottom of the second inner sidewall and forms a third oxide layer.

[0029] Further improvement is that in step seven, the gate dielectric layer is formed on the side surface of the gate trench on top of the third oxide layer.

[0030] Further improvement is that there is a gap between the third oxide layer and the gate oxide layer, and the gate conductive material layer also fills in the gap between the third oxide layer and the gate oxide layer.

[0031] Further improvement is, in step seven, the gate dielectric layer is formed by a second thermal oxidation process.

[0032] The second thermal oxidation process thickens the inter-gate oxide layer.

[0033] Further improvement is, in step one, a first epitaxial layer of the first conductivity type is also formed on the surface of the semiconductor substrate, and the gate trench is formed in the first epitaxial layer.

[0034] Further improvement is, further comprising the following steps:

[0035] Step eight, forming a body region of the second conductivity type on the surface of the semiconductor substrate.

[0036] The gate dielectric layer and the gate conductive material layer pass through the body region, and the surface of the body region covered by the side of the gate conductive material layer serves as a channel region.

[0037] The first epitaxial layer at the bottom of the body region serves as a drift region.

[0038] Step nine, forming a source region of the first conductivity type heavily doped on the surface of the body region.

[0039] Step ten, forming an interlayer film, contact holes and a front metal layer, patterning the front metal layer to form a source electrode and a gate electrode, and the source region, the body region and the shielding gate polysilicon are all connected to the source electrode through the corresponding contact holes on top.

[0040] The gate conductive material layer is connected to the gate electrode through the corresponding contact hole on top.

[0041] Further improvement is, the gate trench extends to a gate lead-out region outside the device unit region, and the gate conductive material layer in the device unit region is connected to the gate electrode through a contact hole arranged on top of the gate conductive material layer in the gate trench in the gate lead-out region.

[0042] Further improvement is, the SGT semiconductor device is an SGT MOSFET, and further comprising the following back surface process:

[0043] Step eleven, thinning the back surface of the semiconductor substrate, and then performing a back surface ion implantation of the first conductivity type heavily doped to form a drain region.

[0044] Step twelve, forming a back metal layer in contact with the drain region, and the back metal layer constitutes a drain electrode.

[0045] Further improvement is, the SGT semiconductor device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type.

[0046] Alternatively, the SGT semiconductor device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0047] The present application forms a bottom dielectric layer and a shield gate polysilicon at the bottom region of the gate trench, and then, instead of forming the gate oxide layer and the inter-gate oxide layer simultaneously by an oxidation process, a second inner sidewall is formed at the side of the gate trench on the top of the bottom dielectric layer, the bottom dielectric layer is etched by using the first hard mask layer and the second inner sidewall as a mask to expose the top region of the shield gate polysilicon, and then, the first heat oxidation process is performed to form the inter-gate oxide layer. Since the top region of the shield gate polysilicon is exposed, the shield gate polysilicon is oxidized from the side and the top surface of the top region of the shield gate polysilicon, so that a thicker inter-gate oxide layer can be obtained. Then, the gate dielectric layer is formed. Therefore, the forming process of the inter-gate oxide layer of the present application can be independent of the forming process of the gate dielectric layer, so the thickness of the inter-gate oxide layer can be independent of the thickness of the gate dielectric layer. Thus, the thickness of the inter-gate oxide layer and the thickness of the gate dielectric layer can be adjusted independently. When the thickness of the gate dielectric layer is thin, a thicker and better quality inter-gate oxide layer can be obtained, and the process flow is simple and the process difficulty is low.

[0048] When the gate dielectric layer of the present application is formed by the second heat oxidation process, the thickness and quality of the inter-gate oxide layer can be further increased.

[0049] In addition, the first heat oxidation process of the present application also forms a third oxide layer on the side of the gate trench. However, the third oxide layer is located at the bottom of the second inner sidewall, the side of the gate trench at the top region of the third oxide layer is protected by the second inner sidewall, and the channel region is formed in the semiconductor substrate at the side of the gate trench at the top region of the third oxide layer. Therefore, the forming process of the inter-gate oxide layer of the present application does not adversely affect the channel region. In addition, since the thickness of the third oxide layer is greater than the thickness of the gate dielectric layer, compared with the prior art in which a weak point formed by a thin gate dielectric layer is present between the bottom corner of the gate conductive material layer and the gate trench, the third oxide layer of the present application increases the thickness of the oxide layer between the bottom corner of the gate conductive material layer and the gate trench, so that the weak point in the prior art can be eliminated.

[0050] The inter-gate oxide layer of the present application can be realized by heat oxidation, without the need for complex process control. Therefore, the present application also has the advantages of simple process flow and low process difficulty, which is also conducive to stable production. BRIEF DESCRIPTION OF DRAWINGS

[0051] The present application will be further described in detail below in conjunction with the drawings and specific embodiments:

[0052] Figure 1This is a flowchart of a method for manufacturing the inter-gate oxide layer of an SGT semiconductor device according to an embodiment of the present invention;

[0053] Figures 2A-2H A schematic diagram of the cross-sectional structure of the device in each step of the manufacturing method of the gate oxide layer of the SGT semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0054] like Figure 1 The diagram shown is a flowchart of a method for manufacturing the gate oxide layer 105 of an SGT semiconductor device according to an embodiment of the present invention; as shown Figures 2A-2H The diagram shows a cross-sectional structure of the device in each step of the manufacturing method of the SGT semiconductor device according to an embodiment of the present invention. The manufacturing method of the SGT semiconductor device according to an embodiment of the present invention includes the following steps:

[0055] Step 1, such as Figure 2A As shown, a gate trench 102 is defined by a first hard mask layer 201, and then the semiconductor substrate 101 is etched to form the gate trench 102.

[0056] In this embodiment of the invention, the semiconductor substrate 101 includes a silicon substrate.

[0057] In some embodiments, a first epitaxial layer doped with a first conductivity type is further formed on the surface of the semiconductor substrate 101, and the gate trench 102 is formed in the first epitaxial layer.

[0058] The first hard mask layer 201 is a silicon nitride layer, or a stacked layer of silicon oxide and silicon nitride, or a stacked layer of silicon oxide, silicon nitride, and silicon oxide. To control stress, the silicon nitride layer of the first hard mask layer 201 is relatively thin. The specific value can be adjusted according to actual needs.

[0059] Step Two, as follows Figure 2C As shown, a bottom dielectric layer 103 and a shielding gate polysilicon 104 are formed in the bottom region of the gate trench 102. The bottom dielectric layer 103 is isolated between the shielding gate polysilicon 104 and the gate trench 102, and the side of the gate trench 102 is exposed at the top of the bottom dielectric layer 103; the material of the bottom dielectric layer 103 is different from the material of the first hard mask layer 201.

[0060] In this embodiment of the invention, step two includes the following sub-steps:

[0061] Step 21, as follows Figure 2BAs shown, a bottom dielectric layer 103a is formed, which covers the bottom surface and side surface of the gate trench 102 and the surface outside the gate trench 102.

[0062] The material of the bottom dielectric layer 103a includes an oxide layer.

[0063] Figure 2B In the subsequent step 24, the bottom dielectric layer before etching is marked separately with 103a.

[0064] Step 22, as follows Figure 2B As shown, the shielding gate polysilicon 104 is formed, which completely fills the gate trench 102 and extends to the surface of the bottom dielectric layer 103a outside the gate trench 102.

[0065] Step 23, as follows Figure 2B As shown, the shielding gate polysilicon 104 is etched back so that the shielding gate polysilicon 104 outside the gate trench 102 is removed and the shielding gate polysilicon 104 inside the gate trench 102 is located only in the bottom region of the gate trench 102.

[0066] In some preferred embodiments, after step 23 and before subsequent step 24, amorphous ion implantation is performed to amorphize the lattice of the top region of the shielding gate polycrystalline silicon 104. Amorphous ion implantation is typically achieved using heavy ion implantation.

[0067] Step 24, as follows Figure 2C As shown, the bottom dielectric layer 103a is etched so that the bottom dielectric layer 103 is located only in the bottom region of the gate trench 102.

[0068] Step 3, as follows Figure 2D As shown, a second inner wall 202 is formed on the side of the gate trench 102 at the top of the bottom dielectric layer 103. The material of the bottom dielectric layer 103 is different from that of the bottom dielectric layer 103. The thickness of the second inner wall 202 is thinner than that of the bottom dielectric layer 103.

[0069] In this embodiment of the invention, the material of the second inner sidewall 202 includes silicon nitride. The second inner sidewall 202 can be formed using a sidewall process, that is, first forming the material layer of the second inner sidewall 202, and then performing full etching to form the second inner sidewall 202 by self-alignment on the side of the gate trench 102.

[0070] Step 4, as follows Figure 2EAs shown, the bottom dielectric layer 103 at the bottom of the second inner sidewall 202 is etched using the first hard mask layer 201 and the second inner sidewall 202 as masks, so that the top region of the shielding gate polysilicon 104 is exposed on the top surface of the bottom dielectric layer 103.

[0071] In this embodiment of the invention, after the bottom dielectric layer 103 at the bottom of the second inner sidewall 202 is etched, the side of the gate trench 102 in the area where the bottom dielectric layer 103 at the bottom of the second inner sidewall 202 has been removed is exposed. That is, grooves are formed on both sides of the top region of the shielding gate polysilicon 104.

[0072] Step 5, as follows Figure 2F As shown, a first thermal oxidation process is used to oxidize the shielding gate polysilicon 104 to form an inter-gate oxide layer 105. This first thermal oxidation process oxidizes the side surface and top surface of the top region of the shielding gate polysilicon 104, thereby increasing the thickness of the inter-gate oxide layer 105. Figure 2F As shown, the inter-gate oxide layer 105 can also effectively cover the bottom shielding gate polysilicon 104.

[0073] In this embodiment of the invention, the first thermal oxidation process also oxidizes the side of the gate trench 102 exposed at the bottom of the second inner wall 202 to form a third oxide layer 1051.

[0074] There is a gap between the third oxide layer 1051 and the inter-gate oxide layer 105, that is, the third oxide layer 1051 and the inter-gate oxide layer 105 cannot fill the grooves on both sides of the top region of the shielding gate polysilicon 104.

[0075] Step 6: Remove the first hard mask layer 201 and the second inner sidewall 202.

[0076] Step 7, as follows Figure 2G As shown, a gate dielectric layer 106 is formed on the side of the gate trench 102 where the inter-gate oxide layer 105 is formed.

[0077] like Figure 2H As shown, a gate conductive material layer 107 is filled in the gate trench 102.

[0078] In this embodiment of the invention, the gate dielectric layer 106 is formed on the side of the gate trench 102 on top of the third oxide layer 1051. Therefore, the channel region is located in the semiconductor substrate 101 covered by the side of the gate dielectric layer 106, so the formation process of the inter-gate oxide layer 105 in this embodiment of the invention will not have an adverse effect on the channel region of the device.

[0079] The gate conductive material layer 107 also fills the gap between the third oxide layer 1051 and the inter-gate oxide layer 105. The material of the gate dielectric layer 106 includes an oxide layer.

[0080] The gate dielectric layer 106 is formed by a second thermal oxidation process; the second thermal oxidation process also thickens the inter-gate oxide layer 105.

[0081] The material of the gate conductive material layer 107 includes polycrystalline silicon.

[0082] like Figure 2G As shown, the SGT semiconductor device in this embodiment of the invention is an SGT MOSFET, and the invention further includes the following steps:

[0083] Step 8: Form a body region 108 doped with a second conductivity type on the surface of the semiconductor substrate 101.

[0084] The gate conductive material layer 107 passes through the body region 108, and the surface of the body region 108 covered by the side of the gate conductive material layer 107 serves as a channel region.

[0085] The first epitaxial layer at the bottom of the body region 108 serves as a drift region.

[0086] In step five above, the first etching only needs to ensure that the surface of the second gate oxide layer 1052 formed is located at the bottom of the body region 108. Therefore, the requirements for the first etching in this embodiment of the invention are not very high; it is only necessary to ensure that the channel region can be formed. Figure 2G Although it is shown that the top surface of the second inter-gate oxide layer 1052 is higher than the top surface of the first inter-gate oxide layer 1051, in other embodiments it may also be that the top surface of the second inter-gate oxide layer 1052 is equal to or lower than the top surface of the first inter-gate oxide layer 1051.

[0087] Step 9: Form a source region 109 with a first conductivity type heavily doped on the surface of the body region 108.

[0088] Step 10: Forming an interlayer membrane 111.

[0089] An opening for a contact hole 112 is formed through the interlayer film 111, and a heavily doped bulk contact region 110 of the second conductivity type is formed at the bottom of the opening of the contact hole 112 at the top of the source region 109.

[0090] The contact hole 112 is formed by filling the opening of the contact hole 112 with metal. The contact hole 112 at the top of the source region 109 contacts the source region 109 and is electrically connected to the body region 108 through the body contact region 110.

[0091] A front-side metal layer 113 is formed, and the front-side metal layer 113 is patterned to form the source and gate electrodes. Both the source region 109 and the shielding gate polysilicon 104 are connected to the source electrode through the top contact hole 112. Figure 2G Only the contact hole 112 at the top of the source region 109 is shown.

[0092] The gate conductive material layer 107 is connected to the gate through a contact hole 112 at the top. In some embodiments, the gate trench 102 extends into the gate lead-out region outside the device cell region, and the gate conductive material layer 107 in the device cell region is connected to the gate through a contact hole at the top of the gate conductive material layer 107 in the gate trench 102 in the gate lead-out region.

[0093] Step 11: Thin the back side of the semiconductor substrate 101, and then perform back side ion implantation with heavy doping of the first conductivity type to form a drain region.

[0094] Step 12: Form a back metal layer that contacts the drain region, and form the drain electrode from the back metal layer.

[0095] In this embodiment of the invention, the SGT semiconductor device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type. In other embodiments, the SGT semiconductor device can also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0096] In this embodiment of the invention, after forming a bottom dielectric layer 103 and a shielding gate polysilicon 104 in the bottom region of the gate trench 102, instead of performing an oxidation process to simultaneously form a gate oxide layer and an inter-gate oxide layer 105, a second inner sidewall 202 is formed on the side of the gate trench 102 at the top of the bottom dielectric layer 103. Using a first hard mask layer 201 defining the gate trench 102 and the second inner sidewall 202 as a mask, the bottom dielectric layer 103 is etched to expose the top region of the shielding gate polysilicon 104. Then, a first thermal oxidation process is performed to form the inter-gate oxide layer 105. Because the top region of the shielding gate polysilicon 104 is exposed, the shielding gate polysilicon... The top region of the crystalline silicon 104 is oxidized together with the side surface and the top surface of the shielding gate polycrystalline silicon 104 to obtain a thicker inter-gate oxide layer 105. Then, the gate dielectric layer 106 is formed. Therefore, the formation process of the inter-gate oxide layer 105 in this embodiment of the invention can be independent of the formation process of the gate dielectric layer 106. Thus, the thickness of the inter-gate oxide layer 105 can be independent of the thickness of the gate dielectric layer 106. Therefore, this embodiment of the invention can independently adjust the thickness of the inter-gate oxide layer 105 and the thickness of the gate dielectric layer 106. When the thickness of the gate dielectric layer 106 is thin, a thicker and higher quality inter-gate oxide layer 105 can be obtained. Moreover, the process flow is simple and the process difficulty is low.

[0097] When the gate dielectric layer 106 of this embodiment is formed by a second thermal oxidation process, the thickness and quality of the inter-gate oxide layer 105 can be further increased.

[0098] Furthermore, the first thermal oxidation process in this embodiment of the invention also forms a third oxide layer 1051 on the side of the gate trench 102. However, the third oxide layer 1051 is located at the bottom of the second inner sidewall 202, and the side of the gate trench 102 in the top region of the third oxide layer 1051 is protected by the second inner sidewall 202. The channel region is formed in the semiconductor substrate 101 on the side of the gate trench 102 in the top region of the third oxide layer 1051. Therefore, the formation process of the inter-gate oxide layer 105 of the present invention will not have an adverse effect on the channel region. In addition, since the thickness of the third oxide layer 1051 is greater than the thickness of the gate dielectric layer 106, compared with the weak point formed by the thinner gate dielectric layer 106 between the bottom corner of the gate conductive material layer 107 and the gate trench 102 in the prior art, the third oxide layer 1051 in this embodiment of the invention increases the thickness of the oxide layer between the bottom corner of the gate conductive material layer 107 and the gate trench 102, thus eliminating the weak point caused by the prior art.

[0099] The inter-gate oxide layer 105 in this embodiment of the invention can be achieved by thermal oxidation without the need for complex process control. Therefore, this embodiment of the invention also has the advantages of simple process flow and low process difficulty, which is also conducive to achieving stable production.

[0100] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating an inter-gate oxide layer in an SGT semiconductor device, characterized in that, Includes the following steps: Step 1: Define the gate trench using the first hard mask layer, and then etch the semiconductor substrate to form the gate trench; Step 2: Form a bottom dielectric layer and a shielding gate polysilicon in the bottom region of the gate trench; The bottom dielectric layer is isolated between the shielding gate polysilicon and the gate trench, and the side of the gate trench at the top of the bottom dielectric layer is exposed; The first hard mask layer has a material layer that is different from the material of the bottom dielectric layer; Step 3: A second inner wall is formed on the side of the gate trench at the top of the bottom dielectric layer. The material of the bottom dielectric layer is different from that of the bottom dielectric layer, and the thickness of the second inner wall is thinner than that of the bottom dielectric layer. Step 4: Using the first hard mask layer and the second inner sidewall as masks, etch the bottom dielectric layer at the bottom of the second inner sidewall to expose the top region of the shielding gate polysilicon on the top surface of the bottom dielectric layer. Step 5: The shielding gate polysilicon is oxidized using a first thermal oxidation process to form an inter-gate oxide layer. The first thermal oxidation process is performed from the side and top surface of the top region of the shielding gate polysilicon to increase the thickness of the inter-gate oxide layer. Step 6: Remove the first hard mask layer and the second inner wall; Step 7: Form a gate dielectric layer on the side of the gate trench where the inter-gate oxide layer is formed, and fill the gate trench with a gate conductive material layer.

2. The method for manufacturing the gate oxide layer of the SGT semiconductor device as described in claim 1, characterized in that: In step one, the semiconductor substrate includes a silicon substrate.

3. The method for manufacturing the gate oxide layer of the SGT semiconductor device as described in claim 2, characterized in that: The material of the bottom dielectric layer includes an oxide layer; In step seven, the material of the gate dielectric layer includes an oxide layer.

4. The method for manufacturing the gate oxide layer of the SGT semiconductor device as described in claim 3, characterized in that: The material of the gate conductive material layer includes polycrystalline silicon.

5. The method for manufacturing the gate oxide layer of the SGT semiconductor device as described in claim 3, characterized in that: In step one, the first hard mask layer is a silicon nitride layer, or a superposition layer of silicon oxide and silicon nitride, or a superposition layer of silicon oxide, silicon nitride and silicon oxide; In step three, the material of the second inner wall includes silicon nitride.

6. The method for manufacturing the gate oxide layer of the SGT semiconductor device according to claim 3, characterized in that, Step two includes the following sub-steps: Step 21: Form the bottom dielectric layer, which covers the bottom surface and side surface of the gate trench and the surface outside the gate trench; Step 22: Form the shielding gate polysilicon, which completely fills the gate trench and extends to the surface of the bottom dielectric layer outside the gate trench; Step 23: Etch back the shielding gate polysilicon to remove the shielding gate polysilicon outside the gate trench and to ensure that the shielding gate polysilicon inside the gate trench is located only in the bottom region of the gate trench; Step 24: Etch the bottom dielectric layer so that the bottom dielectric layer is located only in the bottom region of the gate trench.

7. The method for manufacturing the gate oxide layer of the SGT semiconductor device according to claim 6, characterized in that: Step 23 and step 24 include performing amorphous ion implantation to amorphize the lattice of the top region of the shielding gate polycrystalline silicon.

8. The method for manufacturing the gate oxide layer of the SGT semiconductor device as described in claim 1, characterized in that: In step four, after the etching of the bottom dielectric layer at the bottom of the second inner wall is completed, the side of the gate trench in the area where the bottom dielectric layer at the bottom of the second inner wall is removed is exposed. In step five, the first thermal oxidation process also oxidizes the side of the gate trench exposed at the bottom of the second inner wall to form a third oxide layer.

9. The method for manufacturing the gate oxide layer of the SGT semiconductor device as described in claim 8, characterized in that: In step seven, the gate dielectric layer is formed on the side of the gate trench on top of the third oxide layer.

10. The method for manufacturing the gate oxide layer of the SGT semiconductor device as described in claim 8, characterized in that: A gap exists between the third oxide layer and the inter-gate oxide layer, and the gate conductive material layer also fills the gap between the third oxide layer and the inter-gate oxide layer.

11. The method for manufacturing the gate oxide layer of the SGT semiconductor device as described in claim 3, characterized in that: In step seven, the gate dielectric layer is formed using a second thermal oxidation process; The second thermal oxidation process simultaneously thickens the inter-gate oxide layer.

12. The method for manufacturing the gate oxide layer of the SGT semiconductor device as described in claim 1, characterized in that: In step one, a first epitaxial layer doped with a first conductivity type is also formed on the surface of the semiconductor substrate, and the gate trench is formed in the first epitaxial layer.

13. The method for manufacturing the gate oxide layer of the SGT semiconductor device as described in claim 12, characterized in that, It also includes the following steps: Step 8: Form a bulk region doped with a second conductivity type on the surface of the semiconductor substrate; The gate dielectric layer and the gate conductive material layer pass through the body region, and the surface of the body region covered by the side of the gate conductive material layer serves as the channel region. The first epitaxial layer at the bottom of the body region serves as the drift region; Step 9: Form a heavily doped source region of the first conductivity type on the surface of the body region; Step 10: Form an interlayer film, contact holes, and a front metal layer. Pattern the front metal layer to form the source and gate. The source region, the body region, and the shielding gate polysilicon are all connected to the source through corresponding contact holes at the top. The gate conductive material layer is connected to the gate through a corresponding contact hole at the top.

14. The method for manufacturing the gate oxide layer of the SGT semiconductor device as described in claim 13, characterized in that: The gate trench extends into the gate lead-out region outside the device cell region, and the gate conductive material layer in the device cell region is connected to the gate through a contact hole disposed on the top of the gate conductive material layer in the gate trench in the gate lead-out region.

15. The method for manufacturing the gate oxide layer of the SGT semiconductor device as described in claim 13, characterized in that: SGT semiconductor devices are SGT MOSFETs, and also include the following back-side processes: Step 11: Thin the back side of the semiconductor substrate, and then perform back side ion implantation with heavy doping of the first conductivity type to form a drain region; Step 12: Form a back metal layer that contacts the drain region, and form the drain electrode from the back metal layer.

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