A functionally reconfigurable neuromorphic transistor and its fabrication method
By employing a dual-gate structure in neuromorphic transistors and utilizing antiferroelectric and ferroelectric materials to control channel conductivity respectively, the problem of single-function in existing technologies is solved, enabling the integration of spiking neurons and neural synapses, and reducing manufacturing complexity and cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2022-10-17
- Publication Date
- 2026-05-26
AI Technical Summary
Existing neuromorphic transistors have limited functionality and cannot simultaneously realize the functions of spiking neurons and neural synapses within a single device, increasing the complexity and cost of manufacturing processes.
A neuromorphic transistor with a dual-gate structure is used to control the channel conduction using volatile antiferroelectric materials and non-volatile ferroelectric materials respectively, thereby realizing the functions of spiking neurons and neural synapses.
Implementing spiking neuron and synapse functions within a single transistor simplifies manufacturing processes and reduces costs.
Smart Images
Figure CN115939196B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of transistors, and in particular to a neuromorphic transistor with reconfigurable function and a method for fabricating the same. Background Technology
[0002] Neurons are the basic units of information processing in the brain, and synapses are the functional connections between neurons, serving as crucial sites for information transmission and processing. Developing microelectronic devices with biological synaptic and neuronal functions from the ground up is of great significance for developing ultra-low-power "brain-like chips" and realizing a new generation of artificial intelligence systems.
[0003] In recent years, numerous electronic devices have been constructed to simulate some functions of synapses and neurons. Among these, three-terminal devices, such as transistors, have attracted widespread attention due to their ability to simultaneously perform signal transmission and learning functions, as well as their lower power consumption and higher stability compared to two-terminal devices. Neuromorphic transistors mainly include two types: ferroelectric transistors and double-layer transistors. Compared to double-layer transistors, ferroelectric transistors (FeFETs) offer higher stability and can be mass-produced, making them a strong contender for constructing neuromorphic chips. The working principle of FeFETs in simulating synapses relies on a ferroelectric material with a high dielectric constant that can spontaneously polarize, serving as its insulating layer. Voltage can modulate the polarization state of the ferroelectric material, thereby altering the channel carrier density. This change in channel conductance non-volatility simulates synaptic function. Furthermore, each voltage pulse subtly alters the polarization state of the ferroelectric material, resulting in different conductances in the channel. This multi-level non-volatility variation can be used to record synaptic weights, simulating the STDP learning function of the synapse.
[0004] For spiking neurons, the function is to integrate input pulse signals and output new pulse signals to transmit information. The basic function of a spiking neuron can be abstracted as Leaky-Integrate-and-Fire (LIF). The LIF model describes the change in neuron membrane potential in two processes: an artificially set membrane potential threshold is set. When the membrane potential is below the threshold, the spiking neuron exhibits the function of leakage accumulation, which can be described by a first-order differential equation; once the membrane potential is above the threshold, the spiking neuron fires a pulse and resets the membrane potential. However, ferroelectric devices are non-volatile and can only achieve accumulation, not leakage. A feedback path or special design of the ferroelectric layer is required, which will increase the hardware cost and energy consumption of the neuron implementation. On the other hand, antiferroelectric materials have intrinsic polarization volatility. After the electric field is removed, they gradually return to the unpolarized state, possessing intrinsic accumulation and leakage functions. Therefore, antiferroelectric transistors are strong candidates for biomimetic spiking neurons.
[0005] Currently, a single neuromorphic transistor can only realize neuronal functions or only realize neural synaptic functions, which increases the complexity of the manufacturing process and increases the manufacturing cost.
[0006] Therefore, this invention is proposed. Summary of the Invention
[0007] The main objective of this invention is to provide a functionally reconfigurable neuromorphic transistor and its fabrication method, which solves the problem of the single function of existing neuromorphic transistors. It can use a dual-gate structure to control the modulation of channel conductance separately, and can realize the functions of spiking neurons and neural synapses in a single transistor.
[0008] To achieve the above objectives, the present invention provides the following technical solutions.
[0009] A first aspect of the present invention provides a neuromorphic transistor with reconfigurable function, comprising, from bottom to top, the following layers stacked sequentially: a substrate, a dielectric isolation layer, a first gate layer, a first dielectric layer, a channel layer, a second dielectric layer, and a second gate layer; wherein one of the first dielectric layer and the second dielectric layer is a ferroelectric dielectric layer and the other is an antiferroelectric dielectric layer; and a source layer and a drain layer are respectively provided at both ends of the channel layer.
[0010] The above neuromorphic transistor has a dual-gate structure. The gate dielectric materials of the two gates (the first gate layer and the second gate layer) are composed of volatile antiferroelectric material (i.e., antiferroelectric dielectric layer) and non-volatile ferroelectric material (i.e., ferroelectric dielectric layer), respectively. By controlling the modulation of the channel conductance by the two gates respectively, the functions of spiking neurons and neural synapses can be realized in a single transistor.
[0011] Based on the above, the shape and positional relationship of each layer can be further improved to reduce device defects, reduce leakage current problems, and improve sensitivity.
[0012] Furthermore, the first gate layer is located on a portion of the upper surface of the dielectric isolation layer, and the first dielectric layer surrounds the first gate layer.
[0013] Furthermore, both the source layer and the drain layer cover the sides and part of the upper surface of the channel layer.
[0014] Furthermore, the remaining upper surface of the channel layer is covered by the second dielectric layer.
[0015] Furthermore, the upper surface of the second dielectric layer, the upper surface of the source layer, and the upper surface of the drain layer are flush.
[0016] Furthermore, both the first gate layer and the second gate layer are metal gates.
[0017] Furthermore, the antiferroelectric dielectric layer adopts at least one of the following materials: PbNb[(ZrSn)Ti]O, HfO2-based antiferroelectric materials; the HfO2-based antiferroelectric materials include at least one of HfZrO, HfAlO, HfSiO, HfLaO, and HfGdO.
[0018] Furthermore, the ferroelectric dielectric layer adopts at least one of the following materials: PZT, HfO2-based ferroelectric materials, wherein the HfO2-based ferroelectric materials include at least one of HfAlO, HfSiO, HfLaO, and HfGdO.
[0019] Furthermore, the channel layer is made of at least one of metal oxide semiconductor, ionic oxide semiconductor, and low-dimensional semiconductor material; the metal oxide semiconductor includes at least one of ZnO and SnO, the ionic oxide semiconductor includes at least one of IGZO, IZO, IO, ITO, and IAZO, and the low-dimensional semiconductor material includes at least one of MoS2, SeIn, WS2, and BP.
[0020] A second aspect of the present invention provides a method for fabricating the functionally reconfigurable neuromorphic transistor described above. The steps involved in this method can be implemented using existing equipment and processes, making industrial production easier. The method includes the following steps:
[0021] Provide substrate;
[0022] A dielectric isolation layer, a first gate layer, a first dielectric layer, a channel layer, a second dielectric layer, and a second gate layer are formed sequentially from bottom to top on the surface of the substrate.
[0023] The channel layer is preferably formed using a low-temperature deposition method.
[0024] In summary, compared with the prior art, the present invention achieves the following technical effects:
[0025] (1) Using a transistor with a dual-gate structure, the gate dielectric materials of the two gates are composed of volatile antiferroelectric materials and non-volatile ferroelectric materials, respectively. By controlling the modulation of the channel conductance by the two gates respectively, the functions of spiking neurons and neural synapses can be realized in a single transistor.
[0026] (2) The preparation method is simple and easy to operate. Attached Figure Description
[0027] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.
[0028] Figure 1A schematic diagram of the structure of a neuromorphic transistor provided by the present invention;
[0029] Figure 2 A schematic diagram of another neuromorphic transistor provided by the present invention;
[0030] Figure 3 and 4 for Figure 1 The diagram shows the working principle of the transistor.
[0031] Figures 5 to 11 The structural diagrams obtained in different steps of Embodiment 1 of the present invention are shown below;
[0032] Figure 12 A flowchart of the preparation method provided by the present invention. Detailed Implementation
[0033] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0034] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0035] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0036] Currently, a single neuromorphic transistor can only realize either neuron function or synaptic function, which increases the complexity and cost of manufacturing. Therefore, the ability to achieve volatile and non-volatile conductance modulation within a single transistor, thereby enabling both spiking neuron and synaptic functions within a single device, has become a crucial technological breakthrough for product upgrades.
[0037] Therefore, the present invention provides a neuromorphic transistor with functional reconfigurability, such as... Figure 1 and 2As shown, it includes, from bottom to top, the following layers stacked sequentially: substrate 1, dielectric isolation layer 2, first gate layer 3, first dielectric layer, channel layer 5, second dielectric layer, and second gate layer 7; and one of the first dielectric layer and the second dielectric layer is a ferroelectric dielectric layer 6, and the other is an antiferroelectric dielectric layer 4; the two ends of the channel layer 5 are respectively provided with a source layer 9 and a drain layer 8. Figure 1 The transistor shown has an antiferroelectric layer 4 at the bottom and a ferroelectric layer 6 at the top. Figure 2 The transistor shown is the opposite, with the antiferroelectric layer 4 on top. Both types of transistors can realize the functions of spiking neurons and neural synapses within a single transistor.
[0038] The above neuromorphic transistor has a dual-gate structure. The gate dielectric materials of the two gates (the first gate layer 3 and the second gate layer 7) are composed of volatile antiferroelectric material (i.e., antiferroelectric dielectric layer) and non-volatile ferroelectric material (i.e. ferroelectric dielectric layer), respectively. By controlling the modulation of the channel conductance by the two gates respectively, the functions of spiking neurons and neural synapses can be realized in a single transistor.
[0039] Specifically, with Figure 1 Taking the transistor shown as an example, when the pulse modulates the first gate layer 3, the antiferroelectric layer 4 modulates the conductance of the channel layer 5, thereby realizing the function of a spiking neuron, i.e. Figure 3 The diagram illustrates the leakage accumulation function of a spiking neuron. When the pulse modulates the second gate layer 7, the ferroelectric layer 6 modulates the conductance of the channel layer 5, thereby achieving synaptic function, i.e., as shown... Figure 4 The electrical conductance of the neural synapse is gradually modulated.
[0040] The substrate 1 in the transistor can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator, etc., with the corresponding top semiconductor material being silicon, germanium, silicon germanium, or gallium arsenide, etc.
[0041] For the dielectric isolation layer 2 in the transistor, materials with good insulating properties such as oxides and oxynitrides can be used. At the same time, the etching selectivity ratio between the dielectric isolation layer and the first gate layer can be taken into account to enable more efficient and high-quality patterning of the first gate layer.
[0042] The first gate layer 3 and the second gate layer 7 in the transistor can be made of any suitable conductor or semiconductor material as the gate, preferably a metal gate.
[0043] For the antiferroelectric dielectric layer 4 in the transistor, it can be made of at least one of the following materials: PbNb[(ZrSn)Ti]O, HfO2-based antiferroelectric material; the HfO2-based antiferroelectric material includes at least one of HfZrO, HfAlO, HfSiO, HfLaO, and HfGdO.
[0044] For the ferroelectric dielectric layer 6 in the transistor, it adopts at least one of the following materials: PZT, HfO2-based ferroelectric material, wherein the HfO2-based ferroelectric material includes at least one of HfAlO, HfSiO, HfLaO, and HfGdO.
[0045] For the channel layer 5 in the transistor, it adopts at least one of metal oxide semiconductor, ionic oxide semiconductor, and low-dimensional semiconductor material; the metal oxide semiconductor includes at least one of ZnO and SnO, the ionic oxide semiconductor includes at least one of IGZO, IZO, IO, ITO, and IAZO, and the low-dimensional semiconductor material includes at least one of MoS2, SeIn, WS2, and BP.
[0046] Regarding the shape and positional relationship between the first gate layer 3 and the first dielectric layer in the transistor, it is preferable to place the first gate layer 3 on a portion of the upper surface of the dielectric isolation layer, so that the first dielectric layer surrounds the first gate layer 3. This structure can improve the electrical contact yield and reduce problems such as leakage.
[0047] Alternatively, the electrical properties can be improved through the following structural modifications.
[0048] For example, both the source layer 9 and the drain layer 8 cover the side surface and part of the upper surface of the channel layer.
[0049] Furthermore, the remaining upper surface of the channel layer 5 is covered by the second dielectric layer.
[0050] Furthermore, the upper surface of the second dielectric layer, the upper surface of the source layer 9, and the upper surface of the drain layer 8 are flush.
[0051] The aforementioned functionally reconfigurable neuromorphic transistors can be obtained using a simple fabrication method. The steps involved in this method can be implemented using existing equipment and processes, making industrial production easier. Figure 12 As shown, it includes the following steps:
[0052] Provide substrate;
[0053] A dielectric isolation layer, a first gate layer, a first dielectric layer, a channel layer, a source layer and a drain layer, a second dielectric layer, and a second gate layer are formed sequentially from bottom to top on the surface of the substrate.
[0054] The formation methods of the above layers include, but are not limited to, in-situ oxidation, PECVD, ALCVD, magnetron sputtering, low-temperature deposition, and arc ion plating. The deposition method is selected according to the material type.
[0055] The channel layer is preferably formed using a low-temperature deposition method.
[0056] In addition, the formation of each material layer may involve multiple specific steps, such as thin film deposition, cleaning, patterning, etc., and may involve the deposition and removal of mask or sacrificial layers if necessary. The present invention does not impose any particular limitations on these aspects.
[0057] The present invention also provides the following specific preparation examples.
[0058] Example 1
[0059] The first step is to provide, such as Figure 5 Substrate 1 is shown.
[0060] The second step involves depositing a dielectric isolation layer 2 on the surface of substrate 1 to obtain the following... Figure 6 The structure shown.
[0061] The third step involves depositing the first gate layer 3 on the substrate surface to obtain, as shown in the figure. Figure 7 The structure shown uses a mask or patterning method to ensure that the first metal gate layer only covers a portion of the upper surface of the substrate.
[0062] The fourth step involves depositing an antiferroelectric layer 4 to surround the first gate layer 3, resulting in... Figure 8 The structure shown.
[0063] The fifth step involves depositing a semiconductor channel layer 5, which only covers a portion of the surface of the antiferroelectric layer 4, resulting in... Figure 9 The structure shown.
[0064] The sixth step involves depositing source and drain electrodes on both sides of the semiconductor channel layer 5 and patterning them so that both the source layer 9 and the drain layer 8 cover the sides and part of the upper surface of the semiconductor channel layer. For example... Figure 10 As shown, at this time, the semiconductor channel layer 5 and the source layer 9 and drain layer 8 on both sides form a groove.
[0065] Step 7, in Figure 10 Ferroelectric material is deposited in the groove to form a ferroelectric layer 6, and the surface is planarized to make the upper surface of the ferroelectric layer 6, the upper surface of the source layer 9, and the upper surface of the drain layer 8 flush. Figure 11 As shown.
[0066] Step 8: Deposit a second gate layer 7 on the surface of the ferroelectric layer 6 to obtain the following... Figure 1 The structure shown.
[0067] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A neuromorphic transistor with functional reconfigurability, characterized in that, It includes, from bottom to top, the following layers stacked sequentially: substrate, dielectric isolation layer, first gate layer, first dielectric layer, channel layer, second dielectric layer, and second gate layer; wherein one of the first dielectric layer and the second dielectric layer is a ferroelectric dielectric layer and the other is an antiferroelectric dielectric layer; and source layer and drain layer are respectively provided at both ends of the channel layer.
2. The neuromorphic transistor with functional reconfigurability according to claim 1, characterized in that, The first gate layer is located on a portion of the upper surface of the dielectric isolation layer, and the first dielectric layer surrounds the first gate layer.
3. The neuromorphic transistor with functional reconfigurability according to claim 1 or 2, characterized in that, Both the source layer and the drain layer cover the sides and part of the upper surface of the channel layer.
4. The neuromorphic transistor with functional reconfigurability according to claim 3, characterized in that, The remaining upper surface of the channel layer is covered by the second dielectric layer.
5. The neuromorphic transistor with functional reconfigurability according to claim 4, characterized in that, The upper surface of the second dielectric layer, the upper surface of the source layer, and the upper surface of the drain layer are flush.
6. The neuromorphic transistor with functional reconfigurability according to claim 1, characterized in that, Both the first gate layer and the second gate layer are metal gates.
7. The neuromorphic transistor with functional reconfigurability according to claim 1, characterized in that, The antiferroelectric dielectric layer uses at least one of the following materials: PbNb[(ZrSn)Ti]O, HfO2-based antiferroelectric materials; the HfO2-based antiferroelectric materials include at least one of HfZrO, HfAlO, HfSiO, HfLaO, and HfGdO.
8. The neuromorphic transistor with functional reconfigurability according to claim 1, characterized in that, The ferroelectric dielectric layer uses at least one of the following materials: PZT, HfO2-based ferroelectric materials, wherein the HfO2-based ferroelectric materials include at least one of HfAlO, HfSiO, HfLaO, and HfGdO.
9. The neuromorphic transistor with functional reconfigurability according to claim 1, characterized in that, The channel layer is made of at least one of metal oxide semiconductor, ionic oxide semiconductor, and low-dimensional semiconductor material; the metal oxide semiconductor includes at least one of ZnO and SnO, the ionic oxide semiconductor includes at least one of IGZO, IZO, IO, ITO, and IAZO, and the low-dimensional semiconductor material includes at least one of MoS2, SeIn, WS2, and BP.
10. A method for fabricating a neuromorphic transistor with functional reconfigurability according to any one of claims 1-9, characterized in that, Includes the following steps: Provide substrate; A dielectric isolation layer, a first gate layer, a first dielectric layer, a channel layer, a second dielectric layer, and a second gate layer are formed sequentially from bottom to top on the surface of the substrate. The channel layer is formed using a low-temperature deposition method.