Preparation method of solar cell

Abstract

Embodiments of the present application relate to the technical field of solar cells, and particularly to a method for manufacturing a solar cell, including: providing a substrate having a first surface; forming a doped layer and a passivation layer stacked in sequence along a direction away from the first surface of the substrate on the first surface of the substrate, the passivation layer having a metal pattern region; forming an initial grid electrode on the top surface of the passivation layer in the metal pattern region by using a pre-sintering process, the initial grid electrode penetrating through a part of the thickness of the passivation layer; performing laser treatment on at least a part of the surface of the initial grid electrode to form a first grid electrode, wherein the first grid electrode after laser treatment penetrates through the passivation layer and is in electrical contact with the doped layer. Embodiments of the present application are beneficial to improving the photoelectric conversion performance of the manufactured solar cell.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of solar cells, and particularly to a method for manufacturing a solar cell. Background Art

[0002] Solar cells have good optoelectronic conversion capabilities. In solar cells, a metallization process is required on the surface of a silicon wafer to form multiple fine grids and main grids, so as to collect the current generated by the silicon wafer. Generally, the metallization process includes a sintering step to sinter the metal paste printed on the surface of the silicon wafer, so that the metal paste can penetrate the passivation layer and make electrical contact with the doped conductive layer or the emitter.

[0003] However, the optoelectronic conversion performance of currently manufactured solar cells is not good. Summary of the Invention

[0004] Embodiments of the present application provide a method for manufacturing a solar cell, which is at least beneficial to improving the optoelectronic conversion performance of the solar cell.

[0005] Embodiments of the present application provide a method for manufacturing a solar cell, including: providing a substrate having a first surface; forming a doped layer and a passivation layer stacked in sequence away from the first surface of the substrate on the first surface of the substrate, the passivation layer having a metal pattern area; using a pre-sintering process to form an initial grid electrode on the top surface of the passivation layer in the metal pattern area, the initial grid electrode penetrating through a part of the thickness of the passivation layer; performing laser treatment on at least a part of the surface of the initial grid electrode to form a first grid electrode, wherein the first grid electrode after the laser treatment penetrates the passivation layer and makes electrical contact with the doped layer.

[0006] In addition, the pre-sintering process includes: printing a metal paste on the surface of the passivation layer in the metal pattern area; drying the metal paste to solidify the metal paste and form a solidified metal paste; performing pre-sintering treatment on the solidified metal paste to burn at least part of the solidified metal paste through to a part of the thickness of the passivation layer to form the initial grid electrode.

[0007] In addition, the peak temperature of the pre-sintering treatment is 400°C to 500°C.

[0008] In addition, the ratio of the thickness of the initial grid electrode located in the passivation layer to the thickness of the passivation layer is 0.4 to 1.

[0009] In addition, the surface of the passivation layer has a region to be laser-treated, and the region to be laser-treated faces at least a part of the surface of the initial gate line electrode. The step of laser-treating at least a part of the surface of the initial gate line electrode includes: laser-treating the initial gate line electrode facing the region to be laser-treated to burn through the initial gate line electrode into the doped layer. The initial gate line electrode located in the doped layer and the initial gate line electrode located in a part of the passivation layer form the first gate line electrode. The region to be laser-treated after the laser treatment forms a laser-treated region. The laser power of the laser treatment is 1 W to 40 W, the laser frequency is 10 kHz to 5000 kHz, the laser wavelength is 300 nm to 800 nm, the laser pulse width is 0.2 ps to 500 ps, and the laser line scan speed is 200 mm / s to 20000 mm / s.

[0010] In addition, the region to be laser-treated coincides with the surface of the initial gate line electrode.

[0011] In addition, the region to be laser-treated faces a part of the surface of the initial gate line electrode.

[0012] In addition, the region to be laser-treated includes a plurality of spaced-apart first regions, and each first region faces a part of the initial gate line electrode.

[0013] In addition, the plurality of first regions are arranged at intervals in the extending direction of the initial gate line electrode; or the plurality of first regions are arranged in a staggered manner in the extending direction of the initial gate line electrode.

[0014] In addition, the initial gate line electrode has two first edges opposite to each other in a first direction, the first direction is perpendicular to the extending direction of the initial gate line electrode and parallel to the surface of the passivation layer. In the step of laser-treating at least a part of the surface of the initial gate line electrode, it further includes: laser-treating at least a part of the junction between the first edge and the passivation layer.

[0015] In addition, in the first direction, the ratio of the width of the region to be laser-treated to the width of the initial gate line electrode is 1 to 10.

[0016] In addition, the doping element type of the doped layer is the same as that of the substrate, and the material of the doped layer is at least one of doped amorphous silicon, doped polycrystalline silicon, or doped microcrystalline silicon material.

[0017] In addition, it further includes: a tunneling dielectric layer, and the tunneling dielectric layer is located between the doped layer and the first surface of the substrate.

[0018] In addition, the doping element type of the doped layer is different from that of the substrate, and the material of the doped layer is the same as the material of the substrate.

[0019] In addition, the material of the passivation layer is at least one of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride.

[0020] The technical solution provided by the embodiment of the present application has at least the following advantages:

[0021] In the technical solution of the method for manufacturing a solar cell provided by the embodiment of the present application, first, a pre-sintering process is used to form an initial grid electrode. The initial grid electrode is only sintered through to a part of the passivation layer, resulting in less damage to the passivation layer. As a result, more hydrogen in the passivation layer diffuses to the first surface of the substrate under the action of heat and combines with the dangling bonds on the first surface, playing a hydrogen passivation role on the substrate and significantly reducing the interface defects on the first surface of the substrate. Then, the initial grid electrode is subjected to laser treatment. The laser-treated initial grid electrode penetrates the passivation layer and makes electrical contact with the doped layer, enabling the formed first grid electrode to form a good ohmic contact with the substrate. While ensuring the transmission and collection of carriers through the first grid electrode, it reduces carrier recombination, increases the open-circuit voltage, and improves the photoelectric conversion performance of the solar cell. Description of the Drawings

[0022] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation.

[0023] Figure 1 It is a schematic cross-sectional structure diagram corresponding to the step of providing a substrate in a method for manufacturing a solar cell provided by an embodiment of the present application;

[0024] Figure 2 It is a schematic cross-sectional structure diagram corresponding to the step of forming a tunneling layer in a method for manufacturing a solar cell provided by an embodiment of the present application;

[0025] Figure 3 It is a schematic cross-sectional structure diagram corresponding to the step of forming a doped layer in a method for manufacturing a solar cell provided by an embodiment of the present application;

[0026] Figure 4 It is a schematic cross-sectional structure diagram corresponding to the step of forming a passivation layer in a method for manufacturing a solar cell provided by an embodiment of the present application;

[0027] Figure 5 It is a schematic cross-sectional structure diagram corresponding to the steps of forming a doped layer and a passivation layer in another method for manufacturing a solar cell provided by an embodiment of the present application;

[0028] Figure 6 It is a schematic top view structure diagram corresponding to the step of forming an initial grid electrode in a method for manufacturing a solar cell provided by an embodiment of the present application;

[0029] Figure 7 is Figure 6 a schematic cross-sectional structure diagram in the aa' direction in

[0030] Figure 8 is Figure 6 an enlarged schematic diagram at the dashed box in

[0031] Figure 9 is Figure 6 the first enlarged schematic diagram at the dashed box in

[0032] Figure 10 is Figure 6 the second enlarged schematic diagram at the dashed box in

[0033] Figure 11 is Figure 6 the third enlarged schematic diagram at the dashed box in

[0034] Figure 12 is Figure 6 the fourth enlarged schematic diagram at the dashed box in

[0035] Figure 13 is Figure 6 the fifth enlarged schematic diagram at the dashed box in

[0036] Figure 14 a schematic cross-sectional structure diagram corresponding to the step of forming the first grid line electrode in the preparation method of the solar cell provided by an embodiment of the present application;

[0037] Figure 15 a schematic cross-sectional structure diagram corresponding to the step of forming the second grid line electrode in the preparation method of the solar cell provided by an embodiment of the present application;

[0038] Figure 16 another schematic cross-sectional structure diagram corresponding to the step of forming the second grid line electrode in the preparation method of the solar cell provided by an embodiment of the present application. Detailed implementation manners

[0039] As can be seen from the background art, the current photoelectric conversion performance of solar cells is not good.

[0040] Analysis reveals that one of the reasons for the poor optoelectronic conversion performance of current solar cells is that, currently, in the process of forming the first grid line electrode, a sintering process is usually required to sinter the metal paste printed on the top surface of the passivation layer so that the metal paste can burn through the passivation layer to make electrical contact with the doping layer. However, due to the high sintering temperature and the presence of many highly corrosive components in the metal paste, when the metal paste penetrates the passivation layer to make electrical contact with the doping layer at high temperature, the damage to the passivation layer is relatively large, resulting in a large metal contact recombination between the passivation layer and the doping layer and the first grid line electrode, thereby reducing the optoelectronic conversion efficiency of the solar cell.

[0041] The embodiment of the present application provides a method for manufacturing a solar cell. First, an initial grid line electrode is formed by a pre-sintering process. The initial grid line electrode only burns through to a part of the passivation layer, causing less damage to the passivation layer. As a result, a large amount of hydrogen in the passivation layer diffuses to the first surface of the substrate under the action of heat and combines with the dangling bonds on the first surface, playing a hydrogen passivation role on the substrate and significantly reducing the interface defects on the first surface of the substrate. Then, the initial grid line electrode is subjected to laser treatment. The laser-treated initial grid line electrode penetrates the passivation layer to make electrical contact with the doping layer, enabling the formed first grid line electrode to form a good ohmic contact with the substrate. While ensuring the transmission and collection of carriers through the first grid line electrode, it reduces carrier recombination, increases the open-circuit voltage, and improves the optoelectronic conversion performance of the solar cell.

[0042] The following will elaborate on each embodiment of the present application in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0043] Figure 1 FIG. [X] is a schematic structural diagram of a solar cell provided by an embodiment of the present application. Figure 2 is Figure 1 a partial enlarged view of the dashed box in

[0044] Referring to Figure 1 , a substrate 100 is provided, and the substrate 100 has a first surface.

[0045] The substrate 100 is used to receive incident light and generate photo-generated carriers. In some embodiments, the substrate 100 can be the substrate 100, and the material of the substrate 100 can include at least one of single-crystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. The substrate 100 is an N-type semiconductor substrate, that is, the substrate 100 is doped with an N-type doping element, and the N-type doping element can be any one of phosphorus ions, arsenic ions, or antimony ions. In some other embodiments, the substrate 100 can also be a P-type semiconductor substrate, and the substrate 100 is doped with a P-type doping element, and the P-type doping element can be any one of boron ions, gallium ions, or indium ions.

[0046] The substrate 100 has a second surface opposite to the first surface. Both the first surface and the second surface of the substrate 100 can be used to receive incident light or reflect light. In some embodiments, the first surface can be the back surface of the substrate 100, and the second surface can be the front surface of the substrate 100. In some other embodiments, the first surface can also be the front surface of the substrate 100, and the second surface is the back surface of the substrate 100.

[0047] In some embodiments, a texturing process can be performed on the first surface and the second surface of the substrate 100 to form a pyramid texture on the first surface and the second surface of the substrate 100. In this way, the absorption and utilization rate of the incident light on the first surface and the second surface of the substrate 100 can be enhanced. In some embodiments, one of the first surface or the second surface of the substrate 100 is a pyramid texture, and the other of the first surface or the second surface can also be a non-pyramid texture, such as a stacked stepped morphology, so that the film layer formed on the stacked stepped morphology has a higher density and uniformity, thereby improving the quality of the formed film layer.

[0048] In some embodiments, the solar cell is a TOPCON (Tunnel Oxide Passivated Contact) cell. In some embodiments, the solar cell can also be a PERC (Passivated Emitter and Rear Cell) cell. In some embodiments, the solar cell can also be an HJT (Heterojunction technology solar cell) cell.

[0049] Reference Figures 2 to 5 , a doped layer 110 and a passivation layer 120 are formed on the first surface of the substrate 100 and stacked in sequence away from the first surface of the substrate 100. The passivation layer 120 has a metal pattern region.

[0050] Reference Figures 2 to 3, in some embodiments, the doping element type of the doping layer 110 is the same as that of the substrate 100, and the material of the doping layer 110 is at least one of doped amorphous silicon, doped polycrystalline silicon, or doped microcrystalline silicon materials. That is to say, the doping layer 110 can be used as a doped conductive layer of the solar cell, and the doped conductive layer is used to form a field passivation layer. Among them, the field passivation effect is: an electrostatic field pointing into the interior of the substrate 100 is formed at the interface of the substrate 100, so that minority carriers escape from the interface, thereby reducing the minority carrier concentration, making the recombination rate of carriers at the interface of the substrate 100 relatively low, and thus making the open-circuit voltage, short-circuit current, and fill factor of the solar cell relatively large, improving the photoelectric conversion performance of the solar cell. The formed first grid electrode is in electrical contact with the doped conductive layer, so that the first grid electrode can collect the carriers transmitted to the doped conductive layer.

[0051] In some embodiments, when the doping layer 110 is a doped conductive layer, before forming the doping layer 110, it further includes: forming a tunneling dielectric layer 130, and the tunneling dielectric layer 130 is located between the doping layer 110 and the first surface of the substrate 100. The tunneling dielectric layer 130 and the doped conductive layer can be used as a passivation contact structure. The tunneling dielectric layer 130 is in direct contact with the first surface of the substrate 100, and is used to achieve interface passivation of the first surface of the substrate 100, achieving a chemical passivation effect, promoting the recombination of photo-generated carriers, and improving the fill factor and conversion efficiency of the solar cell. In some embodiments, the material of the tunneling dielectric layer 130 can be a dielectric material, such as at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polycrystalline silicon.

[0052] In some embodiments, the method of forming the tunneling dielectric layer 130 and the doped conductive layer may include:

[0053] Reference Figure 2 , a tunneling dielectric layer 130 is formed on the first surface of the substrate 100 by using a deposition process, such as a chemical vapor deposition process. In some other embodiments, when the material of the tunneling dielectric layer 130 is silicon oxide, the tunneling dielectric layer 130 can also be formed by an in-situ generation process, such as a thermal oxidation process or a nitric acid passivation process to generate the tunneling dielectric layer on the first surface of the substrate 100.

[0054] Reference Figure 3 , after forming the tunneling dielectric layer 130, an amorphous silicon layer is formed on the surface of the tunneling dielectric layer 130 away from the substrate 100 by using a deposition process; then, a crystallization process is performed on the amorphous silicon layer to convert the amorphous silicon layer into a polycrystalline silicon layer; after forming the polycrystalline silicon layer, a doping process can be performed on the polycrystalline silicon layer to form a doped conductive layer. Specifically, conductive ions can be doped into the polycrystalline silicon layer by ion implantation or source diffusion, such as phosphorus ions or boron ions.

[0055] Reference Figure 5 , in some embodiments, the type of doping element of the doping layer 110 is different from that of the substrate 100, and the material of the doping layer 110 is the same as that of the substrate 100. The different types of doping elements between the doping layer 110 and the substrate 100 enable the doping layer 110 to serve as an emitter and form a PN junction with the substrate 100. The PN junction can receive incident light irradiated on the first surface of the substrate 100 and generate electron-hole pairs. When the substrate 100 is an N-type substrate, the separated electrons move into the substrate 100, and the separated holes move into the emitter. Among them, since the first gate line electrode is in electrical contact with the doping layer 110, the electrons moving into the emitter are collected by the first gate line electrode.

[0056] In some embodiments, the doping layer 110 is used to form an emitter. The method of forming the doping layer 110 may include:

[0057] Providing an initial substrate, performing a diffusion process on one surface of the initial substrate to diffuse conductive ions into a part of the initial substrate to form an emitter, and the part of the initial substrate other than the emitter forms the substrate 100. In some embodiments, when the substrate 100 is an N-type substrate, boron diffusion treatment may be performed on the surface of the initial substrate. In some embodiments, when the substrate 100 is a P-type substrate, phosphorus diffusion treatment may be performed on the surface of the initial substrate.

[0058] It should be noted that reference Figure 4 , in some embodiments, if the doping layer 110 on the first surface of the substrate 100 is a doped conductive layer, and a tunneling dielectric layer 130 is further formed between the doping layer 110 and the substrate 100, an emitter 101 may be formed on the second surface of the substrate 100. Reference Figure 5 , in some embodiments, when the doping layer 110 on the first surface of the substrate 100 serves as an emitter, a tunneling dielectric layer 130 and a doped conductive layer 102 may be formed on the second surface of the substrate 100.

[0059] The passivation layer 120 can achieve a good passivation effect on the first surface of the substrate 100. For example, it can perform good chemical passivation on the dangling bonds on the first surface of the substrate 100, reduce the density of defect states on the first surface of the substrate 100, and preferably inhibit the carrier recombination on the first surface of the substrate 100. In some embodiments, the passivation layer 120 may be a single-layer structure. In some embodiments, the passivation layer 120 may also be a multi-layer structure. In some embodiments, the material of the passivation layer 120 may be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0060] Reference Figure 4 and Figure 5, in some embodiments, the method of forming the passivation layer 120 may include: forming the passivation layer 120 on the surface of the doped layer 110 away from the substrate 100 by using the PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

[0061] In some embodiments, after forming the passivation layer 120, it further includes: forming an antireflection layer 150 on the second surface.

[0062] Reference Figure 4 , in some embodiments, when the doped layer 110 on the first surface serves as a doped conductive layer, the second surface of the substrate 100 has an emitter 101, and the antireflection layer 150 is located on the surface of the emitter away from the substrate 100.

[0063] Reference Figure 5 , in some embodiments, when the doped layer 110 on the first surface serves as an emitter, the second surface of the substrate 100 has a tunneling dielectric layer 130 and a doped conductive layer, and the antireflection layer 150 is located on the surface of the doped conductive layer away from the substrate 100. The antireflection layer 150 is used to reduce the reflection of the incident light on the second surface of the substrate 100, thereby increasing the absorption and utilization rate of the incident light by the substrate 100. In some embodiments, the antireflection layer 150 may be a single-layer or multi-layer structure, and the material of the antireflection layer 150 may be at least one of alumina, silicon oxide, silicon nitride, or silicon oxynitride.

[0064] In some embodiments, the antireflection layer 150 may be formed by using the PECVD process.

[0065] Reference Figures 6 to 7 , after forming the passivation layer 120, an initial gate line electrode is formed on the top surface of the passivation layer 120 in the metal pattern region by using a pre-sintering process, and the initial gate line electrode 140 penetrates through a part of the thickness of the passivation layer 120.

[0066] In the pre-sintering process, the initial gate line electrode 140 only penetrates through a part of the thickness of the passivation layer 120, so that the damage of the initial gate line electrode 140 to the passivation layer 120 is small, and then the metal contact recombination between the initial gate line electrode 140 and the passivation layer 120 is small. Under the action of heat treatment, more hydrogen in the passivation layer 120 can diffuse to the first surface of the substrate 100 and combine with the dangling bonds on the first surface, playing a role of hydrogen passivation on the substrate 100, greatly reducing the interface defects on the first surface of the substrate 100, thereby reducing the carrier recombination on the first surface of the substrate 100, increasing the carrier concentration, increasing the open-circuit voltage of the solar cell, and improving the photoelectric conversion performance of the solar cell.

[0067] In some embodiments, the pre-sintering process includes:

[0068] Print a metal paste on the surface of the passivation layer 120 in the metal pattern area. In some embodiments, the metal paste can be printed on the top surface of the passivation layer 120 by a screen printing process.

[0069] In some embodiments, the metal material in the metal paste can include at least one of silver, aluminum, copper, tin, gold, lead, or nickel.

[0070] Dry the metal paste to cure the metal paste and form a cured metal paste. After the drying process, the metal paste cures, and during the subsequent pre-sintering process of the cured metal paste, the probability of the metal paste penetrating into areas outside the metal pattern area can be reduced, so that the formed initial gate line electrode 140 has a relatively straight morphology.

[0071] In some embodiments, the metal paste can be dried by heat treatment. During the drying process, the heat treatment temperature is relatively low, which can prevent the metal paste from penetrating into the passivation layer 120 during the drying process. In some embodiments, the drying temperature can be 120°C to 220°C, for example, it can be 150°C, 180°C, 200°C, or 210°C. In some embodiments, the drying time can be 30s to 180s, for example, it can be 30s to 50s, 50s to 65s, 65s to 80s, 80s to 100s, 100s to 120s, 120s to 150s, or 150s to 180s.

[0072] Perform a pre-sintering treatment on the cured metal paste to burn through at least part of the cured metal paste into the passivation layer 120 with a partial thickness to form the initial gate line electrode 140.

[0073] In some embodiments, the metal paste contains materials with highly corrosive components such as glass. Thus, in the pre-sintering process, the corrosive components will corrode the passivation layer 120 and part of the doping layer 110, thereby allowing the metal paste to penetrate into the passivation layer 120.

[0074] In some embodiments, due to process differences, there may be a small part of the cured metal paste that does not penetrate into the passivation layer 120.

[0075] In some embodiments, during the pre-sintering treatment, all the cured metal paste can penetrate into part of the passivation layer 120 to form the initial gate line electrode 140.

[0076] In some embodiments, the pre-sintering treatment may include: subjecting the cured metal paste to under-sintering treatment, which refers to heat-treating the cured metal paste at a lower temperature compared to the sintering treatment. In this way, it can prevent damage to the passivation layer 120 caused by too high a sintering temperature, ensure that the cured metal paste only penetrates through a partial thickness of the passivation layer 120, thereby reducing the damage to the passivation layer 120. At the same time, at a lower heat-treatment temperature, it can further promote the diffusion of hydrogen in the passivation layer 120 to the first surface of the substrate 100, combine with the dangling bonds on the first surface, and further play a hydrogen passivation role on the substrate 100, thereby enhancing the surface passivation effect of the passivation layer 120 on the first surface of the substrate 100 and improving the optoelectronic conversion performance of the solar cell.

[0077] In addition, adopting a lower sintering temperature can also result in a smaller metal contact recombination between the initial grid electrode 140 and the passivation layer 120, improve the fill factor, short-circuit current, and open-circuit voltage, and further enhance the optoelectronic conversion performance of the solar cell.

[0078] In some embodiments, the peak temperature of the pre-sintering treatment is 400°C to 500°C, for example, it can be 400°C to 420°C, 420°C to 435°C, 435°C to 450°C, 450°C to 465°C, 465°C to 480°C, or 480°C to 500°C. Within the above temperature range, on the one hand, the cured metal paste can be further cured to sinter the cured metal paste into a part of the passivation layer 120. On the other hand, within the above temperature range, the heat-treatment temperature is not too high, which can reduce the damage to the passivation layer 120 caused by the pre-sintering process. At a lower heat-treatment temperature, more hydrogen in the passivation layer 120 can be excited to diffuse to the first surface of the substrate 100, combine with the dangling bonds on the first surface, and play a better hydrogen passivation role.

[0079] In some embodiments, the ratio of the thickness of the initial grid electrode 140 located in the passivation layer 120 to the thickness of the passivation layer 120 is 0.4 to 1, for example, it can be 0.4 to 0.45, 0.45 to 0.5, 0.5 to 0.55, 0.55 to 0.6, 0.6 to 0.68, 0.68 to 0.75, 0.75 to 0.8, 0.8 to 0.85, 0.85 to 0.9, 0.9 to 0.95, or 0.95 to 0.99. Within the above range, the thickness of the initial grid electrode 140 penetrating the passivation layer 120 is smaller, preventing excessive process damage to the passivation layer 120, reducing the metal contact recombination between the initial grid electrode 140 and the passivation layer 120, enabling more hydrogen in the passivation layer 120 to diffuse to the first surface of the substrate 100, combine with the dangling bonds on the first surface of the substrate 100, reducing the interface state defects on the first surface of the substrate 100, reducing the carrier recombination on the first surface of the substrate 100, and enhancing the open-circuit voltage and short-circuit current.

[0080] Reference Figures 8 to 14 After the initial gate line electrode 140 is formed, at least a part of the surface of the initial gate line electrode 140 is subjected to laser treatment to form a first gate line electrode 141. Among them, the laser-treated first gate line electrode 141 penetrates the passivation layer 120 and is in electrical contact with the doping layer 110. The first gate line electrode 141 is in electrical contact with the doping layer 110 and is used to collect the carriers transmitted in the doping layer 110.

[0081] Under the action of laser energy, the initial gate line electrode 140 is further sintered into the doping layer 110. The laser-treated first gate line electrode 141 can form a good ohmic contact with the substrate 100, reduce the metal contact recombination between the first gate line electrode 141 and the doping layer 110, further reduce the carrier recombination, improve the carrier collection ability of the first gate line electrode 141, increase the open-circuit voltage, and realize the improvement of the photoelectric conversion performance of the solar cell.

[0082] In some embodiments, the surface of the passivation layer 120 has an area to be laser processed, and the area to be laser processed faces at least a part of the surface of the initial gate line electrode 140. The steps of laser processing at least a part of the surface of the initial gate line electrode 140 include: laser processing the initial gate line electrode 140 facing the area to be laser processed to burn through the initial gate line electrode 140 into the doping layer 110. The initial gate line electrode 140 located in the doping layer 110 and the initial gate line electrode 140 located in a part of the passivation layer 120 form a first gate line electrode 141. The area to be laser processed after laser processing forms a laser processed area. The laser power of the laser processing is 1W to 40W. For example, it can be 1W to 5W, 5W to 10W, 10W to 15W, 15W to 20W, 20W to 25W, 25W to 30W, 30W to 35W, or 35W to 40W; the laser frequency is 10kHz to 5000kHz. For example, it can be 10kHz to 100kHz, 100kHz to 500kHz, 500kHz to 800kHz, 800kHz to 1000kHz, 1000kHz to 1500kHz, 1500kHz to 1800kHz, 1800kHz to 2500kHz, 2500kHz to 2800kHz, 2800kHz to 3300kHz, 3300kHz to 3800kHz, 3800kHz to 4500kHz, or 4500kHz to 5000kHz; the laser wavelength is 300nm to 800nm. For example, it can be 300nm to 330nm, 330nm to 380nm, 380nm to 450nm, 450nm to 510nm, 510nm to 550nm, 550nm to 590nm, 590nm to 650nm, 650nm to 680nm, 680nm to 750nm, or 750nm to 800nm; the laser pulse width is 0.2ps to 500ps. For example, it can be 0.2 ps to 1 ps, 1 ps to 10 ps, 10 ps to 30 ps, 30 ps to 80 ps, 80 ps to 120 ps, 120 ps to 150 ps, 150 ps to 220 ps, 220 ps to 250 ps, 250 ps to 300 ps, 300 ps to 380 ps, 380 ps to 430 ps, 430 ps to 480 ps or 480 ps to 500 ps; the laser line scanning speed is 200 mm / s to 20,000 mm / s, for example, it can be 200 mm / s to 500 mm / s, 500 mm / s to 1,000 mm / s, 1,000 mm / s to 1,500 mm / s, 1,500 mm / s to 1,800 mm / s, 1,800 mm / s to 2,500 mm / s, 2,500 mm / s to 4,200 mm / s, 4,200 mm / s to 5,500 mm / s, 5,500 mm / s to 7,000 mm / s, 7,000 mm / s to 8,000 mm / s, 8,000 mm / s to 9,600 mm / s, 9,600 mm / s to 11,000 mm / s, 11,000 mm / s to 12,500 mm / s, 12,500 mm / s to 13,800 mm / s, 13,800 mm / s to 15,000 mm / s, 15,000 mm / s to 17,000 mm / s, 17,000 mm / s to 18,500 mm / s, 18,500 mm / s to 19,300 mm / s or 19,300 mm / s to 20,000 mm / s.

[0083] The area to be laser processed is the area where laser processing is carried out, and the laser processing area is the area that has been laser processed. Within the above laser processing parameter range, on the one hand, the laser energy is sufficient to sinter at least part of the initial gate line electrode 140 into the doping layer 110 to form electrical contact with the doping layer 110. On the other hand, within the above range, the laser power is not too large to prevent the problem that the formed first gate line electrode 141 penetrates the doping layer 110 and contacts the substrate 100. In addition, within this range, the damage caused by laser processing to the passivation layer 120, the doping layer 110 and the substrate 100 is less, reducing the generation of recombination centers in the passivation layer 120, the doping layer 110 and the substrate 100.

[0084] In some embodiments, the laser used in the laser process can be any one of infrared laser, green laser, and ultraviolet laser, and the laser used for laser processing can be any one of CO2 laser, excimer laser, titanium sapphire laser, and semiconductor laser. The embodiments of the present application do not make specific limitations on the specific type of laser.

[0085] Reference Figure 8, in some embodiments, the area to be laser-treated 10 coincides with the surface of the initial gate line electrode 140. That is to say, the entire surface of the initial gate line electrode 140 is laser-treated to sinter the entire initial electrode into the doping layer 110, so that the contact area between the formed first gate line electrode 141 and the doping layer 110 is relatively large, thereby reducing the contact resistance between the first gate line electrode 141 and the doping layer 110 and enhancing the carrier collection ability of the first gate line electrode 141.

[0086] Reference Figures 9 to 13 , in some embodiments, the area to be laser-treated faces a part of the surface of the initial gate line electrode 140. That is to say, a part of the surface of the initial gate line electrode 140 is laser-treated. Reference Figure 14 , such that in the formed first gate line electrode 141, only part of the first gate line electrode 141 penetrates the passivation layer 120 to be in electrical contact with the doping layer 110, and the remaining part of the first gate line electrode 141 only penetrates part of the thickness of the passivation layer 120. In this way, the damage to the passivation layer 120 and the doping layer 110 caused by the formed first gate line electrode 141 can be reduced, further reducing the metal contact recombination loss. On the basis of ensuring the carrier collection ability of the first gate line electrode 141 for the carriers in the doping layer 110, the carrier recombination is reduced, the passivation effect on the first surface of the substrate 100 is improved, the open-circuit voltage of the solar cell is increased, and the photoelectric conversion performance of the solar cell is further improved.

[0087] In some embodiments, the area to be laser-treated includes a plurality of spaced-apart first regions 11, and each first region 11 faces a part of the initial gate line electrode 140. Laser treatment can accurately locate the target part of the initial gate line electrode 140, so that only the first region 11 can be treated, and the area outside the first region 11 is not laser-treated, such that in the formed first gate line electrode 141, the arrangement of the first gate line electrode 141 located in the doping layer 110 is the same as the arrangement of the first region 11. That is, only by controlling the arrangement of the first region 11, the morphology of the formed first gate line electrode 141 can be achieved.

[0088] It can be understood that there are various arrangements of the first region 11, and it only needs to satisfy that the first region 11 faces a part of the initial gate line electrode 140 to laser-treat the initial gate line electrode 140 facing the first region 11.

[0089] Reference Figures 9 to 11 , in some embodiments, the plurality of first regions 11 are spaced apart in the extending direction of the initial gate line electrode 140. Reference Figures 12 to 13 , in some embodiments, the plurality of first regions 11 are arranged in a staggered manner in the extending direction of the initial gate line electrode 140. Among them, there are various ways of staggered arrangement. Figure 12 AndFigure 13 Only two different misaligned arrangement modes of the first region 11 are shown, and the specific misaligned arrangement mode in the embodiments of the present application is not limited.

[0090] The first region 11 is arranged along the extension direction of the initial gate line electrode 140. In this way, in the formed first gate line electrode 141, the first gate line electrode 141 in electrical contact with the doping layer 110 can be arranged along the extension direction of the first gate line electrode 141, so that the first gate line electrode 141 can collect carriers in the doping layer 110 at different positions. In other words, carriers in the doping layer 110 can be collected at different positions of the entire first gate line electrode 141, thereby improving the carrier collection ability of the first gate line electrode 141.

[0091] Reference Figures 10 to 13 , in some embodiments, the initial gate line electrode 140 has two first edges 20 opposite to each other in the first direction X, the first direction X is perpendicular to the extension direction of the initial gate line electrode 140 and parallel to the surface of the passivation layer 120. In the step of laser treating at least part of the surface of the initial gate line electrode 140, it further includes: laser treating at least part of the junction between the first edge 20 and the passivation layer 120.

[0092] It can be understood that during the laser treatment, the heat generated by the laser energy causes the initial gate line electrode 140 to sinter into the doping layer 110. That is to say, the essence of the laser treatment is also to perform heat treatment on the initial gate line electrode 140. Based on this, laser treating the junction between the first edge 20 of the initial gate line electrode 140 and the passivation layer 120, that is, performing heat treatment on the junction between the first edge 20 and the passivation layer 120. Under the action of heat treatment, a large number of carriers are generated at the interface between the gate line and the passivation layer 120. The carriers react with the initial gate line electrode 140, promoting the precipitation of metal ions in the initial gate line electrode 140 to form metal micelles. The metal micelles form conductive contact sites in the passivation layer 120 and the doping layer 110, reducing the contact impedance and improving the fill factor of the solar cell.

[0093] Reference Figure 10 , in some embodiments, the area to be laser treated may include a plurality of first regions 11 arranged at intervals along the extension direction of the initial gate line electrode 140, and the first regions 11 are both directly opposite to the two first edges 20 of the initial gate line electrode 140. In this way, more carriers can be generated in the passivation layer 120, increasing the number of generated conductive contact sites and further improving the fill factor of the solar cell.

[0094] Reference Figure 11, in some embodiments, the first region 11 may also be directly opposite to only one of the first edges 20 of the initial gate line electrode 140. In this way, the process damage to the passivation layer 120 caused by laser treatment can be reduced, and the number of carrier recombination centers in the passivation layer 120 can be reduced.

[0095] Reference Figure 12 and Figure 13 , in some embodiments, if the multiple first regions 11 are arranged in a staggered manner along the extension direction of the initial gate line electrode 140, the first region 11 located on the outermost side along the first direction X can be directly opposite to the first edge 20.

[0096] Reference Figure 10 , in some embodiments, along the first direction X, the ratio of the width of the region to be laser-treated to the width of the initial gate line electrode 140 is 1 to 10.

[0097] In some embodiments, the ratio of the width of the region to be laser-treated to the width of the initial gate line electrode 140 is 1, that is, the edge of the region to be laser-treated in the first direction X is flush with the first edge 20 of the initial gate line electrode 140.

[0098] In some embodiments, the ratio of the width of the region to be laser-treated to the width of the initial gate line electrode 140 is greater than 1 and less than or equal to 10. For example, it can be 1.5, 2, 2.3, 2.5, 2.8, 3, 3.4, 3.5, 3.7, 4, 4.5, 5, 5.3, 5.8, 6, 6.4, 6.6, 6.8, 7, 7.5, 7.9, 8, 8.3, 8.5, 8.8, 9, 9.5 or 10. Within the above range, on the one hand, the region to be laser-treated is directly opposite to the two first edges 20 of the initial gate line electrode 140, which can increase the number of carriers generated in the passivation layer 120, thereby increasing the number of formed conductive contact sites. On the other hand, the width of the region to be laser-treated in the first direction X is not too large, so that the part of the region to be laser-treated directly opposite to the passivation layer 120 is small, thereby reducing the process damage to the passivation layer 120 caused by laser treatment.

[0099] Figure 15 is a schematic cross-sectional structure diagram corresponding to the step of forming the second gate line electrode in the method for preparing a solar cell provided in an embodiment of the present application; Figure 16 is another schematic cross-sectional structure diagram corresponding to the step of forming the second gate line electrode in the method for preparing a solar cell provided in an embodiment of the present application. Among them, Figure 15 is a schematic cross-sectional structure diagram in the aa' direction (reference Figure 6 ), Figure 16 is a schematic cross-sectional structure diagram in the bb' direction (reference Figure 6 ).

[0100] ReferenceFigure 15 and Figure 16 In some embodiments, it further includes: forming a second gate line electrode 160, and the second gate line electrode 160 is located on the second surface of the substrate 100. In some embodiments, when the second surface of the substrate 100 has an emitter, the second gate line electrode 160 penetrates the antireflection layer 150 and is in electrical contact with the emitter; in other embodiments, when the second surface of the substrate 100 has a doped conductive layer, the second gate line electrode 160 penetrates the antireflection layer 150 and is in electrical contact with the doped conductive layer.

[0101] In some embodiments, the method of forming the second gate line electrode 160 may be the same as the method of forming the first gate line electrode 141, and the specific method can refer to the description of forming the first gate line electrode 141. Thus, in the process of forming the second gate line electrode 160, the surface passivation ability of the second surface of the substrate 100 can be improved, the carrier recombination on the second surface of the substrate 100 can be reduced, the open circuit voltage can be further increased, and the photoelectric conversion performance of the solar cell can be improved.

[0102] In some embodiments, among the formed second gate line electrodes 160, only part of the second gate line electrodes 160 are laser-treated, so that the metal contact recombination loss can be reduced and the carrier recombination can be reduced.

[0103] In the method for preparing a solar cell provided in the above embodiments, first, an initial gate line electrode 140 is formed by a pre-sintering process. The initial gate line electrode 140 only burns through to a part of the passivation layer 120, and the damage to the passivation layer 120 is small, so that more hydrogen in the passivation layer 120 diffuses to the first surface of the substrate 100 under the action of heat and combines with the dangling bonds on the first surface, playing a hydrogen passivation role on the substrate 100 and greatly reducing the interface defects on the first surface of the substrate 100. Then, the initial gate line electrode 140 is laser-treated. The laser-treated initial gate line electrode 140 penetrates the passivation layer 120 and is in electrical contact with the doped layer 110, so that the formed first gate line electrode 141 forms a good ohmic contact with the substrate 100, while ensuring the transmission and collection of carriers through the first gate line electrode 141, reducing carrier recombination, increasing the open circuit voltage, and improving the photoelectric conversion performance of the solar cell.

[0104] Although this application is disclosed above with preferred embodiments, it is not used to limit the claims. Any person skilled in the art can make several possible changes and modifications without departing from the concept of this application. Therefore, the protection scope of this application should be subject to the scope defined by the claims of this application.

[0105] Those of ordinary skill in the art can understand that the above embodiments are specific examples for implementing the present application. In actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method for preparing a solar cell, characterized in that, Comprising: Providing a substrate having a first surface; Forming a doped layer and a passivation layer stacked in sequence away from the first surface of the substrate on the first surface of the substrate, the passivation layer having a metal pattern area; Forming an initial gate line electrode on the top surface of the passivation layer in the metal pattern area by using a pre-sintering process, the initial gate line electrode penetrating through a part of the thickness of the passivation layer; Wherein, the pre-sintering process includes: Printing a metal paste on the surface of the passivation layer in the metal pattern area; Drying the metal paste to cure the metal paste and form a cured metal paste; Performing a pre-sintering treatment on the cured metal paste to burn at least part of the cured metal paste through to a part of the thickness of the passivation layer to form the initial gate line electrode; the peak temperature of the pre-sintering treatment is 400°C to 500°C; Performing a laser treatment on at least part of the surface of the initial gate line electrode to form a first gate line electrode, wherein the first gate line electrode after the laser treatment penetrates through the passivation layer and is in electrical contact with the doped layer.

2. The method for preparing a solar cell according to claim 1, wherein The ratio of the thickness of the initial gate line electrode located in the passivation layer to the thickness of the passivation layer is 0.4 to 1.

3. The manufacturing method of the solar cell according to claim 1, characterized in that The surface of the passivation layer has an area to be laser-treated, the area to be laser-treated is directly opposite to at least part of the surface of the initial gate line electrode, and the step of performing a laser treatment on at least part of the surface of the initial gate line electrode includes: Performing a laser treatment on the initial gate line electrode directly opposite to the area to be laser-treated to burn the initial gate line electrode through to the doped layer, the initial gate line electrode located in the doped layer and the initial gate line electrode located in part of the passivation layer form the first gate line electrode, and the area to be laser-treated after the laser treatment forms a laser-treated area, the laser power of the laser treatment is 1W to 40W, the laser frequency is 10kHz to 5000kHz, the laser wavelength is 300nm to 800nm, the laser pulse width is 0.2ps to 500ps, and the laser line scan speed is 200mm / s to 20000mm / s.

4. The manufacturing method of the solar cell according to claim 3, wherein, The area to be laser-treated coincides with the surface of the initial gate line electrode.

5. The manufacturing method of the solar cell according to claim 3, characterized in that, The area to be laser-treated is directly opposite to part of the surface of the initial gate line electrode.

6. The manufacturing method of a solar cell according to claim 5, characterized in that, The area to be laser-treated includes a plurality of spaced-apart first regions, and each first region is directly opposite to part of the initial gate line electrode.

7. The manufacturing method of the solar cell according to claim 6, characterized in that, The plurality of first regions are spaced apart in the extending direction of the initial gate line electrode; or the plurality of first regions are arranged in a staggered manner in the extending direction of the initial gate line electrode.

8. The method for preparing a solar cell according to any one of claims 3 to 7, characterized in that, The initial gate line electrode has two first edges opposite to each other in a first direction, the first direction is perpendicular to the extending direction of the initial gate line electrode and parallel to the surface of the passivation layer, and in the step of performing a laser treatment on at least part of the surface of the initial gate line electrode, it further includes: performing a laser treatment on the junction of at least part of the first edge and the passivation layer.

9. The manufacturing method of the solar cell according to claim 8, characterized in that, In the first direction, the ratio of the width of the area to be laser-treated to the width of the initial gate line electrode is 1 to 10.

10. The preparation method of the solar cell according to claim 1, characterized in that, The doping element type of the doping layer is the same as that of the substrate, and the material of the doping layer is at least one of doped amorphous silicon, doped polycrystalline silicon, or doped microcrystalline silicon materials.

11. The method for preparing a solar cell according to claim 10, wherein, Further included is: A tunneling dielectric layer, which is located between the doping layer and the first surface of the substrate.

12. The manufacturing method of the solar cell according to claim 1, wherein, The doping element type of the doping layer is different from that of the substrate, and the material of the doping layer is the same as that of the substrate.

13. The manufacturing method of the solar cell according to claim 1, wherein, The material of the passivation layer is at least one of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride.

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