A single-channel single-ADC analog-to-digital converter sampling precision doubling circuit

Abstract

The application discloses a single-channel single-ADC analog-digital converter sampling precision doubling circuit, which comprises a voltage comparator, a same-phase amplifier, a differential amplifier and an analog switch; the voltage comparator is used for comparing the size between a signal voltage to be sampled and an ADC sampling reference voltage, and outputting comparison result information to an ADC analog-digital converter; the ADC analog-digital converter is used for controlling the analog switch to switch to the output end of the differential amplifier when the signal voltage to be sampled is greater than or equal to the ADC sampling reference voltage, so that the ADC analog-digital converter samples the signal output by the differential amplifier; and the ADC analog-digital converter is also used for controlling the analog switch to switch to the output end of the same-phase amplifier when the signal voltage to be sampled is less than the ADC sampling reference voltage, so that the ADC analog-digital converter samples the signal output by the same-phase amplifier. The application can realize the purpose of expanding the sampling precision to the original 2 times, has low cost and is convenient for popularization and application.

Description

Technical Field

[0001] This invention relates to the field of ADC analog-to-digital converter technology, and in particular to a circuit that doubles the sampling accuracy of a single-channel single-ADC analog-to-digital converter. Background Technology

[0002] Analog-to-digital converters (ADCs), typically designed as integrated circuit devices, are widely used in industrial, consumer electronics, and electromechanical systems. The conversion rate, input channels, and conversion resolution of an ADC are universally essential parameters. In environments with rapidly changing analog inputs and multiple analog inputs, higher control accuracy requires higher rates, more channels, and higher conversion resolution bits. This inevitably leads to more complex ADC designs and higher device costs.

[0003] When designing with a specific ADC analog-to-digital converter, firstly, the resolution of the device selection range is limited, and secondly, in the actual use environment, device drift leads to a decrease in actual accuracy. Therefore, it is necessary and of practical significance to improve the resolution of the currently used device without occupying additional sampling channel resources of the specific ADC. Summary of the Invention

[0004] The purpose of this invention is to provide a circuit that doubles the sampling accuracy of a single-channel, single-ADC analog-to-digital converter. This circuit utilizes the original ADC data (quantized value after sampling) processing components and adds corresponding circuit structures to output a sampled, doubled analog-to-digital conversion value. It is reasonably designed, easy to use, and only uses a single analog input channel of the original ADC. Without occupying additional ADC resources, it can achieve the purpose of expanding the sampling accuracy to twice the original. It is low in cost and easy to promote and apply.

[0005] To achieve the above objectives, the following technical solution is adopted:

[0006] A circuit for doubling the sampling accuracy of a single-channel single-ADC analog-to-digital converter includes a voltage comparator: the non-inverting input of the voltage comparator is used to connect to the signal voltage to be sampled, the inverting input of the voltage comparator is used to connect to the ADC sampling reference voltage, and the output of the voltage comparator is connected to the ADC; a non-inverting amplifier: the non-inverting input of the non-inverting amplifier is used to connect to the signal voltage to be sampled, and the inverting input of the non-inverting amplifier is connected to virtual ground; a differential amplifier: the non-inverting input of the differential amplifier is used to connect to the signal voltage to be sampled, and the inverting input of the differential amplifier is used to connect to the ADC sampling reference voltage; and an analog switch, which is connected to the non-inverting amplifier respectively. The output of the amplifier, the output of the differential amplifier, and the ADC analog-to-digital converter are connected. The voltage comparator is used to compare the magnitude between the signal voltage to be sampled and the ADC sampling reference voltage, and outputs the comparison result to the ADC. The ADC controls the analog switch to switch to the output of the differential amplifier when the signal voltage to be sampled is greater than or equal to the ADC sampling reference voltage, so that the ADC samples the signal output by the differential amplifier. The ADC also controls the analog switch to switch to the output of the non-inverting amplifier when the signal voltage to be sampled is less than the ADC sampling reference voltage, so that the ADC samples the signal output by the non-inverting amplifier.

[0007] Furthermore, the analog switch is a single-pole double-throw switch; the single-pole double-throw switch includes a first stationary terminal, a second stationary terminal, and a first moving terminal; the ADC analog-to-digital converter is also provided with an ADC sampling port; the first stationary terminal is used to connect to the output terminal of the in-phase amplifier, the second stationary terminal is used to connect to the output terminal of the differential amplifier, and the first moving terminal is used to connect to the ADC sampling port of the ADC analog-to-digital converter.

[0008] Furthermore, the ADC analog-to-digital converter is also provided with a switch signal control port connected to the first moving terminal. The ADC analog-to-digital converter is used to control the first moving terminal via the switch signal control port and connect it to the first stationary terminal or the second stationary terminal.

[0009] Furthermore, the ADC analog-to-digital converter is also provided with an Out1 signal input port; the output of the voltage comparator is connected to the Out1 signal input port.

[0010] Furthermore, the in-phase amplifier is powered by a single power supply, and the amplification factor of the in-phase amplifier is 1.

[0011] Furthermore, the differential amplifier is powered by a single power supply, and the differential amplifier has a gain of 1.

[0012] By adopting the above solution, the beneficial effects of the present invention are:

[0013] This circuit utilizes the original ADC data (quantized value after sampling) processing components and adds corresponding circuit structures to output an analog-to-digital conversion value with doubled sampling. It is reasonably designed and easy to use. Moreover, this circuit only uses a single analog input channel of the original ADC. Without occupying additional ADC resources, it can achieve the purpose of expanding the sampling accuracy to twice the original. It is low in cost and easy to promote and apply. Attached Figure Description

[0014] Figure 1 This is a circuit diagram of the present invention;

[0015] Figure 2 This is a flowchart illustrating the sampling process of the present invention.

[0016] The following are explanations of the labels in the attached diagram:

[0017] 1—Voltage comparator; 2—Non-inverting amplifier;

[0018] 3—Differential amplifier; 4—ADC analog-to-digital converter. Detailed Implementation

[0019] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0020] Reference Figures 1 to 2As shown, this invention provides a circuit for doubling the sampling accuracy of a single-channel single-ADC analog-to-digital converter, including a voltage comparator 1: the non-inverting input of the voltage comparator 1 is used to connect to the signal voltage to be sampled, the inverting input of the voltage comparator 1 is used to connect to the ADC sampling reference voltage, and the output of the voltage comparator 1 is connected to the ADC analog-to-digital converter 4; a non-inverting amplifier 2: the non-inverting input of the non-inverting amplifier 2 is used to connect to the signal voltage to be sampled, and the inverting input of the non-inverting amplifier 2 is connected to virtual ground; a differential amplifier 3: the non-inverting input of the differential amplifier 3 is used to connect to the signal voltage to be sampled, and the inverting input of the differential amplifier 3 is used to connect to the ADC sampling reference voltage; and an analog switch, which is connected to the same voltage input and the inverting input of the ADC sampling reference voltage. The output terminals of the phase amplifier 2, the differential amplifier 3, and the ADC analog-to-digital converter 4 are connected. The voltage comparator 1 is used to compare the magnitude between the signal voltage to be sampled and the ADC sampling reference voltage, and outputs the comparison result information to the ADC analog-to-digital converter 4. The ADC analog-to-digital converter 4 is used to control the analog switch to switch to the output terminal of the differential amplifier 3 when the signal voltage to be sampled is greater than or equal to the ADC sampling reference voltage, so that the ADC analog-to-digital converter 4 samples the signal output by the differential amplifier 3. The ADC analog-to-digital converter 4 is also used to control the analog switch to switch to the output terminal of the in-phase amplifier 2 when the signal voltage to be sampled is less than the ADC sampling reference voltage, so that the ADC analog-to-digital converter 4 samples the signal output by the in-phase amplifier 2.

[0021] The analog switch is a single-pole double-throw switch, which includes a first stationary terminal, a second stationary terminal, and a first moving terminal. The ADC (Analog-to-Digital Converter) 4 also has an ADC sampling port. The first stationary terminal is connected to the output of the in-phase amplifier 2, the second stationary terminal is connected to the output of the differential amplifier 3, and the first moving terminal is connected to the ADC sampling port of the ADC 4. The ADC 4 also has a switch signal control port connected to the first moving terminal, which controls the first moving terminal to connect to either the first stationary terminal or the second stationary terminal. The ADC 4 also has an Out1 signal input port. The output of the voltage comparator 1 is connected to the Out1 signal input port. The in-phase amplifier 2 is powered by a single power supply, and its amplification factor is 1. The differential amplifier 3 is powered by a single power supply, and its amplification factor is 1.

[0022] Working principle of this invention:

[0023] Continue to refer to Figures 1 to 2 As shown, to facilitate understanding of this scheme, some terms are named and explained:

[0024] ADC: Analog-to-Digital Conversion, Analog-to-Digital Converter;

[0025] Vref: Reference Voltage. The input signal voltage to be sampled is Vanalog, and its range is 0 to Vref;

[0026] Vref2: ADC Sampling Reference Voltage, where Vref2 = Vref / 2;

[0027] route2: The sampling channel of this solution;

[0028] route1: A general and conventional single sampling channel, that is, the input signal passes through a sampling channel and is sampled by a single ADC

[0029] sampling mode;

[0030] process1: Voltage Comparator 1. Its non-inverting input terminal is connected to Vanalog, the inverting input terminal is connected to Vref2, and the output terminal Out1 is connected to the Out1 signal input port on the ADC Analog-to-Digital Converter 4;

[0031] process2: Non-inverting Amplifier Amp1 (which can be composed of an operational amplifier), powered by a single power supply, with a magnification factor of 1. The non-inverting input terminal is connected to Vanalog, the inverting input terminal is connected to virtual ground (referring to 0 potential), and the output terminal Vsw1 is connected to the first fixed terminal of the analog switch SW1 (an analog switching device, such as a single-pole double-throw switch). In this embodiment, Vsw1 is the value of Vanalog;

[0032] process3: Differential Amplifier Amp2 (which can be composed of an operational amplifier), powered by a single power supply, with a magnification factor of 1. The non-inverting input terminal is connected to Vanalog, the inverting input terminal is connected to Vref2, and the output Vsw2 is connected to the second fixed terminal of the analog switch Sw1 (an analog switching device, such as a single-pole double-throw switch). Among them, Vsw2: When the input voltage < Vref2, due to the single-voltage power supply of the amplifier, no negative voltage is output, and the output is 0. When the input voltage >= Vref2, the output is Vanalog - Vref2;

[0033] ADC Analog-to-Digital Converter 4: Refers to a MCU embedded processor or FPGA Field Programmable Logic with an ADC converter and auxiliary circuits, an arithmetic processing unit that completes AD conversion and subsequent control and arithmetic functions, including an ADC sampling channel (ADC sampling port), an Out1 signal input port, a Vlogic analog switch Sw1 control signal port (switch signal control port), etc.

[0034] The circuit uses components for processing the original ADC data (quantized values after sampling), adds corresponding circuit structures to output the analog-to-digital conversion values with doubled sampling, is reasonably designed and convenient to use. Moreover, the circuit only uses a single analog input channel of the original ADC, and can achieve the purpose of expanding the sampling accuracy to twice the original without occupying additional ADC resources, with low cost and being convenient for popularization and application. In this embodiment, the input analog quantity is a voltage signal, the ADC reference quantity is a voltage signal, and the sampling and quantization of the voltage signal are described. Other analog input quantities can be converted into voltage signals for sampling processing. Specifically:

[0035] In this embodiment, as Figure 1 shown, it further includes an ADC reference voltage divider circuit, a reference voltage divider network R1, R2, where R1 is equal to R2. Let the reference voltage be Vref and the second reference voltage be Vref2, then Vref2 = Vref / 2. Take Vref2 as the ADC reference voltage. The analog quantity of the voltage input to be sampled and quantized after conditioning is Vanalog, and its voltage range is:

[0036] 0 <= Vanalog <= Vref (Vanalog is greater than or equal to 0 and less than or equal to Vref), where

[0037] the ADC is n-bit, that is, the maximum quantization value is 2^n - 1, and the inherent error is 1 (half-bit). For example, for a 12-bit ADC, the maximum quantization value is 4095, the inherent error is 1, and the error percentage is (1 / 4096) * 100%. Here, Vref is the maximum value of the input Vanalog.

[0038] The analog quantity Vanalog after input conditioning, channel 2 (route2) is the channel of this scheme, channel 1 (route1) is the original sampling channel of the ADC and does not participate in the processing of channel 2 of this scheme. Processing 1 (process1) is the voltage amplitude judgment channel, and Out1 of processing 1 is the digital quantity output to the ADC analog-to-digital converter 4 as its input signal. The output signal being 0 indicates that Vanalog < Vref2, and being 1 (high level) indicates that Vanalong is judged by process1 to be greater than or equal to Vref2, that is, Vanalog >= Vref / 2.

[0039] Processing 2 (process2): The magnification of the non-inverting amplifier Amp1 is 1, and the output Vsw1 is switched by the analog switch Sw1 (controlled by the ADC analog-to-digital converter 4) and then input to the ADC.

[0040] Process 3: The differential amplifier Amp2 outputs Vsw2, and the amplification factor of Amp2 is 1. There is an analog switch Sw1. When the input logic level Vlogic from the ADC analog-to-digital converter 4 is 1, Vsw1 is input to the ADC analog-to-digital converter 4. When Vlogic is 0, Vsw2 is input to the ADC analog-to-digital converter 4. The analog switch can be designed using MOS transistors or devices used in the industry, such as a single-pole double-throw switch. In this embodiment, when Out1 is 0, Vlogic is 1; when Out1 is 1, Vlogic is 0.

[0041] Quantization description:

[0042] Vanalog: Through route2, then input to the voltage amplitude judgment channel of process1 (voltage comparator 1), and the output is Out1; input to the Amp1 channel of process2, and its output is Vsw1; input to the Amp2 channel of process3, and its output is Vsw2;

[0043] Sampling time 1: Assume the input voltage is Vanalog. For the voltage comparator 1, when Vanalog >= Vref2 (Vref / 2), Out1 is 1. The ADC analog-to-digital converter 4 determines that Out1 is 1, and Sw1 is set (Vlogic = 0) to 0. The sampling voltage input (the output of the Sw1 analog switch) is Vsw2, that is, Vsw2 = Vanalog - Vref2. The ADC analog-to-digital converter 4 receives the available sampling voltage as: the input voltage Vanalog is greater than Vref / 2, the sampling voltage input is Vsw2, and Vanalog = Vref2 + Vsw2 = Vref2 + (Vanalog - Vref2).

[0044] Sampling time 2: Assume the input voltage is Vanalog, as Figure 1 shown. For the voltage comparator 1, when Vanalog < Vref2 (Vref / 2), Out1 is 0. The ADC analog-to-digital converter 4 determines that Out1 is 0, Sw1 is set to 1, and the sampling voltage input (the output of the Sw1 analog switch) is Vsw1, then Vsw1 = Vanalog. The ADC analog-to-digital converter 4 receives the available sampling voltage as: the input voltage is less than Vref / 2, the sampling voltage input is (Vsw1 = Vanalog) < Vref2, and Vanalog = Vsw1.

[0045] Quantization process: The above two sampling processes cover all cases where Vanalog < Vref. At sampling time 1, the quantization value quantifies Vsw2 through the ADC, and the quantization value range is 0 - (2^n - 1). Then, the Vanalog sampling quantization value is from 2^n + 0 to 2^n + 2^n - 1 (because Vref / 2 is the ADC sampling reference voltage and the quantization value is 2^n, and Out1 being 1 means the quantization value is 2^n), that is, the quantization range is from 2^n to 2^(n + 1) - 1;

[0046] For sampling time 2, the quantization range is 0 - (2^n - 1). Considering sampling times 1 and 2 comprehensively, the Vanalog sampling quantization range is 0 - (2^n - 1) - 2^n - 2^(n + 1) - 1, which is 0 - 2^(n + 1) - 1. Obviously, the quantization range of this scheme is 0 - (2^(n + 1) - 1), the inherent error is 1, and the error percentage is (1 / 2^(n + 1)) * 100%. That is, by using only one sampling channel, the sampling rate is not affected. Compared with the original conventional sampling method of channel 2 (route2), for single - sampling and single - conversion of Vanalog, the quantization range is 0 - (2^n - 1), and the resolution is doubled, achieving a doubling of the sampling resolution.

[0047] Calculation example of one sampling quantization process in this scheme:

[0048] Assume Vref is 5V, then Vref2 is 2.5V. The input voltage Vanalog ranges from 0 to 5V, the ADC reference voltage is 2.5V, and the maximum quantization value is 4095 (12 - bit quantization accuracy);

[0049] When the input voltage is less than 2.5V, the quantization value is (Vanalog / 2.5) * 4095. For example, when the input is 1V, the quantized value is 1638;

[0050] When the input is equal to 2.5V, Out1 is 1. According to the scheme's logic, the quantization value is 4096 + the quantization value of Vsw2. Since Vsw2 = Vanalog - 2.5 = 2.5 - 2.5 = 0, the quantization value of Vsw2 is 0. Then 4096 + the quantization value of Vsw2 is 4096 + 0 = 4096. The quantization value corresponding to 2.5V is 4096 (which is half of the doubled quantization accuracy value 8192, and 2.5V is half of the input sampling voltage range);

[0051] When the input is greater than 2.5V, for example, 3.5V, because Out1 is 1, according to the scheme's logic, the quantization value is 4096 + the quantization value of Vsw2. The quantization value is 4096 + ((3.5 - 2.5) * 4096 / 2.5), which is 5734;

[0052] When the input is 5V, which is the maximum value, because Out1 is 1, the logic of the scheme determines the quantization value as 4096+Vsw2, and the quantization value is 4096+((5-2.5)*4096 / 2.5), which is 8192. Since the maximum quantization value is the theoretical quantization value -1, this quantization value is 8191.

[0053] From the above calculation example, when the input is within the sampling range, a sampling accuracy of 13 bits is achieved by using a single 12-bit quantization ADC. That is, the ADC conversion accuracy is improved without changing the quantization channel and ADC structure through this sampling circuit.

[0054] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A circuit for doubling the sampling accuracy of a single-channel, single-ADC analog-to-digital converter, characterized in that, Includes a voltage comparator: the non-inverting input of the voltage comparator is used to connect to the signal voltage to be sampled, the inverting input of the voltage comparator is used to connect to the ADC sampling reference voltage, and the output of the voltage comparator is used to connect to the ADC analog-to-digital converter; Non-inverting amplifier: The non-inverting input terminal of the non-inverting amplifier is used to connect to the signal voltage to be sampled, and the inverting input terminal of the non-inverting amplifier is used to connect to virtual ground; A differential amplifier, wherein the non-inverting input terminal of the differential amplifier is used to connect to the signal voltage to be sampled, and the inverting input terminal of the differential amplifier is used to connect to the ADC sampling reference voltage; Analog switches are connected to the output terminals of the in-phase amplifier, the differential amplifier, and the ADC analog-to-digital converter, respectively. The voltage comparator is used to compare the magnitude between the signal voltage to be sampled and the ADC sampling reference voltage, and outputs the comparison result to the ADC analog-to-digital converter. The ADC (Analog-to-Digital Converter) is used to control the analog switch to switch to the output of the differential amplifier when the voltage of the signal to be sampled is greater than or equal to the ADC sampling reference voltage, so that the ADC samples the signal output by the differential amplifier; the ADC is also used to control the analog switch to switch to the output of the non-inverting amplifier when the voltage of the signal to be sampled is less than the ADC sampling reference voltage, so that the ADC samples the signal output by the non-inverting amplifier.

2. The circuit for doubling the sampling accuracy of a single-channel single-ADC analog-to-digital converter according to claim 1, characterized in that, The analog switch is a single-pole double-throw switch; the single-pole double-throw switch includes a first stationary terminal, a second stationary terminal, and a first moving terminal; the ADC analog-to-digital converter is also provided with an ADC sampling port; the first stationary terminal is used to connect to the output terminal of the in-phase amplifier, the second stationary terminal is used to connect to the output terminal of the differential amplifier, and the first moving terminal is used to connect to the ADC sampling port of the ADC analog-to-digital converter.

3. The circuit for doubling the sampling accuracy of a single-channel single-ADC analog-to-digital converter according to claim 2, characterized in that, The ADC analog-to-digital converter is also provided with a switch signal control port connected to the first moving terminal. The ADC analog-to-digital converter is used to control the first moving terminal via the switch signal control port and connect it to the first stationary terminal or the second stationary terminal.

4. The circuit for doubling the sampling accuracy of a single-channel single-ADC analog-to-digital converter according to claim 1, characterized in that, The ADC analog-to-digital converter is also provided with an Out1 signal input port; the output of the voltage comparator is connected to the Out1 signal input port.

5. The circuit for doubling the sampling accuracy of a single-channel single-ADC analog-to-digital converter according to claim 1, characterized in that, The in-phase amplifier is powered by a single power supply and has a gain of 1.

6. The circuit for doubling the sampling accuracy of a single-channel single-ADC analog-to-digital converter according to claim 1, characterized in that, The differential amplifier is powered by a single power supply and has a gain of 1.

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