Display panel, manufacturing method thereof, and display device

Abstract

The present disclosure relates to a display panel, a manufacturing method thereof and a display device, and belongs to the field of display technology. The display panel includes a substrate, a plurality of first pixel units and a plurality of signal lines; the substrate has a display area and a peripheral area, the display area includes a first display area and a second display area, and the transmittance of the first display area is greater than the transmittance of the second display area; the plurality of first pixel units are located on the substrate and located in the first display area; the plurality of signal lines are at least located in the first display area and are electrically connected to the plurality of first pixel units; wherein the plurality of signal lines include a plurality of first signal lines and a plurality of second signal lines, the first part of each of the plurality of first signal lines is a metal signal line, the first part of each of the plurality of second signal lines is a metal oxide signal line, the first part of the first signal line is at least located in the first display area, and the first part of the second signal line is at least located in the first display area.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Full-screen display devices have a high screen-to-body ratio and provide a good viewing effect. In order to increase the screen-to-body ratio of full-screen display devices, under-screen camera technology has gradually been developed in display devices such as mobile phones.

[0003] The full-screen display device includes a display panel and a full display camera (FDC). The display panel has a camera display area, and pixel units are arranged in the camera display area so that the camera display area can display images. The FDC is arranged below the display panel and opposite to the camera display area. Summary of the invention

[0004] The embodiments of the present disclosure provide a display panel and a manufacturing method thereof and a display device, which can improve the display uniformity of the display device. The technical solution is as follows:

[0005] On the one hand, the present disclosure provides a display panel, which includes: a base substrate having a display area and a peripheral area at least partially surrounding the display area, the display area including a first display area and a second display area at least located on one side of the first display area, the transmittance of the first display area being greater than the transmittance of the second display area; a plurality of first pixel units located on the base substrate and located in the first display area; a plurality of signal lines located at least in the first display area and electrically connected to the plurality of first pixel units; wherein the plurality of signal lines include a plurality of first signal lines and a plurality of second signal lines, a first portion of each of the plurality of first signal lines being a metal signal line, and a first portion of the first signal line being at least located in the first display area; a first portion of each of the plurality of second signal lines being a metal oxide signal line, and a first portion of the second signal line being at least located in the first display area.

[0006] In an implementation of the embodiment of the present disclosure, the first signal line includes at least one of the following signal lines: a gate signal line, a data signal line, a reset signal line, a light emitting control signal line, an initial voltage signal line, and a power signal line.

[0007] In an implementation of the embodiment of the present disclosure, the first signal line includes a gate signal line and a data signal line.

[0008] In one implementation of the embodiment of the present disclosure, the first signal line also includes a second portion located in the second display area, the second signal line also includes a second portion located in the second display area, and the second portion of the first signal line and the second portion of the second signal line are both metal signal lines.

[0009] In one implementation of the embodiment of the present disclosure, the display panel also includes a first metal layer, a first insulating layer, and a metal oxide layer which are sequentially located on the base substrate in a direction away from the base substrate; the first signal line is located in the first metal layer; at least one of the multiple second signal lines has a first portion located in the metal oxide layer within the first display area and a second portion located in the first metal layer within the second display area, the first portion and the second portion of the second signal line are connected by a first via hole penetrating the first insulating layer, and the first via hole is at the junction of the first display area and the second display area.

[0010] In one implementation of the embodiment of the present disclosure, the first metal layer includes a first gate metal layer and a first source-drain metal layer, and the first insulating layer includes a first passivation layer and an interlayer dielectric layer; along the direction away from the substrate, the first gate metal layer, the interlayer dielectric layer, the first source-drain metal layer and the first passivation layer are stacked in sequence.

[0011] In one implementation of the embodiment of the present disclosure, the display panel also includes a second insulating layer and a second metal layer, and the second metal layer, the second insulating layer, the first metal layer, the first insulating layer and the metal oxide layer are stacked in sequence along the direction away from the base substrate; another part of the multiple second signal lines has a first part in the first display area located in the metal oxide layer, and a second part in the second display area located in the second metal layer, and the first part and the second part of the second signal line are connected by a second via hole that penetrates the first insulating layer and the second insulating layer, and the second via hole is at the junction of the first display area and the second display area.

[0012] In an implementation manner of the embodiment of the present disclosure, the second metal layer includes a second gate metal layer, and the second insulating layer includes a first gate insulating layer.

[0013] In one implementation of the embodiment of the present disclosure, when the ratio of the first size of the first display area to the second size of the first display area is greater than 2, the first signal line is a gate signal line, the first size of the first display area is the size of the first display area in the extension direction of the gate signal line, and the second size of the first display area is the size of the first display area in the extension direction of the data signal line.

[0014] In one implementation of the embodiment of the present disclosure, when the ratio of the first size of the first display area to the second size of the first display area is less than 0.5, the first signal line is a data signal line, the first size of the first display area is the first size of the first display area in the extension direction of the gate signal line, and the second size of the first display area is the size of the first display area in the extension direction of the data signal line.

[0015] In one implementation of the embodiment of the present disclosure, when the ratio of the first size of the first display area to the second size of the first display area is between 0.5 and 2, the first signal line includes a gate signal line and a data signal line, the first size of the first display area is the size of the first display area in the extension direction of the gate signal line, and the second size of the first display area is the size of the first display area in the extension direction of the data signal line.

[0016] In one implementation of the embodiment of the present disclosure, the display panel also includes a plurality of second pixel units, the plurality of second pixel units are located in the second display area, the plurality of first pixel units and the plurality of second pixel units are arranged into a plurality of rows of pixel units, and in the arrangement direction of a row of pixel units, the pixel units in two adjacent rows of pixel units are staggered with each other; the pixel units in two adjacent rows of pixel units are connected via a gate signal line.

[0017] In an implementation of the embodiment of the present disclosure, the gate signal line is in a wavy line shape, and the crests and troughs of the gate signal line respectively connect the pixel units in two adjacent rows of pixel units.

[0018] In an implementation manner of the embodiment of the present disclosure, the data signal line is in a wavy line shape, and the crest and trough of the data signal line respectively connect two adjacent pixel units in the same column of pixel units.

[0019] In an implementation of the embodiment of the present disclosure, the metal signal line includes a molybdenum signal line or a titanium signal line.

[0020] In an implementation manner of the embodiment of the present disclosure, the metal oxide signal line is a transparent metal oxide signal line.

[0021] In an implementation manner of the embodiment of the present disclosure, the metal oxide signal line is an indium tin oxide signal line.

[0022] In another aspect, the present disclosure provides a method for manufacturing a display panel, the method comprising:

[0023] A base substrate is provided, wherein the base substrate has a display area and a peripheral area at least partially surrounding the display area, wherein the display area includes a first display area and a second display area at least located on one side of the first display area, and the transmittance of the first display area is greater than the transmittance of the second display area; a plurality of first pixel units and a plurality of signal lines are formed on the base substrate, wherein the plurality of first pixel units are located in the first display area; a plurality of signal lines are at least located in the first display area and are electrically connected to the plurality of first pixel units, wherein the plurality of signal lines include a plurality of first signal lines and a plurality of second signal lines, wherein the first portion of each of the plurality of first signal lines is a metal signal line, and the first portion of the first signal line is at least located in the first display area; and the first portion of each of the plurality of second signal lines is a metal oxide signal line, and the first portion of the second signal line is at least located in the first display area.

[0024] On the other hand, the present disclosure provides a display device, comprising a power supply component and a display panel as described in any one of the above aspects, wherein the power supply component is used to supply power to the display panel.

[0025] In one implementation of the embodiment of the present disclosure, the display device further includes a light sensor, which is located on a side of the display panel away from the plurality of first pixel units, and whose orthographic projection on the substrate at least partially overlaps with the first display area.

[0026] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0027] In the disclosed embodiment, the light transmittance of the first display area is relatively high, and the light sensor (for example, a full-screen camera) can be arranged in an area corresponding to the first display area, so that light can be transmitted through the first display area to the light sensor. The first part of the first signal line in the first display area is a metal signal line. The resistance of the metal is smaller than that of the metal oxide, which can reduce the resistance of the first signal line and the load of the first signal line, so that the voltage received by the pixel unit in the first display area increases, and the voltage received by the pixel unit in the first display area is less different from the voltage received by the pixel unit in other areas, thereby improving the phenomenon of uneven display. At the same time, the first part of the second signal line is a metal oxide signal line, thereby ensuring the light transmittance of the first display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 is a schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0030] Figure 2 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0031] Figure 3 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0032] Figure 4 yes Figure 2 Cross-section view of the AA surface;

[0033] Figure 5 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0034] Figure 6 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0035] Figure 7 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0036] Figure 8 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0037] Fig. 9 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0038] Fig.10 is a schematic diagram of a film layer of a pixel provided by an embodiment of the present disclosure;

[0039] Fig.11 is a top view of a first display area provided by an embodiment of the present disclosure;

[0040] Fig.12 is a top view of another first display area provided by an embodiment of the present disclosure;

[0041] Fig.13 is a pixel arrangement diagram of a first display area provided by an embodiment of the present disclosure;

[0042] Fig.14 is a top view of another first display area provided by an embodiment of the present disclosure;

[0043] Fig.15 is a top view of another first display area provided by an embodiment of the present disclosure;

[0044] Fig.16 is a top view of another first display area provided by an embodiment of the present disclosure;

[0045] Fig.17 is a top view of another first display area provided by an embodiment of the present disclosure;

[0046] Fig.18 is another pixel arrangement diagram of the first display area provided by an embodiment of the present disclosure;

[0047] Fig.19 is a top view of another first display area provided by an embodiment of the present disclosure;

[0048] Fig. 20 is a top view of another first display area provided by an embodiment of the present disclosure;

[0049] Fig.21 is a top view of another first display area provided by an embodiment of the present disclosure;

[0050] Fig. 22 is a top view of another first display area provided by an embodiment of the present disclosure;

[0051] Fig.23 is another pixel arrangement diagram of the first display area provided by an embodiment of the present disclosure;

[0052] Fig.24 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0053] Fig.25 is a 7T1C pixel circuit diagram provided by an embodiment of the present disclosure;

[0054] Fig.26 is a flow chart of a method for manufacturing a display panel provided by the present disclosure;

[0055] Fig. 27 is a flow chart of a method for manufacturing a display panel provided by the present disclosure;

[0056] Fig.28 is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure;

[0057] Fig.29 is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure;

[0058] Fig.30is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure;

[0059] Fig.31 is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure;

[0060] Fig.32 is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure;

[0061] Fig.33 is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure;

[0062] Fig.34 is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure;

[0063] Fig.35 It is a process diagram of a method for manufacturing a display panel provided in an embodiment of the present disclosure.

[0064] Reference numerals:

[0065] 100, display area; 200, peripheral area; 10, substrate; 101, first display area; 102, second display area; 20, pixel unit; 30, signal line; 301, first signal line; 302, second signal line; 201, first metal layer; 202, first insulating layer; 203, metal oxide layer; 221, first via hole; 211, first gate metal layer; 212, first source and drain metal layer; 222, first passivation layer; 223, interlayer dielectric layer; 204, second insulating layer; 205, second metal layer; 241, second via hole; 251, second gate metal layer; 242, First gate insulating layer; 206, active layer; 207, second gate insulating layer; 208, second passivation layer; 209, second source and drain metal layer; 2010, buffer layer; 2011, planarization layer; 2012, anode layer; 2013, pixel defining layer; 2014, spacer layer; 2015, light-emitting layer; 2016, cathode layer; 2017, first inorganic encapsulation layer; 2018, organic encapsulation layer; 2019, second inorganic encapsulation layer; L1, first size; L2, second size; 40, second pixel unit; 50, light sensor; 60, capacitor; 601, first plate; 602, second plate. DETAILED DESCRIPTION

[0066] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0067] In the related art, in order to improve the transmittance of the camera display area so that the FDC can receive enough light for imaging, the signal lines between the pixel units in the camera display area are all transparent metal oxide signal lines, such as indium tin oxide (ITO) signal lines.

[0068] The larger resistance of the metal oxide signal line will produce a larger load, causing the voltage received by the pixel unit connected to the metal oxide signal line to be smaller than the voltage received by the pixel units in other display areas, resulting in a larger difference in the display effect of the camera display area and the display effect of other display areas, causing uneven display.

[0069] Figure 1 is a schematic plan view of a display panel provided by an embodiment of the present disclosure. Figure 1 The display panel includes a substrate 10, which has a display area 100 and a peripheral area 200 that at least partially surrounds the display area 100. The display area 100 can be used to arrange pixel circuits, and the peripheral area 200 can be used to arrange integrated circuits, which are used to drive the pixel circuits to work. Exemplarily, the peripheral area 200 at least partially surrounds the display area 100, which means that the peripheral area 200 can surround the display area 100; or, both sides of the display area 100 are connected to the peripheral area 200; or, the display area 100 and the peripheral area 200 are side by side, and at this time, one side of the display area 100 is connected to the peripheral area 200.

[0070] The display area 100 includes a first display area 101 and a second display area 102 at least located on one side of the first display area 101. The light transmittance of the first display area 101 is greater than the light transmittance of the second display area 102. The light transmittance of the first display area 101 is relatively high, so there is no need to perform hole digging on the base substrate 10, and the required hardware structures such as the light sensor can be directly set at a position opposite to the first display area 101, thereby realizing a true full-screen display device. Exemplarily, the light sensor can be a camera.

[0071] exist Figure 1 In the embodiment, the shape of the first display area 101 is a rectangle. In other implementations, the shape of the first display area 101 may be a circle, a polygon, or other regular or irregular shapes.

[0072] Exemplarily, the second display area 102 located at least on one side of the first display area 101 indicates that the second display area 102 can surround the first display area 101; or, both sides of the first display area 101 are connected to the second display area 102; or, the first display area 101 and the second display area 102 are side by side, in which case one side of the first display area 101 is connected to the second display area 102.

[0073] See again Figure 1 , the second display area 102 surrounds the first display area 101. Exemplarily, the first display area 101 is located in the middle of the top area of ​​the base substrate 10.

[0074] In some embodiments, the first display area 101 may also be located at other positions of the base substrate 10. Figure 1 , the first display area 101 may be located at the upper left corner or the upper right corner of the base substrate 10 .

[0075] Figure 2 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 2 The display panel further includes a plurality of first pixel units 20 and a plurality of signal lines 30. The plurality of first pixel units 20 are located on the base substrate 10 and located in the first display area 101. The plurality of signal lines 30 are at least located in the first display area 101 and are electrically connected to the plurality of first pixel units 20.

[0076] Figure 3 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 3 , the plurality of signal lines 30 include a plurality of first signal lines 301 and a plurality of second signal lines 302. For example, the first signal line 301 may include a gate signal line and a data signal line, and the second signal line 302 may include a reset signal line. The plurality of first pixel units 20 are arranged into a plurality of rows of pixel units, and in the arrangement direction of a row of pixel units, the pixel units in two adjacent rows of pixel units are staggered with each other, and the pixel units in two adjacent rows of pixel units are connected by a first signal line 301 or a second signal line 302. Both the first signal line 301 and the second signal line 302 are wavy line-shaped.

[0077] The first portion of each of the plurality of first signal lines 301 is a metal signal line, and the first portion of the first signal line 301 is at least located in the first display area 101. The first portion of each of the plurality of second signal lines 302 is a metal oxide signal line, and the first portion of the second signal line 302 is at least located in the first display area 101.

[0078] In the disclosed embodiment, the light transmittance of the first display area 101 is relatively high, and the light sensor (e.g., full-screen camera) can be arranged in the area corresponding to the first display area 101, so that light can pass through the first display area 101 to the light sensor. The first part of the first signal line 301 in the first display area 101 is a metal signal line. The resistance of the metal is smaller than that of the metal oxide, which can reduce the resistance of the first signal line 301 and the load of the first signal line, so that the voltage received by the pixel unit 20 in the first display area 101 increases, and the voltage received by the pixel unit 20 in the first display area 101 is less different from the voltage received by the pixel unit 20 in other areas, thereby improving the phenomenon of uneven display. At the same time, the first part of the second signal line 302 is a metal oxide signal line, thereby ensuring the light transmittance of the first display area 101.

[0079] At the same time, since the first pixel units 20 in the first display area 101 are regularly arranged, and the gaps between the pixel units 20 are also regularly arranged, the light is prone to diffraction when passing through the gaps in the first display area 101. The light that has diffracted is then propagated to the full-screen camera, which will affect the camera effect of the full-screen camera. In the embodiment of the present disclosure, the first part of each of the first signal lines 301 passing through the first display area 101 is arranged as a metal signal line, and the metal signal line is not transparent, thereby breaking the regular arrangement of the gaps between the pixel units 20, and improving the diffraction of the light to a certain extent, thereby improving the camera effect of the full-screen camera.

[0080] In the disclosed embodiment, the first signal line 301 also includes a second portion located in the second display area 102 , and the second signal line 302 also includes a second portion located in the second display area 102 . The second portion of the first signal line 301 and the second portion of the second signal line 302 are both metal signal lines.

[0081] In the embodiment of the present disclosure, there is no need to arrange a light sensor in the second display area 102, so the second display area 102 does not need to have a high light transmittance. The first signal line 301 and the second signal line 302 in the second display area 102 are arranged as metal signal lines, which can reduce the load of the first signal line 301 and the second signal line 302, increase the display brightness of the display panel, and improve the display effect.

[0082] In the disclosed embodiment, the first portion of each of the plurality of second signal lines 302 is a transparent metal oxide signal line, so that part of the signal lines 30 in the first display area 101 are transparent signal lines, thereby ensuring the light transmittance of the first display area 101 .

[0083] In an implementation of the embodiment of the present disclosure, the first signal line 301 includes at least one of a gate signal line and a data signal line.

[0084] Each first pixel unit 20 includes a switching transistor and a driving transistor. The gate signal line is responsible for providing a turn-on voltage to the gate of the switching transistor, and the data signal line is responsible for providing a turn-on voltage to the gate of the driving transistor. The resistance of the transparent metal oxide signal line is relatively large. The use of the transparent metal oxide signal line will result in a smaller turn-on voltage, which makes the switch thin film transistor unable to turn on, or the switch thin film transistor is turned on for a short time, and the brightness is inconsistent compared to the area using the metal signal line, which affects the display uniformity of the display panel. In the embodiment of the present disclosure, by replacing at least one of the gate signal line and the data signal line in the first display area 101 with a metal signal line, the resistance of the gate signal line or the data signal line can be reduced, and the turn-on voltage of the first pixel unit 20 located in the first display area 101 can be increased, thereby improving the display uniformity.

[0085] Exemplarily, the metal oxide signal line may be an indium tin oxide signal line. Indium tin oxide has good transparency, which ensures the transparency of the metal oxide signal line.

[0086] See again Figure 2 The display panel further includes a plurality of second pixel units 40 , the plurality of second pixel units 40 are located in the second display area 102 , and the plurality of second pixel units 40 and the plurality of first pixel units 20 are arranged into a plurality of rows of pixel units.

[0087] Since the light transmittance of the first pixel unit 20 and the second pixel unit 40 are both poor, in order to improve the light transmittance of the first display area 101, the size of the first pixel unit 20 can be designed to be smaller than the size of the second pixel unit 40 during manufacturing to improve the light transmittance of the first display area 101.

[0088] In one implementation of the embodiment of the present disclosure, the signal line 30 further includes a reset (Reset) signal line, a light emission control (EM) signal line, an initial voltage (Vinit) signal line, and a power supply (VDD) signal line. Except for the first signal line 301, all signal lines 30 are second signal lines 302, that is, the reset signal line, the light emission control signal line, the initial voltage signal line, and the power supply signal line are all second signal lines 302.

[0089] The metal signal line has a small resistance but poor light transmittance, while the transparent metal oxide signal line has a large resistance but high light transmittance. Since the area corresponding to the first display area 101 in the display device is arranged with a light sensor, while reducing the resistance of the signal line in the first display area 101, it is also necessary to ensure the light transmittance of the first display area 101. Through experimental simulation, it is found that signal lines such as the reset signal line, the light control signal line, the initial voltage signal line and the power signal line have little effect on the display brightness. Arranging these signal lines as transparent metal oxide signal lines can ensure the light transmittance of the first display area 101.

[0090] In an implementation of the embodiment of the present disclosure, the first signal line 301 includes a gate signal line and a data signal line, and the second signal line 302 includes a reset signal line, a light emitting control signal line, an initial voltage signal line, and a power signal line.

[0091] In an implementation of the embodiment of the present disclosure, the gate signal line includes a molybdenum signal line, and the data signal line includes a titanium signal line.

[0092] In the related art, the material of the first portion of the first signal line passing through the first display area is metal oxide. In the embodiment of the present disclosure, the material of the first portion of the first signal line passing through the first display area is metal. In this way, the first signal line passing through the first display area and the first signal line not passing through the first display area can be manufactured in the same way, that is, the entire signal line is on the same layer.

[0093] Figure 4 yes Figure 2 Schematic diagram of the cross section of the AA surface. Figure 4 The display panel includes a first metal layer 201, a first insulating layer 202 and a metal oxide layer 203 which are sequentially located on the base substrate 10 in a direction away from the base substrate 10, a first signal line 301 ( Figure 4 The first metal layer 201 is provided with a plurality of second signal lines 302 (not shown), and at least one second signal line 302 among the plurality of second signal lines 302 located in the first display area 101 has a first portion located in the metal oxide layer 203 in the first display area 101, and a second portion in the second display area 102 is located in the first metal layer 201. The first portion and the second portion of the second signal line 302 are connected through a first via hole 221 penetrating the first insulating layer 202, and the first via hole 221 is located at the junction of the first display area 101 and the second display area 102. The junction of the first display area 101 and the second display area 102 refers to the area where the boundary connecting the first display area 101 and the second display area 102 is located. At least one second signal line 302 among the plurality of second signal lines 302 means that it can be one second signal line 302, or a plurality of second signal lines 302, or all second signal lines 302.

[0094] In the embodiment of the present disclosure, the first signal line 301 is a metal signal line, arranged in the first metal layer 201, the second signal line 302 is a transparent metal oxide signal line in the first display area 101, and is a metal line in the second display area 102. The second signal line 302 in the first display area 101 is arranged in the metal oxide layer 203 to ensure the transmittance of the first part of the second signal line 302. The second signal line 302 in the second display area 102 is arranged in the first metal layer 201 to reduce the resistance of the second part of the second signal line 302. At the same time, the first part and the second part of the second signal line 302 are connected through the first via 221 to ensure the effectiveness of the electrical connection.

[0095] In the embodiment of the present disclosure, the first metal layer 201 includes a first gate metal layer and a first source-drain metal layer, and the first insulating layer 202 includes a first passivation layer and an interlayer dielectric layer.

[0096] Exemplarily, the first signal line 301 includes one of a gate signal line and a data signal line, and the second signal line 302 includes the other of the gate signal line and the data signal line. For example, the first signal line 301 is a gate signal line, the second signal line 302 is a data signal line, the gate signal line is located in the first gate metal layer 211, the data signal line in the first display area 101 is located in the metal oxide layer 203, and the data signal line in the second display area 102 is located in the first source-drain metal layer 212.

[0097] Figure 5 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 4 and Figure 5 They are cross-sectional views at different cross sections, see Figure 5 , the display panel includes a first gate metal layer 211, a first passivation layer 222, a first source-drain metal layer 212, an interlayer dielectric layer 223 and a metal oxide layer 203 which are sequentially located on the substrate 10 in a direction away from the substrate 10. At this time, the display panel only includes one gate metal layer and one source-drain metal layer. The aforementioned first metal layer 201 includes the first gate metal layer 211 and the first source-drain metal layer 212. The aforementioned first insulating layer 202 includes the first passivation layer 222 and the interlayer dielectric layer 223. The first signal line 301 includes both a gate signal line and a data signal line. In the first display area 101 and the second display area 102, the gate signal line is located in the first gate metal layer 211. In the first display area 101 and the second display area 102, the data signal line is located in the first source-drain metal layer 212. Figure 5 Only the first signal line 301 is shown.

[0098] Figure 6is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 6 The display panel includes a first gate metal layer 211, a first passivation layer 222, a first source-drain metal layer 212, an interlayer dielectric layer 223 and a metal oxide layer 203. In a direction away from the base substrate 10, the first gate metal layer 211, the first passivation layer 222, the first source-drain metal layer 212, the interlayer dielectric layer 223 and the metal oxide layer 203 are stacked in sequence.

[0099] Exemplarily, the second signal line 302 includes an initial voltage signal line. In the first display area 101, the second signal line 302 is located in the metal oxide layer 203, and in the second display area 102, the second signal line 302 is located in the first gate metal layer 211. Figure 6 Only the second signal line 302 is shown.

[0100] Exemplarily, the second signal line 302 also includes a reset signal line and a light-emitting control signal line. In the second display area 102, the reset signal line and the light-emitting control signal line are located in the first gate metal layer 211, and in the first display area 101, the reset signal line and the light-emitting control signal line are located in the metal oxide layer 203. The reset signal line located in the first display area 101 and the reset signal line located in the second display area 102 are electrically connected through the first via 221, and the light-emitting control signal line located in the first display area 101 and the light-emitting control signal line located in the second display area 102 are electrically connected through the first via 221, and at this time, the first via 221 passes through the first passivation layer 222, the first source-drain metal layer 212 and the interlayer dielectric layer 223.

[0101] Figure 7 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 7 , the display panel includes a first gate metal layer 211, a first passivation layer 222, a first source-drain metal layer 212, an interlayer dielectric layer 223 and a metal oxide layer 203 located on the base substrate 10. At this time, the second signal line 302 includes a power signal line. In the first display area 101, the second signal line 302 is located in the metal oxide layer 203, and in the second display area 102, the second signal line 302 is located in the first source-drain metal layer 212. Figure 7 Only the second signal line 302 is shown.

[0102] See again Figure 7The second signal line 302 is a power signal line. In the second display area 102, the power signal line is located in the first source-drain metal layer 212. In the first display area 101, the power signal line is located in the metal oxide layer 203. The power signal line located in the first display area 101 and the power signal line located in the second display area 102 are electrically connected through the first via 221. At this time, the first via 221 passes through the interlayer dielectric layer 223. In other implementations, the power signal line can also be located in the second source-drain metal layer.

[0103] Figure 8 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 8 , compared to Figure 4 The display panel further includes a second insulating layer 204 and a second metal layer 205, wherein the second insulating layer 204 is located between the first metal layer 201 and the second metal layer 205. A first portion of another portion of the second signal lines 302 in the first display region 101 is located in the metal oxide layer 203, and a second portion in the second display region 102 is located in the second metal layer 205. The first portion and the second portion of the second signal line 302 are connected via a second via hole 241 penetrating through the first insulating layer 202 and the second insulating layer 204, and the second via hole 241 is located at the boundary between the first display region 101 and the second display region 102.

[0104] In an implementation of the embodiment of the present disclosure, the second metal layer 205 is a second gate metal layer, and the second insulating layer 204 is a first gate insulating layer.

[0105] Exemplarily, the second signal line 302 may also include a reset signal line, a light-emitting control signal line, an initial voltage signal line and a power signal line. In the first display area 101, the reset signal line, the light-emitting control signal line, the initial voltage signal line and the power signal line are located in the metal oxide layer 203. In the second display area 102, the reset signal line, the light-emitting control signal line, the initial voltage signal line and the power signal line are located in the second gate metal layer.

[0106] In an implementation of the embodiment of the present disclosure, the second metal layer 205 is a second gate metal layer, and the second insulating layer 204 is a first gate insulating layer.

[0107] Fig. 9 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Fig. 9 , compared to Figure 8The display panel includes a second gate metal layer 251, a first gate insulating layer 242, a first gate metal layer 211, a first passivation layer 222, a first source and drain metal layer 212, an interlayer dielectric layer 223 and a metal oxide layer 203 which are sequentially located on the base substrate 10 in a direction away from the base substrate 10.

[0108] See again Fig. 9 The second signal line 302 is an initial voltage signal line. In the second display area 102, the initial voltage signal line is located at the second gate metal layer 251. In the first display area 101, the initial voltage signal line is located at the metal oxide layer 203. Part of the initial voltage signal line located in the first display area 101 and part of the initial voltage signal line located in the second display area 102 are electrically connected through the second via 241. At this time, the second via 241 passes through the first gate insulating layer 242, the first gate metal layer 211, the first passivation layer 222, the first source and drain metal layer 212 and the interlayer dielectric layer 223.

[0109] It should be noted that the gate signal line is located in the first gate metal layer 211 , and the data signal line is located in the first source-drain metal layer 212 .

[0110] See again Fig. 9 The display panel further includes an active layer 206, a second gate insulating layer 207, a second passivation layer 208 and a second source-drain metal layer 209. The second gate insulating layer 207 is located between the active layer 206 and the second gate metal layer 251, and the second passivation layer 208 is located between the metal oxide layer 203 and the second source-drain metal layer 209.

[0111] The active layer 206 may be a polycrystalline silicon (Polycrystalline Silicon) material layer, referred to as a Poly layer. The second gate insulating layer 207 separates the active layer 206 from the second gate metal layer 251. The second source-drain metal layer 209 is a turn layer, and the second passivation layer 208 separates the first source-drain metal layer 212 from the second source-drain metal layer 209.

[0112] In the embodiment of the present disclosure, the first gate metal layer 211 and the second gate metal layer 251 include a metal molybdenum layer, and the first source-drain metal layer 212 and the second source-drain metal layer 209 include a metal titanium layer. The second gate insulating layer 207, the first gate insulating layer 242, the interlayer dielectric layer 223, the first passivation layer 222 and the second passivation layer 208 can be one of a silicon nitride layer, a silicon oxide layer or an epoxy resin layer.

[0113] In the embodiment of the present disclosure, the base substrate 10 may be a glass substrate or a polyimide substrate.

[0114] Front Figures 4 to 9All of them show part of the film layer of the display panel. Fig.10 Introducing the relatively complete film structure of the display panel. Fig.10 The film structure corresponds to the above Figure 2 Detailed description of the structure of the first pixel unit 20.

[0115] Fig.10 Schematic diagram of a film layer of a pixel provided by an embodiment of the present disclosure. Fig.10 The display panel includes a buffer layer (Buffer) 2010, an active layer 206, a second gate insulating layer 207, a second gate metal layer 251, a first gate insulating layer 242, a first gate metal layer 211, an interlayer dielectric layer 223, a first source-drain metal layer 212, a second passivation layer 208, a planarization layer 2011, an anode layer 2012, a pixel defining layer 2013, a spacer layer 2014, a light-emitting layer 2015, a cathode layer 2016, a first inorganic encapsulation layer 2017, an organic encapsulation layer 2018, and a second inorganic encapsulation layer 2019, which are sequentially located on the substrate 10 in a direction away from the substrate 10. At this time, the display panel includes only one source-drain metal layer, namely, the first source-drain metal layer 212.

[0116] The buffer layer 2010 is located between the base substrate 10 and the active layer 206 . The buffer layer 2010 is used to reduce the impact on the base substrate 10 when etching the active layer 206 .

[0117] The planarization layer 2011 is located on a side of the second passivation layer 208 away from the first source-drain metal layer 212 . The planarization layer 2011 is used to make the surface of the display panel having the first source-drain metal layer 212 more flat.

[0118] The anode layer 2012 is located on a side of the planarization layer 2011 away from the first source-drain metal layer 212, and the anode layer 2012 is electrically connected to the first source-drain metal layer 212. The pixel defining layer 2013 is located on a side of the anode layer 2012 and the first source-drain metal layer 212, and the pixel defining layer 2013 has an opening, which is connected to the anode layer 2012, and the light-emitting layer 2015 is located in the opening. The spacer layer 2014 can be used to support the mask when evaporating the light-emitting layer 2015. The cathode layer 2016 is located on a side of the light-emitting layer 2015 away from the first source-drain metal layer 212, and a voltage is formed between the cathode layer 2016 and the anode layer 2012, thereby controlling the light-emitting layer 2015 to emit light. The first inorganic encapsulation layer 2017, the organic encapsulation layer 2018 and the second inorganic encapsulation layer 2019 together constitute an encapsulation layer, which encapsulates the display panel to ensure the integrity of the display panel.

[0119] In the embodiment of the present disclosure, the pixel unit includes a capacitor 60. Fig.10The first electrode plate 601 of the capacitor 60 is located on the second gate metal layer 251 , and the second electrode plate 602 of the capacitor is located on the first gate metal layer 211 .

[0120] exist Fig.10 In the embodiment, the second gate insulating layer 207, the second gate metal layer 251, the first gate insulating layer 242, and the first gate metal layer 211 are sequentially arranged in a direction away from the base substrate 10. In other implementations, the second gate insulating layer 207, the first gate metal layer 211, the first gate insulating layer 242, and the second gate metal layer 251 may be sequentially arranged, and the present disclosure is not limited thereto.

[0121] Fig.11 is a top view of the first display area provided by the embodiment of the present disclosure. Fig.11 The first display area 101 is in the shape of a long strip, the first size L1 of the first display area 101 is greater than the second size L2 of the first display area 101, the first size L1 of the first display area 101 is the size of the first display area 101 in the extension direction of the gate signal line, and the second size L2 of the first display area 101 is the size of the first display area 101 in the extension direction of the data signal line. The display device includes a plurality of light sensors 50, the orthographic projections of the plurality of light sensors 50 on the display panel are located in the first display area 101, and the extension direction of the plurality of light sensors 50 is parallel to the extension direction of the gate signal line.

[0122] exist Fig.11 In the embodiment, three light sensors 50 are arranged in the area corresponding to the first display area 101 in the display device.

[0123] Fig.12 is a top view of another first display area provided by an embodiment of the present disclosure. Fig.12 The display device includes four light sensors 50. The four light sensors 50 are divided into two groups. One group includes two light sensors 50. The distance between the two light sensors 50 in the same group is 0, and there is a certain gap between two adjacent groups.

[0124] In other implementations, other numbers of light sensors 50 may be arranged in the display device, and the present disclosure does not limit this.

[0125] for Fig.11 and Fig.12 In the first display area 101 shown, a ratio of a first size L1 of the first display area 101 to a second size of the first display area 101 is greater than 2.

[0126] Fig.13 is a pixel arrangement diagram of a first display area provided by an embodiment of the present disclosure. Figures 11 to 13When the ratio of the first size L1 of the first display area 101 to the second size of the first display area 101 is greater than 2, the first signal line 301 is a gate signal line.

[0127] The gate signal line is electrically connected to a plurality of first pixel units 20, and the gate signal line has a load, so the first pixel unit 20 closer to the driving circuit will receive a larger gate voltage, and the first pixel unit 20 farther from the driving circuit will receive a smaller gate voltage. When the ratio of the first size L1 of the first display area 101 to the second size L2 of the first display area 101 is greater than 2, it means that the length of the gate signal line in the first display area 101 is greater than the length of the data signal line in the first display area 101. The length of the signal line is negatively correlated with the resistance of the resistance signal line, so in the first display area 101, the display unevenness caused by the gate signal line is greater. Arranging the gate signal line as a metal signal line can reduce the display unevenness caused by the gate signal line and improve the display unevenness.

[0128] exist Figures 11 to 13 In the embodiment, the first display area 101 extends along the extension direction of the first size L1. In other implementations, the first display area 101 may also extend along other directions.

[0129] Fig.14 is a top view of another first display area provided by an embodiment of the present disclosure. Fig.14 The first display area 101 is also in the shape of a long strip. The first size L1 of the first display area 101 is smaller than the second size L2 of the first display area 101. A plurality of light sensors 50 are arranged in the first display area 101. The extension direction of the plurality of light sensors 50 is the extension direction of the second size L2.

[0130] exist Fig.14 In the embodiment, the display device includes two light sensors 50 . Fig.15 is a top view of another first display area provided by an embodiment of the present disclosure. Fig.15 The display device includes four light sensors 50. The four light sensors 50 are divided into two groups. One group includes two light sensors 50. The distance between the two light sensors 50 in the same group is 0, and there is a certain gap between two adjacent groups.

[0131] Fig.16 is a top view of another first display area provided by an embodiment of the present disclosure. Fig.16 The display device includes four light sensors 50, and the distance between two adjacent light sensors 50 is 0.

[0132] Fig.17is a top view of another first display area provided by an embodiment of the present disclosure. Fig.17 The display device includes three light sensors 50, and the distance between two adjacent light sensors 50 is 0.

[0133] In other implementations, the display device may also be provided with other numbers of light sensors 50 , which is not limited in the present disclosure.

[0134] for Figures 14 to 17 In the first display area 101 shown, a ratio of a first size L1 of the first display area 101 to a second size L2 of the first display area 101 is less than 0.5. Fig.18 is another pixel arrangement diagram of the first display area provided by an embodiment of the present disclosure. Figures 14 to 18 When the ratio of the first size L1 of the first display area 101 to the second size L2 of the first display area 101 is less than 0.5, the first signal line 301 is a data signal line.

[0135] The data signal line is similar to the gate signal line. The first pixel unit 20 closer to the driving circuit will receive a larger data voltage, and the first pixel unit 20 farther from the driving circuit will receive a smaller data voltage. When the ratio of the first size L1 of the first display area 101 to the second size L2 of the first display area 101 is less than 0.5, it means that the length of the data signal line in the first display area 101 is greater than the length of the gate signal line in the first display area 101. In the first display area 101, the uneven display caused by the data signal line is greater. Arranging the data signal line as a metal signal line can reduce the uneven display caused by the data signal line and improve the uneven display phenomenon.

[0136] exist Figures 11 to 18 In the embodiment, the first display area 101 is in the shape of a long strip. In other implementations, the first display area 101 may also be in the shape of a square.

[0137] Fig.19 is a top view of another first display area provided by an embodiment of the present disclosure. Fig.19 The first display area 101 is in a square shape, a first size L1 of the first display area 101 is substantially equal to a second size L2 of the first display area 101 , and three light sensors 50 are arranged in the first display area 101 , and the three light sensors 50 are arranged in a triangle.

[0138] exist Fig.19 In the embodiment, the display device includes three light sensors 50 . Fig. 20 is a top view of another first display area provided by an embodiment of the present disclosure. Fig. 20The display device includes four light sensors 50, and the four light sensors 50 are arranged in a square.

[0139] Fig.21 is a top view of another first display area provided by an embodiment of the present disclosure. Fig.21 The display device includes five light sensors 50, and the five light sensors 50 are arranged in a pentagon.

[0140] Fig. 22 is a top view of another first display area provided by an embodiment of the present disclosure. Fig. 22 The display device includes six light sensors 50, and the six light sensors 50 are arranged in a hexagonal shape.

[0141] In other implementations, the display device may also be provided with other numbers of light sensors 50 , which is not limited in the present disclosure.

[0142] for Figures 19 to 22 In the first display area 101 shown, a ratio of a first size of the first display area 101 to a second size of the first display area 101 is between 0.5 and 2. Fig.23 is another pixel arrangement diagram of the first display area provided by an embodiment of the present disclosure. Figures 19 to 23 When the ratio of the first size L1 of the first display area 101 to the second size L2 of the first display area 101 is between 0.5 and 2, the first signal line 301 includes a gate signal line and a data signal line.

[0143] When the ratio of the first size L1 of the first display area 101 to the second size L2 of the first display area 101 is between 0.5 and 2, it means that in the first display area 101, the length of the gate signal line and the length of the data signal line are not much different, and the display unevenness phenomenon caused by the gate signal line and the data signal line is also not much different. Arranging the gate signal line and the data signal line as metal signal lines can simultaneously reduce the display unevenness phenomenon caused by the gate signal line and the data signal line, and improve the display unevenness phenomenon.

[0144] Fig.24 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Fig.24 The display panel includes a plurality of first pixel units 20 and a plurality of second pixel units 40. The plurality of first pixel units 20 and the plurality of second pixel units 40 are arranged in a plurality of rows of pixel units, and in the arrangement direction of a row of pixel units, the pixel units in two adjacent rows of pixel units are staggered with each other, and the pixel units in two adjacent rows of pixel units are connected by a gate signal line.

[0145] Multiple rows of pixel units are staggered, and more pixel units can be arranged on the same area, thereby increasing the density of pixel units, thereby increasing the resolution of the display panel and further improving the display effect. At the same time, the pixel units in two adjacent rows of pixel units are connected through gate signal lines to avoid overly complicated wiring and simplify the circuit structure.

[0146] See again Figure 3 and Fig.24 The gate signal line is in a wavy line shape, and the crest and trough of the gate signal line are respectively connected to the first pixel unit 20 or the second pixel unit 40.

[0147] See again Figure 3 and Fig.24 , the data signal line is also wavy.

[0148] In the embodiment of the present disclosure, both the first pixel unit 20 and the second pixel unit 40 include a 7T1C pixel circuit.

[0149] Fig.25 7T1C pixel circuit diagram provided by the embodiment of the present disclosure. Fig.25 The pixel circuit includes a first switch transistor T1, a first compensation transistor T2, a first reset transistor T3, a second reset transistor T4, a driving transistor T5, a first light emission control transistor T6, a second light emission control transistor T7 and a capacitor Cst.

[0150] The control electrode of the first switch transistor T1 is electrically connected to a gate line through the first scan signal terminal (Scan[n]), the first electrode of the first switch transistor T1 is electrically connected to a data line through the data input terminal (Data[m]), and the second electrode of the first switch transistor T1 is electrically connected to the first node N1.

[0151] The control electrode of the first compensation transistor T2 is electrically connected to a gate line through the first scan signal terminal (Scan[n]), the first electrode of the first compensation transistor T2 is electrically connected to the second node N2, and the second electrode of the first compensation transistor T2 is electrically connected to the third node N3.

[0152] The control electrode of the first reset transistor T3 is electrically connected to another gate line through the second scan signal terminal (Scan[n-1]), the first electrode of the first reset transistor T3 is electrically connected to the initial voltage signal line through the initialization voltage terminal (Vinit), and the second electrode of the first reset transistor T3 is electrically connected to the third node N3.

[0153] The control electrode of the second reset transistor T4 is electrically connected to a gate line through the first scan signal terminal (Scan[n]), the first electrode of the second reset transistor T4 is electrically connected to the initial voltage signal line through the initialization voltage terminal (Vinit), and the second electrode of the second reset transistor T4 is electrically connected to the fourth node N4.

[0154] The control electrode of the driving transistor T5 is electrically connected to the third node N3 , the first electrode of the driving transistor T5 is electrically connected to the first node N1 , and the second electrode of the driving transistor T5 is electrically connected to the second node N2 .

[0155] The control electrode of the first light emission control transistor T6 is electrically connected to the light emission control signal line through the light emission control signal terminal (EM[n]), the first electrode of the first light emission control transistor T6 is electrically connected to the first node N1, and the second electrode of the first light emission control transistor T6 is electrically connected to the fifth node N5. The fifth node N5 is electrically connected to the power signal line through the first voltage signal terminal (ELVDD).

[0156] The control electrode of the second light emitting control transistor T7 is electrically connected to the light emitting control signal line through the light emitting control signal terminal (EM[n]), the first electrode of the second light emitting control transistor T7 is electrically connected to the second node N2, and the second electrode of the second light emitting control transistor T7 is electrically connected to the fourth node N4.

[0157] A first plate of the capacitor Cst is electrically connected to the fifth node N5, and a second plate of the capacitor Cst is electrically connected to the third node N3.

[0158] See again Fig.25 The pixel circuit further includes a light emitting diode LED, the fourth node N4 is electrically connected to one end of the light emitting diode LED, and one end of the light emitting diode LED is electrically connected to the second voltage signal end (ELVSS).

[0159] The 7T1C pixel circuit in the embodiment of the present disclosure is only used as an example. In other implementations, the pixel circuit may also be other structures, for example, the pixel circuit is a 2T1C pixel circuit.

[0160] Fig.26 is a flow chart of a method for manufacturing a display panel provided by the present disclosure. The display panel has a first light-transmitting display area. Fig.26 , the preparation method comprises:

[0161] In step S401 , a base substrate is provided.

[0162] The base substrate has a display area and a peripheral area at least partially surrounding the display area, the display area includes a first display area and a second display area at least located on one side of the first display area, and the transmittance of the first display area is greater than that of the second display area.

[0163] In the embodiment of the present disclosure, the substrate may be a glass substrate or a polyimide substrate.

[0164] In step S402, a plurality of first pixel units and a plurality of signal lines are formed on a base substrate.

[0165] Among them, multiple first pixel units are located in the first display area; multiple signal lines are at least located in the first display area and electrically connected to the multiple first pixel units, the multiple signal lines include multiple first signal lines and multiple second signal lines, the first part of each of the multiple first signal lines is a metal signal line, the first part of the first signal line is at least located in the first display area, the first part of each of the multiple second signal lines is a metal oxide signal line, and the first part of the second signal line is at least located in the first display area.

[0166] Exemplarily, step S402 may include the following steps:

[0167] Fig. 27 is a flow chart of a method for manufacturing a display panel provided by the present disclosure. Fig. 27 , the method comprising:

[0168] S421: forming an active layer on one side of the base substrate.

[0169] Exemplarily, the active layer may be a polysilicon layer. Fig.28 is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure. Fig.28 , an active thin film can be formed on one side of the substrate by evaporation, and then the active thin film is patterned by a composition process to obtain a Fig.28 It is worth noting that the active layer 206 includes active patterns corresponding to a plurality of pixel units, such as Fig.28 As shown, the middle part is a complete active pattern, and the four corners are parts of the other four active patterns. Figure 29 to Figure 35 and Fig.28 Similarly, the middle part of the pattern is a pixel unit, and the four corners are parts of other pixel units. Figure 28 to Figure 35 The display panel shown is located in the first display area.

[0170] S422: forming a second gate insulating layer on a side of the active layer away from the substrate.

[0171] Exemplarily, the second gate insulating layer may be a silicon nitride layer, and the second gate insulating layer may be formed on one side of the active layer by evaporation, and the second gate insulating layer covers the active layer.

[0172] S423: forming a first gate metal layer on a side of the second gate insulating layer away from the substrate.

[0173] Fig.29 is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure. Fig.29 A first gate metal layer 211 is formed on the second gate insulating layer. In the first display area, the first gate metal layer includes a second electrode 602 of the capacitor, a control electrode G of the thin film transistor, and a gate signal line Gate.

[0174] In the embodiment of the present disclosure, the gate signal line Gate in the first display area and the second display area are both located in the first gate metal layer, and in the second display area, the reset signal line and the first part of the light emitting control signal line are located in the first gate metal layer.

[0175] Exemplarily, the first gate metal layer may be a metal molybdenum layer, and a first gate metal film may be formed on one side of the first gate insulating layer by sputtering, and then the first gate metal film may be patterned by a composition process to obtain the first gate metal layer.

[0176] S424: forming a first gate insulating layer on a side of the first gate metal layer away from the substrate.

[0177] Exemplarily, the first gate insulating layer may be a silicon nitride layer, and the first gate insulating layer may be formed on one side of the second gate metal layer by evaporation, and the first gate insulating layer covers the second gate metal layer.

[0178] S425: forming a second gate metal layer on a side of the first gate insulating layer away from the substrate.

[0179] Exemplarily, the second gate metal layer may be a metal molybdenum layer. Fig.30 is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure. Fig.30 A second gate metal film can be formed on one side of the first gate insulating layer by sputtering, and then the second gate metal film is patterned by a composition process to obtain a second gate metal layer 251. In the first display area, the second gate metal layer 251 includes a first electrode 601 of a capacitor.

[0180] S426: forming a first passivation layer on a side of the second gate metal layer away from the substrate.

[0181] Exemplarily, the first passivation layer may be a silicon nitride layer, and the first passivation layer may be formed on one side of the second gate metal layer by evaporation.

[0182] Fig.31is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure. Fig.31 , a first via hole 221 is formed in the first passivation layer.

[0183] Exemplarily, the first via hole 221 may be formed by etching.

[0184] S427: forming a first source-drain metal layer on a side of the first passivation layer away from the substrate.

[0185] Fig.32 is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure. Fig.32 A first source-drain metal film can be formed on one side of the first passivation layer by sputtering, and then the first source-drain metal film is patterned by a composition process to obtain a first source-drain metal layer 212.

[0186] In the embodiment of the present disclosure, the data signal line Data is located in the first source-drain metal layer.

[0187] S428: forming an interlayer dielectric layer on a side of the first source / drain metal layer away from the substrate.

[0188] Exemplarily, the interlayer dielectric layer may be a silicon nitride layer, and the interlayer dielectric layer may be formed on one side of the metal oxide layer by evaporation.

[0189] S429: forming a metal oxide layer on a side of the interlayer dielectric layer away from the substrate.

[0190] Fig.33 is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure. Fig.33 , a metal oxide film can be formed on one side of the interlayer dielectric layer by sputtering, and then the metal oxide film is patterned by a composition process to obtain a metal oxide layer 203.

[0191] In the embodiment of the present disclosure, in the first display area, the second parts of the reset signal line Reset, the light emitting control signal line EM and the initial voltage signal line Vinit are all located in the metal oxide layer 203, and the first part of the power signal line VDD is located in the metal oxide layer.

[0192] The first and second parts of the reset signal line are electrically connected through a first via hole, the first and second parts of the light emitting control signal line are electrically connected through a first via hole, and the first and second parts of the initial voltage signal line are electrically connected through a second via hole.

[0193] S4210: forming a second passivation layer on a side of the metal oxide layer away from the substrate.

[0194] Exemplarily, the second passivation layer may be a silicon nitride layer, and the first passivation layer may be formed on one side of the first source / drain metal layer by evaporation.

[0195] S4211: forming a second source-drain metal layer on a side of the second passivation layer away from the substrate.

[0196] Exemplarily, the second source-drain metal layer may be a metal titanium layer. Fig.34 is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure. Fig.34 , a second source-drain metal film can be formed on one side of the second passivation layer by sputtering, and then the second source-drain metal film is patterned by a composition process to obtain a second source-drain metal layer 209. Fig.34 In the embodiment, the second source-drain metal layer 209 shields the first source-drain metal layer 212. The second portion of the power signal line is located in the second source-drain metal layer 209.

[0197] Finally, other film layers of the display panel, such as a planarization layer, a pixel defining layer, a light-emitting layer and a packaging layer, are formed on the second source-drain metal layer to complete the manufacture of the display panel.

[0198] For example, Fig.35 is a process diagram of a method for manufacturing a display panel provided by an embodiment of the present disclosure. Fig.35 , an anode layer 2012 is formed on the second source-drain metal layer 209 .

[0199] It should be noted that, in order to clearly illustrate the manufacturing process of the metal layer and the metal oxide layer, the manufacturing process diagram of the insulating layer is omitted in the above manufacturing process diagram.

[0200] An embodiment of the present disclosure further provides a display device, which includes a power supply component and the above-mentioned display panel, wherein the power supply component is used to supply power to the display panel.

[0201] In specific implementation, the display device provided in the embodiment of the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0202] In an implementation of the embodiment of the present disclosure, the display device further includes a light sensor, which is located on a side of the display panel away from the plurality of first pixel units, and an orthographic projection of the light sensor on the base substrate at least partially overlaps with the first display area.

[0203] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel comprises: A base substrate, comprising a display area and a peripheral area at least partially surrounding the display area, wherein the display area comprises a first display area and a second display area at least located on one side of the first display area, and the light transmittance of the first display area is greater than the light transmittance of the second display area; A plurality of first pixel units, located on the base substrate and located in the first display area; a plurality of signal lines, at least located in the first display area and electrically connected to the plurality of first pixel units; The plurality of signal lines include a plurality of first signal lines and a plurality of second signal lines, the first portion of each of the plurality of first signal lines is a metal signal line, and the first portion of the first signal line is at least located in the first display area; the first portion of each of the plurality of second signal lines is a metal oxide signal line, and the first portion of the second signal line is at least located in the first display area; the first signal line and the second signal line are both in a wavy line shape; The first signal line includes a gate signal line and / or a data signal line; When the ratio of the first size of the first display area to the second size of the first display area is greater than 2, the first signal line is a gate signal line, the first size of the first display area is the size of the first display area in the extension direction of the gate signal line, and the second size of the first display area is the size of the first display area in the extension direction of the data signal line; When the ratio of the first size of the first display area to the second size of the first display area is less than 0.5, the first signal line is a data signal line, the first size of the first display area is the first size of the first display area in the extension direction of the gate signal line, and the second size of the first display area is the size of the first display area in the extension direction of the data signal line; When the ratio of the first size of the first display area to the second size of the first display area is between 0.5 and 2, the first signal line includes a gate signal line and a data signal line, the first size of the first display area is the size of the first display area in the extension direction of the gate signal line, and the second size of the first display area is the size of the first display area in the extension direction of the data signal line.

2. The display panel according to claim 1, characterized in that: The first signal line further includes at least one of the following signal lines: a reset signal line, a light emission control signal line, an initial voltage signal line, and a power supply signal line.

3. The display panel according to claim 1 or 2, characterized in that: The first signal line further includes a second portion located in the second display area, the second signal line further includes a second portion located in the second display area, and the second portion of the first signal line and the second portion of the second signal line are both metal signal lines.

4. The display panel according to claim 3, characterized in that: The display panel further comprises a first metal layer, a first insulating layer and a metal oxide layer which are sequentially located on the base substrate in a direction away from the base substrate; The first signal line is located in the first metal layer; At least one of the multiple second signal lines has a first portion located in the metal oxide layer within the first display area, and a second portion located in the first metal layer within the second display area, and the first portion and the second portion of the second signal line are connected through a first via hole penetrating the first insulating layer, and the first via hole is at the junction of the first display area and the second display area.

5. The display panel according to claim 4, characterized in that: The first metal layer includes a first gate metal layer and a first source-drain metal layer, and the first insulating layer includes a first passivation layer and an interlayer dielectric layer; Along a direction away from the base substrate, the first gate metal layer, the interlayer dielectric layer, the first source-drain metal layer and the first passivation layer are stacked in sequence.

6. The display panel according to claim 4, characterized in that: The display panel further comprises a second insulating layer and a second metal layer, and along a direction away from the base substrate, the second metal layer, the second insulating layer, the first metal layer, the first insulating layer and the metal oxide layer are stacked in sequence; Another part of the multiple second signal lines has a first part located in the metal oxide layer within the first display area, and a second part located in the second metal layer within the second display area, and the first part and the second part of the second signal line are connected through a second via hole that penetrates the first insulating layer and the second insulating layer, and the second via hole is at the junction of the first display area and the second display area.

7. The display panel according to claim 6, characterized in that: The second metal layer includes a second gate metal layer, and the second insulating layer includes a first gate insulating layer.

8. The display panel according to any one of claims 1 to 2 and claims 4 to 7, characterized in that: The display panel further includes a plurality of second pixel units, the plurality of second pixel units are located in the second display area, the plurality of first pixel units and the plurality of second pixel units are arranged in a plurality of rows of pixel units, and in an arrangement direction of a row of pixel units, the pixel units in two adjacent rows of pixel units are staggered with each other; The pixel units in two adjacent rows of pixel units are connected via a gate signal line.

9. The display panel according to claim 8, characterized in that: The gate signal line is in a wavy line shape, and the crests and troughs of the gate signal line are respectively connected to the pixel units in two adjacent rows of pixel units.

10. The display panel according to claim 8, characterized in that: The data signal line is in a wavy line shape, and the crest and trough of the data signal line are respectively connected to two adjacent pixel units in the same column of pixel units.

11. The display panel according to any one of claims 1 to 2 and claims 4 to 7, characterized in that: The metal signal line includes a molybdenum signal line or a titanium signal line.

12. The display panel according to any one of claims 1 to 2 and claims 4 to 7, characterized in that: The metal oxide signal line is a transparent metal oxide signal line.

13. The display panel according to claim 12, characterized in that: The metal oxide signal line is an indium tin oxide signal line.

14. A method for manufacturing a display panel, characterized in that: The production method comprises: Providing a base substrate, the base substrate having a display area and a peripheral area at least partially surrounding the display area, the display area comprising a first display area and a second display area at least located on one side of the first display area, and the light transmittance of the first display area is greater than the light transmittance of the second display area; A plurality of first pixel units and a plurality of signal lines are formed on the base substrate, wherein the plurality of first pixel units are located in the first display area; a plurality of signal lines are located at least in the first display area and are electrically connected to the plurality of first pixel units, wherein the plurality of signal lines include a plurality of first signal lines and a plurality of second signal lines, wherein a first portion of each of the plurality of first signal lines is a metal signal line, and a first portion of the first signal line is at least located in the first display area; a first portion of each of the plurality of second signal lines is a metal oxide signal line, and a first portion of the second signal line is at least located in the first display area; Wherein, the first signal line includes a gate signal line and / or a data signal line; When the ratio of the first size of the first display area to the second size of the first display area is greater than 2, the first signal line is a gate signal line, the first size of the first display area is the size of the first display area in the extension direction of the gate signal line, and the second size of the first display area is the size of the first display area in the extension direction of the data signal line; When the ratio of the first size of the first display area to the second size of the first display area is less than 0.5, the first signal line is a data signal line, the first size of the first display area is the first size of the first display area in the extension direction of the gate signal line, and the second size of the first display area is the size of the first display area in the extension direction of the data signal line; When the ratio of the first size of the first display area to the second size of the first display area is between 0.5 and 2, the first signal line includes a gate signal line and a data signal line, the first size of the first display area is the size of the first display area in the extension direction of the gate signal line, and the second size of the first display area is the size of the first display area in the extension direction of the data signal line.

15. A display device, characterized in that: The display device comprises a power supply component and a display panel according to any one of claims 1 to 13, wherein the power supply component is used to supply power to the display panel.

16. The display device according to claim 15, characterized in that: The display device further includes a light sensor, which is located at a side of the display panel away from the plurality of first pixel units, and an orthographic projection of the light sensor on the base substrate at least partially overlaps with the first display area.

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