A fault tolerance detection method, device, electronic device and readable storage medium

Abstract

The embodiments of the present application provide a fault tolerance detection method, apparatus, electronic device, and readable storage medium. The method includes: obtaining a bus degradation criterion according to the model information of a bus device; determining a fault tolerance detection scheme according to the bus degradation criterion; determining a target switch corresponding to each round of detection according to a status adjustment strategy; in each round of detection, disconnecting the target switch and determining the theoretical bus bandwidth and the actual bus bandwidth of the bus device; and when the detection stop condition is satisfied, determining the fault tolerance detection result of the bus device according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection. The embodiments of the present application perform fault tolerance detection on the bus device by controlling the bandwidth of the bus device with a control switch, accurately controlling the variable in each round of detection, that is, the theoretical bus bandwidth, improving the accuracy of the fault tolerance detection, and also reducing the wear of the bus device during the fault tolerance detection process.

Description

Technical Field

[0001] This application relates to the field of servers, and in particular, to a fault tolerance detection method, apparatus, electronic device, and readable storage medium. Background Art

[0002] With the continuous increase in the main frequency of current processors, the bandwidth of bus devices that support the Peripheral Component Interconnect (PCI) standard is getting higher and higher. Since the PCI bus belongs to a time-division multiplexing two-way response mode bus, it requires the mutual cooperation between the initiation / response signals. During the data transmission process, a fault may occur in a certain PCI bus device or a response signal cannot be generated, resulting in the paralysis of the entire PCI bus system. Therefore, during research and development, it is necessary to verify the fault tolerance of bus devices that support the Peripheral Component Interconnect Express (PCIE) standard. Specifically, it is necessary to verify the identification of each device when the PCIE bus device has an occasional fault or no response signal.

[0003] In the prior art, a method of using non-conductive tape to block the channel (lane) signals of the conductive contacts on the PCIE bus interface is used to achieve the fault tolerance of the PCIE bus.

[0004] This method has the problem of low accuracy rate due to inaccurate tape blocking during the operation process, and this method requires multiple pluggings and unplugging of the PCIE device, which will cause wear and tear on the conductive contacts of the PCIE device during the plugging and unplugging process. Summary of the Invention

[0005] Embodiments of this application provide a fault tolerance detection method, apparatus, electronic device, and readable storage medium, which can improve the accuracy rate of bus bandwidth fault tolerance detection and reduce the wear and tear on bus devices during the fault tolerance detection process.

[0006] In a first aspect, embodiments of this application provide a fault tolerance detection method, which is applied to a terminal device, and the method includes:

[0007] Obtain a bus degradation criterion according to the model information of the bus device;

[0008] Determine a fault tolerance detection scheme for the bus device according to the bus degradation criterion, where the fault tolerance detection scheme includes a state adjustment strategy for channels in the connection unit of the bus device and a detection stop condition in each round of detection; the connection unit includes at least two channels, and each channel is configured with a control switch; the control switch is used to control the conduction state of the channels in the connection unit;

[0009] Determine the target switch corresponding to each round of detection among the respective control switches corresponding to the connection unit according to the state adjustment strategy;

[0010] In each round of detection, disconnect the target switch and determine the theoretical bus bandwidth and the actual bus bandwidth of the bus device;

[0011] When the detection stop condition is satisfied, determine the fault tolerance detection result of the bus device according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection.

[0012] Optionally, the determining the fault tolerance detection scheme of the bus according to the bus degradation criterion includes:

[0013] Obtain the original bus bandwidth of the bus device;

[0014] According to the original bus bandwidth and the bus degradation criterion, determine the remaining bus bandwidth corresponding to the bus device at each conduction level;

[0015] Determine the target channels in the conduction state at each conduction level according to the remaining bus bandwidth;

[0016] Determine the state adjustment strategy of each channel in the connection unit in each round of detection according to the target channels.

[0017] Optionally, a basic input / output system is installed in the electronic device; the determining the theoretical bus bandwidth and the actual bus bandwidth of the bus device includes:

[0018] Determine the channels in the conduction state according to the target switch;

[0019] Determine the theoretical bus bandwidth of the connection unit according to the channels in the conduction state and the channel bandwidth;

[0020] Use the basic input / output system to query the current actual bus bandwidth of the connection unit.

[0021] Optionally, the determining the fault tolerance detection result of the bus according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection includes:

[0022] Determine the theoretical number of opened channels and the actual number of opened channels of the connection device in each round of detection according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection;

[0023] Compare the theoretical number of opened channels and the actual number of opened channels in each round of detection to determine the fault condition of the bus device in each round of detection;

[0024] Determine the fault tolerance detection result of the bus device according to the fault condition of the bus device in each round of detection.

[0025] Optionally, each channel includes four signal transmission channels, the control switch includes a DIP switch, and each DIP switch includes 4*n sub-switches, and one sub-switch controls one signal transmission channel, where n is a positive integer.

[0026] Optionally, when any one of the signal transmission channels in a channel is in a non-conductive state, then the channel is in a non-conductive state; the disconnecting the target switch includes:

[0027] Disconnect at least one sub-switch of the target switch.

[0028] Optionally, the detection stop condition includes that all channels in the connection unit are in a non-conductive state.

[0029] In a second aspect, an embodiment of the present application provides a fault tolerance detection device, which is applied to an electronic device. The electronic device is connected to a bus device through a connection unit. The device includes:

[0030] A bus degradation criterion acquisition module, configured to acquire a bus degradation criterion according to the model information of the bus device;

[0031] A fault tolerance detection scheme determination module, configured to determine a fault tolerance detection scheme for the bus device according to the bus degradation criterion. The fault tolerance detection scheme includes a state adjustment strategy and a detection stop condition for the channels in the connection unit of the bus device in each round of detection; the connection unit includes at least two channels, and each channel is configured with a control switch; the control switch is used to control the conduction state of the channels in the connection unit;

[0032] A target switch determination module, configured to determine a target switch corresponding to each round of detection among the respective control switches corresponding to the connection unit according to the state adjustment strategy;

[0033] A loop detection module, configured to disconnect the target switch in each round of detection and determine the theoretical bus bandwidth and the actual bus bandwidth of the bus device;

[0034] A fault tolerance detection result determination module, configured to determine the fault tolerance detection result of the bus device according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection when the detection stop condition is satisfied.

[0035] In a third aspect, an embodiment of the present application provides an electronic device, including: a processor and a memory, and the processor executes a computer program stored in the memory to implement the method described in the first aspect.

[0036] In a fourth aspect, an embodiment of the present application provides a readable storage medium storing computer instructions, which, when executed by a processor, implement the method described in the first aspect.

[0037] The embodiments of the present application have the following advantages:

[0038] In summary, an embodiment of the present application provides a fault tolerance detection method applied to an electronic device, which is connected to a bus device through a connection unit. After obtaining a bus degradation criterion according to the model information of the bus device, first determine a fault tolerance detection scheme for the bus device according to the bus degradation criterion, and then determine a target switch corresponding to each round of detection among the respective control switches corresponding to the connection unit according to the state adjustment strategy in the fault tolerance detection scheme. Then, perform a cyclic detection of the bus device in each round. In each round of detection, disconnect the target switch, and determine the theoretical bus bandwidth and the actual bus bandwidth of the bus device. When the detection stop condition is met, determine the fault tolerance detection result of the bus device according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection. Combining the bus degradation criterion, use the control switch to control the bandwidth of the bus device to perform fault tolerance detection on the bus device, accurately control the variable in each round of detection, that is, the theoretical bus bandwidth, improve the accuracy of the fault tolerance detection of the bus device, and also reduce the wear of the bus device during the fault tolerance detection process. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments of the present application. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0040] Figure 1 Shows a flowchart of an embodiment of a fault tolerance detection method of the present application;

[0041] Figure 2 Shows a schematic diagram of a channel switch on a connection unit of a bus device according to an embodiment of the present application;

[0042] Figure 3 Shows a structural block diagram of an embodiment of a fault tolerance detection device of the present application;

[0043] Figure 4 Shows a schematic structural diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application. And it should be noted that the processes of obtaining various data in the embodiments of the present application are all carried out on the premise of complying with the corresponding data protection regulations and policies of the country where the location is located and obtaining the authorization given by the owner of the corresponding device.

[0045] With the continuous increase of the current processor main frequency, the bandwidth of the supported bus devices, such as peripheral component interconnect standard devices like PCI (Peripheral Component Interconnect) devices, is getting higher and higher. Since the PCI bus belongs to a time-division multiplexing two-way response mode bus, it requires the mutual cooperation between the initiate / response signals. During the data transmission process, a device failure or the inability to generate a response signal may occur, resulting in the paralysis of the entire peripheral component bus system. Therefore, during research and development, it is necessary to verify the fault tolerance of bus devices such as PCIE (peripheral component interconnect express) devices, and verify the identification of each device in the case of occasional failures of bus devices or no response signals from devices.

[0046] In the prior art, a method of using non-conductive tape to block the channel (lane) signals of the conductive contacts on the PCIE interface is adopted to achieve the fault tolerance detection of PCIE bus devices. This method has the problem of low accuracy rate due to inaccurate tape blocking during the operation process, and this method requires multiple pluggings and unplugging of PCIE devices, which will cause wear to the conductive contacts of PCIE devices during the plugging and unplugging process.

[0047] Based on the above problems and related content, referring to Figure 1 , a flowchart of an embodiment of a fault tolerance detection method of the present application is shown. The method is applied to an electronic device, and the electronic device is connected to a bus device through a connection unit. The method includes:

[0048] Step 101, obtain a bus degradation criterion according to the model information of the bus device.

[0049] A bus device is also called a bus (Bus), which is a common communication trunk for transmitting information between various functional components of a computer and needs to follow a communication protocol. For example, a PCIE bus refers to a bus that follows the high-speed serial computer expansion bus standard. The bus degradation criterion refers to the rule for reducing the bus bandwidth. For example, in a PCIE bus, a sixteen-channel PCIE can be reduced to an eight-channel, but cannot be reduced to fifteen, nine, etc. channels.

[0050] Different bus devices usually have different bus degradation criteria, and the corresponding bus degradation criteria can be queried according to device information such as the model of the bus device.

[0051] The fault tolerance refers to the identification situation of each device in the case of occasional faults or no response signals of the bus device. In the embodiments of the present application, the transmission situation of the bus device signal can be controlled by a switch to verify the fault tolerance of the bus device. Therefore, it is necessary to clarify the bus degradation criteria of different bus devices, which is beneficial to controlling the transmission signals during fault tolerance monitoring.

[0052] Step 102: Determine the fault tolerance detection scheme of the bus according to the bus degradation criteria. The fault tolerance detection scheme includes a channel state adjustment strategy and a detection stop condition for the channels in the connection unit of the bus device in each round of detection; the connection unit includes at least two channels, and a control switch is configured on each channel; the control switch is used to control the conduction state of the channels in the connection unit.

[0053] In the embodiments of the present application, the fault tolerance detection of the bus can be performed by an electronic device. The electronic device includes, but is not limited to, a computer, a mobile phone, a server, etc. that can be used for information interaction. The electronic device establishes a connection with the bus device through a connection unit. Corresponding to the channel interface of the bus device, the connection unit includes at least two channels, and the channels on the connection unit are connected to the channel interface of the bus device. Therefore, the electronic device establishes a connection with the bus device channel interface through the connection unit. At the same time, a control switch is configured on each channel, and the control switch is used to control the conduction state of the channels in the connection unit, so as to control the bandwidth of the bus device.

[0054] As an example, the PCIe x16 bus device is a sixteen-channel bus device. By setting control switches on the connection line matching the PCIe x16 bus device, the conduction state of each channel is controlled, so as to control the bandwidth of the transmission signals on the bus device, and then detect the actual signal transmission situation of the bus device under different theoretical signal transmission bandwidths.

[0055] Therefore, the fault tolerance detection consists of multiple rounds of detection, including the state adjustment strategy and detection stop condition for the channels in the connection unit of the bus device in each round of detection. Among them, the state adjustment strategy is a strategy for adjusting the conduction state of the channels in the connection unit according to the bus degradation criterion. Further, essentially, it follows the bus degradation criterion to adjust the conduction state of the channels, and then adjusts the available bandwidth to obtain the theoretically available bandwidth of the bus device, that is, the theoretical bus bandwidth. Each kind of theoretical bus bandwidth corresponds to at least one conduction state of the channels in the connection unit, and one conduction state of the channels corresponds to one control state of the switch.

[0056] As an example, referring to the degradation criterion of the PCIE bus device shown in Table 1 below, it is explained how to confirm the fault tolerance detection scheme, where m represents the available bandwidth of each channel. When performing fault tolerance detection on a PCIEx16 bus device, in the embodiment of the present application, according to the PCIEx16 bus

[0057] When performing fault tolerance detection on the line device, it is necessary to detect the signal transmission failure of the bus under each kind of theoretical bus bandwidth. Therefore, the fault tolerance detection scheme of the PCIEx16 bus includes the adjustment strategies for the conduction states of the channels corresponding to different theoretical bus bandwidths such as 16m, 8m, 4m, 2m, and 1m, and each kind of theoretical bus state includes at least one switch state of the channels. For example, when detecting an eight-channel PCIEx16 device, the PCIEx16 device can be degraded to an eight-channel device by controlling the switch to close channel 7 or channel 8, such as a DIP switch, a power switch, etc. Each round of detection only detects the bus device with one conduction state of the channels. Then, the PCIEx16 bus device under eight channels includes two rounds of detection.

[0058] Table 1

[0059]

[0060] Therefore, the fault tolerance detection scheme includes the state adjustment strategy for the channels of the bus device in different conduction states, and each conduction state of the channels of each bus device corresponds to one round of detection; the fault tolerance detection scheme also includes the detection stop condition. By way of example, for a PCIEx16 bus device, if the detection is performed step by step according to the conduction level of the channels, then when the PCIEx16 bus device in the single-channel state is detected, all channels are closed and the detection is stopped.

[0061] Step 103: Determine the target switch corresponding to each round of detection in the respective control switches corresponding to the connection unit according to the state adjustment strategy.

[0062] After determining the fault tolerance detection scheme for the bus, in the embodiments of the present application, according to the channel status adjustment strategy for the connection unit of the bus device in each round of detection, that is, the channels that need to be adjusted to the on state and the corresponding control switches in each round of detection, the target switches that need to be disconnected in each round of detection can be determined to adjust the channel on state of the bus device.

[0063] Step 104: In each round of detection, disconnect the target switch and determine the theoretical bus bandwidth and the actual bus bandwidth of the bus device.

[0064] After determining the target switches that need to be disconnected in each round of detection, the fault tolerance detection of the bus can be started.

[0065] In each round of detection, after disconnecting the target switch, according to the channels in the on state in each round, calculate the theoretically maximum available bandwidth of the bus device in the current channel on state, that is, the theoretical bus bandwidth, and further use the electronic device connected to the bus device to query the actual available bandwidth of the bus device. In each round of detection, a set of comparison data of the theoretical bus bandwidth and the actual bus bandwidth is obtained.

[0066] As an example, referring to Table 1, when detecting a PCIe x16 bus device with channels 0-7 in the on state, disconnect the switch controlling channel 8, so that only channels 0-7 in the PCIe x16 bus device are in the on state. According to the maximum available bandwidth of each channel in channels 0-7, calculate the theoretical bus bandwidth of the current PCIe x16 bus device, and then use the electronic device connected to the PCIe x16 bus device to query the actual available bandwidth of the current PCIe x16 bus device, and record the theoretical bus bandwidth and the actual available bandwidth in this round of detection as a reference for subsequent fault tolerance evaluation of the bus device.

[0067] Step 105: When the detection stop condition is met, determine the fault tolerance detection result of the bus device according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection.

[0068] When the detection stop condition is met, according to the theoretical bus bandwidth and the actual bus bandwidth data obtained in each round of detection, determine the fault situation of the bus device in each round of detection, and comprehensively consider the fault situations of each round of detection to obtain the final fault tolerance detection result of the bus device.

[0069] Optionally, the determining the fault tolerance detection scheme of the bus device according to the bus degradation criterion in step 102 includes:

[0070] Step S100: Obtain the original bus bandwidth of the bus device;

[0071] Step S101: Determine the remaining bus bandwidth corresponding to the bus device at each conduction level according to the original bus bandwidth and the bus degradation criterion.

[0072] Step S102: Determine the target channels in the conduction state at each conduction level according to the remaining bus bandwidth.

[0073] Step S103: Determine the state adjustment strategy of each channel in the connection unit in each round of detection according to the target channels.

[0074] Before determining the fault tolerance detection scheme of the bus, it is necessary to clarify the original bandwidth of the bus device first, so as to make targeted strategy arrangements according to the bus degradation criterion. Different bus devices have different original bus bandwidths. Taking Table 1 as an example, PCIe x16 has a total original bus bandwidth of 16m with 16 channels accumulated, while PCIe x8 has a total original bus bandwidth of 8m with 8 channels accumulated. The specific original bus bandwidth can be obtained by the electronic device reading the self-attributes of the bus device or querying according to the signals of the bus device.

[0075] Different original bus bandwidths mean different channel conduction levels. For example, the PCIe x16 bus device has 5 channel conduction levels, such as 16 channels, 8 channels, 4 channels, 2 channels, and single channel. The maximum available bandwidth, that is, the remaining bus bandwidth, corresponding to different conduction levels is also different. Therefore, the different conduction levels of different bus devices can be calculated according to the bus degradation criterion. For example, in the PCIe x16 bus device, the maximum available bandwidth of each channel is the same. Therefore, the remaining bus bandwidth corresponding to different channel conduction levels is determined by the number of channels in the conduction state.

[0076] After that, further determine the target channels in the conduction state at each conduction level according to the bus degradation criterion. As an example, as shown in Table 1, after the PCIe x16 bus device degrades to 8 channels, there are two conduction situations of the target channels, that is, channels 0 - 7 are in the conduction state or channels 8 - 15 are in the conduction state.

[0077] Each round of detection corresponds to a channel conduction state of the bus device. One channel conduction level corresponds to at least one channel conduction state. Therefore, after determining the target channels in the conduction state, it is possible to determine the channels that need to be in the conduction state in each round of detection. Other channels that need to be in the non-conduction state need to be controlled by the control switches connected to the channels, so as to obtain the state adjustment strategy of each channel in the connection unit in each round of detection.

[0078] Determine the status adjustment strategy of each channel in the connection unit in each round of detection according to each conduction level of the bus device, realizing the all-round fault-tolerant detection of the signal transmission of the bus device, and improving the accuracy and scientificity of the fault-tolerant detection result.

[0079] Optionally, a basic input / output system is installed in the electronic device;

[0080] The determining of the theoretical bus bandwidth and the actual bus bandwidth of the bus device in step 104 includes:

[0081] Step S200: Determine the channels in the on state according to the target switch;

[0082] Step S201: Determine the theoretical bus bandwidth of the bus device according to the channels in the on state and the channel bandwidth;

[0083] Step S202: Use the basic input / output system to query the current actual bus bandwidth of the connection unit.

[0084] Disconnecting the target switch is used to switch the conduction state of the channel controlled by the target switch to the non-conduction state. Then, the maximum available bandwidth of the current bus device, that is, the theoretical bus bandwidth, can be determined according to the sum of the maximum available bandwidths of other channels in the on state.

[0085] The actual bus bandwidth refers to the available bandwidth of the bus device during the actual data transmission process. Specifically, since the electronic device is connected to the bus device through the connection unit, when the electronic device and the bus device perform data interaction, the connectivity of the network, that is, the actual bus bandwidth, can be queried in the preinstallation environment (PE) of the basic input / output system (BIOS) installed in the electronic device, and the actual bus bandwidth in each round of detection can be queried in real time and quickly.

[0086] Optionally, the determining of the fault-tolerant detection result of the bus device according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection in step 105 includes:

[0087] Step S300: Determine the theoretical number of opened channels and the actual number of opened channels of the connection device in each round of detection according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection;

[0088] Step S301: Compare the theoretical number of opened channels and the actual number of opened channels in each round of detection to determine the fault situation of the bus device in each round of detection;

[0089] Step S302: Determine the fault tolerance detection result of the bus device according to the fault conditions of the bus device in each round of detection.

[0090] Considering the maximum available bandwidth of each channel of the bus device, the theoretical number of enabled channels can be determined according to the theoretical bus bandwidth, and the actual number of enabled channels can be determined according to the actual bus bandwidth. If the theoretical number of enabled channels and the actual number of enabled channels are different in a certain round of detection, it means that there is a fault in a channel in this round of detection. If they are the same, it means that the signal transmission of the bus device channels is normal. Record the fault conditions of the channels in each round of detection and conduct a comprehensive analysis to obtain the fault tolerance detection result of the bus device.

[0091] Optionally, each channel includes four signal transmission channels, the control switch includes a DIP switch, and each DIP switch includes 4*n sub-switches, where one sub-switch controls one signal transmission channel and n is a positive integer.

[0092] The DIP switch is used to operate the control address switch and adopts the binary coding principle of 0 / 1.

[0093] Refer to Figure 2 The schematic diagram of the channel switch embodiment on a bus device connection unit of the present application shown in the figure is applied to a PCIe x16 bus device.

[0094] Eight DIP switches SW1 - SW8 are set on this bus device connection unit. Each DIP switch controls two channels. There are 8 sub-switches on each DIP switch, and each sub-switch controls one signal transmission channel. Each channel is composed of four signal transmission channels. The target switch can be disconnected in each round of detection and the conduction state of the channels in the bus device connection unit can be adjusted in the following manner:

[0095] 1. Channel conduction level x1 of the bus device: Switch at least one of the sub-switches corresponding to the transmission lines 9, 11, 13, and 15 on SW1 to the off state, that is, disconnect. The DIP switches SW2 - SW8 remain in the non-DIP state, or switch at least one of the sub-switches corresponding to the transmission lines 1, 3, 5, and 7 on SW8 to the off state, and the DIP switches SW1 - SW7 remain in the non-DIP state.

[0096] 2. Channel conduction level x2 of the bus device: Switch at least one of the sub-switches corresponding to the transmission lines 1, 3, 5, and 7 on SW2 to the off state, and the DIP switches SW1, SW3 - SW8 remain in the non-DIP state, or switch at least one of the sub-switches corresponding to the transmission lines 9, 11, 13, and 15 on SW7 to the off state, and the DIP switches SW8, SW1 - SW6 remain in the non-DIP state.

[0097] 3. Channel conduction level x4 of the bus device: Set the sub-switches corresponding to at least one transmission line among the 1st, 3rd, 5th, and 7th on SW3 to the off state, and keep the corresponding DIP switches on SW1 - SW2 and SW4 - SW8 unswitched; or set the sub-switches corresponding to at least one transmission line among the 9th, 11th, 13th, and 15th on SW6 to the off state, and keep the corresponding DIP switches on SW7 - SW8 and SW1 - SW5 unswitched.

[0098] 4. Channel conduction level x8 of the bus device: Set the sub-switches corresponding to at least one transmission line among the 1st, 3rd, 5th, and 7th on SW5 to the off state, and keep the corresponding DIP switches on SW1 - SW4 and SW6 - SW8 unswitched; or set the sub-switches corresponding to at least one transmission line among the 9th, 11th, 13th, and 15th on SW4 to the off state, and keep the corresponding DIP switches on SW1 - SW3 and SW5 - SW8 unswitched.

[0099] 5. Bus channel conduction level x16: Keep the DIP switches on SW1 - SW8 and the corresponding DIP switches unswitched.

[0100] Optionally, referring to Figure 2 the channel switch schematic diagram on the bus device connection unit shown, when any one signal transmission channel in a channel is in a non-conductive state, then the said channel is in a non-conductive state; the disconnecting of the target switch includes:

[0101] Step S400: Disconnect at least one sub-switch of the target switch.

[0102] The conduction state of a channel is controlled by four sub-switches. Disconnecting at least one of the four sub-switches can switch the state of the said channel to non-conductive. And when performing step-by-step detection on the bus device according to the conduction level, the DIP switches can be disconnected one by one according to the bus degradation criterion until all channels of the bus device are closed.

[0103] Optionally, according to the fault tolerance detection method described in any of the foregoing, the detection stop condition includes that all channels in the connection unit are in a non-conductive state.

[0104] In summary, the embodiment of the present application provides a fault tolerance detection method, which is applied to an electronic device. The electronic device is connected to a bus device through a connection unit. After obtaining the bus degradation criterion according to the model information of the bus device, first determine the fault tolerance detection scheme of the bus device according to the bus degradation criterion, and then determine the target switch corresponding to each round of detection among the control switches corresponding to the connection unit according to the state adjustment strategy in the fault tolerance detection scheme. Then, perform cyclic detection on the bus device in each round. In each round of detection, disconnect the target switch, and determine the theoretical bus bandwidth and the actual bus bandwidth of the bus device. When the detection stop condition is met, determine the fault tolerance detection result of the bus device according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection. By combining the bus degradation criterion and using the control switch to control the bandwidth of the bus device for fault tolerance detection, accurately control the variable in each round of detection, that is, the theoretical bus bandwidth, improve the accuracy of the bus bandwidth fault tolerance detection, and also reduce the wear of the bus device during the fault tolerance detection process.

[0105] Referring to Figure 3 , a structural block diagram of an embodiment of a fault tolerance detection device according to the present application is shown. The device is applied to an electronic device. The electronic device is connected to a bus device through a connection unit. The device 200 may include:

[0106] A bus degradation criterion acquisition module 201, configured to obtain a bus degradation criterion according to the model information of the bus device;

[0107] A fault tolerance detection scheme determination module 202, configured to determine a fault tolerance detection scheme of the bus device according to the bus degradation criterion. The fault tolerance detection scheme includes a state adjustment strategy and a detection stop condition for the channels in the connection unit of the bus device in each round of detection; the connection unit includes at least two channels, and each channel is configured with a control switch; the control switch is used to control the conduction state of the channels in the connection unit;

[0108] A target switch determination module 203, configured to determine the target switch corresponding to each round of detection among the control switches corresponding to the connection unit according to the state adjustment strategy;

[0109] A cyclic detection module 204, configured to disconnect the target switch in each round of detection, and determine the theoretical bus bandwidth and the actual bus bandwidth of the bus device;

[0110] A fault tolerance detection result determination module 205, configured to determine the fault tolerance detection result of the bus device according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection when the detection stop condition is met.

[0111] Optionally, the fault tolerance detection scheme determination module may include:

[0112] An original bus bandwidth acquisition sub-module, configured to acquire the original bus bandwidth of the bus device;

[0113] A remaining bus bandwidth determination sub-module, configured to determine the corresponding remaining bus bandwidth of the bus device at each conduction level according to the original bus bandwidth and the bus degradation criterion;

[0114] A target channel determination sub-module, configured to determine the target channels in the conduction state at each conduction level according to the remaining bus bandwidth;

[0115] A state adjustment strategy determination sub-module, configured to determine the state adjustment strategy of each channel in the connection unit in each round of detection according to the target channels.

[0116] Optionally, a basic input / output system is installed in the electronic device;

[0117] The loop detection module may include:

[0118] A channel determination sub-module, configured to determine the channels in the conduction state according to the target switch;

[0119] A theoretical bus bandwidth determination sub-module, configured to determine the theoretical bus bandwidth of the connection unit according to the channels in the conduction state and the channel bandwidth;

[0120] An actual bus bandwidth query sub-module, configured to query the current actual bus bandwidth of the connection unit by using the basic input / output system.

[0121] Optionally, the fault tolerance detection result determination module may include:

[0122] A channel number determination sub-module, configured to determine the theoretical number of opened channels and the actual number of opened channels of the connection device in each round of detection according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection;

[0123] A fault determination sub-module, configured to compare the theoretical number of opened channels and the actual number of opened channels in each round of detection, and determine the fault condition of the bus device in each round of detection;

[0124] A fault tolerance detection result determination sub-module, configured to determine the fault tolerance detection result of the bus device according to the fault condition of the bus device in each round of detection.

[0125] Optionally, each channel includes four signal transmission channels, the control switch includes a DIP switch, each DIP switch includes 4*n sub-switches, and one sub-switch controls one signal transmission channel, where n is a positive integer.

[0126] Optionally, when any one of the signal transmission channels in a channel is in a non-conductive state, then the channel is in a non-conductive state; the loop detection module may include:

[0127] A switch control sub-module for disconnecting the target switch;

[0128] The switch control sub-module may include:

[0129] A sub-switch control sub-module for disconnecting at least one sub-switch of the target switch

[0130] Optionally, the detection stop condition includes that all channels in the connection unit are in a non-conductive state.

[0131] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For related parts, refer to the partial description of the method embodiment.

[0132] Figure 4 It is a structural block diagram of an electronic device 600 for fault tolerance detection shown in an embodiment of the present invention. For example, the electronic device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0133] Referring to Figure 4 , the electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power supply component 606, a multimedia component 608, an audio component 610, an input / output (I / O) interface 612, a sensor component 614, and a communication component 616.

[0134] The processing component 602 generally controls the overall operation of the electronic device 600, such as operations associated with display, telephone call, data communication, camera operation, and recording operation. The processing element 602 may include one or more processors 620 to execute instructions to complete all or part of the steps of the above-mentioned fault tolerance detection method. In addition, the processing component 602 may include one or more modules to facilitate the interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.

[0135] The memory 604 is configured to store various types of data to support the operation of the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phone book data, messages, pictures, videos, and the like. The memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0136] The power supply component 606 provides power to various components of the electronic device 600. The power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 600.

[0137] The multimedia component 608 includes a screen that provides an output interface between the electronic device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can not only sense the boundaries of the touch or swipe actions, but also detect the duration and pressure associated with the touch or swipe operations. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the electronic device 600 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.

[0138] The audio component 610 is configured to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 600 is in an operating mode, such as a call mode, a recording mode, and a voice message processing mode. The received audio signals can be further stored in the memory 604 or transmitted via the communication component 616. In some embodiments, the audio component 610 further includes a speaker for outputting audio signals.

[0139] The I / O interface 612 provides an interface between the processing component 602 and a peripheral interface module, which can be a keyboard, a click wheel, buttons, etc. These buttons can include, but are not limited to: a home button, a volume button, a start button, and a lock button.

[0140] The sensor assembly 614 includes one or more sensors for providing an assessment of the status of various aspects of the electronic device 600. For example, the sensor assembly 614 can detect the on / off state of the electronic device 600, the relative positioning of components, such as the display and keypad of the device 600. The sensor assembly 614 can also detect a change in the position of the electronic device 600 or a component of the electronic device 600, the presence or absence of user contact with the electronic device 600, the orientation or acceleration / deceleration of the electronic device 600, and a change in the temperature of the electronic device 600. The sensor assembly 814 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 614 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 can also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0141] The communication component 616 is configured to facilitate communication between the electronic device 600 and other devices in a wired or wireless manner. The electronic device 600 can access a wireless network based on communication standards, such as WiFi, 2G, or 3G, or a combination thereof. In an exemplary embodiment, the communication component 616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 616 further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0142] In an exemplary embodiment, the electronic device 600 can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above-described fault tolerance detection method.

[0143] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as the memory 604 including instructions that can be executed by the processor 620 of the electronic device 600 to complete the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0144] A non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to execute Figure 1 the fault tolerance detection method shown.

[0145] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.

[0146] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0147] The above has introduced in detail a fault tolerance detection method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A fault tolerance detection method, characterized in that, Applied to an electronic device, the electronic device is connected to a bus device through a connection unit, and the method includes: Obtaining a bus degradation criterion according to the model information of the bus device; Determining a fault tolerance detection scheme for the bus device according to the bus degradation criterion, where the fault tolerance detection scheme includes a state adjustment strategy for channels in the connection unit of the bus device and a detection stop condition in each round of detection; the connection unit includes at least two channels, and each channel is configured with a control switch; the control switch is used to control the conduction state of the channels in the connection unit; Determining a target switch corresponding to each round of detection among the respective control switches corresponding to the connection unit according to the state adjustment strategy; the state adjustment strategy is a strategy for adjusting the conduction state of the channels in the connection unit according to the bus degradation criterion; In each round of detection, disconnect the target switch, and determine the theoretical bus bandwidth and the actual bus bandwidth of the bus device; When the detection stop condition is satisfied, determine the fault tolerance detection result of the bus device according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection; the detection stop condition includes that all channels in the connection unit are in a non-conducted state.

2. The method according to claim 1, characterized in that The determining the fault tolerance detection scheme for the bus device according to the bus degradation criterion includes: Obtaining the original bus bandwidth of the bus device; Determining the remaining bus bandwidth corresponding to the bus device at each conduction level according to the original bus bandwidth and the bus degradation criterion; Determining the target channels in a conducted state at each conduction level according to the remaining bus bandwidth; Determining the state adjustment strategy for each channel in the connection unit in each round of detection according to the target channels.

3. The method according to claim 1, wherein The electronic device is equipped with a basic input / output system; The determining the theoretical bus bandwidth and the actual bus bandwidth of the bus device includes: Determining the channels in a conducted state according to the target switch; Determining the theoretical bus bandwidth of the connection unit according to the channels in a conducted state and the channel bandwidth; Querying the current actual bus bandwidth of the connection unit by using the basic input / output system.

4. The method according to claim 1, wherein The determining the fault tolerance detection result of the bus device according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection includes: Determining the theoretical number of opened channels and the actual number of opened channels of the connection unit in each round of detection according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection; Comparing the theoretical number of opened channels and the actual number of opened channels in each round of detection to determine the fault condition of the bus device in each round of detection; Determining the fault tolerance detection result of the bus device according to the fault condition of the bus device in each round of detection.

5. The method according to claim 1, characterized in that, Each channel includes four signal transmission channels, the control switch includes a DIP switch, and each DIP switch includes 4*n sub-switches, and one sub-switch controls one signal transmission channel, where n is a positive integer.

6. The method according to claim 5, wherein When any one of the signal transmission channels in a channel is in a non-conducted state, then the channel is in a non-conducted state; Disconnecting the target switch includes: Disconnecting at least one sub-switch of the target switch.

7. A fault-tolerant detection device, characterized in that, Applied to an electronic device, the electronic device is connected to a bus device through a connection unit, and the apparatus includes: A bus degradation criterion acquisition module, configured to acquire a bus degradation criterion according to the model information of the bus device; A fault tolerance detection scheme determination module, configured to determine a fault tolerance detection scheme for the bus device according to the bus degradation criterion, where the fault tolerance detection scheme includes a status adjustment strategy for channels in the connection unit of the bus device and a detection stop condition in each round of detection; the connection unit includes at least two channels, and each channel is configured with a control switch; the control switch is configured to control the conduction state of the channels in the connection unit; A target switch determination module, configured to determine a target switch corresponding to each round of detection among the respective control switches corresponding to the connection unit according to the status adjustment strategy; the status adjustment strategy is a strategy for adjusting the conduction state of the channels in the connection unit according to the bus degradation criterion; A loop detection module, configured to disconnect the target switch in each round of detection and determine the theoretical bus bandwidth and the actual bus bandwidth of the bus device; A fault tolerance detection result determination module, configured to determine a fault tolerance detection result of the bus device according to the theoretical bus bandwidth and the actual bus bandwidth corresponding to each round of detection when the detection stop condition is satisfied; the detection stop condition includes that all channels in the connection unit are in a non-conducted state.

8. An electronic device, characterized in that, including: A processor and a memory, where the processor executes a computer program stored in the memory to implement the method according to any one of claims 1 to 6.

9. A readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the apparatus, the apparatus is enabled to execute the method according to any one of method claims 1 to 6.

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