Display panel, integrated chip and display device

Abstract

The present application discloses a display panel, an integrated chip and a display device. The display panel includes a first display area and a second display area; a first driving circuit includes a multi-stage first shift register for receiving a first control signal and providing a first driving signal for a pixel circuit in the first display area; a second driving circuit includes a multi-stage second shift register for receiving a second control signal and providing a second driving signal for a pixel circuit in the second display area; the pulse change frequency of the first control signal and the pulse change frequency of the second control signal are different. According to the embodiment of the present application, the driving circuit is designed by region, and different display requirements of different display areas in the display panel can be flexibly realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, an integrated chip and a display device. Background Art

[0002] With the continuous update of display panel technology, the display size of the display panel is increased, and different display areas can be designed to present different display contents at the same time. For example, the display panel can work in split screen, with the upper display area of ​​the display panel displaying dynamic scenes and the lower display area displaying static scenes.

[0003] Different display areas of a display panel may require different display functions or display effects. How to design a drive circuit differently according to the display functions or display effects of different display areas in the display panel is a hot topic of research in this field at the current stage. Summary of the invention

[0004] The embodiments of the present application provide a display panel, an integrated chip and a display device, which perform a regional design on a driving circuit and can flexibly meet different display requirements of different display areas in the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising a first display area and a second display area; a first driving circuit, comprising a multi-stage first shift register, for receiving a first control signal and providing a first driving signal for a pixel circuit in the first display area; a second driving circuit, comprising a multi-stage second shift register, for receiving a second control signal and providing a second driving signal for a pixel circuit in the second display area; a pulse change frequency of the first control signal and a pulse change frequency of the second control signal are different.

[0006] Based on the same inventive concept, in the second aspect, an embodiment of the present application provides an integrated chip for providing a signal for the display panel described in the embodiment of the first aspect, the display panel comprising: a first display area and a second display area; a first driving circuit comprising a multi-stage first shift register for receiving a first control signal and providing a first driving signal for a pixel circuit in the first display area; a second driving circuit comprising a multi-stage second shift register for receiving a second control signal and providing a second driving signal for a pixel circuit in the second display area; a pulse change frequency of the first control signal and a pulse change frequency of the second control signal are different; the integrated chip provides at least one of the first control signal and the second control signal.

[0007] Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a display device, characterized in that it includes a display panel as described in the embodiment of the first aspect.

[0008] The above-mentioned display panel, integrated chip and display device provided in the present application have designed driving circuits in different areas according to different display areas. Specifically, the pixel circuit of the first display area is driven by the first driving circuit, and the pixel circuit of the second display area is driven by the second driving circuit. The first driving circuit receives a first control signal, and the second driving circuit receives a second driving signal. Since the pulse change frequency of the first control signal and the pulse change frequency of the second control signal are different, the first driving signal generated by the first driving circuit and the second driving signal generated by the second driving circuit will also be different. Therefore, different display requirements of the first display area and the second display area can be flexibly realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0010] Figure 1 A schematic diagram showing the structure of a display panel provided in an embodiment of the present application is shown;

[0011] Figure 2 A schematic diagram showing a structure of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0012] Figure 3 Show Figure 2 A timing diagram of

[0013] Figure 4 A schematic diagram showing a control signal in a display panel provided in an embodiment of the present application;

[0014] Figure 5 A schematic diagram showing a structure of a first shift register in a display panel provided in an embodiment of the present application is shown;

[0015] Figure 6 Show Figure 5 A timing diagram of

[0016] Figure 7 A schematic diagram showing a structure of a second shift register in a display panel provided in an embodiment of the present application is shown;

[0017] Figure 8 Another structural schematic diagram of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0018] Fig. 9 Show Figure 8 A timing diagram of

[0019] Fig.10Another structural schematic diagram of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0020] Fig.11 Show Fig.10 A timing diagram of

[0021] Fig.12 Another structural schematic diagram of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0022] Fig.13 Show Fig.12 A timing diagram of

[0023] Fig.14 Another structural schematic diagram of a pixel circuit in a display panel provided in an embodiment of the present application is shown;

[0024] Fig.15 Show Fig.14 A timing diagram of

[0025] Fig.16 Another schematic diagram showing a control signal in a display panel provided by an embodiment of the present application;

[0026] Fig.17 Another schematic diagram showing a control signal in a display panel provided by an embodiment of the present application;

[0027] Fig.18 Another schematic diagram showing a control signal in a display panel provided by an embodiment of the present application;

[0028] Fig.19 Another schematic diagram showing a control signal in a display panel provided by an embodiment of the present application;

[0029] Fig. 20 Another schematic diagram showing a control signal in a display panel provided by an embodiment of the present application;

[0030] Fig.21 Another schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown;

[0031] Fig. 22 Another schematic diagram showing a control signal in a display panel provided by an embodiment of the present application;

[0032] Fig.23 A schematic diagram showing a structure of a third shift register in a display panel provided in an embodiment of the present application is shown;

[0033] Fig.24 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0034] Fig.25Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0035] Fig.26 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0036] Fig. 27 A schematic diagram showing a film layer structure of a display panel provided in an embodiment of the present application is shown;

[0037] Fig.28 Another schematic diagram of a film layer structure of a display panel provided in an embodiment of the present application is shown;

[0038] Fig.29 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0039] Fig.30 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0040] Fig.31 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0041] Fig.32 A schematic diagram of the structure of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0042] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0043] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0044] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0045] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0046] In the embodiments of the present application, the term “connection” may refer to a direct electrical connection between two components, or may refer to a connection between two components via one or more other components.

[0047] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0048] As introduced in the background technology, different display areas of a display panel may require different display functions or display effects. How to differentiate the design of the driving circuit according to the display functions or display effects of different display areas in the display panel is a hot topic of research in this field at the current stage.

[0049] Based on this, the embodiments of the present application provide a display panel, an integrated chip and a display device. The embodiments of the display panel, the integrated chip and the display device will be described below in conjunction with the accompanying drawings.

[0050] The display panel provided in the embodiment of the present application may be an organic light emitting diode (OLED) display panel, or a micro light emitting diode display panel, or other types of display panels.

[0051] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown. Figure 1 As shown, the display panel 100 provided in the embodiment of the present application may include a first display area 101 and a second display area 102. Pixel circuits Pixel are distributed in the first display area 101 and the second display area 102. The pixel circuits Pixel can be used to drive the light emitting element ( Figure 1 In order to better distinguish the area to which the pixel circuit Pixel belongs, Figure 1 Different filling colors are used to represent pixel circuits Pixel in the first display area 101 and the second display area 102. The pixel circuit Pixel may include components such as transistors and capacitors, and the transistor may be turned on or off under the control of a driving signal.

[0052] The display panel 100 may be provided with a first driving circuit 10 and a second driving circuit 20 corresponding to the first display area 101 and the second display area 102 , respectively.

[0053] Specifically, the first driving circuit 10 may include a multi-stage first shift register VSR1. The first driving circuit 10 may be used to receive a first control signal and generate a first driving signal according to the first control signal. The first driving circuit 10 provides the first driving signal generated by it to the pixel circuit Pixel in the first display area 101, so that the transistor of the pixel circuit Pixel in the first display area 101 can be turned on or off under the control of the first driving signal.

[0054] The second driving circuit 20 may include a multi-stage second shift register VSR2. The second driving circuit 20 may be used to receive a second control signal and generate a second driving signal according to the second control signal. The second driving circuit 20 provides the second driving signal generated by it to the pixel circuit Pixel in the second display area 102, so that the transistor of the pixel circuit Pixel in the second display area 102 can be turned on or off under the control of the second driving signal.

[0055] For example, Figure 2As shown, the pixel circuit Pixel may include transistors M1 to M7 and a storage capacitor Cst. Among them, S1 and S2 represent scan signals, EMIT represents a light emitting control signal, Vdata represents a data signal, PVDD represents a first power signal terminal, PVEE represents a second power signal terminal, Vref1 represents a reset signal, Vref2 represents an initialization signal, and D represents a light emitting element. Figure 3 for Figure 2 A timing diagram of Figure 2 The operation process of the pixel circuit shown will be described below. Figure 2 The circuit structure of the pixel circuit shown is merely an example and is not intended to limit the present application.

[0056] As an example, the first driving circuit 10 and the second driving circuit 20 may be scanning driving circuits, so that the types of the first driving signal and the second driving signal may be scanning signals S1 and S2. The first driving circuit 10 provides scanning signals S1 and S2 to the pixel circuit Pixel of the first display area 101, and the second driving circuit 20 provides scanning signals S1 and S2 to the pixel circuit Pixel of the second display area 102.

[0057] As another example, the first driving circuit 10 and the second driving circuit 20 may be light-emitting driving circuits, so that the types of the first driving signal and the second driving signal may be a light-emitting control signal EMIT, the first driving circuit 10 provides the light-emitting control signal EMIT to the pixel circuit Pixel of the first display area 101, and the second driving circuit 20 provides the light-emitting control signal EMIT to the pixel circuit Pixel of the second display area 102.

[0058] In the embodiment of the present application, the pulse change frequency of the first control signal is different from the pulse change frequency of the second control signal.

[0059] It is understandable that both the first control signal and the second control signal are pulse signals. Figure 4 As shown, both the first control signal and the second control signal may include alternating high and low levels. For example, the period of the first control signal is T1, and the pulse change frequency of the first control signal can be understood as the number of times the first control signal completes periodic changes within a unit time (e.g., within 1 second), and the pulse change frequency of the first control signal can be equal to 1 / T1. Similarly, for example, the period of the second control signal is T2, and the pulse change frequency of the second control signal can be understood as the number of times the second control signal completes periodic changes within a unit time (e.g., within 1 second), and the pulse change frequency of the second control signal can be equal to 1 / T2.

[0060] For example, the pulse change frequency of the first control signal may be 120 Hz, and the pulse change frequency of the second control signal may be 60 Hz. For another example, the pulse change frequency of the first control signal may be 1 Hz, and the pulse change frequency of the second control signal may be 90 Hz. Of course, these numbers are only examples and are not intended to limit the present application.

[0061] According to the display panel provided in the embodiment of the present application, the driving circuit is designed in different areas for different display areas. Specifically, the pixel circuit of the first display area is driven by the first driving circuit, and the pixel circuit of the second display area is driven by the second driving circuit. The first driving circuit receives a first control signal, and the second driving circuit receives a second driving signal. Since the pulse change frequency of the first control signal and the pulse change frequency of the second control signal are different, the first driving signal generated by the first driving circuit and the second driving signal generated by the second driving circuit will also be different. Therefore, different display requirements of the first display area and the second display area can be flexibly realized.

[0062] Please refer to Figure 1 The first driving circuit 10 and the second driving circuit 20 may be located in the non-display area NA of the display panel 100 , and the non-display area NA may at least partially surround the first display area 101 and the second display area 102 .

[0063] The control signals received by the first driving circuit 10 and the second driving circuit 20 may include different types of control signals. For example, the control signals received by both may include a trigger signal and a clock signal. Figure 5 As shown, the first shift register VSR1 may include transistors M11-M18 and capacitors C1 and C2. Figure 5 In the figure, STV1 represents the first trigger signal, CK1 represents the first sub-clock signal, XCK1 represents the second sub-clock signal, VGH represents a high level signal, VGL represents a low level signal, and OUT1 represents the output end of the first shift register VSR1.

[0064] The first control signal received by the first driving circuit 10 may include a first trigger signal STV1 and a first clock signal. In this paper, the first clock signal may include a first sub-clock signal CK1 and a second sub-clock signal XCK1. The working process of the first shift register VSR1 can be as follows: Figure 6 As shown, under the control of the first trigger signal STV1 and the first clock signal, the output terminal OUT1 of the first shift register VSR1 can output the first driving signal.

[0065] It is understandable that the signal outputted from the output terminal of the first shift register VSR1 of the previous stage can be used as the first trigger signal of the first shift register VSR1 of the next stage.

[0066] The circuit structure of the second shift register VSR2 and the first shift register VSR1 may be the same, except that: Figure 7 As shown, the second control signal received by the second driving circuit 20 may include a second trigger signal STV2 and a second clock signal. In this article, the second clock signal may include a third sub-clock signal CK2 and a fourth sub-clock signal XCK2. The working process of the second shift register VSR2 may be the same as the working process of the first shift register VSR1. Under the control of the second trigger signal STV2 and the second clock signal, the output terminal OUT2 of each stage of the second shift register VSR2 of the second driving circuit 20 may output the second driving signal.

[0067] It is understandable that the signal outputted from the output terminal of the second shift register VSR2 of the previous stage can be used as the second trigger signal of the second shift register VSR2 of the next stage.

[0068] Optionally, the circuit structures of the first shift register VSR1 and the second shift register VSR2 may be different, and they respectively output the first control signal and the second control signal to achieve different display requirements of the first display area 101 and the second display area 102 .

[0069] Both the trigger signal and the clock signal can control the output of the shift register. For example, the effective writing of the trigger signal can control whether the shift register outputs or not, and the clock signal can determine the time when the shift register outputs the signal. Therefore, for the first driving circuit 10 and the second driving circuit 20, at least one of the trigger signal and the clock signal is different, so that the first driving signal provided by the first driving circuit 10 and the second driving signal provided by the second driving circuit 20 can be different.

[0070] As an example, the pulse change frequency of the first trigger signal STV1 and the pulse change frequency of the second trigger signal STV2 may be different.

[0071] As another example, the pulse change frequency of the first clock signal and the pulse change frequency of the second clock signal may be different. Specifically, the pulse change frequency of the first sub-clock signal CK1 and the pulse change frequency of the third sub-clock signal CK2 may be different, and the pulse change frequency of the second sub-clock signal XCK1 and the pulse change frequency of the fourth sub-clock signal XCK2 may be different.

[0072] As another example, the pulse change frequency of the first trigger signal STV1 and the pulse change frequency of the second trigger signal STV2 may be different, and the pulse change frequency of the first clock signal and the pulse change frequency of the second clock signal may be different. Specifically, the pulse change frequency of the first sub-clock signal CK1 and the pulse change frequency of the third sub-clock signal CK2 may be different, and the pulse change frequency of the second sub-clock signal XCK1 and the pulse change frequency of the fourth sub-clock signal XCK2 may be different.

[0073] Exemplarily, the pulse change frequency of the first sub-clock signal CK1 and the pulse change frequency of the second sub-clock signal XCK1 may be the same, the rising edge of the first sub-clock signal CK1 and the rising edge of the second sub-clock signal XCK1 may be staggered in time, and the falling edge of the first sub-clock signal CK1 and the falling edge of the second sub-clock signal XCK1 may be staggered in time. Similarly, the pulse change frequency of the third sub-clock signal CK2 and the pulse change frequency of the fourth sub-clock signal XCK2 may be the same, the rising edge of the third sub-clock signal CK2 and the rising edge of the fourth sub-clock signal XCK2 may be staggered in time, and the falling edge of the third sub-clock signal CK2 and the falling edge of the fourth sub-clock signal XCK2 may be staggered in time. Among them, the rising edge may represent the moment when the signal changes from a low level to a high level, and the falling edge may represent the moment when the signal changes from a high level to a low level.

[0074] In addition, when the pulse change frequency of the first trigger signal STV1 and the pulse change frequency of the second trigger signal STV2 are different, the pulse change frequency of the first clock signal and the pulse change frequency of the second clock signal may be the same. Specifically, the pulse change frequencies of the first sub-clock signal CK1, the second sub-clock signal XCK1, the third sub-clock signal CK2, and the fourth sub-clock signal XCK2 may be the same.

[0075] Likewise, when the pulse changing frequency of the first clock signal CK1 and the pulse changing frequency of the second clock signal CK2 are different, the pulse changing frequency of the first trigger signal STV1 and the pulse changing frequency of the second trigger signal STV2 may be the same.

[0076] As described above, different display areas of the display panel may have different display functions or display effects. For example, the first display area 101 and the second display area 102 may have different screen refresh rates. The screen refresh rate may be equal to the effective data refresh rate of the pixel circuit Pixel. For example, the effective data refresh rate corresponding to the first display area 101 may be greater than the effective data refresh rate corresponding to the second display area 102.

[0077] Specifically, the first display area 101 may include pixel circuits Pixel from the Mth row to the Nth row, and the second display area 102 may include pixel circuits Pixel from the Pth row to the Qth row, and the effective data refresh frequency of the pixel circuits Pixel from the Mth row to the Nth row may be greater than the effective data refresh frequency of the pixel circuits Pixel from the Pth row to the Qth row. M<N,P<Q,M, N, P, Q are all positive integers. For example, the number of rows of pixel circuits included in the first display area 101 may be equal to the number of rows of pixel circuits included in the second display area 102, that is, NM=QP. For another example, the number of rows of pixel circuits included in the first display area 101 may be greater than the number of rows of pixel circuits included in the second display area 102, that is, NM>QP. For another example, the number of rows of pixel circuits included in the first display area 101 may be less than the number of rows of pixel circuits included in the second display area 102, that is, NM<QP.

[0078] In addition, the meaning of the effective data refresh frequency will be introduced below.

[0079] In the case where the effective data refresh frequency corresponding to the first display area 101 is greater than the effective data refresh frequency corresponding to the second display area 102, in some examples, the pulse change frequency of the first trigger signal STV1 may be greater than the pulse change frequency of the second trigger signal STV2. In other examples, the pulse change frequency of the first clock signal may be greater than the pulse change frequency of the second clock signal. In still other examples, the pulse change frequency of the first trigger signal STV1 is greater than the pulse change frequency of the second trigger signal STV2, and the pulse change frequency of the first clock signal is greater than the pulse change frequency of the second clock signal.

[0080] Among them, the specific situation in which the pulse change frequency of the first clock signal is greater than the pulse change frequency of the second clock signal may include: the pulse change frequency of the first sub-clock signal CK1 is greater than the pulse change frequency of the third sub-clock signal CK2, and the pulse change frequency of the second sub-clock signal XCK1 is greater than the pulse change frequency of the fourth sub-clock signal XCK2.

[0081] It is understandable that, since the pulse change frequency of the second trigger signal and / or the second clock signal received by the second driving circuit is relatively low, the frequency of the voltage reversal of the second trigger signal and / or the second clock signal is also relatively low, and the lower the frequency of the voltage reversal, the lower the power consumption. Therefore, in the embodiment of the present application, for the second display area with a lower effective data refresh frequency, the pulse change frequency of the second trigger signal and / or the second clock signal received by the corresponding second driving circuit is relatively low, which is conducive to reducing power consumption. For the first display area with a higher effective data refresh frequency, the pulse change frequency of the first trigger signal and / or the first clock signal received by the corresponding first driving circuit is relatively high, which can ensure the display effect of the first display area.

[0082] It should be noted that, in a certain display state, the effective data refresh frequency corresponding to the first display area 101 may be different from the effective data refresh frequency corresponding to the second display area 102; in another display state, the effective data refresh frequency corresponding to the first display area 101 and the effective data refresh frequency corresponding to the second display area 102 may have other corresponding relationships, for example, the effective data refresh frequency corresponding to the first display area 101 may be equal to the effective data refresh frequency corresponding to the second display area 102.

[0083] The effective data refresh frequency is introduced below.

[0084] Herein, the effective data refresh frequency may be equal to the number of times the data signal Vdata is written into the gate of the driving transistor in the pixel circuit Pixel within 1 second.

[0085] As an example, Figure 2 and Figure 3 As shown, the pixel circuit may include a driving transistor M3, a reset transistor M5, a data writing transistor M2, a compensation transistor M4, an initialization transistor M7 and a light emitting control transistor M1 / M6. Among them, the reset transistor M5 is used to selectively provide a reset signal Vref1 to the gate of the driving transistor M3. Figure 2 For example, the reset transistor M5 can be connected to the control terminal of the driving transistor M3. The initialization transistor M7 is used to selectively provide the light emitting element D with an initialization signal Vref2.

[0086] The light-emitting control transistor is used to selectively allow the light-emitting element D to enter the light-emitting stage. The light-emitting control transistor includes a first light-emitting control transistor M1 and a second light-emitting control transistor M6. The first light-emitting control transistor M1 is connected between the first power signal terminal PVDD and the source of the driving transistor M3. The second light-emitting control transistor M6 is connected between the drain of the driving transistor M3 (node ​​N3 in the figure is used as an illustration) and the light-emitting element D (node ​​N4 in the figure is used as an illustration). The first electrode of the compensation transistor M4 is connected to the output terminal N3 of the driving transistor M3, and the second electrode of the compensation transistor M4 is connected to the control terminal N1 of the driving transistor M3. The compensation transistor M4 is used to compensate for the threshold voltage deviation of the driving transistor M3.

[0087] The data writing transistor M2 is used to provide a data signal to the driving transistor M3. Figure 2 For example, the data writing transistor M2 is connected to the input terminal of the driving transistor M3 (node ​​N2 is used as an illustration in the figure). The storage capacitor Cst, the first end of the holding capacitor Cst is connected to the first power signal terminal PVDD, and the second end of the holding capacitor Cst is connected to the gate of the driving transistor M3.

[0088] Optionally, the reset signal Vref1 and the initialization signal Vref2 may be the same or different. The reset signal Vref1 may be different in different time periods of the same display panel, and / or the voltage value of the initialization signal Vref2 may be different in different time periods of the same display panel.

[0089] like Figure 2 and Figure 3 As shown, the scan signal S2 can control whether the data signal Vdata can be written into the gate of the driving transistor M3. When the scan signal S2 is at an effective level, the data signal Vdata can be written into the gate of the driving transistor M3 (the gate of the driving transistor M3 is connected to the node N1). Here, the effective data refresh frequency can be equal to the pulse change frequency of the scan signal S2.

[0090] It should be noted that, for a PMOS transistor, the effective level of the scan signal is a low level signal, and when the transistor is an NMOS transistor, the effective level of the scan signal is a high level signal.

[0091] As another example, the structure of the pixel circuit can be as follows Figure 8 It should be noted that in the drawings of the pixel circuit of the present application, transistors with the same position are marked with the same reference numerals, which will not be described in detail here.

[0092] like Figure 8 As shown, the compensation transistor M4 and the reset transistor M5 are oxide transistors.

[0093] The control end of the reset transistor M5 receives the first scan signal S1 , the control end of the data writing transistor M2 receives the second scan signal S2 , the control end of the compensation transistor M4 receives the third scan signal S3 , and the control end of the initialization transistor M7 receives the fourth scan signal S3 .

[0094] like Figure 8 and Fig. 9 As shown, the second scan signal S2 and the third scan signal S3 input valid levels at the same time, the data write transistor M2 and the compensation transistor M4 are turned on, the data signal Vdata is written into the gate of the driving transistor M3, and the effective level overlap time period of the second scan signal S2 and the third scan signal S3 is the effective data write phase d. Here, the effective data refresh frequency can be equal to the pulse change frequency of the effective level overlap time period of the second scan signal S2 and the third scan signal S3, which can also be understood as the effective data refresh frequency can be equal to the pulse change frequency of the second scan signal S2.

[0095] As another example, in order to optimize the structure of the pixel circuit, the structure of the pixel circuit may be as follows: Fig.10 As shown, Fig.11 Shows Fig.10 A timing diagram of .

[0096] like Fig.10 and Fig.11 As shown, the working process of the pixel circuit includes a bias phase p and a valid data writing phase d. In the valid data writing phase d, the data writing transistor M2 is used to provide a data signal Vdata. In the bias phase p, the data writing transistor M2 is used to provide a bias signal Vobs.

[0097] In the bias phase p, the second scanning signal S2 is a low level signal, the data writing transistor M2 is turned on, the driving transistor M3 is turned on, and the bias signal Vobs is written into the drain of the driving transistor M3 to adjust the bias state of the driving transistor M3.

[0098] The voltage value of the bias signal Vobs may be greater than or equal to the voltage value of the data signal Vdata, or the voltage value of the bias signal Vobs may be less than the voltage value of the data signal Vdata.

[0099] The working process of the pixel circuit includes a data writing frame and a holding frame, the data writing frame includes a biasing stage, and / or the holding frame includes a biasing stage.

[0100] like Fig.10 and Fig.11As shown, in the effective data writing stage d, the second scanning signal S2 is a low level signal, the data transistor M2 is turned on, the third scanning signal S3 is a high level signal, the compensation transistor M4 is turned on, and the data signal Vdata is written to the gate of the driving transistor M3. The effective level overlap period of the second scanning signal S2 and the third scanning signal S3 is the effective data writing stage d. Here, the effective data refresh frequency can be equal to the pulse change frequency of the effective level overlap period of the second scanning signal S2 and the third scanning signal S3.

[0101] As another example, the structure of the pixel circuit can be as follows Fig.12 As shown, Fig.13 Shows Fig.12 A timing diagram of .

[0102] like Fig.12 and Fig.13 As shown, this embodiment is compared with Figure 8 The pixel circuit shown, Fig.12 The provided pixel circuit further includes a bias transistor M8, which is used to adjust the bias state of the driving transistor M3. A first electrode of the bias transistor M8 receives a bias signal Vobs, and a second electrode of the bias transistor M8 is connected to an input terminal N2 of the driving transistor M3.

[0103] The operation process of the pixel circuit may include a bias phase p and a valid data writing phase d. In the valid data writing phase d, the data writing transistor M2 is used to provide a data signal Vdata. In the bias phase p, the bias transistor M8 is used to provide a bias signal Vobs. In the bias phase p, the fifth scanning signal S5 is a low-level signal, the bias transistor M8 is turned on, the driving transistor M3 is turned on, and the bias signal Vobs is written into the drain of the driving transistor M3 to adjust the bias state of the driving transistor M3.

[0104] The voltage value of the bias signal Vobs may be greater than or equal to the voltage value of the data signal Vdata, or the voltage value of the bias signal Vobs may be less than the voltage value of the data signal Vdata.

[0105] The working process of the pixel circuit includes a data writing frame and a holding frame, the data writing frame includes a biasing stage, and / or the holding frame includes a biasing stage.

[0106] Optionally, the fifth scan signal S5 and the fourth scan signal S4 may be the same scan signal.

[0107] like Fig.12 and Fig.13As shown, in the effective data writing stage d, the second scanning signal S2 is a low level signal, the data transistor M2 is turned on, the third scanning signal S3 is a high level signal, the compensation transistor M4 is turned on, and the data signal Vdata is written to the gate of the driving transistor M3. The effective level overlap period of the second scanning signal S2 and the third scanning signal S3 is the effective data writing stage d. Here, the effective data refresh frequency can be equal to the pulse change frequency of the effective level overlap period of the second scanning signal S2 and the third scanning signal S3.

[0108] As another example, the structure of the pixel circuit can be as follows Fig.14 As shown, Fig.15 Shows Fig.14 A timing diagram of .

[0109] like Fig.14 and Fig.15 As shown, the reset transistor M5 is used to selectively provide a reset signal Vref1 to the gate of the driving transistor M3. Fig.14 As shown, the reset transistor M5 is connected to the output terminal N3 of the driving transistor M3.

[0110] like Fig.14 and Fig.15 As shown, the working process of the pixel circuit includes a reset phase c, a bias phase p and a valid data writing phase d. In the valid data writing phase d, the data writing transistor M2 is used to provide a data signal Vdata, in the reset phase c, the reset transistor M5 is used to provide a reset signal Vref1, and in the bias phase p, the reset transistor M5 is used to provide a bias signal Vobs. In the bias phase p, the first scanning signal S1 is a low-level signal, the reset transistor M5 is turned on, and the bias signal Vobs is written to the drain of the driving transistor M3 to adjust the bias state of the driving transistor M3.

[0111] The voltage value of the bias signal Vobs may be greater than or equal to the voltage value of the reset signal Vref1 , or the voltage value of the bias signal Vobs may be less than the voltage value of the reset signal Vref1 .

[0112] Optionally, the first scanning signal S2 and the fifth scanning signal S5 may be the same scanning signal.

[0113] The working process of the pixel circuit includes a data writing frame and a holding frame, the data writing frame includes a biasing stage, and / or the holding frame includes a biasing stage.

[0114] like Fig.14 and Fig.15As shown, in the effective data writing stage d, the second scanning signal S2 is a low level signal, the data transistor M2 is turned on, the third scanning signal S3 is a high level signal, the compensation transistor M4 is turned on, and the data signal Vdata is written to the gate of the driving transistor M3. The effective level overlap period of the second scanning signal S2 and the third scanning signal S3 is the effective data writing stage d. Here, the effective data refresh frequency can be equal to the pulse change frequency of the effective level overlap period of the second scanning signal S2 and the third scanning signal S3.

[0115] In some embodiments, when the effective data refresh frequency of the pixel circuit of the first display area 101 is K1 times the effective data refresh frequency of the pixel circuit of the second display area 102, the pulse change frequency of the first trigger signal STV1 may be K1 times the pulse change frequency of the second trigger signal STV2, K1> 1. Here, by synchronizing the multiple relationship between the pulse change frequencies of the two trigger signals with the multiple relationship between the effective data refresh frequencies of the two display areas, signal disorder output by the first drive circuit and the second drive circuit can be avoided, thereby avoiding display defects such as flickering.

[0116] For example, the effective data refresh frequency of the pixel circuit of the first display area 101 is 120 Hz, and the effective data refresh frequency of the pixel circuit of the second display area 102 is 60 Hz, then K1 = 2. Exemplarily, the pulse change frequency of the first trigger signal STV1 may be equal to the effective data refresh frequency of the pixel circuit of the first display area 101. The pulse change frequency of the second trigger signal STV2 may be equal to the effective data refresh frequency of the pixel circuit of the second display area 102.

[0117] In other embodiments, when the effective data refresh frequency of the pixel circuit of the first display area 101 is K2 times the effective data refresh frequency of the pixel circuit of the second display area 102, K2>1, the pulse change frequency of the first trigger signal STV1 may be K2 times the pulse change frequency of the second trigger signal STV2, and the pulse change frequency of the first clock signal may be K2 times the pulse change frequency of the second clock signal. Here, by synchronizing the multiple relationship between the pulse change frequencies of the two trigger signals and the multiple relationship between the pulse change frequencies of the two clock signals with the multiple relationship between the effective data refresh frequencies of the two display areas, signal disorder of the outputs of the first drive circuit and the second drive circuit can be further avoided, thereby further avoiding display defects such as flickering.

[0118] The pulse change frequency of the first clock signal is K2 times the pulse change frequency of the second clock signal, which may specifically include: the pulse change frequency of the first sub-clock signal CK1 is K2 times the pulse change frequency of the third sub-clock signal CK2, and the pulse change frequency of the second sub-clock signal XCK1 is K2 times the pulse change frequency of the fourth sub-clock signal XCK2.

[0119] In some embodiments, the effective pulse time lengths of the two trigger signals may be kept unchanged, and the duty ratios of the two trigger signals may be changed to achieve different pulse change frequencies of the two trigger signals, wherein the duty ratio may be the ratio of the effective pulse time length to the invalid pulse time length.

[0120] Specifically, when the pulse change frequency of the first trigger signal STV1 is greater than the pulse change frequency of the second trigger signal STV2, as shown in FIG. Fig.16 As shown, the effective pulse time length of the first trigger signal STV1 is t1, the invalid pulse time length of the first trigger signal STV1 is t2, the effective pulse time length of the second trigger signal STV2 is t3, the invalid pulse time length of the second trigger signal STV2 is t4, t1=t3,

[0121] Exemplarily, t1<t2, t3<t4.

[0122] As described above, the first drive signal output by the first drive circuit can control the transistor in the pixel circuit to be turned on or off, and the first shift registers at each level of the first drive circuit can shift and output the valid pulse of the first trigger signal, so the valid pulse of the first trigger signal can be understood as being able to control the transistor to be turned on, and the invalid pulse of the first trigger signal can be understood as being able to control the transistor to be turned off. Similarly, the valid pulse of the second trigger signal can be understood as being able to control the transistor to be turned on, and the invalid pulse of the second trigger signal can be understood as being able to control the transistor to be turned off. In the drawings of this article, the valid pulses of the two trigger signals are shown as low levels and the invalid pulses are shown as high levels, which is not used to limit this application.

[0123] In the embodiment of the present application, since the effective pulse time lengths of the two trigger signals are equal, the conduction time of the transistors of the pixel circuits respectively controlled by the first driving circuit and the second driving circuit is equal, that is, the charging time of the pixel circuits in the two display areas can be equal, which is beneficial to improving the consistency of the charging effect.

[0124] At t1=t3 and In the case of , further, t4, t1 and t2 can satisfy the following relationship:

[0125] t4=n*t2+(n-1)*t1, n≥2, and n is an integer.

[0126] In this way, it can be ensured that t4 is large enough, thereby ensuring that the pulse change frequency of the second trigger signal STV2 is lower than the pulse change frequency of the first trigger signal STV1.

[0127] In other embodiments, the duty cycles of the two trigger signals may be kept unchanged, and the effective pulse time lengths of the two trigger signals may be changed to achieve different pulse change frequencies of the two trigger signals.

[0128] Specifically, when the pulse change frequency of the first trigger signal STV1 is greater than the pulse change frequency of the second trigger signal STV2, as shown in FIG. Fig.17 As shown, the effective pulse time length of the first trigger signal STV1 is t1, the invalid pulse time length of the first trigger signal STV1 is t2, the effective pulse time length of the second trigger signal STV2 is t3, the invalid pulse time length of the second trigger signal STV2 is t4, t1<t3,

[0129] It can be understood that t2<t4.

[0130] In the embodiment of the present application, since the duty cycles of the two trigger signals are equal, it is equivalent to lengthening the effective pulse time length and the invalid pulse time length of the first trigger signal STV1 by the same multiple, thereby obtaining the second trigger signal STV2. In other words, it is equivalent to shortening the effective pulse time length and the invalid pulse time length of the second trigger signal STV2 by the same multiple, thereby obtaining the first trigger signal STV1. In this way, the first trigger signal STV1 and the second trigger signal STV2 can be conveniently formed.

[0131] For example, the effective data refresh frequency of the pixel circuit of the first display area 101 is K1 times the effective data refresh frequency of the pixel circuit of the second display area 102. When t1<t3, In the case of further K1>1.

[0132] It can be understood that this is equivalent to lengthening the effective pulse time length and the invalid pulse time length of the first trigger signal STV1 by K1 times to obtain the second trigger signal STV2. This can further avoid signal disorder output by the first drive circuit and the second drive circuit, thereby further avoiding display defects such as screen flickering.

[0133] In some embodiments, when the pulse change frequency of the first trigger signal STV1 is K2 times the pulse change frequency of the second trigger signal STV2, and the pulse change frequency of the first clock signal is K2 times the pulse change frequency of the second clock signal, Fig.18As shown, the effective pulse time length of the first trigger signal STV1 is t1, the invalid pulse time length of the first trigger signal STV1 is t2, the effective pulse time length of the second trigger signal STV2 is t3, and the invalid pulse time length of the second trigger signal STV2 is t4. The effective pulse time length of the first clock signal is t5, the invalid pulse time length of the first clock signal is t6, the effective pulse time length of the second clock signal is t7, and the invalid pulse time length of the second clock signal is t8,

[0134]

[0135] It can be understood that this is equivalent to lengthening the effective pulse time length and the invalid pulse time length of the first trigger signal STV1 by K2 times to obtain the second trigger signal STV2, and is equivalent to lengthening the effective pulse time length and the invalid pulse time length of the first clock signal by K2 times to obtain the second clock signal. In this way, signal disorder of the outputs of the first drive circuit and the second drive circuit can be further avoided, thereby further avoiding display defects such as screen flickering.

[0136] The level of the valid pulse of the first clock signal may be the same as the level of the valid pulse of the first trigger signal, and the level of the invalid pulse of the first clock signal may be the same as the level of the invalid pulse of the first trigger signal. The level of the valid pulse of the second clock signal may be the same as the level of the valid pulse of the second trigger signal, and the level of the invalid pulse of the second clock signal may be the same as the level of the invalid pulse of the second trigger signal. For example, the valid pulses of the first clock signal and the second clock signal are both low level, and the invalid pulses of the first clock signal and the second clock signal are both high level.

[0137] like Fig.18 As shown, the valid pulse time lengths of the first sub-clock signal CK1 and the second sub-clock signal XCK1 included in the first clock signal are both t5, and the invalid pulse time lengths of the first sub-clock signal CK1 and the second sub-clock signal XCK1 are both t6. The valid pulse time lengths of the third sub-clock signal CK2 and the fourth sub-clock signal XCK2 included in the second clock signal are both t7, and the invalid pulse time lengths of the third sub-clock signal CK2 and the fourth sub-clock signal XCK2 are both t8.

[0138] For a single clock signal, the pulse change frequency may be different at different stages. In some embodiments, the operation process of the pixel circuit in the display panel may include a data writing frame and a holding frame. In the data writing frame, the data signal is written to the gate of the driving transistor of the pixel circuit. In the holding frame, the data signal is no longer written to the gate of the driving transistor of the pixel circuit, and the gate of the driving transistor holds the data signal written in the data writing frame.

[0139] The pulse change frequency of the first clock signal in the data writing frame may be different from the pulse change frequency in the holding frame. And / or, the pulse change frequency of the second clock signal in the data writing frame may be different from the pulse change frequency in the holding frame.

[0140] In an embodiment of the present application, since the writing requirements of the data write frame and the hold frame for the data signal are different, the pulse change frequencies of the first clock signal and / or the second clock signal in the data write frame and the hold frame are set to be different, which can flexibly adapt to the different requirements of the data write frame and the hold frame.

[0141] Specifically, the first clock signal includes a first sub-clock signal CK1 and a second sub-clock signal XCK1, the pulse change frequency of the first sub-clock signal CK1 in the data write frame may be different from the pulse change frequency in the hold frame, and the pulse change frequency of the second sub-clock signal XCK1 in the data write frame may be different from the pulse change frequency in the hold frame. The pulse change frequencies of the first sub-clock signal CK1 and the second sub-clock signal XCK1 in the data write frame may be the same, and the pulse change frequencies of the first sub-clock signal CK1 and the second sub-clock signal XCK1 in the hold frame may be the same.

[0142] The second clock signal includes a third sub-clock signal CK2 and a fourth sub-clock signal XCK2, wherein the pulse change frequency of the third sub-clock signal CK2 in the data write frame may be different from the pulse change frequency in the hold frame, and the pulse change frequency of the fourth sub-clock signal XCK2 in the data write frame may be different from the pulse change frequency in the hold frame. The pulse change frequency of the third sub-clock signal CK2 and the fourth sub-clock signal XCK2 in the data write frame may be the same as the pulse change frequency in the hold frame, and the pulse change frequency of the third sub-clock signal CK2 and the fourth sub-clock signal XCK2 in the hold frame may be the same as the pulse change frequency in the hold frame.

[0143] As an example, the pulse change frequency of the first clock signal in the data write frame is greater than that in the hold frame; and / or the pulse change frequency of the second clock signal in the data write frame is greater than that in the hold frame.

[0144] In the embodiment of the present application, since the frame does not need to write a data signal, the pulse change frequency of the first clock signal and / or the second clock signal in the frame is relatively small, which can further reduce power consumption while avoiding affecting data writing.

[0145] Specifically, Fig.19As shown, the first clock signal includes a first sub-clock signal CK1 and a second sub-clock signal XCK1, the pulse change frequency of the first sub-clock signal CK1 in the data writing frame is greater than the pulse change frequency in the holding frame, and the pulse change frequency of the second sub-clock signal XCK1 in the data writing frame is greater than the pulse change frequency in the holding frame. The pulse change frequencies of the first sub-clock signal CK1 and the second sub-clock signal XCK1 in the data writing frame may be the same, and the pulse change frequencies of the first sub-clock signal CK1 and the second sub-clock signal XCK1 in the holding frame may be the same.

[0146] The second clock signal includes a third sub-clock signal CK2 and a fourth sub-clock signal XCK2, wherein the pulse change frequency of the third sub-clock signal CK2 in the data write frame is greater than the pulse change frequency in the hold frame, and the pulse change frequency of the fourth sub-clock signal XCK2 in the data write frame is greater than the pulse change frequency in the hold frame. The pulse change frequency of the third sub-clock signal CK2 and the fourth sub-clock signal XCK2 in the data write frame may be the same as the pulse change frequency in the hold frame, and the pulse change frequency of the third sub-clock signal CK2 and the fourth sub-clock signal XCK2 in the hold frame may be the same as the pulse change frequency in the hold frame.

[0147] For different first clock signals and second clock signals, the different pulse change frequencies of the two signals may refer to different pulse change frequencies of the two signals in the data writing frame. Fig. 20 As shown, in the data writing frame, the pulse changing frequency of the first clock signal is different from the pulse changing frequency of the second clock signal; in the holding frame, the pulse changing frequency of the first clock signal and the pulse changing frequency of the second clock signal may be the same.

[0148] Specifically, the first clock signal includes a first sub-clock signal CK1 and a second sub-clock signal XCK1, and the second clock signal includes a third sub-clock signal CK2 and a fourth sub-clock signal XCK2. In a data write frame, the pulse change frequency of the first sub-clock signal CK1 is different from the pulse change frequency of the third sub-clock signal CK2, and the pulse change frequency of the second sub-clock signal XCK1 is different from the pulse change frequency of the fourth sub-clock signal XCK2. In a hold frame, the pulse change frequency of the first sub-clock signal CK1 is the same as the pulse change frequency of the third sub-clock signal CK2, and the pulse change frequency of the second sub-clock signal XCK1 is the same as the pulse change frequency of the fourth sub-clock signal XCK2.

[0149] In some embodiments, Fig.21 As shown, the display panel 100 may further include a third display area 103 and a third driving circuit 30. The third display area 103 is provided with pixel circuits Pixel. In order to better distinguish the area to which the pixel circuits Pixel belong, Fig.21Different filling colors are used to represent the pixel circuits Pixel in the first display area 101 , the second display area 102 and the third display area 103 .

[0150] The third driving circuit 30 may include a multi-stage third shift register VSR3. The third driving circuit 30 is used to receive a third control signal and generate a third driving signal according to the third control signal. The third driving circuit 30 provides the third driving signal generated by it to the pixel circuit Pixel in the third display area 103, so that the transistor of the pixel circuit Pixel in the third display area 103 can be turned on or off under the control of the third driving signal.

[0151] As an example, the third driving circuit 30 may be a scanning driving circuit, so the type of the third driving signal may be Figure 2 The third driving circuit 30 provides the scanning signals Scan(n-1) and Scan(n) to the pixel circuit Pixel of the third display area 103 .

[0152] As another example, the third driving circuit 30 may be a light-emitting driving circuit, so the type of the third driving signal may be: Figure 2 The third driving circuit 30 provides the light emitting control signal Emit to the pixel circuit Pixel of the third display area 103 .

[0153] In the embodiment of the present application, the pulse change frequency of the first control signal, the pulse change frequency of the second control signal and the pulse change frequency of the third control signal are different.

[0154] It is understandable that the third control signal is also a pulse signal. Fig. 22 As shown, the third control signal may also include alternating high and low levels. For example, the period of the third control signal is T3, and the pulse change frequency of the third control signal can be understood as the number of times the third control signal completes periodic changes within a unit time (for example, within 1 second), and the pulse change frequency of the third control signal may be equal to 1 / T3.

[0155] For example, the pulse change frequency of the first control signal may be 120 Hz, the pulse change frequency of the second control signal may be 90 Hz, and the pulse change frequency of the third control signal may be 60 Hz. Of course, these numbers are only examples and are not used to limit the present application.

[0156] According to the embodiments of the present application, the driving circuit is designed in different areas for different display areas. Specifically, the pixel circuit of the first display area is driven by the first driving circuit, the pixel circuit of the second display area is driven by the second driving circuit, and the pixel circuit of the third display area is driven by the third driving circuit. The first driving circuit receives a first control signal, the second driving circuit receives a second driving signal, and the third driving circuit receives a third driving signal. Since the pulse change frequency of the first control signal, the pulse change frequency of the second control signal, and the pulse change frequency of the third control signal are different, the first driving signal generated by the first driving circuit, the second driving signal generated by the second driving circuit, and the third driving signal generated by the third driving circuit will also be different. Therefore, different display requirements of the first display area, the second display area, and the third display area can be flexibly realized.

[0157] In some examples, the circuit structure of the third shift register VSR3 may be the same as the circuit structure of the first shift register VSR1, except that, Fig.23 As shown, the third control signal received by the third driving circuit 30 may include a third trigger signal STV3 and a third clock signal. In this document, the third clock signal may include a fifth sub-clock signal CK3 and a sixth sub-clock signal XCK3. The working process of the third shift register VSR3 may be the same as the working process of the first shift register VSR1. Under the control of the third trigger signal STV3 and the third clock signal, the output terminal OUT3 of each stage of the third shift register VSR3 of the third driving circuit 30 may output a third driving signal.

[0158] It is understandable that the signal outputted from the output terminal of the third shift register VSR3 of the previous stage can be used as the third trigger signal of the third shift register VSR3 of the next stage.

[0159] As an example, the pulse change frequencies of the first trigger signal STV1, the second trigger signal STV2 and the third trigger signal STV3 may be different, and the pulse change frequencies of the first clock signal, the second clock signal and the third clock signal may be different.

[0160] The pulse change frequency of the first clock signal, the pulse change frequency of the second clock signal and the pulse change frequency of the third clock signal are different, and specifically may include: the pulse change frequency of the first sub-clock signal CK1, the pulse change frequency of the third sub-clock signal CK2 and the pulse change frequency of the fifth sub-clock signal CK3 may be different, and the pulse change frequency of the second sub-clock signal XCK1, the pulse change frequency of the fourth sub-clock signal XCK2 and the pulse change frequency of the sixth sub-clock signal XCK3 may be different.

[0161] As another example, the pulse change frequency of the first trigger signal STV1, the pulse change frequency of the second trigger signal STV2, and the pulse change frequency of the third trigger signal STV3 may be different, and the pulse change frequency of the first clock signal is different from the pulse change frequency of the second clock signal, and the pulse change frequency of the third clock signal is the same as one of the pulse change frequency of the first clock signal and the pulse change frequency of the second clock signal. In other words, the third display area shares the clock signal of one of the first display area and the second display area, so that the number of clock signal terminals can be reduced, which is conducive to reducing costs.

[0162] In some embodiments, the two display areas sharing the clock signal may be set according to the valid data refresh frequencies corresponding to the three display areas.

[0163] For example, the first display area 101 includes pixel circuits Pixel from the Mth row to the Nth row, and the effective data refresh frequency of the pixel circuits Pixel from the Mth row to the Nth row is F1. The second display area 102 includes pixel circuits Pixel from the Pth row to the Qth row, and the effective data refresh frequency of the pixel circuits Pixel from the Pth row to the Qth row is F2. The third display area 103 includes pixel circuits Pixel from the Rth row to the Sth row, and the effective data refresh frequency of the pixel circuits Pixel from the Rth row to the Sth row is F3.

[0164] In the case of |F3-F1|<|F3-F2|, the pulse change frequency of the third clock signal can be the same as the pulse change frequency of the second clock signal. In other words, the effective data refresh frequency corresponding to the third display area is closer to the effective data refresh frequency corresponding to the first display area, so that the two display areas with relatively close effective data refresh frequencies can share the clock signal, which can ensure that the third display area has a relatively good display effect.

[0165] In the case of F1>F2, the pulse change frequency of the first clock signal is greater than the pulse change frequency of the second clock signal, and the pulse change frequency of the third clock signal is equal to the pulse change frequency of the second clock signal. In other words, the third display area shares the lower pulse change frequency of the second clock signal corresponding to the second display area, which can further reduce power consumption.

[0166] The pulse change frequency of the third clock signal is the same as the pulse change frequency of the second clock signal, and specifically may include: the pulse change frequency of the fifth sub-clock signal CK3 is the same as the pulse change frequency of the third sub-clock signal CK2, and the pulse change frequency of the sixth sub-clock signal XCK3 is the same as the pulse change frequency of the fourth sub-clock signal XCK2.

[0167] As described above, the pulse change frequency of the first trigger signal STV1 and the pulse change frequency of the second trigger signal STV2 may be different. As an example, different trigger signal lines may be set to transmit the first trigger signal STV1 and the second trigger signal STV2 respectively. Fig.24 As shown, the display panel 100 may further include a first trigger signal line 41 and a second trigger signal line 51. The first trigger signal line 41 is used to provide a first trigger signal STV1 to the first stage first shift register VSR1. The second trigger signal line 51 is used to provide a second trigger signal STV2 to the first stage second shift register VSR2.

[0168] In the embodiment of the present application, by setting two trigger signal lines, the first drive circuit 10 and the second drive circuit 20 can be made independent of each other, which can improve the working stability of the first drive circuit 10 and the second drive circuit 20; in addition, the first drive circuit 10 and the second drive circuit 20 can start working at the same time, so that the first drive circuit 10 only needs to drive multiple rows of pixel circuits in the first display area within one frame, and the second drive circuit 20 only needs to drive multiple rows of pixel circuits in the second display area. Compared with driving all rows of pixel circuits of the display panel within one frame, the number of rows of pixel circuits driven by the first drive circuit 10 and the second drive circuit 20 within one frame is reduced, so the charging time of the pixel circuit can be extended, which is beneficial to improving the charging effect, and then improving the display effect.

[0169] As another example, only one trigger signal line may be provided and the frequency conversion module may be connected between the first shift register VSR1 and the second shift register VSR2. Fig.25 As shown, the display panel 100 may further include a first trigger signal line 41 and a frequency conversion module 60. The first trigger signal line 41 is used to provide a first trigger signal STV1 to the first-stage first shift register VSR1. The frequency conversion module 60 is connected between the first shift register VSR1 and the second shift register VSR2, and the frequency conversion module 60 may be used to generate a second trigger signal STV2, and provide the second trigger signal STV2 to the first-stage second shift register VSR2.

[0170] Specifically, the frequency conversion module 60 can be connected between the output end of the last-stage first shift register VSR1 and the trigger signal input end of the first-stage second shift register VSR2. The frequency conversion module 60 can be used to change the pulse change frequency of the first drive signal output by the last-stage first shift register VSR1 to obtain the second trigger signal STV2, and provide the second trigger signal STV2 to the first-stage second shift register VSR2.

[0171] In the embodiment of the present application, by providing the frequency conversion module 60, the number of trigger signal lines can be reduced, which is conducive to achieving a narrow frame.

[0172] The embodiment of the present application introduces the frequency conversion module by taking the trigger signal as an example. It is understandable that the frequency conversion module is not only applicable to the frequency conversion of the trigger signal, but also applicable to the frequency conversion of the clock signal, which will not be repeated here.

[0173] Exemplarily, the frequency conversion module 60 may include a control terminal, an input terminal, and an output terminal. The input terminal of the frequency conversion module 60 is connected to the output terminal of the first shift register VSR1, for example, the input terminal of the frequency conversion module 60 may be connected to the output terminal of the last stage first shift register VSR1. The output terminal of the frequency conversion module 60 is connected to the trigger signal input terminal of the second shift register VSR2, for example, the output terminal of the frequency conversion module 60 is connected to the trigger signal input terminal of the first stage second shift register VSR2. The control terminal of the frequency conversion module 60 may receive a control signal, and the frequency conversion module 60 may be turned on or off under the control of the control signal.

[0174] The frequency conversion module 60 may include a transistor, a gate g of the transistor serves as a control terminal of the frequency conversion module 60, a first electrode of the transistor serves as an input terminal of the frequency conversion module 60, and a second electrode of the transistor serves as an output terminal of the frequency conversion module 60. The first electrode of the transistor may be a source electrode, and the second electrode of the transistor may be a drain electrode.

[0175] In some examples, different control signal lines may be set to transmit the first control signal and the second control signal respectively. Fig.24 , the display panel 100 may further include a first control signal line 40 and a second control signal line 50. The first control signal line 40 may be used to provide a first control signal to the first drive circuit 10, and the second control signal line 50 may be used to provide a second control signal to the second drive circuit 20. The routing length of the first control signal line 40 is greater than the routing length of the second control signal line 50, and the routing width of the first control signal line 40 is greater than the routing width of the second control signal line 50. In this way, the impedances of the first control signal line 40 and the second control signal line 50 may be made equivalent, which is beneficial to improving display uniformity.

[0176] Specifically, the first control signal line 40 may include a first trigger signal line 41 and a first clock signal line 42. The first clock signal line 42 may include a first sub-clock signal line 421 and a second sub-clock signal line 422. The first trigger signal line 41 is connected to the first-stage first shift register VSR1, and the first trigger signal line 41 is used to increase the first trigger signal STV1 for the first-stage first shift register VSR1. The first sub-clock signal line 421 and the second sub-clock signal line 422 are connected to each first shift register VSR1, and are used to provide the first sub-clock signal CK1 and the second sub-clock signal XCK1 for each first shift register VSR1.

[0177] The second control signal line 50 may include a second trigger signal line 51 and a second clock signal line 52. The second clock signal line 52 may include a third sub-clock signal line 521 and a fourth sub-clock signal line 522. The second trigger signal line 51 is connected to the first-stage second shift register VSR2, and the second trigger signal line 51 is used to increase the second trigger signal STV2 for the first-stage second shift register VSR2. The third sub-clock signal line 521 and the fourth sub-clock signal line 522 are connected to each second shift register VSR2, and are used to provide the third sub-clock signal CK2 and the fourth sub-clock signal XCK2 for each second shift register VSR2.

[0178] The routing length of the first trigger signal line 41 is greater than the routing length of the second trigger signal line 51 , and the routing width of the first trigger signal line 41 is greater than the routing width of the second trigger signal line 51 .

[0179] The routing length of the first sub-clock signal line 421 is greater than the routing length of the third sub-clock signal line 521 , and the routing width of the first sub-clock signal line 421 is greater than the routing width of the third sub-clock signal line 521 .

[0180] The routing length of the second sub-clock signal line 422 is greater than the routing length of the fourth sub-clock signal line 522 , and the routing width of the second sub-clock signal line 422 is greater than the routing width of the fourth sub-clock signal line 522 .

[0181] As an example, Fig.24 As shown, in the row direction X, the first control signal line 40 and the second control signal line 50 may be on the side of the first shift register VSR1 and the second shift register VSR2 away from the display area. That is, the orthographic projection of the first control signal line 40 on the light emitting surface of the display panel and the orthographic projection of the first shift register VSR1 on the light emitting surface of the display panel may not overlap, and / or, the orthographic projection of the second control signal line 50 on the light emitting surface of the display panel and the orthographic projection of the second shift register VSR2 on the light emitting surface of the display panel may not overlap.

[0182] As another example, the orthographic projection of the first control signal line 40 on the light-emitting surface of the display panel may overlap with the orthographic projection of the first shift register VSR1 on the light-emitting surface of the display panel, and / or the orthographic projection of the second control signal line 50 on the light-emitting surface of the display panel may overlap with the orthographic projection of the second shift register VSR2 on the light-emitting surface of the display panel. In this way, it is conducive to achieving a narrow frame.

[0183] Exemplarily, the orthographic projection of the first control signal line 40 on the light emitting surface of the display panel and the orthographic projection of the second shift register VSR2 on the light emitting surface of the display panel may also overlap.

[0184] As described above, the first control signal line 40 may include a first trigger signal line 41 and a first clock signal line 42. The second control signal line 50 may include a second trigger signal line 51 and a second clock signal line 52.

[0185] As an example, the first trigger signal line 41 and the first clock signal line 42 may be located in the same film layer; and / or, the second trigger signal line 51 and the second clock signal line 52 may be located in the same film layer.

[0186] Since the first trigger signal line 41 and the first clock signal line 42 both need to be connected to the first drive circuit 10, they can be easily manufactured by being located in the same film layer. Similarly, since the second trigger signal line 51 and the second clock signal line 52 both need to be connected to the second drive circuit 20, they can be easily manufactured by being located in the same film layer.

[0187] Specifically, the first clock signal line 42 may include a first sub-clock signal line 421 and a second sub-clock signal line 422. The first trigger signal line 41, the first sub-clock signal line 421 and the second sub-clock signal line 422 may be located in the same film layer.

[0188] Specifically, the second clock signal line 52 may include a third sub-clock signal line 521 and a fourth sub-clock signal line 522. The second trigger signal line 51, the third sub-clock signal line 521 and the fourth sub-clock signal line 522 may be located in the same film layer.

[0189] As another example, the first trigger signal line 41 and the first clock signal line 42 may be located in different film layers; and / or, the second trigger signal line 51 and the second clock signal line 52 may be located in different film layers. Since the trigger signal line and the clock signal line transmit different signals, usually within the same time, the voltage flip frequency of the clock signal is greater than the voltage flip frequency of the trigger signal. Setting the trigger signal line and the clock signal line in different film layers can reduce interference between the two signal lines.

[0190] Specifically, the first clock signal line 42 may include a first sub-clock signal line 421 and a second sub-clock signal line 422. The first sub-clock signal line 421 and the second sub-clock signal line 422 may be located in the same film layer, or the first sub-clock signal line 421 and the second sub-clock signal line 422 may be located in different film layers. The first trigger signal line 41 and any one of the first sub-clock signal line 421 and the second sub-clock signal line 422 are located in different film layers.

[0191] Specifically, the second clock signal line 52 may include a third sub-clock signal line 521 and a fourth sub-clock signal line 522. The third sub-clock signal line 521 and the fourth sub-clock signal line 522 may be located in the same film layer, or the third sub-clock signal line 521 and the fourth sub-clock signal line 522 may be located in different film layers. The second trigger signal line 51 and any one of the third sub-clock signal line 521 and the fourth sub-clock signal line 522 are located in different film layers.

[0192] In some embodiments, Fig. 27 As shown, the film structure of the display panel may include a stacked substrate 01, a first semiconductor layer b1, a first metal layer M1, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4, adjacent metal layers are insulated from each other, and the metal layers are insulated from the first semiconductor layer b1. As an example, the display panel may be a low temperature polycrystalline oxide (LTPO) type display panel, such as Fig. 27 As shown, the display panel may further include a first semiconductor layer b2. The first semiconductor layer b2 may be located between the second metal layer M2 and the third metal layer M3. The first semiconductor layer b2 and the second metal layer M2 and the third metal layer M3 are insulated from each other.

[0193] When the first trigger signal line 41 and the first clock signal line 42 are located in different film layers, the first trigger signal line 41 can be located in the third metal layer M3, and the first clock signal line 42 can be located in the fourth metal layer M4. The first sub-clock signal line 421 and the second sub-clock signal line 422 can both be located in the fourth metal layer M4.

[0194] When the second trigger signal line 51 and the second clock signal line 52 are located in different film layers, the second trigger signal line 51 can be located in the third metal layer M3, and the second clock signal line 52 can be located in the fourth metal layer M4. The third sub-clock signal line 521 and the fourth sub-clock signal line 522 can both be located in the fourth metal layer M4.

[0195] In other embodiments, Fig.28 As shown, Fig.28 and Fig. 27 The difference is that the film structure of the display panel may further include an auxiliary metal layer M0, the auxiliary metal layer M0 is located between the substrate 01 and the first semiconductor layer b1, and the auxiliary metal layer M0 and the first semiconductor layer b1 are insulated.

[0196] In the case where the first trigger signal line 41 and the first clock signal line 42 are located in different film layers, the first trigger signal line 41 may be located in the third metal layer M3, and the first clock signal line 42 may be located in the fourth metal layer M4 or the auxiliary metal layer M0. For example, both the first sub-clock signal line 421 and the second sub-clock signal line 422 may be located in the fourth metal layer M4. For another example, both the first sub-clock signal line 421 and the second sub-clock signal line 422 may be located in the auxiliary metal layer M0. For another example, one of the first sub-clock signal line 421 and the second sub-clock signal line 422 may be located in the fourth metal layer M4, and the other may be located in the auxiliary metal layer M0.

[0197] In the case where the second trigger signal line 51 and the second clock signal line 52 are located in different film layers, the second trigger signal line 51 may be located in the third metal layer M3, and the second clock signal line 52 may be located in the fourth metal layer M4 or the auxiliary metal layer M0. For example, the third sub-clock signal line 521 and the fourth sub-clock signal line 522 may both be located in the fourth metal layer M4. For another example, the third sub-clock signal line 521 and the fourth sub-clock signal line 522 may both be located in the auxiliary metal layer M0. For another example, one of the third sub-clock signal line 521 and the fourth sub-clock signal line 522 may be located in the fourth metal layer M4, and the other may be located in the auxiliary metal layer M0.

[0198] In some embodiments, the first control signal line 40 and the second control signal line 50 may be located in different film layers. Fig.29 As shown, the orthographic projection of the first control signal line 40 on the light emitting surface of the display panel and the orthographic projection of the second control signal line 50 on the light emitting surface of the display panel can overlap. In this way, it is beneficial to achieve a narrow frame.

[0199] For example, the first trigger signal line 41 and the second trigger signal line 51 may be located in different film layers, and the orthographic projection of the first trigger signal line 41 on the light emitting surface of the display panel may overlap with the orthographic projection of the second trigger signal line 51 on the light emitting surface of the display panel.

[0200] The first sub-clock signal line 421 and the third sub-clock signal line 521 may be located in different film layers, and the orthographic projection of the first sub-clock signal line 421 on the light emitting surface of the display panel may overlap with the orthographic projection of the third sub-clock signal line 521 on the light emitting surface of the display panel.

[0201] The second sub-clock signal line 422 and the fourth sub-clock signal line 522 may be located in different film layers, and the orthographic projection of the second sub-clock signal line 422 on the light emitting surface of the display panel may overlap with the orthographic projection of the fourth sub-clock signal line 522 on the light emitting surface of the display panel.

[0202] like Fig.30As shown, the first driving circuit 10 may be located at one side of the display panel in the row direction X, and the second driving circuit 20 may be located at the other side of the display panel in the row direction X. The multi-stage first shift register VSR of the first driving circuit 10 may be arranged in the column direction Y, and the multi-stage second shift register VSR2 of the second driving circuit 20 may also be arranged in the column direction Y.

[0203] The display panel may further include a first control signal line 40, a second control signal line 50, and a plurality of dummy shift registers Dummy VSR.

[0204] The first control signal line 40 is used to provide a first control signal to the first shift register VSR1. The second control signal line 50 is used to provide a second control signal to the second shift register VSR2.

[0205] Dummy shift registers Dummy VSR are distributed on both sides of the row direction X. Some of the dummy shift registers Dummy VSR are connected to the first control signal line 40 , and some of the dummy shift registers Dummy VSR are connected to the second control signal line 50 .

[0206] In an embodiment of the present application, a virtual shift register is set up and connected to the first control signal line, and part of the virtual shift register is connected to the second control signal line. The virtual shift register and the actual shift register together constitute the load of the first control signal line and the second control signal line. In this way, the load of the first control signal line and the second control signal line can be balanced, and the signal difference caused by different loads can be reduced, which helps to improve the display effect.

[0207] The circuit structure of the dummy shift register Dummy VSR may be the same as that of the first shift register VSR1 and / or the second shift register VSR2. The dummy shift register Dummy VSR is not connected to the pixel circuit Pixel.

[0208] Please continue to refer to Fig.30 The virtual shift register Dummy VSR may include a first virtual shift register DummyVSR1 and a second virtual shift register Dummy VSR2.

[0209] The first control signal line 40 connects i1 first shift registers VSR1 and j1 first dummy shift registers Dummy VSR1, and the second control signal line 50 connects i2 second shift registers VSR2 and j2 second dummy shift registers Dummy VSR2, i1+j1=i2+j2.

[0210] In this way, the first control signal line and the second control signal line have the same load, which further reduces the signal difference caused by different loads, thereby further helping to improve the display effect.

[0211] Specifically, the first control signal line 40 may include a first trigger signal line 41 and a first clock signal line 42. The first clock signal line 42 may include a first sub-clock signal line 421 and a second sub-clock signal line 422. The first sub-clock signal line 421 and the second sub-clock signal line 422 are both connected to each first virtual shift register Dummy VSR1. A plurality of first virtual shift registers Dummy VSR1 are cascaded, and the output end of the last stage of the first shift register VSR1 may be connected to the trigger signal input end of the first stage of the first virtual shift register Dummy VSR1. The first drive circuit 10 may be close to the first display area 101, and a plurality of first virtual shift registers Dummy VSR1 may be close to the second display area 102.

[0212] The second control signal line 50 may include a second trigger signal line 51 and a second clock signal line 52. The second clock signal line 52 may include a third sub-clock signal line 521 and a fourth sub-clock signal line 522. Among them, a plurality of second virtual shift registers Dummy VSR2 are cascaded, and the output end of the last-stage second virtual shift register Dummy VSR2 may be connected to the trigger signal input end of the first-stage second shift register VSR2. The second trigger signal line 51 is connected to the trigger signal input end of the first-stage second virtual shift register Dummy VSR2. The third sub-clock signal line 521 and the fourth sub-clock signal line 522 are both connected to each second virtual shift register Dummy VSR2.

[0213] In some embodiments, Fig.31 As shown, the display panel 100 may further include a third display area 103. A third driving circuit 30 may be provided corresponding to the third display area 103. The third driving circuit 30 includes a multi-stage third shift register VSR3, and the third driving circuit 30 is used to receive a third control signal, and the third driving circuit 30 provides a third driving signal for the pixel circuit Pixel of the third display area 103.

[0214] The first driving circuit 10 may be located on one side of the display panel in the row direction X, the second driving circuit 20 may be located on the other side of the display panel in the row direction X, and the third driving circuit 30 and the second driving circuit 20 are located on the same side of the display panel.

[0215] In the column direction Y, the first display area 101 is located between the second display area 102 and the third display area 103. In the column direction Y, a dummy shift register Dummy VSR may be provided on both sides of the first driving circuit 10, and a dummy shift register Dummy VSR may be provided between the second driving circuit 20 and the third driving circuit 30.

[0216] like Fig.31 As shown, the one above the first driving circuit 10 is called the first sub-virtual shift register Dummy VSR11, and the one below the first driving circuit 10 is called the second sub-virtual shift register Dummy VSR12. Multiple first sub-virtual shift registers Dummy VSR11 are cascaded, and the output end of the last-stage first sub-virtual shift register Dummy VSR11 can be connected to the trigger signal input end of the first-stage first shift register VSR1. Multiple second sub-virtual shift registers Dummy VSR12 are cascaded, and the output end of the last-stage first shift register VSR1 can be connected to the trigger signal input end of the first-stage second sub-virtual shift register Dummy VSR12.

[0217] The first control signal line 40 may include a first trigger signal line 41 and a first clock signal line 42. The first clock signal line 42 may include a first sub-clock signal line 421 and a second sub-clock signal line 422. The first sub-clock signal line 421 and the second sub-clock signal line 422 are both connected to each first sub-virtual shift register Dummy VSR11, and the first sub-clock signal line 421 and the second sub-clock signal line 422 are both connected to each second sub-virtual shift register Dummy VSR12. The first trigger signal line 41 is connected to the trigger signal input terminal of the first-stage first sub-virtual shift register Dummy VSR11.

[0218] The second control signal line 50 may include a second trigger signal line 51 and a second clock signal line 52. The second clock signal line 52 may include a third sub-clock signal line 521 and a fourth sub-clock signal line 522. Each third shift register VSR3 of the third driving circuit 30 may be connected to both the third sub-clock signal line 521 and the fourth sub-clock signal line 522, that is, the third driving circuit 30 and the second driving circuit 20 share a clock signal line.

[0219] The second trigger signal line 51 may be connected to a trigger signal input terminal of the first-stage second shift register VSR2.

[0220] The display panel may further include a third trigger signal line 71 , which is connected to the first-stage third shift register VSR3 and is used to provide a third trigger signal to the third shift register VSR3 .

[0221] A plurality of second virtual shift registers Dummy VSR2 are cascaded, and an output end of the last stage of the third shift register VSR3 can be connected to a trigger signal input end of the second virtual shift register Dummy VSR2.

[0222] Of course, in the case of three display areas, the control signal line and the virtual shift register may also be connected in other ways.

[0223] Based on the same inventive concept, the embodiment of the present application also provides an integrated chip for providing a signal for the display panel provided in the above embodiment. The display panel includes: a first display area and a second display area; a first driving circuit, including a multi-stage first shift register, for receiving a first control signal and providing a first driving signal for a pixel circuit in the first display area; a second driving circuit, including a multi-stage second shift register, for receiving a second control signal and providing a second driving signal for a pixel circuit in the second display area; a pulse change frequency of the first control signal and a pulse change frequency of the second control signal are different; the integrated chip provides at least one of the first control signal and the second control signal.

[0224] It should be noted that, in this embodiment, at least one of the first control signal and the second control signal is provided by an integrated chip, and the features of the first control signal and the second control signal in any of the aforementioned embodiments can all be provided by the integrated chip.

[0225] Based on the same inventive concept, the embodiment of the present application also provides a display device, which includes the display panel provided in the embodiment of the present application. Therefore, the display device has the technical features of the display panel and the driving method thereof provided in the embodiment of the present application, and can achieve the beneficial effects of the display panel provided in the embodiment of the present application. The similarities can be referred to the above description of the display panel provided in the embodiment of the present application, and will not be repeated here.

[0226] For example, Fig.32 A schematic structural diagram of a display device provided according to an embodiment of the present application is shown. Fig.32 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig.32 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Fig.32 The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0227] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: include: a first display area and a second display area; A first driving circuit, comprising a multi-stage first shift register, configured to receive a first control signal and provide a first driving signal for the pixel circuit of the first display area; A second driving circuit, comprising a multi-stage second shift register, configured to receive a second control signal and provide a second driving signal for the pixel circuit of the second display area; The pulse change frequency of the first control signal is different from the pulse change frequency of the second control signal; The first driving circuit is located at one side of the display panel in the row direction, and the second driving circuit is located at the other side of the display panel in the row direction; The display panel further includes: A first control signal line, used for providing the first control signal to the first shift register; A second control signal line, used for providing the second control signal to the second shift register; A plurality of virtual shift registers, wherein the virtual shift registers are distributed on both sides of the row direction, some of the virtual shift registers are connected to the first control signal line, and some of the virtual shift registers are connected to the second control signal line; The virtual shift register includes a first virtual shift register and a second virtual shift register; The first control signal line connects i1 first shift registers and j1 first virtual shift registers, and the second control signal line connects i2 second shift registers and j2 second virtual shift registers, i1+j1=i2+j2.

2. The display panel according to claim 1, characterized in that: The first control signal includes a first trigger signal, the second control signal includes a second trigger signal, and a pulse change frequency of the first trigger signal is different from a pulse change frequency of the second trigger signal.

3. The display panel according to claim 2, characterized in that: The first display area includes pixel circuits from the Mth to the Nth rows, and the second display area includes pixel circuits from the Pth to the Qth rows. The effective data refresh frequency of the pixel circuits from the Mth to the Nth rows is greater than the effective data refresh frequency of the pixel circuits from the Pth to the Qth rows, and the pulse change frequency of the first trigger signal is greater than the pulse change frequency of the second trigger signal.

4. The display panel according to claim 3, characterized in that: The effective data refresh frequency of the pixel circuit in the first display area is K1 times the effective data refresh frequency of the pixel circuit in the second display area, K1>1, and the pulse change frequency of the first trigger signal is K1 times the pulse change frequency of the second trigger signal.

5. The display panel according to claim 3, characterized in that: The effective pulse time length of the first trigger signal is t1, the invalid pulse time length of the first trigger signal is t2, the effective pulse time length of the second trigger signal is t3, the invalid pulse time length of the second trigger signal is t4, t1=t3, 6. The display panel according to claim 5, characterized in that: t4=n*t2+(n-1)*t1, n≥2, and n is an integer.

7. The display panel according to claim 3, characterized in that: The effective pulse time length of the first trigger signal is t1, the invalid pulse time length of the first trigger signal is t2, the effective pulse time length of the second trigger signal is t3, the invalid pulse time length of the second trigger signal is t4, t1<t3, 8. The display panel according to claim 7, characterized in that: The effective data refresh frequency of the pixel circuit in the first display area is K1 times the effective data refresh frequency of the pixel circuit in the second display area, K1>1, 9. The display panel according to claim 2, characterized in that: The first control signal further includes a first clock signal, and the second control signal further includes a second clock signal. The pulse change frequency of the first clock signal is the same as the pulse change frequency of the second clock signal.

10. The display panel according to claim 1, characterized in that: The first control signal further includes a first clock signal, and the second control signal further includes a second clock signal. The pulse change frequency of the first clock signal is different from the pulse change frequency of the second clock signal.

11. The display panel according to claim 10, characterized in that: The first display area includes pixel circuits from the Mth to the Nth rows, and the second display area includes pixel circuits from the Pth to the Qth rows. The effective data refresh frequency of the pixel circuits from the Mth to the Nth rows is greater than the effective data refresh frequency of the pixel circuits from the Pth to the Qth rows, and the pulse change frequency of the first clock signal is greater than the pulse change frequency of the second clock signal.

12. The display panel according to claim 1, characterized in that: The first control signal includes a first trigger signal, the second control signal includes a second trigger signal, and the pulse change frequency of the first trigger signal is greater than the pulse change frequency of the second trigger signal; The first control signal further includes a first clock signal, and the second control signal further includes a second clock signal. The pulse change frequency of the first clock signal is greater than the pulse change frequency of the second clock signal.

13. The display panel according to claim 12, characterized in that: The effective data refresh frequency of the pixel circuit in the first display area is K2 times the effective data refresh frequency of the pixel circuit in the second display area, K2>1; The pulse change frequency of the first trigger signal is K2 times the pulse change frequency of the second trigger signal; The pulse change frequency of the first clock signal is K2 times the pulse change frequency of the second clock signal.

14. The display panel according to claim 13, characterized in that: The effective pulse time length of the first trigger signal is t1, the invalid pulse time length of the first trigger signal is t2, the effective pulse time length of the second trigger signal is t3, and the invalid pulse time length of the second trigger signal is t4. The effective pulse time length of the first clock signal is t5, the invalid pulse time length of the first clock signal is t6, the effective pulse time length of the second clock signal is t7, and the invalid pulse time length of the second clock signal is t8, 15. The display panel according to claim 12, characterized in that: The working process of the pixel circuit in the display panel includes data writing frame and maintaining frame; The pulse change frequency of the first clock signal in the data writing frame is different from the pulse change frequency in the holding frame; And / or, a pulse change frequency of the second clock signal in the data writing frame is different from a pulse change frequency of the second clock signal in the holding frame.

16. The display panel according to claim 15, characterized in that: The pulse change frequency of the first clock signal in the data writing frame is greater than the pulse change frequency of the first clock signal in the holding frame; And / or, the pulse change frequency of the second clock signal in the data writing frame is greater than the pulse change frequency of the second clock signal in the holding frame.

17. The display panel according to claim 12, characterized in that: The working process of the pixel circuit in the display panel includes data writing frame and maintaining frame; In the data writing frame, the pulse changing frequency of the first clock signal is different from the pulse changing frequency of the second clock signal; In the holding frame, the pulse change frequency of the first clock signal is the same as the pulse change frequency of the second clock signal.

18. The display panel according to claim 1, characterized in that: The display panel further includes: The third display area; A third driving circuit, comprising a multi-stage third shift register, configured to receive a third control signal and provide a third driving signal for the pixel circuit of the third display area; The pulse change frequency of the first control signal, the pulse change frequency of the second control signal, and the pulse change frequency of the third control signal are different.

19. The display panel according to claim 1, characterized in that: The display panel further includes: The third display area; A third driving circuit, comprising a multi-stage third shift register, configured to receive a third control signal and provide a third driving signal for the pixel circuit of the third display area; The first control signal includes a first trigger signal and a first clock signal, the second control signal includes a second trigger signal and a second clock signal, and the third control signal includes a third trigger signal and a third clock signal; The pulse change frequency of the first trigger signal, the pulse change frequency of the second trigger signal and the pulse change frequency of the third trigger signal are all different; The pulse changing frequency of the first clock signal is different from the pulse changing frequency of the second clock signal, and the pulse changing frequency of the third clock signal is the same as one of the pulse changing frequency of the first clock signal and the pulse changing frequency of the second clock signal.

20. The display panel according to claim 19, characterized in that: The first display area includes M-th to N-th rows of pixel circuits, and the effective data refresh frequency of the M-th to N-th rows of pixel circuits is F1; The second display area includes pixel circuits in rows P to Q, and the effective data refresh frequency of the pixel circuits in rows P to Q is F2; The third display area includes pixel circuits in the Rth row to the Sth row, and the effective data refresh frequency of the pixel circuits in the Rth row to the Sth row is F3; |F3-F1|<|F3-F2|, the pulse change frequency of the third clock signal is the same as the pulse change frequency of the second clock signal.

21. The display panel according to claim 19, characterized in that: The first display area includes M-th to N-th rows of pixel circuits, and the effective data refresh frequency of the M-th to N-th rows of pixel circuits is F1; The second display area includes pixel circuits in rows P to Q, and the effective data refresh frequency of the pixel circuits in rows P to Q is F2; The third display area includes pixel circuits in the Rth row to the Sth row, and the effective data refresh frequency of the pixel circuits in the Rth row to the Sth row is F3; F1>F2, the pulse change frequency of the first clock signal is greater than the pulse change frequency of the second clock signal, and the pulse change frequency of the third clock signal is equal to the pulse change frequency of the second clock signal.

22. The display panel according to claim 2, characterized in that: The display panel further includes: A first trigger signal line, used for providing the first trigger signal to the first shift register of the first stage; The second trigger signal line is used to provide the second trigger signal to the first stage second shift register.

23. The display panel according to claim 2, characterized in that: The display panel further includes: A first trigger signal line, used for providing the first trigger signal to the first shift register of the first stage; The frequency conversion module is connected between the first shift register and the second shift register, and is used for generating the second trigger signal and providing the second trigger signal to the first-stage second shift register.

24. The display panel according to claim 23, characterized in that: The frequency conversion module comprises: Control terminal; An input terminal connected to the output terminal of the first shift register; The output end is connected to the trigger signal input end of the second shift register.

25. The display panel according to claim 1, characterized in that: The display panel further includes: A first control signal line, used for providing the first control signal to the first driving circuit; A second control signal line, used for providing the second control signal to the second driving circuit; The routing length of the first control signal line is greater than the routing length of the second control signal line, and the routing width of the first control signal line is greater than the routing width of the second control signal line.

26. The display panel according to claim 1, characterized in that: The display panel further includes: A first control signal line, used for providing the first control signal to the first shift register; A second control signal line, used for providing the second control signal to the second shift register; The orthographic projection of the first control signal line on the light emitting surface of the display panel overlaps with the orthographic projection of the first shift register on the light emitting surface of the display panel, and / or the orthographic projection of the second control signal line on the light emitting surface of the display panel overlaps with the orthographic projection of the second shift register on the light emitting surface of the display panel.

27. The display panel according to claim 26, characterized in that: The first control signal line includes a first trigger signal line and a first clock signal line, and the first control signal includes a first trigger signal and a first clock signal; The first trigger signal line and the first clock signal line are located in the same film layer; And / or, the second control signal line includes a second trigger signal line and a second clock signal line, and the second control signal includes a second trigger signal and a second clock signal; The second trigger signal line and the second clock signal line are located in the same film layer.

28. The display panel according to claim 26, characterized in that: The first control signal line includes a first trigger signal line and a first clock signal line, and the first control signal includes a first trigger signal and a first clock signal; The first trigger signal line and the first clock signal line are located in different film layers; And / or, the second control signal line includes a second trigger signal line and a second clock signal line, and the second control signal includes a second trigger signal and a second clock signal; The second trigger signal line and the second clock signal line are located in different film layers.

29. The display panel according to claim 28, characterized in that: The display panel further comprises a stacked substrate, a first semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer, wherein adjacent metal layers are insulated from each other, and the metal layers are insulated from the first semiconductor layer; The first trigger signal line is located at the third metal layer, and the first clock signal line is located at the fourth metal layer; And / or, the second trigger signal line is located in the third metal layer, and the second clock signal line is located in the fourth metal layer.

30. The display panel according to claim 28, characterized in that The display panel further comprises a stacked substrate, an auxiliary metal layer, a first semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer, wherein adjacent metal layers are insulated from each other, and the metal layer is insulated from the first semiconductor layer; The first trigger signal line is located in the third metal layer, and the first clock signal line is located in the fourth metal layer or the auxiliary metal layer; And / or, the second trigger signal line is located in the third metal layer, and the second clock signal line is located in the fourth metal layer or the auxiliary metal layer.

31. The display panel according to claim 1, characterized in that: The display panel further includes: A first control signal line, used for providing the first control signal to the first shift register; A second control signal line, used for providing the second control signal to the second shift register; The first control signal line and the second control signal line are located in different film layers, and the orthographic projection of the first control signal line on the light emitting surface of the display panel overlaps with the orthographic projection of the second control signal line on the light emitting surface of the display panel.

32. The display panel according to claim 1, characterized in that: The display panel further includes: The third display area; A third driving circuit, comprising a multi-stage third shift register, for receiving a third control signal and providing a third driving signal for the pixel circuit of the third display area, wherein the second driving circuit and the third driving circuit are located on the same side of the display panel; In the column direction, the virtual shift registers are arranged on both sides of the first driving circuit, and the virtual shift register is arranged between the second driving circuit and the third driving circuit.

33. An integrated chip, characterized in that: Used to provide a signal for the display panel according to any one of claims 1 to 32, the display panel comprising: a first display area and a second display area; A first driving circuit, comprising a multi-stage first shift register, configured to receive a first control signal and provide a first driving signal for the pixel circuit of the first display area; A second driving circuit, comprising a multi-stage second shift register, configured to receive a second control signal and provide a second driving signal for the pixel circuit of the second display area; The pulse change frequency of the first control signal is different from the pulse change frequency of the second control signal; The integrated chip provides at least one of the first control signal and the second control signal.

34. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 32.

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