A method for operating a memory

Abstract

This invention discloses a memory operation method, which includes the following steps: receiving operation instructions: a write operation and a refresh operation; if the operation instruction is a write state 1 operation, then applying a write state 1 operation voltage to the selected memory cell; if it is a write state 0 operation, then applying a write state 0 operation voltage to the selected memory cell; if it is a refresh operation, then applying a write state 1 operation voltage to the selected memory cell and detecting whether there is current in the selected memory cell; if there is no current, then first applying a write state 0 operation voltage to the selected memory cell, and then applying a write state 1 operation voltage to the selected memory cell; if there is current, then applying a write state 0 operation voltage to the selected memory cell. This invention eliminates the need for a read operation before writing data, effectively shortening the write process and improving write efficiency.

Description

Technical Field

[0001] This invention belongs to the field of memory technology, and more specifically, relates to a method for operating a memory. Background Technology

[0002] In the von Neumann architecture of computers, DRAM (Dynamic Random Access Memory) serves as the main memory, directly exchanging data with the CPU. Currently, the performance requirements for memory, including storage density, are increasingly demanding. However, traditional methods of increasing storage density through miniaturization are insufficient to meet the rapidly growing data processing needs. Developing a third-dimensional architecture to circumvent planar scaling limitations is a mainstream solution. However, because DRAM has a 1T1C structure (one transistor and one memory cell connected in series), it is a three-port device, making three-dimensional stacking difficult. The external control circuitry also consumes significant area, hindering the development of DRAM towards higher storage densities.

[0003] To address the low storage density of DRAM, the academic and industrial communities in the memory field have explored many new types of memory that could potentially replace DRAM. Among them, the Chinese invention patent CN202111280349.1 mentions a memory cell (1S1C memory cell) constructed by connecting an OTS gate transistor and a capacitor in series. This technology rivals DRAM in read, write, and erase speeds and power consumption, making it a promising alternative. However, current read / write / erase schemes for this array, like DRAM, require reading data from the memory cell before writing data, resulting in a longer write process and lower write efficiency. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a memory operation method that eliminates the need for reading operations before writing data, thereby effectively shortening the writing process and improving writing efficiency.

[0005] To achieve the above objectives, the present invention provides a method for operating a memory, the memory comprising word lines and bit lines arranged perpendicularly to each other, and memory cells arranged in an array between the word lines and bit lines, wherein each memory cell includes an OTS select transistor and a capacitor connected in series, the OTS select transistor having a threshold turn-on voltage V. th and holding voltage V hold The operation method includes the following steps:

[0006] (1) Receive operation instructions sent by an external controller in real time. The operation instructions include the location information of the selected storage unit and the operation instruction type information. The operation instruction type information includes write state 1 operation, write state 0 operation and refresh operation. The refresh operation is a refresh instruction sent by the external controller to the memory at regular intervals. The refresh period is T.

[0007] (2) Perform corresponding operations on the selected memory cell according to the operation instruction type information in the operation instruction. If the received operation instruction type information is a write state 1 operation, apply a write state 1 operation voltage for one cycle to the selected memory cell; if the received operation instruction type information is a write state 0 operation, apply a write state 0 operation voltage for one cycle to the selected memory cell; if the received operation instruction type information is a refresh operation, execute step (3).

[0008] (3) Apply a one-cycle write state 1 operating voltage to the selected memory cell and detect whether there is current in the selected memory cell. If there is no current, first apply a one-cycle write state 0 operating voltage to the selected memory cell, and then apply a one-cycle write state 1 operating voltage to the selected memory cell. If there is current, apply a one-cycle write state 0 operating voltage to the selected memory cell.

[0009] The memory operation method provided by this invention does not perform read operations during the write phase. This is because, on the one hand, the 1S1C memory array, which is composed of an OTS gate and a capacitor connected in series, is different from the 1T1C memory array. The gate only turns on when the bit line and word line are simultaneously applied with an operating voltage, unlike DRAM where a row is turned on at the same time. Therefore, it is possible to perform a write operation on only one memory cell. On the other hand, since the 1S1C memory array is refreshed periodically, the read operation can be canceled during the write phase, thereby increasing its write efficiency.

[0010] In one embodiment, the operating voltage for write state 1 is a voltage V applied for one cycle to the bit line where the selected memory cell is located. S Apply a voltage -V for one cycle to the word line containing the selected memory cell. S The operation voltage for writing to state 0 is a voltage of -V applied to the bit line containing the selected memory cell for one cycle. S A voltage V of one cycle is applied to the word line containing the selected memory cell. S .

[0011] In one embodiment, the voltage V S The value can be:

[0012] In one embodiment, the capacitor voltage for state 1, which is valid during the write operation, is 2V. S -V th ~2V S -V hold The capacitor voltage for a valid state of 0 during a write operation is -|2V. S -V hold |~-|2V S -V th |

[0013] In one embodiment, the refresh period T is less than the voltage across the capacitor in the memory cell dropping to the failure voltage of 2V. S -V th The time T used invalid .

[0014] In one embodiment, the refresh operation refreshes an entire row of storage cells at a time during the timed refresh operation, and storage cells in non-adjacent layers are refreshed simultaneously.

[0015] In one embodiment, the memory is a two-dimensional memory or a three-dimensional memory.

[0016] In one embodiment, the location information of the selected storage cell in the operation instruction includes bitwise, row-wise, column-wise, or matrix location information. Attached Figure Description

[0017] Figure 1 This is a flowchart of a memory operation method provided in an embodiment of the present invention;

[0018] Figure 2 This is a diagram showing the voltage change when a 4.4V write-1 voltage is applied to a memory cell in state 0 according to a specific embodiment of the present invention;

[0019] Figure 3 This is a diagram showing the voltage change when a 4.4V write-1 voltage is applied to a memory cell in state 1 according to a specific embodiment of the present invention;

[0020] Figure 4 This is a diagram showing the change in a 4.4V write-to-0 voltage applied to a memory cell in state 1 according to a specific embodiment of the present invention;

[0021] Figure 5 This is a diagram showing the voltage change when a -4.4V write-1 voltage is applied to a memory cell in state 0 according to a specific embodiment of the present invention.

[0022] Figure 6 This is a voltage and current change diagram of a specific embodiment of the present invention when performing a refresh operation on a memory cell in state 0;

[0023] Figure 7This is a voltage and current change diagram of a specific embodiment of the present invention when a refresh operation is performed on a memory cell in state 1. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0025] To improve the write efficiency of memory, this invention provides a memory operation method applicable to two-dimensional or three-dimensional 1S1C memory. Considering that 1S1C memory does not turn on all the selectors of an entire row during operation, this invention designs an operation scheme that can directly write data based on the characteristics of the storage cells in 1S1C memory, without the need for a read operation before writing, thus shortening the operation process of writing and improving writing efficiency.

[0026] The 1S1C memory includes word lines and bit lines arranged perpendicularly to each other, and memory cells arranged in an array between the word lines and bit lines. The memory cells include OTS gates and capacitors connected in series.

[0027] like Figure 1 As shown, the memory operation method provided by the present invention includes steps S10 to S30, which are detailed below:

[0028] S10 receives operation instructions from an external controller in real time. The operation instructions include the location information of the selected storage unit and the operation instruction type information.

[0029] The operation instruction type information includes write status 1 operation, write status 0 operation, and refresh operation. The refresh operation is a refresh instruction issued by the external controller to the memory at regular intervals, with a refresh period of T. The location information of the selected memory cell specifically refers to the location information of the word line and bit line where the selected memory cell is located. It can be used to select memory cells in the memory by bit, row, column, or matrix.

[0030] S20: Perform corresponding operations on the selected memory cell according to the operation instruction type information in the operation instruction. If the received operation instruction type information is a write state 1 operation, apply a write state 1 operation voltage for one cycle directly to the selected memory cell. If the received operation instruction type information is a write state 0 operation, apply a write state 0 operation voltage for one cycle directly to the selected memory cell. If the received operation instruction type information is a refresh operation, execute step S30.

[0031] Specifically, in this embodiment, the operation voltage for writing state 1 is a voltage V applied to the bit line where the selected memory cell is located for one cycle.S Apply a voltage -V for one cycle to the word line containing the selected memory cell. S The operation voltage for write state 0 is a voltage of -V applied to the bit line containing the selected memory cell for one cycle. S A voltage V of one cycle is applied to the word line containing the selected memory cell. S .

[0032] S30: Apply a one-cycle write state 1 operating voltage to the selected memory cell and detect whether there is current in the selected memory cell. If there is no current, first apply a one-cycle write state 0 operating voltage to the selected memory cell, and then apply a one-cycle write state 1 operating voltage to the selected memory cell. If there is current, apply a one-cycle write state 0 operating voltage to the selected memory cell.

[0033] In step S30, if the received operation instruction type information is a refresh operation, then in the first operation cycle, a write state 1 operation is performed on the selected memory cell, and it is detected whether current is generated on the selected memory cell at this time; in the second operation cycle, a write state 0 operation is performed on the selected memory cell; in the third operation cycle, if the selected memory cell has current in the first operation cycle, it means that the selected memory cell is initially in state 0, and no operation is performed in the third operation cycle; if the selected memory cell has no current in the first operation cycle, it means that the selected memory cell is initially in state 1, and a write state 1 operation is performed in the third operation cycle.

[0034] This embodiment provides a memory operation method. Existing 1S1C array operation methods employ a write method similar to traditional DRAM, where a read operation is performed before writing. For example, after receiving an operation command, a read operation is performed on the memory cell to put it in state 0. If the received operation command is for writing state 1, a write 1 operation is performed; if the received command is for writing state 0, a write state 1 operation is performed first, followed by a write state 0 operation. The purpose of reading before writing in traditional methods is to refresh the memory cell during each write operation, keeping its storage voltage high. This embodiment uses a method that does not perform a read operation during the write phase. This is because, firstly, unlike 1T1C memory arrays, 1S1C memory arrays only turn on the selector when both the bit line and word line are simultaneously applied with an operation voltage, unlike DRAM where a row is turned on simultaneously. Therefore, only one memory cell can be written to at a time. Secondly, since 1S1C memory arrays are refreshed periodically, the read operation can be eliminated during the write phase, increasing its write efficiency.

[0035] In one embodiment, during write and refresh operations, it must be ensured that the applied operating voltage is sufficient to turn on the OTS selector of the selected memory cell, but not on the OTS selector of the unselected memory cell. In an unselected memory cell, the voltage across the OTS selector is at most equal to the storage voltage across the storage capacitor, and since one end of the memory cell has an operating voltage while the other does not, V... S V C The following requirements should be met:

[0036] 2V S >V th

[0037] V S +V C <V th

[0038] V C =2V S -V hold

[0039] Obtain the operating voltage V S The conditions that must be met are:

[0040]

[0041] Among them, V th V is the threshold turn-on voltage of the OTS selector. hold This is the holding voltage for the OTS selector.

[0042] In one embodiment, due to leakage in the storage capacitor, a certain window period is required for the storage voltage in different states. During a write operation, the capacitor voltage in the effective state 1 is 2V. S -V th ~2V S -V hold The capacitor voltage in state 0 is -|2V S -V hold |~-|2V S -V th |

[0043] Simultaneously, the refresh period T in the refresh operation should satisfy T. <T invalid The voltage across the storage capacitor drops to the failure voltage of 2V due to capacitor leakage. S -V th The time used is the failure time T. invalid Furthermore, when performing a timed refresh operation, an entire row of storage cells can be refreshed at once, and storage cells in non-adjacent layers can be refreshed simultaneously.

[0044] The following detailed description is provided in conjunction with specific embodiments:

[0045] A 1S1C memory, wherein the threshold voltage V of the selected OTS gate transistor is... th 4V, holding voltage V hold The applied operating voltage is 3V. S The storage voltage is 2.2V. C It is 1.4V.

[0046] The capacitor voltage in state 1 is 0V to 1.4V; the capacitor voltage in state 0 is -1.4V to 0V.

[0047] If the received instruction is a write state 1 operation, then the memory cell bit line end ( Figure 2 Chinese number 21 and Figure 3 (Number 31) Apply V S =2.2V voltage, for the word line terminal of the memory cell ( Figure 2 Chinese number 22 and Figure 3 (Number 32) Apply -V S = -2.2V voltage. If the initial state of the memory cell is state 0, then as Figure 2 As shown, the OTS selector is turned on, which sets the capacitor voltage ( Figure 2 (Subject No. 23) Charge to 1.4V; if the initial state of the memory cell is state 1, then as follows Figure 3 As shown, the OTS gate will not turn on, and the capacitor voltage ( Figure 3 (Number 33) Keep the original state.

[0048] If the received instruction is a write operation in state 0, then the memory cell bit line end ( Figure 4 Chinese number 41 and Figure 5 (51) Apply -V S = -2.2V voltage, for the word line terminal of the memory cell ( Figure 4 Chinese number 42 and Figure 5 (Issue No. 52) Apply V S =2.2V voltage. If the initial state of the memory cell is state 1, then as follows Figure 4 As shown, the OTS selector is turned on, which sets the capacitor voltage ( Figure 4 (Subject No. 43) Charge to -1.4V; if the initial state of the memory cell is state 0, then as follows Figure 5 As shown, the OTS gate will not turn on, and the capacitor voltage ( Figure 5 (Number 53) Keep the original state.

[0049] If the received instruction is a refresh operation, different initial states correspond to different refresh operation schemes. For example... Figure 6 As shown, if the initial state is 1, then the first operation cycle will be performed on the bit line terminal of the memory cell ( Figure 6 (Issue No. 61) Apply VS =2.2V voltage, for word line terminals ( Figure 6 (Category 62) Apply -V S = -2.2V; At this time, the OTS selector will not be turned on, so no current will be generated on the memory cell; In the second cycle, a -2.2V voltage is applied to the bit line and a 2.2V voltage is applied to the word line. At this time, the OTS selector of the memory cell is turned on, and the memory cell is charged negatively and changes to state 0; Since there is no current on the memory cell in the first cycle, a 2.2V voltage is applied to the bit line and a -2.2V voltage is applied to the word line in the third cycle. At this time, the OTS selector of the memory cell is turned on, the storage capacitor is charged positively and changes to state 1, and the refresh operation ends and the refresh is completed.

[0050] like Figure 7 As shown, if the initial state is 0, then the first operation cycle will be performed on the bit line of the memory cell ( Figure 7 (Issue No. 71) Apply V S =2.2V voltage, for word line terminals ( Figure 7 (Category 72) Apply -V S = -2.2V; At this time, the OTS selector is turned on, so there is current in the memory cell; In the second cycle, a -2.2V voltage is applied to the bit line terminal and a 2.2V voltage is applied to the word line terminal. At this time, the OTS selector of the memory cell is turned on, and the memory cell is charged negatively and changes to state 0; Since there is current in the memory cell in the first cycle, no operating voltage is applied in the third cycle, the memory voltage is kept in state 0, and the refresh operation ends and the refresh is completed.

[0051] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for operating a memory, characterized in that, The memory includes word lines and bit lines arranged perpendicularly to each other, and memory cells arranged in an array between the word lines and bit lines. Each memory cell includes an OTS selector and a capacitor connected in series. The OTS selector has a threshold turn-on voltage. V th and holding voltage V hold The operation method includes the following steps: (1) Receive operation instructions sent by an external controller in real time. The operation instructions include the location information of the selected storage unit and the operation instruction type information. The operation instruction type information includes write state 1 operation, write state 0 operation and refresh operation. The refresh operation is a refresh instruction sent by the external controller to the memory at regular intervals. The refresh period is T. (2) Perform corresponding operations on the selected memory cell according to the operation instruction type information in the operation instruction. If the received operation instruction type information is write state 1 operation, apply a write state 1 operation voltage for one cycle to the selected memory cell. If the received operation instruction type information is a write state 0 operation, then apply a write state 0 operation voltage for one cycle to the selected memory cell; if the received operation instruction type information is a refresh operation, then execute step (3). (3) Apply a one-cycle write state 1 operating voltage to the selected memory cell and detect whether there is current in the selected memory cell. If there is no current, first apply a one-cycle write state 0 operating voltage to the selected memory cell, and then apply a one-cycle write state 1 operating voltage to the selected memory cell. If current is present, an operating voltage for one cycle of write state 0 is applied to the selected memory cell.

2. The method for operating the memory according to claim 1, characterized in that, The operation voltage for write state 1 is a voltage applied for one cycle to the bit line containing the selected memory cell. V S A voltage of one cycle is applied to the word line containing the selected memory cell. -V S The operation voltage for write state 0 is a voltage applied for one cycle to the bit line containing the selected memory cell. -V S A voltage of one cycle is applied to the word line containing the selected memory cell. V S .

3. The method for operating the memory according to claim 2, characterized in that, Voltage V S The value can be: .

4. The method for operating the memory according to claim 3, characterized in that, The capacitor voltage in valid state 1 during a write operation is 2V. S -V th ~2V S -V hold The capacitor voltage for a valid state of 0 during a write operation is -|2V. S -V hold |~ - |2V S -V th | 5. The method for operating the memory according to claim 3, characterized in that, The refresh cycle T is less than the voltage drop across the capacitor in the memory cell to the failure voltage of 2V. S -V th The time T used invalid .

6. The method for operating the memory according to claim 1, characterized in that, When performing a timed refresh operation, the refresh operation refreshes an entire row of storage cells at a time, and storage cells in non-adjacent layers are refreshed simultaneously.

7. The method for operating the memory according to claim 1, characterized in that, The memory is a two-dimensional memory or a three-dimensional memory.

8. The method of operating the memory according to claim 1, characterized in that, The location information of the selected storage cell in the operation instruction includes bitwise, row-wise, column-wise, or matrix location information.

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