An SGT device and method of manufacturing the same

Abstract

The application discloses an SGT device and a manufacturing method thereof, and the method comprises the following steps: providing a semiconductor substrate, a trench is formed in the semiconductor substrate, an inner surface of the trench is covered with a first dielectric layer, and a shield gate is formed in the trench; etching back the first dielectric layer to expose the top of the shield gate and the semiconductor substrate of the trench sidewall; depositing a dielectric material layer covering the top of the shield gate, the top of the first dielectric layer and the trench sidewall; etching back the dielectric material layer, and the remaining dielectric material of the top of the shield gate is used as a second dielectric layer. According to the SGT device and the manufacturing method thereof provided by the application, the IPO is formed by depositing a dielectric material layer covering the top of the shield gate and the trench sidewall in the trench, the diffusion of the doping ions of the shield gate can be avoided, the thickness uniformity of the gate dielectric layer (GOX) is improved, the consistency of the threshold voltage (Vth) is improved, meanwhile, the thickness of the formed IPO is ensured, and the risk of the increase of the gate leakage current (IGSS) or the failure of the device is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a SGT device and a manufacturing method thereof. BACKGROUND

[0002] Power MOSFET devices with shield gate trench (SGT) can achieve low on-resistance (Rdson) and low reverse recovery capacitance (Crss) at the same time, thereby reducing the on-loss and switching loss of the system at the same time and improving the efficiency of the system.

[0003] The gate structure of the SGT device includes a shield gate (also known as source polysilicon or shield polysilicon) and a control gate (also known as polysilicon gate), both of which are formed in a trench. According to the different settings of the shield gate and the control gate in the trench, it is usually divided into up-down structure and left-right structure. In the up-down structure, the shield gate is located at the bottom of the trench, the control gate is located at the top of the trench, the shield gate and the control gate are in an up-down structure relationship, and the inter-poly oxide (IPO) is located between the shield gate and the control gate.

[0004] In the one-step forming SGT device IPO layer forming process, after etching back the liner oxide, the trench sidewall and the top of the shield gate are exposed. During the formation of the gate oxide (GOX), the doping ions (for example, phosphorus ions) in the shield gate are easy to diffuse to the trench sidewall, causing pollution to the trench sidewall, resulting in poor GOX thickness uniformity and poor threshold voltage (Vth) consistency. In addition, the one-step forming SGT device IPO layer is formed by thermal oxidation of the shield gate, and the thickness of the IPO layer is mainly determined by the ion doping concentration of the shield gate and the oxidation temperature. High doping concentration is easy to cause filling problem, and ion diffusion may also cause gate leakage current (IGSS) to rise or device failure and other problems.

[0005] Therefore, it is necessary to propose a new SGT device and a manufacturing method thereof to solve the above technical problems. SUMMARY

[0006] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to try to limit the key features and necessary technical features of the claimed technical solution, nor to try to determine the protection scope of the claimed technical solution.

[0007] The present application provides a manufacturing method of a SGT device, comprising the following steps:

[0008] A semiconductor substrate is provided, the semiconductor substrate having a trench formed therein, an inner surface of the trench being covered with a first dielectric layer, a shield gate being formed in the trench;

[0009] The first dielectric layer is etched back to expose a top of the shield gate and a semiconductor substrate of the trench sidewall;

[0010] A dielectric material layer is deposited to cover the top of the shield gate, the top of the first dielectric layer, and the trench sidewall;

[0011] The dielectric material layer is etched back, the dielectric material remaining on the top of the shield gate as a second dielectric layer.

[0012] Further, depositing the dielectric material layer to cover the top of the shield gate, the top of the first dielectric layer, and the trench sidewall includes:

[0013] Performing a first chemical vapor deposition to form a first dielectric material layer having a first thickness on the top of the shield gate, the top of the first dielectric layer, and the trench sidewall;

[0014] Performing a second chemical vapor deposition to form a second dielectric material layer on the top of the shield gate, the top of the first dielectric layer, and the trench sidewall, wherein the second dielectric material layer on the top of the shield gate has a second thickness, and the second dielectric material layer on the trench sidewall has a third thickness.

[0015] Further, the first chemical vapor deposition includes sub-atmospheric chemical vapor deposition, and the second chemical vapor deposition includes high-density plasma chemical vapor deposition.

[0016] Further, after forming the second dielectric layer, further comprising a step of forming a third dielectric layer covering the trench sidewall.

[0017] Further, forming the third dielectric layer covering the trench sidewall includes:

[0018] Etching back the dielectric material layer until the semiconductor substrate of the trench sidewall is exposed;

[0019] Oxidizing the exposed semiconductor substrate of the trench sidewall to form the third dielectric layer covering the trench sidewall.

[0020] Further, forming the third dielectric layer covering the trench sidewall includes etching back the dielectric material layer, the dielectric material remaining on the trench sidewall as the third dielectric layer.

[0021] Further, the second dielectric layer has a thickness greater than a thickness of the third dielectric layer.

[0022] Further, the first thickness is in a range of The second thickness is in a range of The third thickness is in a range of

[0023] Further, the second dielectric layer has a thickness in a range of

[0024] The present application also provides an SGT device, comprising:

[0025] A semiconductor substrate, wherein a trench is formed in the semiconductor substrate, and a shield gate is formed in the trench;

[0026] A first dielectric layer is formed between the shield gate and the semiconductor substrate, a second dielectric layer is formed on top of the shield gate, and a third dielectric layer is formed on the trench sidewall above the second dielectric layer.

[0027] Further, the second dielectric layer has a thickness greater than that of the third dielectric layer.

[0028] According to the SGT device and the manufacturing method thereof provided by the present application, by depositing a dielectric material layer covering the top of the shield gate and the trench sidewall in the trench to form an interpoly oxide layer (IPO), the diffusion of the doped ions of the shield gate can be avoided, the thickness uniformity of the gate dielectric layer (GOX) can be improved, and the consistency of the threshold voltage (Vth) can be improved, while ensuring the thickness of the formed interpoly oxide layer (IPO) and reducing the risk of rising gate leakage current (IGSS) or device failure. BRIEF DESCRIPTION OF DRAWINGS

[0029] The following drawings of the present application are hereby incorporated as part of the present application for the purpose of understanding the present application. The embodiments of the present application and the description thereof shown in the drawings are used to explain the principles of the present application.

[0030] In the drawings:

[0031] Figure 1 A process flow chart of the SGT device manufacturing method according to an embodiment of the present application;

[0032] Figures 2A-2F A structural schematic diagram of the device obtained by the related steps of the SGT device manufacturing method according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art upon

[0034] It should be understood that the present application can be practiced with the elements in different order, and that none is necessary before another in order for the application to be practiced. Furthermore, some of the features of the present application can be used to advantage without the corresponding use of other features. As such, the foregoing description should be considered as merely illustrative of the principles of the present application, and not in limitation thereof. For the sake of brevity and clarity, detailed descriptions of functions integral to the art will not be described in more detail, such as the detailed construction of integrated circuit chips, logic elements that perform various computing functions, or the software processes that execute on computer or networked systems.

[0035] It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Pronouns in the masculine form include the feminine form, and vice versa, except as otherwise expressly specifically herein. It is further understood that the terms "comprise" and "comprising" and the like are to be construed with a open ended non-limiting intent, indicating the described features can be augmented with further features in various embodiments of the application. Likewise it is to be understood that the terms "coupled" and "coupling" and the like should not be construed with an exclusive or restrictive sense, and can include, in various embodiments of the application, both indirect and direct coupling, association, or the like.

[0036] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface over which the implantation was performed. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application.

[0039] For a thorough understanding of the present application, reference should be made to the following detailed description together with the accompanying drawings, in which:

[0040] In a one-step SGT device inter-gate oxide (IPO) formation process, after etching back the liner oxide, the trench sidewall and the top of the shield gate are exposed. During the gate oxide (GOX) formation, the dopant ions (e.g. phosphorus ions) in the shield gate can easily diffuse to the trench sidewall, causing contamination to the trench sidewall, resulting in poor GOX thickness uniformity and poor threshold voltage (Vth) consistency. In addition, the one-step SGT device IPO layer is formed by thermal oxidation of the shield gate. The thickness of the IPO layer is mainly determined by the ion doping concentration of the shield gate and the oxidation temperature. Too high doping concentration can easily cause filling problems. Ion diffusion can also cause gate leakage current (IGSS) to increase or device failure, etc.

[0041] To solve the above problems, the present application provides a manufacturing method of an SGT device, as shown in Figure 1 The method mainly comprises the following steps:

[0042] Step S101: providing a semiconductor substrate in which a trench is formed, an inner surface of the trench is covered with a first dielectric layer, and a shield gate is formed in the trench;

[0043] Step S102: etching back the first dielectric layer to expose a top of the shield gate and a semiconductor substrate of the trench sidewall;

[0044] Step S103: depositing a dielectric material layer covering the top of the shield gate, the top of the first dielectric layer and the trench sidewall;

[0045] Step S104: etching back the dielectric material layer, the remaining dielectric material of the top of the shield gate as a second dielectric layer.

[0046] Hereinafter, the manufacturing method of the SGT device of the present application will be described in detail with reference to the accompanying drawings. In the drawings, Figures 2A to 2F Fig. 1 shows a schematic diagram of the structure of a device obtained from the relevant steps of the manufacturing method of the SGT device according to an embodiment of the present application.

[0047] Firstly, step S101 is performed, as shown in Fig. 1, a semiconductor substrate 200 is provided, in which a trench is formed, an inner surface of the trench is covered with a first dielectric layer 201, and a shield gate 202 is formed in the trench. Figure 2A

[0048] Exemplarily, the semiconductor substrate 200 can be any suitable semiconductor material known to those skilled in the art, such as germanium or silicon or a combination thereof, etc. The semiconductor substrate 200 has a first conductivity type, such as N-type or P-type, which is reasonably selected according to the type of the device to be prepared in practice. In the present embodiment, the conductivity type of the semiconductor substrate 200 is N-type.

[0049] In an embodiment, the semiconductor substrate 200 can be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked silicon (SSOI), silicon-on-insulator stacked germanium silicon (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), etc. As an example, in the present embodiment, the constituent material of the semiconductor substrate 200 is selected to be monocrystalline silicon.

[0050] Exemplarily, the material of the first dielectric layer 201 can use any suitable insulating material, and optionally, the material of the first dielectric layer 201 can include one or more of SiO2, SiCN, SiN, SiC, SiOF, SiON. The first dielectric layer 201 can be formed using a chemical vapor deposition method, an atomic layer deposition method, or a physical vapor deposition method, etc. ​

[0051] In one embodiment, the first dielectric layer 201 is a liner oxide. The material of the first dielectric layer 201 includes an oxide, such as silicon oxide. In this embodiment, the first dielectric layer 201 is silicon oxide, which can be formed by thermal oxidation of the surface of the semiconductor substrate 200.

[0052] Exemplarily, the shield gate 202 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the material of the metal gate can be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi). In this embodiment, the material of the shield gate 202 includes polysilicon (Poly).

[0053] Exemplarily, the shield gate 202 can be formed by any prior art known to those skilled in the art, preferably by chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), and plasma enhanced chemical vapor deposition (PECVD).

[0054] Then, step S102 is performed, as shown in FIG. 2B, the first dielectric layer 201 is etched back to expose the top of the shield gate 202 and the semiconductor substrate of the trench sidewall. Figure 2B

[0055] Exemplarily, the etching back of the first dielectric layer 201 can be performed by dry etching or wet etching, and can use a single etching method or more than one etching method. In this embodiment, the wet etching process is used to etch back the first dielectric layer 201 until the top of the shield gate 202 and the semiconductor substrate of the trench sidewall are exposed. In one embodiment, the wet etching method can use a hydrofluoric acid solution, such as buffered oxide etchant (BOE) or buffered hydrofluoric acid solution (BHF).

[0056] It should be noted that due to the isotropic etching characteristics of wet etching, when the first dielectric layer 201 is etched back, it will not only etch in the direction perpendicular to the trench sidewall, but also etch in the direction parallel to the trench sidewall, resulting in the top surface of the etched first dielectric layer 201 being lower than the top surface of the shield gate 202, as shown in FIG. 2C. Figure 2B

[0057] Next, step S103 is performed, as shown in FIG. 2D, the second dielectric layer 202 is formed on the exposed top surface of the first dielectric layer 201 and the top of the shield gate 202. Figure 2C 2D ​​​A dielectric material layer is formed to cover the top of the shield gate, the top of the first dielectric layer and the sidewall of the trench.

[0058] Exemplarily, the step of forming the dielectric material layer to cover the top of the shield gate, the top of the first dielectric layer and the sidewall of the trench comprises the following steps:

[0059] performing a first chemical vapor deposition to form a first dielectric material layer 2031 having a first thickness on the top of the shield gate, the top of the first dielectric layer and the sidewall of the trench;

[0060] performing a second chemical vapor deposition to form a second dielectric material layer 2032 on the top of the shield gate, the top of the first dielectric layer and the sidewall of the trench, wherein the second dielectric material layer on the top of the shield gate has a second thickness, and the second dielectric material layer on the sidewall of the trench has a third thickness.

[0061] Exemplarily, the first chemical vapor deposition comprises sub-atmospheric chemical vapor deposition (SACVD). SACVD process refers to a chemical vapor deposition reaction in which the pressure in the chamber is 500 torr to 600 torr when the reaction gas is deposited. The sub-atmospheric chemical vapor deposition process has better step coverage and trench filling capability, and its reaction process is a pure chemical reaction without plasma damage.

[0062] In one embodiment, when chemical vapor deposition is performed using the SACVD process, the power is 200 W to 400 W, the temperature in the chamber is heated to 300 °C to 400 °C, the pressure in the chamber is 500 mTorr to 600 mTorr, the gas flow of O2 is 2000 to 6000 cubic centimeters per minute (sccm / slm), the gas flow of N2 is 4000 to 8000 cubic centimeters per minute (sccm), and the deposition time lasts for 80 to 100 s.

[0063] Referring to Figure 2C By the above steps, the first dielectric material layer 2031 having a first thickness is formed on the top of the shield gate, the top of the first dielectric layer and the sidewall of the trench, and the first thickness is in the range of

[0064] By first forming the first dielectric material layer 2031 having a first thickness on the top of the shield gate, the top of the first dielectric layer and the sidewall of the trench, the doped ions (e.g., phosphorus ions) in the shield gate are prevented from diffusing to the sidewall of the trench, the contamination to the sidewall of the trench is avoided, the GOX thickness uniformity is improved, and the threshold voltage (Vth) consistency is improved.

[0065] Exemplarily, the second chemical vapor deposition includes high density plasma chemical vapor deposition (HDP-CVD). HDP-CVD is a kind of chemical vapor deposition equipment using inductively coupled plasma source. In order to avoid the pinch-off and voids in the middle of the gap when filling the gap with high aspect ratio, HDP-CVD synchronously performs deposition and etching processes in the same reaction chamber, while meeting the filling and cost control of high aspect ratio gap, and improving the trench or hole filling capacity.

[0066] In one embodiment, when chemical vapor deposition is performed by using HDP-CVD process, the power is 200W-400W, the temperature in the cavity is heated to 600-700℃, the pressure in the cavity is 800mTorr-1Torr, the gas flow of SiH4 is 100-140sccm, the gas flow of O2 is 260-300sccm, and the deposition time lasts for 60-90s.

[0067] Referring to Figure 2D By the above steps, a second dielectric material layer 2032 is formed on the top of the shield gate, the top of the first dielectric layer and the sidewall of the trench, wherein the second dielectric material layer on the top of the shield gate has a second thickness, the second dielectric material layer on the sidewall of the trench has a third thickness, the second thickness is in the range of The third thickness is in the range of

[0068] Next, step S104 is performed, as shown in Figure 2E The dielectric material layer is etched back, and the remaining dielectric material on the top of the shield gate serves as a second dielectric layer 203.

[0069] Exemplarily, the dielectric material layer can be etched back by dry etching or wet etching, and a single etching method or more than one etching method can be used. In this embodiment, the dielectric material layer is etched back by wet etching process. In one embodiment, the wet etching method can use hydrofluoric acid solution, such as buffered oxide etchant (BOE) or hydrofluoric acid buffered solution (BHF).

[0070] In one embodiment, the second dielectric layer 203 is an interpoly oxide layer (IPO). The material of the second dielectric layer 203 includes oxide, such as silicon oxide. The thickness of the second dielectric layer 203 is in the range of

[0071] As shown in Figure 2FAs shown, after forming the second dielectric layer 203, a step of forming a third dielectric layer 204 covering the trench sidewall is further included.

[0072] In one embodiment, when etching back the dielectric material layer, the dielectric material remaining on top of the shield gate is etched back until it reaches a predetermined thickness as the second dielectric layer 203, while the dielectric material on the trench sidewall reaches a predetermined thickness as the third dielectric layer 204. Here, the thickness of the second dielectric layer 203 is greater than the thickness of the third dielectric layer 204.

[0073] In one embodiment, in step S104, the dielectric material layer is etched back until the trench sidewall exposes the semiconductor substrate, the dielectric material remaining on top of the shield gate as the second dielectric layer 203, and then the exposed semiconductor substrate of the trench sidewall is oxidized to form the third dielectric layer 204 covering the trench sidewall.

[0074] In one embodiment, the exposed semiconductor substrate of the trench sidewall is oxidized by a thermal oxidation process, which includes dry oxygen oxidation or wet oxygen oxidation.

[0075] In one embodiment, the third dielectric layer 204 is a gate oxide layer (GOX). The material of the third dielectric layer 204 includes an oxide, such as silicon oxide. The thickness of the third dielectric layer 204 ranges from 1 nm to 10 nm.

[0076] So far, the key steps of the manufacturing method of the SGT device of the present application have been introduced. Other processes may be required for the complete device preparation, such as the step of forming a control gate, which will not be described here.

[0077] The present application further provides an SGT device, such as Figure 2F As shown, comprising:

[0078] a semiconductor substrate 200, in which a trench is formed, and in the trench, a shield gate 202 is formed;

[0079] a first dielectric layer 201 is formed between the shield gate 202 and the semiconductor substrate 200, a second dielectric layer 203 is formed on top of the shield gate 202, and a third dielectric layer 204 is formed on the trench sidewall above the second dielectric layer 203;

[0080] The thickness of the second dielectric layer 203 is greater than the thickness of the third dielectric layer 204.

[0081] By way of example, the semiconductor substrate 200 can be any suitable semiconductor material known to those skilled in the art, such as germanium or silicon or a combination thereof, etc. The semiconductor substrate 200 has a first conductivity type, such as N-type or P-type, which is reasonably selected according to the type of device to be fabricated, in the present embodiment, the semiconductor substrate 200 has an N-type conductivity.

[0082] In one embodiment, the semiconductor substrate 200 can be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked silicon (SSOI), silicon-on-insulator stacked germanium silicon (S-SiGeOI), silicon-on-insulator germanium silicon (SiGeOI), and germanium-on-insulator (GeOI), etc. By way of example, in the present embodiment, the semiconductor substrate 200 is made of single crystal silicon.

[0083] By way of example, the shield gate 202 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the material of the metal gate can be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi). In the present embodiment, the material of the shield gate 202 includes polysilicon (Poly).

[0084] By way of example, the material of the first dielectric layer 201, the second dielectric layer 203, and the third dielectric layer 204 can use any suitable insulating material, including but not limited to one or more of SiO2, SiCN, SiN, SiC, SiOF, SiON.

[0085] In one embodiment, the first dielectric layer 201 is a liner oxide, the second dielectric layer 203 is an inter-poly oxide (IPO), and the third dielectric layer 204 is a gate oxide (GOX). The material of the first dielectric layer 201, the second dielectric layer 203, and the third dielectric layer 204 includes an oxide, such as silicon oxide.

[0086] By way of example, the thickness of the second dielectric layer 203 is greater than the thickness of the third dielectric layer 204. In the present embodiment, the thickness of the second dielectric layer 203 ranges from 5 nm to 20 nm. The thickness of the third dielectric layer 204 ranges from 1 nm to 5 nm.

[0087] According to the SGT device and the manufacturing method thereof, the gate inter-oxide layer (IPO) is formed by depositing a dielectric material layer covering the top of the shield gate and the sidewall of the trench, so that the diffusion of the doped ions of the shield gate is avoided, the thickness uniformity of the gate dielectric layer (GOX) is improved, the consistency of the threshold voltage (Vth) is improved, the thickness of the formed gate inter-oxide layer (IPO) is ensured, and the risk of the increase of the gate leakage current (IGSS) or the failure of the device is reduced.

[0088] The present application has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of example and illustration, and are not intended to limit the present application to the scope of the described embodiments. Furthermore, those skilled in the art can understand that the present application is not limited to the above-mentioned embodiments, and more various modifications and changes can be made according to the teachings of the present application, which all fall within the scope of the present application. The scope of protection of the present application is defined by the attached claims and their equivalent scope.

Claims

1. A method for manufacturing an SGT device, characterized in that, Includes the following steps: A semiconductor substrate is provided, wherein a trench is formed therein, the inner surface of the trench is covered with a first dielectric layer, and a shielding gate is formed therein; The first dielectric layer is etched back to expose the top of the shielding gate and the semiconductor substrate of the trench sidewalls; A dielectric material layer is deposited to cover the top of the shielding gate, the top of the first dielectric layer, and the sidewalls of the trench; The dielectric material layer is etched back, and the remaining dielectric material on top of the shielding gate serves as a second dielectric layer; The deposition of a dielectric material layer covering the top of the shielding gate, the top of the first dielectric layer, and the sidewalls of the trench includes: Perform a first chemical vapor deposition to form a first dielectric material layer having a first thickness on top of the shielding gate, on top of the first dielectric layer, and on the trench sidewalls; A second chemical vapor deposition is performed to form a second dielectric material layer on top of the shielding gate, on top of the first dielectric layer, and on the trench sidewall, wherein the second dielectric material layer on top of the shielding gate has a second thickness, and the second dielectric material layer on the trench sidewall has a third thickness.

2. The method as described in claim 1, characterized in that, The first chemical vapor deposition includes sub-atmospheric pressure chemical vapor deposition, and the second chemical vapor deposition includes high-density plasma chemical vapor deposition.

3. The method as described in claim 1, characterized in that, After forming the second dielectric layer, the method further includes the step of forming a third dielectric layer covering the trench sidewalls.

4. The method as described in claim 3, characterized in that, Forming a third dielectric layer covering the sidewalls of the trench includes: Etch back the dielectric material layer until the semiconductor substrate with the trench sidewalls exposed; The semiconductor substrate with exposed trench sidewalls is oxidized to form a third dielectric layer covering the trench sidewalls.

5. The method as described in claim 3, characterized in that, Forming a third dielectric layer covering the sidewalls of the trench includes: The dielectric material layer is etched back, and the remaining dielectric material on the trench sidewall serves as a third dielectric layer.

6. The method as described in claim 3, characterized in that, The thickness of the second dielectric layer is greater than the thickness of the third dielectric layer.

7. The method as described in claim 1, characterized in that, The range of the first thickness is The range of the second thickness is The range of the third thickness is:

8. An SGT device, characterized in that, The SGT device is manufactured by the manufacturing method according to any one of claims 1-7, and the SGT device comprises: A semiconductor substrate, wherein trenches are formed in the semiconductor substrate and shielding gates are formed in the trenches; A first dielectric layer is formed between the shielding gate and the semiconductor substrate, a second dielectric layer is formed on top of the shielding gate, and a third dielectric layer is formed on the trench sidewall above the second dielectric layer.

Images