Method and apparatus for performing frequency domain equalization with low complexity and cyclic delay

Abstract

The present invention describes a method and apparatus for performing frequency domain equalization with low complexity and cyclic delay. The transmitter inserts pilot symbols into the data signal at intervals of every n data bits. The receiver side frequency domain equalizer uses these pilot symbols to calculate the error level and equalize the received data signal to affect impairment compensation, for example, SOP tracking. QPSK or BPSK symbols can be used for the pilot symbols, simplifying the error calculation to an addition operation instead of the traditional multiplication operation required by traditional FDEQ. The present invention describes an equalizer that can operate in pilot-assisted mode, traditional decision-oriented mode, or both modes.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to a previously filed U.S. non-provisional application having application number 16 / 936,098, filed on July 22, 2020, and entitled “METHOD AND APPARATUS FOR FREQUENCYDOMAIN EQUALIZATION WITH LOW COMPLEXITY AND LOOP DELAY,” the contents of which are incorporated herein by reference in jurisdictions that allow such incorporation. Technical Field

[0003] The present invention relates to a method and apparatus for signal equalization, and more particularly to a method and apparatus for performing frequency domain equalization with low complexity and cyclic delay. Background Art

[0004] Signals transmitted through wireless, wired or optical channels are subject to various linear and nonlinear impairments. To compensate for these linear and nonlinear impairments, various coherent receivers are used to perform coherent detection while performing digital signal processing.

[0005] Digital signal processing can include fixed and adaptive equalization to compensate for linear impairments. Adaptive equalizers can mainly compensate for time-varying adaptive impairments such as polarization mode dispersion (PMD), state of polarization (SOP) tracking, and polarization decomposition multiplexing, residual chromatic dispersion (CD), and inter-symbol interference (ISI) mitigation. Adaptive equalizers typically implement a butterfly configuration, which is often referred to as 2×2 multiple input multiple output (MIMO). Equalization can be performed in both the time domain and the frequency domain. However, time domain equalization can account for a large portion of the overall digital signal processing complexity, especially in implementations with a large number of equalizer taps. One technical solution to reduce complexity is to use a frequency-domain equalizer (FDEQ) to implement a block-by-block update strategy and efficiently implement discrete Fourier transform (DFT) operations.

[0006] However, in some applications, the complexity required by FDEQ can even be a major issue. In addition, FDEQ may include a carrier recovery path in its equalization loop and may require a large number of error calculations, both of which may introduce significant delays in the equalization loop, resulting in slower or less effective equalization.

[0007] Therefore, there is a need for frequency domain equalization that overcomes one or more limitations of the prior art. Summary of the invention

[0008] In various embodiments described herein, methods and apparatus are disclosed for providing frequency domain equalization with low complexity and cyclic delay for fast SOP tracking. Various embodiments may include a transmitter for inserting pilot symbols into a data signal at the transmitter at intervals of every n data bits: the pilot symbol is inserted after every n-1 data symbols, so that a data block of N symbols contains N-k data symbols and k pilot symbols, where N=nk. In some embodiments, the receiver-side frequency domain equalizer uses these pilot symbols to calculate error levels and equalize the received data signal for impairment compensation. Since the error calculation is performed only on k symbols out of every N symbols, the calculation speed is significantly faster and the equalization cycle delay may be significantly reduced. In addition, by using pilot symbols to calculate the error level, the equalizer can eliminate the need to include a carrier recovery path in the equalization cycle, further reducing the cycle delay. Cycle delays spanning multiple equalization cycles may impair the SOP tracking ability of the equalizer; in some cases involving rapid changes, the cycle delay must be relatively short to effectively track the SOP. Some embodiments use quadrature-phase shift keying (QPSK) or bit-phase shift keying (BPSK) symbols for the pilot symbols, simplifying the error calculation to an addition operation instead of the traditional multiplication operation required by the traditional FDEQ. Therefore, the SOP tracking capability can be improved by reducing the complexity and loop delay of the equalizer.

[0009] The claims refer to various signal values ​​and the use of X, W, E pilot , E, N, n, k, m, p, Δφ, etc. These references are not limited to the specific values ​​described in the specification in conjunction with the specific embodiments, but are intended to clarify the scope of the claims in conjunction with other claim elements and to simplify the expression of equations and formulas in the claims.

[0010] As used herein, the term "update" or "updating" may refer to any process in which a signal value is replaced by a new or different signal value. In some cases, such an update may be performed by perturbing, offsetting, modulating, incrementing or otherwise modifying an existing signal value to achieve a new or updated signal value. In other cases, such an update may be performed by replacing an existing signal value or setting a new or updated signal value. Specifically, the equalizer described herein is described as updating an equalizer tap value. An equalizer tap may be any position or component of a circuit or device at which a signal may be tapped and provided as an input to another component. The signal present at the equalizer tap may be regarded as an equalized signal for equalizing a data signal received by the equalizer to compensate for damage. The value of the equalizer signal at the equalizer tap may be "updated", for example, by replacing the current value with a new value calculated based on an error data block, as described herein. The equalizer tap in turn may "update" a data signal to an equalized version of the data signal, for example, by multiplying the data signal by an equalized signal (i.e., one or more tap values) using a signal multiplier to generate an equalized version of the data signal. Thus, in some cases, "updating" may refer to replacement, while in other cases it may refer to generating a new signal from a previous signal.

[0011] As used herein, the statement that an element is "for" a particular purpose may mean that the element performs a particular function or is used to perform one or more particular steps or operations, as described herein.

[0012] As used herein, a statement that a second signal or value is "based on" a first signal or value may mean that a characteristic of the second signal or value is at least partially affected or determined by a characteristic of the first signal or value. The first signal or value may be considered as an input to an operation or calculation or a series of operations or calculations that produces the second signal or value as an output related to the first signal or value.

[0013] In some aspects, the present invention describes an apparatus. The apparatus includes: a coherent receiver for receiving an optical signal and generating an electrical signal based on the optical signal. The electrical signal includes: a plurality of pilot symbols and a plurality of data symbols. The apparatus also includes: a frequency-domain adaptive equalizer (FDEQ) for receiving a digital signal based on the electrical signal. The FDEQ includes: an equalization path including one or more equalizer taps for generating an equalizer based on a pilot error signal E pilotThe digital signal is equalized in the frequency domain using one or more tap values ​​W, thereby generating an equalized digital signal. The FDEQ also includes: a pilot error tap update path, which is used to: calculate a phase angle Δφ based on the angle between one or more predetermined pilot symbols of the equalized digital signal and one or more received pilot symbols, and generate the pilot error signal E pilot According to the pilot error update interval, according to the pilot error signal E pilot The device further comprises: a decision error tap update path, comprising a carrier recovery path for generating a phase compensation decision signal according to the equalized digital signal, wherein the decision error tap update path is used to: generate a decision error signal E according to a difference between the equalized digital signal and the phase compensation decision signal; and update the equalizer tap according to the decision error signal E according to a decision error update interval. The pilot error update interval is shorter than the decision error update interval. The tap value W is also based on the decision error signal E.

[0014] According to another aspect, the present invention provides a method. The method comprises: receiving a digital signal including a plurality of pilot symbols and a plurality of data symbols; using one or more equalizer taps, according to a pilot error signal E pilot The digital signal is equalized in the frequency domain using one or more tap values ​​W, thereby generating an equalized digital signal; a phase angle Δφ is calculated based on the angle between one or more predetermined pilot symbols of the equalized digital signal and one or more received pilot symbols, thereby generating the pilot error signal E pilot According to the pilot error update interval, according to the pilot error signal E pilot Update the equalizer taps; generate a phase compensation decision signal based on the equalized digital signal; generate a decision error signal E based on the difference between the equalized digital signal and the phase compensation decision signal; update the equalizer taps according to the decision error signal E based on a decision error update interval, wherein the pilot error update interval is shorter than the decision error update interval, and the tap value W is also based on the decision error signal E.

[0015] In some examples, the method further includes: receiving an optical signal at a coherent receiver, wherein the optical signal includes a plurality of pilot symbols and a plurality of data symbols; and generating a digital signal based on the optical signal.

[0016] In some examples, the apparatus is configured to selectively activate and deactivate the decision error tap update path.

[0017] In some examples, the apparatus is configured to selectively activate and deactivate the pilot error tap update path.

[0018] In some examples, the device is used to: deactivate the decision error tap update path after the equalizer is locked.

[0019] In some examples, the device is also used to: when the pilot error tap update path is deactivated, use the decision error tap update path to update the equalizer taps until the equalizer is locked; after the equalizer is locked, activate the pilot error tap update path.

[0020] In some examples, the method further includes: updating the equalizer tap according to the decision error signal E until the equalizer is locked; after the equalizer is locked, updating the equalizer tap according to the pilot error signal E pilot The equalizer taps are updated.

[0021] In some examples, the method further includes: according to the decision error signal E and the pilot error signal E pilot Update the equalizer tap until the equalizer is locked; after the equalizer is locked, according to the pilot error signal E pilot The equalizer taps are updated.

[0022] In some examples, the equalizer further comprises: a conjugate path for generating a conjugate signal X* of the digital signal in the frequency domain X. The pilot error tap update path is used to update the equalizer tap in the pilot error time interval p by: generating a gradient signal by multiplying the following two: the pilot error signal E in the previous pilot time interval (p–1) pilot , the conjugate signal X* in the previous pilot time interval (p–1); applying a gradient constraint G{.} to the gradient signal to generate a constrained gradient signal; multiplying the constrained gradient signal by the pilot error step size μ pilot twice to generate a step scaling signal; adding the step scaling signal to the equalizer tap value W(p–1) of the previous pilot time interval (p–1) stored by one or more delay units to generate one or more updated tap values ​​WW(p); updating the equalizer tap with the updated tap value W(p) in the pilot error time interval p, so that W(p)=W(p–1)+2μ pilot G{E pilot (p–1)X(p–1)*}.

[0023] In some examples, the equalizer also includes: a conjugate path for generating a conjugate signal X* of the digital signal in the frequency domain X. The decision error tap update path is used to update the equalizer tap in a decision error time interval m in the following manner: generating a decision error gradient signal by multiplying the following two: the decision error signal E in the previous decision time interval (m–1), the conjugate signal X* in the previous decision time interval (m–1); applying a gradient constraint G{.} to the decision error gradient signal to generate a constrained decision error gradient signal; multiplying the constrained decision error gradient signal by twice the decision error step size μ to generate a decision error step scaling signal. The pilot error tap update path is used to update the equalizer tap in a pilot error time interval p in the following manner: generating a pilot error gradient signal by multiplying the following two: the pilot error signal E in the previous pilot time interval (p–1) pilot , the conjugate signal X* in the previous pilot time interval (p–1); applying a gradient constraint G{.} to the pilot error gradient signal to generate a constrained pilot error gradient signal; multiplying the constrained pilot error gradient signal by the pilot error step size μ pilot twice to generate a pilot error step scaling signal; adding the pilot error step scaling signal and the decision error step scaling signal to the equalizer tap value W(p–1) of the previous pilot time interval (p–1) stored by one or more delay units to generate one or more updated tap values ​​W(p); updating the equalizer tap with the updated tap value W(p) in the pilot error time interval p, so that W(p)=W(p–1)+2μ pilot G{E pilot (p–1)X(p–1)*}+2μG{E(m–1)X(m–1)*}.

[0024] In some examples, the pilot symbol of the optical signal is a quadrature phase shift keying (QPSK) symbol or a binary phase shift keying (BPSK) symbol; and the calculating of the phase angle Δφ includes an addition operation.

[0025] In some examples, the pilot error tap update path generates the pilot error signal E by performing the following steps: pilot:The pilot error tap update path receives a data block of N symbols of the equalized digital signal, wherein the N symbols include k received pilot symbols distributed between every (n–1) data symbols at regular intervals, wherein kn=N; for each of the k pilot symbols, the phase angle Δφ is calculated as the sum of the angles between a predetermined pilot symbol and a corresponding received pilot symbol of the data block, wherein N=kn. The pilot error tap update path generates an error block of k symbols, wherein each symbol is the difference between: one of the k predetermined pilot symbols adjusted by the phase angle Δφ, and one of the corresponding k received pilot symbols. The pilot error tap update path concatenates the error block with a zero block of k zero-valued symbols. The pilot error tap update path applies Fourier transform to transform the cascaded error block and the zero block to the frequency domain to generate a frequency domain block of 2k symbols; the pilot error tap update path replicates the frequency domain block n times to generate the error signal E of 2N symbols. pilot of blocks.

[0026] According to another aspect, the present invention provides a device. The device includes: a coherent transmitter for transmitting an optical signal including a plurality of pilot symbols and a plurality of data symbols, so that for each data block in N symbols of the optical signal, the N symbols include k pilot symbols distributed at regular intervals between every (n-1) data symbols, where kn=N. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Reference will now be made by way of example to the accompanying drawings which show exemplary embodiments of the present application, in which:

[0028] FIG. 1 (Prior Art) is a high-level block diagram of a conventional coherent system showing a more detailed block diagram of a receiver digital signal processor (DSP) including an adaptive equalizer;

[0029] FIG. 2 (Prior Art) is a block diagram of a conventional frequency-domain equalizer (FDEQ) including a carrier recovery path;

[0030] Figure 3 A block diagram of a pilot-assisted FDEQ is provided for the examples described herein;

[0031] Figure 4 A schematic diagram of a digital signal frame including pilot symbols provided for examples described herein;

[0032] Figure 5 For calculation Figure 3 The pilot error signal E of the pilot-aided FDEQpilot A flowchart of an exemplary method of;

[0033] Figure 6 A block diagram of a hybrid FDEQ with a pilot error tap update path and a decision error update path provided for examples described herein;

[0034] Figure 7 A flow chart of an exemplary method for providing frequency domain equalization to a digital signal provided for the examples described herein;

[0035] Figure 8 Based on Figure 6 A flowchart of an exemplary method for updating equalizer taps in a decision-directed mode according to a decision error signal E of FDEQ;

[0036] Fig. 9 Based on Figure 3 or Figure 6 The FDEQ is used according to the pilot error signal E pilot A flow chart of an exemplary method of updating equalizer taps in pilot-assisted mode;

[0037] Fig.10 Based on Figure 6 The FDEQ is used to determine the error signal E and the pilot error signal E. pilot Flowchart of an exemplary method of updating equalizer taps in hybrid mode.

[0038] Like reference numerals are used in different drawings to denote like components. DETAILED DESCRIPTION

[0039] In the examples disclosed herein, methods and apparatus for providing frequency domain equalization with low complexity and cyclic delay are described. Pilot symbols are inserted into the data signal of the transmitter at intervals of every n data bits: a pilot symbol is inserted after every n-1 data bits, so that a data block of N bits contains N-k data bits and k pilot symbols, where N=nk. Each pilot symbol has a predetermined characteristic, for example, a predetermined phase rotation. Used in the context of pilot symbols, the term "predetermined" shall mean that the transmitter and the receiver share a mutual representation of the pilot symbol characteristics before the transmitter generates and transmits a signal including the pilot symbol to the receiver. The receiver-side frequency domain equalizer uses these pilot symbols to calculate error levels and equalize the received data signal to affect impairment compensation, for example, state of polarization (SOP) tracking. The predetermined characteristics of the pilot symbol are compared with the characteristics of the received pilot symbol to determine the phase distortion introduced in the transmission, including frequency offset and phase noise. The error is then obtained by calculating the difference between the predetermined pilot symbol and the received pilot symbol after rotating the phase angle by the same amount. Since the error calculation is performed only on k bits out of every N bits, the calculation speed is significantly faster and the equalization cycle delay can be significantly reduced. In addition, by using pilot symbols to calculate the error level, the equalizer can eliminate the need to include a carrier recovery path in the equalization cycle, further reducing the cycle delay. If the pilot symbols are quadrature-phase shift keying (QPSK) or bit-phase shift keying (BPSK) symbols, the error calculation can be simplified to an addition operation instead of the traditional multiplication operation required by traditional FDEQ.

[0040] FIG. 1 (PRIOR ART) is a high-level block diagram of a conventional coherent system 1, showing a more detailed block diagram of a receiver digital signal processor (DSP) including an adaptive equalizer. As shown, the coherent system 1 includes a transmitter 2, which includes a transmitter DSP 18, a digital to analog converter (DAC) 16, a driver 14, an in-phase quadrature modulator (IQM) 12, and a first laser 10. The coherent system 1 also includes an optical link (such as an optical fiber link) 6 and a receiver 4. The receiver 4 includes a coherent receiver (e.g., an integrated coherent receiver (ICR)) 20, a second laser 22, an analog to digital converter (ADC) 24, and a receiver DSP 26. It should be understood that for the purpose of operability and simplicity, other elements may be present, but are not shown.

[0041] The transmitter DSP 18 is used to receive the digital signal and perform up-sampling and pre-compensation on the received digital signal. The DAC 16 is used to convert the up-sampled and pre-compensated digital signal into an analog signal. The analog signal is amplified by the driver 14. Then, the amplified analog signal is modulated to the output of the first laser 10 by the IQM 12 to convert the amplified analog signal into an optical signal having an X polarization channel and a Y polarization channel.

[0042] The X polarization channel and the Y polarization channel of the optical signal are transmitted through the optical fiber link 6. It should be understood that the conventional coherent system 1 is used to transmit optical signals, but in other conventional coherent systems, analog signals can be transmitted as radio frequency signals in a wireless medium. The transmitted signal, whether optical or radio frequency, will be subject to various linear and nonlinear impairments.

[0043] The X polarization channel and the Y polarization channel of the optical signal are detected by the ICR 20 using a local oscillator including a second laser 22. In doing so, the ICR 20 converts the optical signal into an X polarization electrical signal channel and a Y polarization electrical signal channel. The ADC 24 is used to convert the X polarization electrical signal channel and the Y polarization electrical signal channel into an X polarization digital signal channel and a Y polarization digital signal channel. Then, the X polarization digital signal channel and the Y polarization digital signal channel are forwarded to the receiver DSP 26 for various digital signal processing operations, including damage compensation such as SOP compensation.

[0044] Receiver DSP 26 also includes resampling block 30, frame synchronization block 32, adaptive equalizer 100, carrier recovery module 124, demapping module 34, and error calculator 36. It should be understood that other elements may be present but are not shown for purposes of operability and simplicity.

[0045] The adaptive equalizer 100 is used to compensate for time-varying adaptive impairments, such as polarization mode dispersion (PMD), polarization decomposition multiplexing, state of polarization (SOP) tracking, residual chromatic dispersion (CD), and mitigation of inter-symbol interference. The carrier recovery module 124 is used to provide frequency offset compensation to the time-varying adaptive impairment compensation digital signal channel in X polarization and Y polarization. The carrier recovery module 124 is also used to recover the phase of the carrier signal from the time-varying adaptive impairment compensation digital signal. The demapping module 34 is used to convert the X polarization digital signal channel and the Y polarization digital signal channel of the carrier recovery into bits, and the error calculator 36 is used to calculate the bit error rate (BER) in the bit. In some configurations, the carrier recovery module 124 can be integrated with the adaptive equalizer 100 to provide carrier signal information to assist the operation of the adaptive equalizer 100, as described in more detail below with reference to Figure 2.

[0046] FIG. 2 (Prior Art) is a block diagram of a conventional adaptive equalizer 100 as a decision-directed frequency-domain equalizer (FDEQ), the equalizer including a carrier recovery path of an integrated carrier recovery module 124. The equalizer 100 will be described as a polarization multiplexing equalizer for equalizing input signals having an X polarization channel and a Y polarization channel, or a single polarization equalizer for equalizing a single polarization input signal. It should be understood that most operations of the polarization multiplexing FDEQ involve repeating the same steps for two polarization components, even if not explicitly described as doing so; however, updating the equalization taps may involve more complex interactions between the two polarization components. In addition, different polarization components of the data signal (e.g., an X polarization component or a Y polarization component) can be referred to as "channels", regardless of whether they coexist in a common transmission medium or in separate physical transmission channels.

[0047] A conventional FDEQ such as the adaptive equalizer 100 is described by John N. Shink in "Frequency Domain and Multirate Adaptive Filtering," IEEE SP Magazine, January 1992, pp. 14-37, which is incorporated herein by reference in its entirety.

[0048] The equalizer 100 receives a digital data signal 102 as an input, for example, from the frame synchronization block 32 of the receiver DSP 26. The digital data signal 102 is a time domain digital signal at the equalizer input stage.

[0049] The concatenation module 104 is used to concatenate (time domain) data samples (i.e., symbols) of the digital data signal 102. If polarization multiplexing is used, the concatenation module 104 concatenates symbols in the X polarization channel and the Y polarization channel. For example, the concatenation module 104 concatenates the mth block of the most recent N data samples of X polarization with the previous block (i.e., the (m–1)th block) of the N data samples of X polarization of the digital data signal 102. Similarly, the concatenation module 104 concatenates the mth block of the most recent N data samples of Y polarization with the previous block of the N data samples of Y polarization of the digital data signal 102. Therefore, the total length of the mth block of the digital data signal 102 is 2N; if polarization multiplexing is used, the length of each channel in the X polarization channel and the Y polarization channel of the digital data signal 102 is 2N.

[0050] The fast Fourier transform (FFT) module 108 performs a discrete 2N-point fast Fourier transform operation to transform a block of data samples of the (time domain) digital data signal 102 into the frequency domain. The symbol block can now be represented as a data signal X(m) 110 in a single polarization equalizer, or as data channels X(m) and Y(m) in a polarization multiplexing equalizer. As used herein, m is used as an index to distinguish sequential blocks of data signals. Each block of the data signal is equalized by the equalizer tap using a new, updated set of tap values. Therefore, the time period between data block m and data block m+1 determines the throughput of the equalizer. This time period can also be called a "tap update interval" because the taps are updated between each equalization of the data block. Therefore, at each index m indicating a single tap update interval, a new data block is equalized by the equalizer 100: the data signal block X(m-1) is equalized during the time interval index (m-1), then the data signal block X(m) is equalized during the time interval index m, and so on. The tap update interval of the decision-directed FDEQ 100 may be referred to herein as a decision error-based tap update time interval, or simply a "decision error tap update interval," and refers to the time interval between a block of equalized data signals and the time required to update the taps 162 by the equalization operation of the decision-directed equalizer 100. As used herein, the tap value W(m) 160 refers to a tap value calculated based on the data signal X(m–1) 110. As described above, the tap value 160 may represent an equalized signal for equalizing a data signal (e.g., the digital data signal 102). The tap value 160 may be represented by the symbol W, and the tap value 160 at a particular time interval may be represented by W(m), W(p), etc. The use of the symbol W is arbitrary and does not indicate the use of any particular mathematical function, such as the Lambert W function; the calculation of the tap value W 160 is described in detail herein.

[0051] The loop delay of the equalizer 100 introduces delay into the tap update process. The tap update path of the equalizer 100 may require a long time to update the tap value 160; this loop delay may correspond to any number of update intervals, such as 10 or 20 update intervals. Thus, when the tap 162 is updated with the tap value 160 based on the equalized data block (m–1), the tap 162 may apply the updated tap value W(m) 160 to the data block (m+10) or (m+20). This longer time interval may be variously referred to herein as “loop delay,” “equalizer delay,” or “tap update delay.” The decision-directed FDEQ 100 is typically configured such that the decision error tap update interval corresponds to a fixed portion of the loop delay, such that a fixed number of data blocks are equalized during each cycle of the tap update delay. The number of data blocks equalized within a single cycle of the tap update delay may be represented by L, such that the tap value W(m) 160 is used to equalize the data block (m+L).

[0052] The multiplier 112 multiplies a set of equalized tap values ​​W(m+L) 160 of the equalizer taps 162 by the mth block of the (frequency domain) data signal X(m) 110 to generate an equalized signal 114. The taps 162 may be 2×2 MIMO taps as described above. The equalizer tap values ​​W(m) 160 are used to compensate for time-varying adaptive impairments such as SOP tracking. If polarization multiplexing is used, the equalized tap values ​​W(m) 160 may include four different components W xx (m), W yx (m), W xy (m) and W yy (m). The calculation of the tap value W(m) 160 is performed by various components of the tap update path of the equalizer 100, as described below. Typically, the number of taps 162 of the FDEQ 100 is equal to the number of symbols in the block of digital data signal 102 to be equalized by the multiplier 112 in one multiplication, i.e., 2N equalizer taps 162 in this example.

[0053] To generate the equalized (frequency domain) digital data signal 114, the multiplier 112 updates X110 to X=X·W. If polarization multiplexing is used, then X=X·W xx +Y·W yx And Y = X·W xy +Y·W yy The equalized digital data signal 114 is provided to an inverse fast Fourier transform (IFFT) module 116, which performs a discrete 2N-point inverse fast Fourier transform to convert the equalized digital data signal 114 to the time domain. The save last block module 120 discards the first N symbols of the data block (corresponding to the m-1th block) to generate the mth data block 123 of the N symbols of the equalized digital data signal 114 in the time domain, also referred to as the equalized data block 123. If polarization multiplexing is used, N symbols are discarded from each channel block in the X channel block and the Y channel block.

[0054] The carrier recovery module 124 performs frequency offset compensation and phase noise mitigation on the equalized data block 123, using a slicer 130 to generate a phase compensated decision signal 132. An adder 134 subtracts the output of the save last block module 120 from the phase compensated decision signal 132 (representing the desired response) to generate a time domain error signal 136. It should be understood that the length of the time domain error signal is N. The N-symbol block of the equalized digital data signal in the time domain passes through the carrier recovery block 124 as the carrier recovery output signal 126.

[0055] The time domain error signal 136 is provided to insert a zero block 138. The zero block 138 is used to add a block of N zero bits to the time domain error signal 136 to generate a time domain error signal block of length 2N. The second FFT module 142 performs a discrete 2N point fast Fourier transform to convert the 2N symbol time domain error signal block into the frequency domain, thereby generating an error signal E(m) 144. If polarization multiplexing is used, both the X channel and the Y channel are added with a block of N zero bits, and each channel is converted to the frequency domain. E(m) 144 represents the channel E of the X polarization channel and the Y polarization channel, respectively. x (m) and E y The error signal E(m) 144 is provided to a second multiplier 146 .

[0056] The conjugation module 164 receives the digital data signal block X(m) 110 in the frequency domain and generates a conjugated signal X(m)*162, which is the complex conjugate of the digital data signal X(m) 110. The conjugated signal X(m)*162 is provided to the second multiplier 146. As used herein, a conjugated version of a signal (e.g., signal X(m)) may be represented as X*(m) or X(m)*. An asterisk (*) following a signal signifier (e.g., X or X(m)) shall indicate a conjugated version of such a signal.

[0057] The second multiplier 146 multiplies the conjugate signal X(m)*162 and the error signal E(m)144 to generate a gradient signal 148. The gradient signal 148 is provided to a gradient constraint unit 150, which is used to apply a gradient constraint G{.} to the gradient signal 148. Typically, the gradient constraint unit 150 performs an IFFT on the received data samples of length 2N, deletes the last N samples of the time-domain received data samples, adds a block of N zero bits, and performs a 2N-point FFT on the gradient constraint G{.} to generate a constrained gradient signal 152.

[0058] The constrained gradient signal 152 is multiplied by a third multiplier 153 by twice the step size μ 154 to generate a step scale signal 156. The step scale signal 156 is then added to the previous set of tap values ​​W, i.e., W(m–1), stored in the delay unit 158 ​​by a second adder 159. The output of the second adder 159 is an updated tap value W(m) 160. The delay unit 158 ​​is shown in FIG. 2 as a single-interval delay unit; the delay unit 158 ​​provides a previous value of the equalization tap 162 for updating the current value W(m) 160 of the equalization tap 162 using the tap value W of the previous decision error update interval (m–1), denoted as W(m–1). Typically, the number of delay units 158 (i.e., 2N delay units 158 in this example) of a conventional FDEQ 100 is equal to the number of equalizer taps 162. The time delay of each delay unit 158 ​​is the update interval of the equalizer 100, i.e., the decision error tap update interval in this example.

[0059] Thus, the exemplary conventional decision-directed equalizer 100 can be characterized as including two paths for equalizing the digital data signal 102. The first path is an equalization path that constitutes the cascade module 104, the FFT module 108, the 2×2 MIMO equalizer taps 162, the multiplier 112, the IFFT module 116, and the save last block module 120. Thus, the equalization path takes the (time domain) digital signal 102 as input and generates an equalized (time domain) digital signal 123 as output. The second path is a tap update path for updating the value 160 of the tap 162, referred to in this example as a decision error tap update path (because the tap is updated using a decision-directed error calculation process). The decision error tap update path receives the equalized data block 123 as one of its inputs and generates an updated tap value 160 as output. The decision error tap update path includes components for updating the equalizer tap value W160, such as an adder 134, a zero insertion block 138, an FFT 142, a second multiplier 146, a gradient constraint unit 150, a third multiplier 153, a second adder 159, and a delay unit 158. The equalizer also has a carrier recovery path through a carrier recovery module 124 and a slicer 130, and a conjugate path through a conjugate module 164. However, since the decision error tap update path relies on the outputs of both paths and incorporates their outputs into its calculations before updating the tap 162, the carrier recovery path and the conjugate path can be considered part of the decision error tap update path. Therefore, it will be understood that the term "path" does not refer to a single linear data propagation path, but can include all operations required to generate a path output based on an input to the path, including operations arranged in parallel or operations that receive additional inputs (e.g., a pre-equalization digital signal block 110 received as a conjugate path input). It will also be understood that the tap update path, so long as it includes a conjugate path and a carrier recovery path, receives as inputs the equalized data block 123 (input to the right side of the carrier recovery path and the tap update path) and the pre-equalized digital data signal block X(m) 110 (input to the conjugate path).

[0060] Therefore, between each decision error tap update interval, the decision error tap update path updates the values ​​of the MIMO equalizer taps according to the following equation:

[0061] W(m)=W(m–1)+2μG{E(m–1)X(m–1)*} (1)

[0062] Or, if polarization multiplexed:

[0063] W xx (m) = W xx (m–1)+2μG{E x (m–1)X(m–1)*} (2)

[0064] W yx (m) = W yx (m–1)+2μG{E x (m–1)Y(m–1)*} (3)

[0065] W xy (m) = W xy (m–1)+2μG{E y (m–1)X(m–1)*} (4)

[0066] W yy (m) = W yy (m–1)+2μG{E y (m–1)Y(m–1)*} (5)

[0067] In operation, before the first round of equalization (m=1), the gradient constraint unit 144 may set the initial tap value 160 of the MIMO equalization tap 162 to W=all one-valued bits [111 . . . 1] in the polarization multiplexing configuration, or W xx =W yy = all one-valued bits [111...1] and W xy =Wy X =all one-valued bits [000...0].

[0068] Now refer to Figures 3 to 10 Describing exemplary embodiments of the present disclosure, some embodiments may significantly reduce the delay introduced by the decision error tap update path and / or the carrier recovery path of the conventional FDEQ 100 while presenting a low complexity pilot-assisted FDEQ for impairment compensation such as tracking SOP.

[0069] Figure 3 1 is a block diagram of a pilot-assisted FDEQ 300 used as an adaptive equalizer by a receiver DSP such as DSP 26. As described above, pilot-assisted FDEQ 300 performs equalization on a data signal including pilot symbols inserted between every (n-1) data symbols by a transmitter. Thus, pilot-assisted FDEQ 300 is used by a receiver 4, a coherent receiver (e.g., ICR 20) of which receives an optical signal (e.g., via optical link 6) including a plurality of pilot symbols and a plurality of data symbols, and the coherent receiver generates an electrical signal based on the optical signal. ADC 24 generates a digital signal 302 based on the electrical signal, such that digital signal 302 also includes a plurality of pilot symbols and a plurality of data symbols.

[0070] The pilot-assisted FDEQ 300 includes an equalization path substantially similar to the conventional FDEQ 100. The digital signal 302 has two blocks cascaded and is converted into the frequency domain to generate a frequency domain data block 310 of size 2N. The equalizer tap 352 is used to multiply the tap value 350 by the frequency domain data block 310 using the multiplier 112 to generate a (frequency domain) equalized signal 314, which is converted back to the time domain and the first N symbol blocks are removed to generate the equalizer output signal 123. As with the conventional FDEQ 100, these operations are performed on each of the X polarization channel and the Y polarization channel of the digital signal 302 for a polarization multiplexing configuration.

[0071] The tap update path of pilot-assisted FDEQ 300 (referred to as a pilot error tap update path because it updates tap values ​​350 based on errors based on pilot symbols) also includes a conjugation path substantially similar to conventional FDEQ 100 , constituting conjugation module 164 .

[0072] However, the tap update path of the pilot-assisted FDEQ 300 is significantly different from the tap update path of the conventional FDEQ 100, and the delay and / or complexity of damage compensation such as SOP tracking can be significantly reduced. The pilot-assisted FDEQ 300 has a pilot error tap update path that calculates errors based only on k pilot symbols, rather than the decision-oriented error calculation of the decision error tap update path of the conventional FDEQ 100 that calculates errors based on N data symbols. Calculating errors based on pilot symbols also reduces the complexity of the components required for the tap update path. Therefore, due to the reduction in the time required to perform pilot-based errors rather than decision-oriented errors, in some embodiments, the pilot error tap update delay (i.e., cyclic delay) can be significantly shorter than the decision error tap update delay. In addition, in some embodiments, the pilot error tap update interval can be different from the decision error tap update interval (e.g., shorter). Therefore, the pilot error tap update interval may be represented as the time period between the pth data block and the (p+1)th data block, using the index p of the pilot-assisted FDEQ 300 instead of the index m used by the conventional FDEQ 100 to represent different tap update intervals.

[0073] The pilot error tap update path of the pilot-assisted FDEQ 300 includes a frequency domain error calculation module 330 for calculating the error based on the N symbol blocks of the equalizer output signal 123. Figure 5 The method 500 shown in detail describes the operation of the frequency domain error calculation module 330. The frequency domain error calculation module 330 generates a pilot error signal E pilot 332, forming a block of 2N symbols. Pilot error signal E pilot332 is multiplied by the conjugate signal X*162 using the second pilot multiplier 334, and the result is propagated to the gradient descent unit 336 as in the conventional FDEQ 100. The constrained pilot error gradient signal 338 generated by the gradient constraint unit 336 is multiplied by the pilot step size μ through the third pilot multiplier 342. pilot 154 times to generate a pilot step scaled signal 344. A second pilot adder 348 adds the pilot step scaled signal 344 to a previous value of the equalizer tap for a previous pilot error update interval W(p–1) held by a delay unit 346 of the equalizer tap 352 to generate an updated equalizer tap value W(p) 350.

[0074] Therefore, the pilot error tap update path updates the values ​​of the MIMO equalizer taps according to the following equation:

[0075] W(p)=W(p–1)+2μ pilot G{E pilot (p–1)X(p–1)*} (6)

[0076] Or, if polarization multiplexed:

[0077] W xx (p) = W xx (p–1)+2μ pilot G{E xpilot (p–1)X(p–1)*} (7)

[0078] W yx (p) = W yx (p–1)+2μ pilot G{E xpilot (p–1)Y(p–1)*} (8)

[0079] W xy (p) = W xy (p–1)+2μ pilot G{E ypilot (p–1)X(p–1)*} (9)

[0080] W yy (p) = W yy (p–1)+2μ pilot G{E ypilot (p–1)Y(p–1)*} (10)

[0081] Therefore, it should be understood that in some embodiments, the pilot-assisted FDEQ 300 may be different from the conventional FDEQ 100 in the following four aspects: first, the pilot-assisted FDEQ 300 does not rely on the carrier recovery path as part of its tap update path, and therefore does not need to delay its error calculation to wait for the carrier recovery path output; second, since the carrier recovery path is omitted, the pilot error tap update path of the pilot-assisted FDEQ 300 calculates the error based on the k symbols of the equalized digital signal 123 instead of the N symbols of the phase compensation decision signal 136; third, the pilot-assisted FDEQ 300 calculates the pilot error signal E pilot 332 is different from the way in which the traditional FDEQ 100 calculates the decision error signal E 144; fourthly, due to the above reasons, the equalization cycle delay of the pilot-assisted FDEQ 300 is smaller.

[0082] Figure 4 Schematic diagram of a frame 400 of a digital signal including pilot symbols (e.g., digital signal 302 received and equalized by pilot-assisted FDEQ 300). Frame 400 is generated and transmitted by a transmitter (e.g., transmitter 2 of FIG. 1 ) using the pilot-assisted scheme described herein. It should be understood that conventional transmitter 2 can be modified to generate pilot symbols and insert them into a data stream using a modified version of conventional transmitter DSP 18. After generating frame 400, the transmitter transmits frame 400 in the form of an optical signal over optical link 6.

[0083] The frame 400 includes N symbols, where N=kn. Each n symbols 406 of the frame 400 includes 1 pilot symbol 402 and (n-1) data symbols 404, so that the frame 400 includes k pilot symbols 402 and (N-k) data symbols. In some embodiments, the pilot symbols are distributed between each (n-1) data symbol 404 at regular intervals. In some embodiments, the frame 400 starts with the pilot symbol 402; in other embodiments, the frame may start with the (n-1) data symbol 404.

[0084] Although reference Figure 4 The pilot symbol insertion scheme of frame 400 is used to describe an exemplary embodiment, but it should be understood that some embodiments may use alternative pilot symbol distributions throughout the data signal frame.

[0085] A single frame 400 of the digital signal 302 received by the pilot-assisted FDEQ 300 corresponds to a single block of N symbols, eg, the pth block of the digital signal 302 .

[0086] Figure 5 To calculate using the frequency domain error calculation module 330 Figure 3 The pilot error signal E of the pilot-aided FDEQ 300 pilot332 is a flow chart of an exemplary method 500 .

[0087] In 502, the frequency domain error calculation module 330 receives N symbol blocks of the equalized data signal 314 in the time domain, and for each of the k pilot symbols of the data block, calculates a phase angle Δφ as the sum of the angles between the characteristics of a predetermined pilot symbol (referred to as pilot and represented as (1+1j)) and the characteristics of the corresponding received actual pilot symbol (referred to as data and represented as (a+bj)). In some embodiments, the phase angle can be calculated as Δφ=∠Σ(data*pilot), or the sum angle of the multiplication of each conjugate of the actually received pilot symbol and each corresponding predetermined pilot symbol. In an embodiment using quadrature phase shift keying (QPSK) symbols or binary phase shift keying (BPSK) symbols for pilot symbols, the calculation can be simplified from the multiplication operation* to the addition operation (a+bj)*·(1+1j)=(a–bj)·(1+1j)=a–b+(a+b)j.

[0088] In 504, the frequency domain error calculation module 330 generates an error block of k symbols, where each symbol is the difference between: (1) one of the k predetermined pilot symbols adjusted by the phase angle Δφ and (2) one of the corresponding k received pilot symbols, i.e.

[0089] In 506, the frequency domain error calculation module 330 concatenates the zero block of k zero bits to the error block to generate a block of 2k symbols, eg, k zero bits followed by k error bits.

[0090] In 508, the frequency domain error calculation module 330 applies a discrete 2k Fast Fourier Transform to transform the concatenated error block and the zero block into the frequency domain, generating a frequency domain block of 2k symbols.

[0091] In 510, the frequency domain error calculation module 330 replicates the frequency domain block n times to generate an error signal E of 2N symbols. pilot of blocks.

[0092] In some embodiments, the pilot symbols of the optical signal (and therefore the digital signal 302) are quadrature phase shift keying (QPSK) symbols or binary phase shift keying (BPSK) symbols. This enables the phase angle Δφ to be calculated using addition operations instead of the multiplication required for error calculation in conventional FDEQ 100.

[0093] In some embodiments, the receiver 4 can use a hybrid FDEQ having a pilot error tap update path in a pilot-assisted FDEQ 300 and a decision error tap update path in a conventional FDEQ 100. In some embodiments, the hybrid FDEQ with these two paths can be used to selectively activate and deactivate one or two tap update paths, so that the hybrid FDEQ can operate in a pilot-assisted mode using only a pilot error tap update path, a decision-guided mode using only a decision error tap update path, or a hybrid mode using two tap update paths. In some embodiments, the hybrid FDEQ can initially operate in a decision-guided mode or a hybrid mode until the equalizer signal is locked (i.e., the value of the equalizer tap achieves a balance for damage compensation such as SOP tracking). This state can be referred to here as the equalizer tap being locked, the tap value being locked, or the equalizer being locked. In some embodiments, determining that the MIMO tap value has been locked includes calculating the root mean square (RMS) value of the time domain error, and determining that the RMS error value is less than a threshold. It should be understood that reference to a value or component being "locked" or "locked" refers to a state of equilibrium or steady state, such as in the context of a phase-locked loop, and not to a state where the value or component can no longer change.

[0094] After the tap values ​​are locked, the hybrid FDEQ can continue to operate in pilot-assisted mode, deactivate the decision error tap update path, and use only the pilot error tap update path, which has lower latency and lower complexity, to equalize the digital signal. In some embodiments, the activation and deactivation of the tap update path and the detection of equalizer signal lock can be performed by a controller included in the receiver 4. Figure 6 An exemplary hybrid FDEQ is described. Figure 7 Describe the operation of the hybrid FDEQ, combining Figure 8 (Decision-oriented model), Fig. 9 (Pilot Assisted Mode) and Fig.10 (Hybrid Mode) Describes the tap update method using hybrid FDEQ.

[0095] Figure 66 is a block diagram of a hybrid FDEQ 600 having a pilot error tap update path and a decision error update path. It should be understood that each component of the hybrid FDEQ 600 corresponds to a component of the conventional FDEQ 100 or the pilot-assisted FDEQ 300 and operates in a substantially similar manner unless otherwise indicated. In the decision-directed mode, the pilot error tap update path is deactivated and the hybrid FDEQ 600 operates as the conventional FDEQ 100. In the pilot-assisted mode, the decision error tap update path is deactivated and the hybrid FDEQ 600 operates as the pilot-assisted FDEQ 300. In the hybrid mode, the two update paths may operate simultaneously to provide a control scheme according to the following reference. Fig.10 The described method updates the equalizer taps.

[0096] In some embodiments, the phase compensated decision signal 322 may include pilot symbols, making it different from the phase compensated decision signal 132 of the conventional FDEQ 100 .

[0097] In the hybrid FDEQ 600 , the conjugation path including the conjugation module 164 can be considered as part of the pilot error tap update path and the decision error tap update path.

[0098] Hybrid FDEQ 600 can include Figure 6 Additional logic not shown in the figure is used to synchronize the decision error tap update path with the pilot error update path. For example, in an embodiment where the decision error update interval is different from the pilot error update interval (e.g., longer), the tap value W350 can be updated by the pilot error tap update path at each pilot error update interval, but the tap value W350 is only updated by the decision error tap update path once every few pilot error update intervals. Therefore, in an exemplary embodiment, the decision error update interval can be set to five times the duration of the pilot error update interval. In such an embodiment, the controller switch of the decision error tap update block can be turned on once every 5 blocks, and the order of tap value updates can be defined as follows:

[0099] W(10)=W(9)+2μ Pilot G{E pilot (9)X*(9)}+2μG{E(9)X*(9)}

[0100] W(11)=W(10)+2μ Pilot G{E pilot (10)X*(10)}

[0101] W(12)=W(11)+2μ Pilot G{E pilot (11)X*(11)}

[0102] W(13)=W(12)+2μ Pilot G{E pilot (12)X*(12)}

[0103] W(14)=W(13)+2μ Pilot G{E pilot (13)X*(13)}

[0104] W(15)=W(14)+2μ Pilot G{E pilot (14)X*(14)}+2μG{E(14)X*(14)}

[0105] W(16)=W(15)+2μ Pilot G{E pilot (15)X*(15)}

[0106] W(17)=W(16)+2μ Pilot G{E pilot (16)X*(16)}

[0107] W(18)=W(17)+2μ Pilot G{E pilot (17)X*(17)}

[0108] W(19)=W(18)+2μ Pilot G{E pilot (18)X*(18)}

[0109] The indices m and p are both used in various equations described herein to distinguish between different tap update intervals and different tap update delays for the two tap update paths, and the relationship between m and p will be defined by the design of the particular hybrid FDEQ 600 .

[0110] Figure 7 Flowchart of an exemplary method 700 for providing frequency domain equalization to a digital signal using a pilot-assisted FDEQ (e.g., pilot-assisted FDEQ 300) or a hybrid FDEQ (e.g., hybrid FDEQ 600). The optional steps of the method 700, as shown by the dashed lines, correspond to the decision-directed tap updates performed by the decision error tap update path of the hybrid FDEQ in hybrid mode. If these steps are omitted, the method 700 corresponds to the operation of the pilot-assisted FDEQ, or the operation of the hybrid FDEQ in pilot-assisted mode.

[0111] Refer to the above example FDEQ description Figure 5 Method 500 and Figures 7 to 10However, it should be understood that these methods can be performed by different embodiments of pilot-assisted FDEQ or hybrid FDEQ.

[0112] In 702, a coherent receiver (eg, ICR 20) receives a pilot-assisted optical signal, the pilot-assisted optical signal comprising a plurality of pilot symbols and a plurality of data symbols. In some embodiments, the pilot symbol insertion scheme of frame 400 may be used.

[0113] At 704, a coherent receiver (eg, ICR 20) generates an electrical signal based on the pilot-assisted optical signal.

[0114] In 706, an equalizer (e.g., pilot-assisted FDEQ 300 or hybrid FDEQ 600) receives a digital signal (e.g., digital signal 302) that includes a plurality of pilot symbols and a plurality of data symbols. The digital signal is based on an electrical signal. In some embodiments, the digital signal is generated by ADC 24 based on the electrical signal generated by the coherent receiver.

[0115] In 708, the equalizer tap 352 is adjusted based on the pilot error signal E pilot 332 equalizes the digital signal in the frequency domain using tap value W350, thereby generating an equalized digital signal 314.

[0116] In 710, the frequency domain error calculation module 330 calculates the phase angle Δφ according to the angle between one or more predetermined pilot symbols and one or more received pilot symbols of the equalized digital signal 314, and generates a pilot error signal E pilot . Reference above Figure 5 The method 500 is described in more detail including the calculation of additional steps after calculating the phase angle.

[0117] At 712 , the conjugation module 164 generates a conjugate signal X* of the digital signal in the frequency domain X.

[0118] In 714, according to the pilot error update interval, according to the pilot error signal E pilot Update the equalizer tap value 350, that is, after the pilot error update interval p has passed, update the tap 352 with the updated tap value W(p+1) 350. Fig. 9 Method 900 describes step 714 in more detail.

[0119] Optionally, steps 716 to 720 are performed, corresponding to the operation of the decision error tap update path of the hybrid FDEQ.

[0120] In 716, a phase compensated decision signal 322 is generated by the carrier recovery path (e.g., the carrier recovery module 124 and the slicer 130), and a time domain error is generated by the adder 134 based on the equalized digital signal 314 (more specifically, based on the equalizer output signal 123 in the time domain) and the phase compensated decision signal 322.

[0121] At 718, the zero insertion block 138 and FFT module 142 generate a frequency domain error signal E 144 based on the difference between the equalized digital signal 314 (more specifically, the equalizer output signal 123) and the phase compensation decision signal 322. The details of this calculation are described above with reference to the zero insertion block 138 of FIG.

[0122] At 720, the equalizer taps 352 are updated according to the pilot error signal E 144 according to the pilot error update interval. As described above, in some embodiments, the pilot error update interval is shorter than the decision error update interval. Fig.10 Method 1000 describes step 720 in more detail.

[0123] Figure 8 8 is a flow chart of an exemplary method 800 for updating equalizer taps based on a decision error signal E. The method 800 corresponds to the operation of a hybrid FDEQ such as the hybrid FDEQ 600 in a decision-directed mode. Therefore, the method generally corresponds to the operating steps of the tap update path of the conventional FDEQ 100.

[0124] In 802, a decision error gradient signal 148 is generated by multiplying the decision error signal E 144 at the previous decision time interval (m-1) by the conjugate signal X* at the previous decision time interval (m-1), such that the decision error gradient signal 148 = E(m-1)×X*(m-1).

[0125] At 804 , the gradient constraint unit 150 applies a gradient constraint G{.} to the decision error gradient signal 148 to generate a constrained decision error gradient signal 152 .

[0126] In 806 , the constrained decision error gradient signal 152 is multiplied by twice the decision error step size μ 154 using the multiplier 153 to generate a decision error step scale signal 156 .

[0127] At 808 , the adder 348 adds the decision error step scale signal 156 to the previous tap value W(m−1) stored by the delay unit 346 to generate an updated tap value W(m) 350 .

[0128] At 810, the equalizer taps 352 are updated using the updated tap values ​​W(m) 350, where W(m) = W(m-1) + 2μG{E(m-1)X*(m-1)} (according to Equation 1 above, or Equations 2 to 5 for polarization multiplexing configurations).

[0129] Fig. 9 is used to calculate the pilot error signal E pilot 332 is a flowchart of an exemplary method of updating equalizer taps. The method 900 corresponds to the operation of a hybrid FDEQ such as the hybrid FDEQ 600 in a pilot-assisted mode, or the operation of a pilot-assisted FDEQ such as the pilot-assisted FDEQ 300 .

[0130] In 902, the pilot error signal E at the previous pilot time interval (p-1) is calculated by pilot The pilot error gradient signal is generated by multiplying 332 by the conjugate signal X* at the previous pilot time interval (m-1), so that the pilot error gradient signal 148 = E(m-1)×X*(m-1).

[0131] At 904 , the gradient constraint unit 336 applies a gradient constraint G{.} to the pilot error gradient signal to generate a constrained pilot error gradient signal 338 .

[0132] At 906, the constrained pilot error gradient signal 338 is multiplied by the pilot error step size μ using the multiplier 342. pilot 340 times to generate a pilot error step scaling signal 344.

[0133] At 908 , the adder 348 adds the pilot error step scale signal 344 to the previous tap value W(p−1) stored by the delay unit 346 to generate an updated tap value W(p) 350 .

[0134] At 910, the equalizer taps 352 are updated using the updated tap values ​​W(p) 350, where W(p) = W(p-1) + 2μ pilot G{E pilot (p–1)X*(p–1)} (according to equation 6 above, or equations 7 to 10 for polarization multiplexing configurations).

[0135] Fig.10 is used to determine the error signal E 144 and the pilot error signal E pilot 332 is a flow chart of an exemplary method for updating equalizer taps. The method 1000 corresponds to the operation of a hybrid FDEQ such as the hybrid FDEQ 600 in a hybrid mode.

[0136] Method 1000 performs steps 802 to 808 of method 800 to generate a tap update value based on a decision error and simultaneously performs steps 902 to 908 of method 900 to generate a tap update value based on a pilot error. Method 800 is performed in time with a decision error update interval, while method 900 is performed in time with a pilot error update interval.

[0137] At 1010, the equalizer taps 352 are updated using updated tap values ​​W(p) 350 according to Equation 1 or Equations 12 to 15 for a polarization multiplexing configuration. Some embodiments may update the equalizer taps by considering the current value of the pilot step scale signal 344 and the current value of the step scale signal 156, wherein the pilot error tap update path updates the taps at each pilot error update interval and the decision error tap update path updates the taps at each decision error update interval.

[0138] Therefore, the tap update path jointly updates the values ​​of the MIMO equalizer taps according to the following equation:

[0139] W(p)=W(p–1)+2μ pilot G{E pilot (p–1)X(p–1)*}+2μG{E(m–1)X(m–1)*} (11)

[0140] Or, if polarization multiplexed:

[0141] W xx (p) = W xx (p–1)+2μ pilot G{E xpilot (p–1)X(p–1)*}+2μG{E x (m–1)X(m–1)*} (12)

[0142] W yx (p) = W yx (p–1)+2μ pilot G{E xpilot (p–1)Y(p–1)*}+2μG{E x (m–1)Y(m–1)*} (13)

[0143] W xy (p) = W xy (p–1)+2μ pilot G{E ypilot (p–1)X(p–1)*}+2μG{E y (m–1)X(m–1)*} (14)

[0144] W yy (p) = W yy(p–1)+2μ pilot G{E ypilot (p–1)Y(p–1)*}+2μG{E y (m–1)Y(m–1)*} (15)

[0145] Simulation results show that the pilot-assisted FDEQ described in this paper can significantly improve the bit error rate (BER) at large SOP rates. Specifically, for SOP rates below 50kHz, pilot-assisted FDEQ or hybrid FDEQ in pilot-assisted mode has very good performance. For SOP rates above 50kHz, pilot-assisted mode may not be able to correct BER as effectively as hybrid mode.

[0146] Although the present invention describes the method and process in a specific order, one or more steps of the method and process may be omitted or modified as appropriate. One or more steps may be performed in sequence, but not in the order described (as appropriate).

[0147] Although the present invention has been described, at least in part, in terms of methods, it will be understood by those skilled in the art that the present invention also relates to various components for performing at least some aspects and features of the described methods by hardware components, software, or any combination of the two. Accordingly, the technical solution of the present invention may be embodied in the form of a software product. Suitable software products may be stored in a pre-recorded storage device or other similar non-volatile or non-transient computer-readable medium, such as a DVD, CD-ROM, USB flash drive, removable hard disk or other storage medium. The software product includes instructions stored thereon that enable a processor device (e.g., a personal computer, a server, or a network device) to execute examples of the methods disclosed herein.

[0148] The present invention may be embodied in other specific forms without departing from the subject matter of the claims. The described exemplary embodiments are merely illustrative and not restrictive in all respects. Selected features from one or more of the above embodiments may be combined to create alternative embodiments not explicitly described, and it is understood that features suitable for such combinations are within the scope of the present invention.

[0149] All values ​​and sub-ranges within the disclosed range are also disclosed. In addition, although the systems, devices, and processes disclosed and shown herein may include a specific number of elements / components, the systems, devices, and assemblies may be modified to include more or fewer of such elements / components. For example, although any element / component disclosed may be referenced as a singular, the embodiments disclosed herein may be modified to include a plurality of such elements / components. The subject matter described herein is intended to cover and encompass all appropriate technical changes.

Claims

1. A device, characterized in that: include: a coherent receiver, configured to receive an optical signal and generate an electrical signal based on the optical signal, wherein the optical signal includes a plurality of pilot symbols and a plurality of data symbols; A frequency-domain adaptive equalizer (FDEQ), configured to receive a digital signal according to the electrical signal, wherein the frequency-domain adaptive equalizer comprises: The equalization path includes one or more equalizer taps for adjusting the pilot error signal E according to the pilot error signal E. pilot equalizing the digital signal in the frequency domain using one or more tap values ​​W to generate an equalized digital signal; Pilot error tap update path for: The pilot error signal E is generated by calculating the phase angle Δφ according to the angle between one or more predetermined pilot symbols of the equalized digital signal and one or more received pilot symbols. pilot ; According to the pilot error update interval, according to the pilot error signal E pilot updating the equalizer taps; A decision error tap update path, comprising a carrier recovery path for generating a phase compensation decision signal based on the equalized digital signal, wherein the decision error tap update path is used to: generating a decision error signal E according to a difference between the equalized digital signal and the phase compensation decision signal; updating the equalizer taps according to the decision error signal E according to a decision error update interval, wherein the pilot error update interval is shorter than the decision error update interval, The tap value W is also based on the decision error signal E.

2. The device according to claim 1, characterized in that The device is used to selectively activate and deactivate the decision error tap update path.

3. The device according to claim 2, characterized in that The apparatus is configured to selectively activate and deactivate the pilot error tap update path.

4. The device according to claim 3, characterized in that The device is used to deactivate the decision error tap update path after the equalizer is locked.

5. The device according to claim 4, characterized in that The device is also used to: In a case where the pilot error tap update path is deactivated, updating the equalizer taps using the decision error tap update path until the equalizer is locked; After the equalizer is locked, the pilot error tap update path is activated.

6. The device according to any one of claims 1 to 5, characterized in that The equalizer further comprises a conjugate path for generating a conjugate signal X* of the digital signal in the frequency domain; The pilot error tap update path is used to update the equalizer taps in the pilot error time interval p by: The gradient signal is generated by multiplying: The pilot error signal E in the previous pilot time interval (p–1) pilot , the conjugate signal X* in the previous pilot time interval (p–1); Applying a gradient constraint G{.} to the gradient signal to generate a constrained gradient signal; Multiply the constrained gradient signal by the pilot error step size μ pilot twice, generating a step-scaling signal; Adding the step-scaled signal to the equalizer tap value W(p-1) of the previous pilot time interval (p-1) stored by one or more delay units to generate one or more updated tap values ​​W(p); The equalizer taps are updated with the updated tap values ​​W(p) at the pilot error time interval p, so that W(p) = W(p-1) + 2μ pilot G{E pilot (p–1)X(p–1)*}.

7. The device according to claim 1, characterized in that The equalizer further comprises a conjugate path for generating a conjugate signal X* of the digital signal in the frequency domain; The decision error tap update path is used to update the equalizer taps in the decision error time interval m in the following manner: The decision error gradient signal is generated by multiplying: The decision error signal E in the previous decision time interval (m–1), the conjugate signal X* in the previous decision time interval (m–1); Applying a gradient constraint G{.} to the decision error gradient signal to generate a constrained decision error gradient signal; Multiplying the constrained decision error gradient signal by twice the decision error step size μ to generate a decision error step scaling signal; The pilot error tap update path is used to update the equalizer taps in the pilot error time interval p by: The pilot error gradient signal is generated by multiplying: The pilot error signal E in the previous pilot time interval (p–1) pilot , the conjugate signal X* in the previous pilot time interval (p–1); Applying a gradient constraint G{.} to the pilot error gradient signal to generate a constrained pilot error gradient signal; Multiply the constrained pilot error gradient signal by the pilot error step size μ pilot twice, generating a pilot error step scaling signal; adding the pilot error step-scaled signal and the decision error step-scaled signal to the equalizer tap value W(p-1) of the previous pilot time interval (p-1) stored by one or more delay units to generate one or more updated tap values ​​W(p); The equalizer taps are updated with the updated tap values ​​W(p) at the pilot error time interval p, so that W(p) = W(p-1) + 2μ pilot G{E pilot (p–1)X(p–1)*}+2μG{E(m–1)X(m–1)*}.

8. The device according to any one of claims 1 to 5, characterized in that The pilot symbol of the optical signal is a quadrature phase shift keying (QPSK) symbol or a binary phase shift keying (BPSK) symbol; The calculating of the phase angle Δφ includes an addition operation.

9. The device according to claim 8, characterized in that The pilot error tap update path generates the pilot error signal E in the following manner: pilot : receiving a data block of N symbols of the equalized digital signal, wherein the N symbols include k received pilot symbols distributed between every (n-1) data symbols at regular intervals, wherein kn=N; For each of the k received pilot symbols, calculating the phase angle Δφ as the sum of the angles between the predetermined pilot symbol and the received pilot symbol corresponding to the data block, wherein N=kn; Generate an error block of k symbols, where each symbol is the difference between: one predetermined pilot symbol among k predetermined pilot symbols adjusted by the phase angle Δφ, and one received pilot symbol among corresponding k received pilot symbols; concatenating the error block with a zero block of k zero-valued symbols; Applying Fourier transform to transform the concatenated error block and the zero block into the frequency domain to generate a frequency domain block of 2k symbols; The frequency domain block is replicated n times to generate the error signal E of 2N symbols. pilot of blocks.

10. A method for applying a frequency domain adaptive equalizer, characterized in that: The method comprises: receiving a digital signal including a plurality of pilot symbols and a plurality of data symbols; Using one or more equalizer taps, according to the pilot error signal E pilot equalizing the digital signal in the frequency domain using one or more tap values ​​W to generate an equalized digital signal; The pilot error signal E is generated by calculating the phase angle Δφ according to the angle between one or more predetermined pilot symbols of the equalized digital signal and one or more received pilot symbols. pilot ; According to the pilot error update interval, according to the pilot error signal E pilot updating the equalizer taps; generating a phase compensation decision signal according to the equalized digital signal; generating a decision error signal E according to a difference between the equalized digital signal and the phase compensation decision signal; updating the equalizer taps according to the decision error signal E according to a decision error update interval, wherein the pilot error update interval is shorter than the decision error update interval, The tap value W is also based on the decision error signal E.

11. The method according to claim 10, characterized in that The method further comprises: updating the equalizer taps according to the decision error signal E until the equalizer is locked; After the equalizer is locked, the pilot error signal E pilot The equalizer taps are updated.

12. The method according to claim 11, characterized in that The method further comprises: According to the decision error signal E and the pilot error signal E pilot updating the equalizer taps until the equalizer is locked; After the equalizer is locked, the pilot error signal E pilot The equalizer taps are updated.

13. The method according to any one of claims 10 to 12, characterized in that Also includes: Generate a conjugate signal X* of the digital signal in the frequency domain; The equalizer taps are updated in the pilot error time interval p by: The gradient signal is generated by multiplying: The pilot error signal E in the previous pilot time interval (p–1) pilot , the conjugate signal X* in the previous pilot time interval (p–1); Applying a gradient constraint G{.} to the gradient signal to generate a constrained gradient signal; Multiply the constrained gradient signal by the pilot error step size μ pilot twice, generating a step-scaling signal; adding the step-scaled signal to the tap value W(p-1) of the previous pilot time interval (p-1) stored by the equalizer tap to generate one or more updated tap values ​​W(p); The equalizer taps are updated with the updated tap values ​​W(p) at the pilot error time interval p, so that W(p) = W(p-1) + 2μ pilot G{E pilot (p–1)X(p–1)*}.

14. The method according to claim 10, characterized in that The method further comprises: Generate a conjugate signal X* of the digital signal in the frequency domain; The equalizer taps are updated at the decision error time interval m by: The decision error gradient signal is generated by multiplying: The decision error signal E in the previous decision time interval (m–1), the conjugate signal X* in the previous decision time interval (m–1); Applying a gradient constraint G{.} to the decision error gradient signal to generate a constrained decision error gradient signal; Multiplying the constrained decision error gradient signal by twice the decision error step size μ to generate a decision error step scaling signal; The equalizer taps are updated in the pilot error time interval p by: The pilot error gradient signal is generated by multiplying: The pilot error signal E in the previous pilot time interval (p–1) pilot , the conjugate signal X* in the previous pilot time interval (p–1); Applying a gradient constraint G{.} to the pilot error gradient signal to generate a constrained pilot error gradient signal; Multiply the constrained pilot error gradient signal by the pilot error step size μ pilot twice, generating a pilot error step scaling signal; adding the pilot error step-scaled signal and the decision error step-scaled signal to the equalizer tap value W(p-1) of the previous pilot time interval (p-1) stored by the equalizer tap to generate one or more updated tap values ​​W(p); The equalizer taps are updated with the updated tap values ​​W(p) at the pilot error time interval p, so that W(p) = W(p-1) + 2μ pilot G{E pilot (p–1)X(p–1)*}+2μG{E(m–1)X(m–1)*}.

15. The method according to any one of claims 10 to 12, characterized in that Also includes: The coherent receiver receives an optical signal, wherein the optical signal includes a plurality of pilot symbols and a plurality of data symbols; A digital signal is generated based on the optical signal.

16. The method according to claim 15, characterized in that The pilot symbol of the optical signal is a quadrature phase shift keying (QPSK) symbol or a binary phase shift keying (BPSK) symbol; The calculating of the phase angle Δφ includes an addition operation.

17. The method according to claim 16, characterized in that The pilot error tap update path generates the pilot error signal E in the following manner: pilot : receiving a data block of N symbols of the equalized digital signal, wherein the N symbols include k received pilot symbols distributed between every (n-1) data symbols at regular intervals, wherein kn=N; For each of the k received pilot symbols, calculating a phase angle Δφ as the sum of angles between a predetermined pilot symbol and a corresponding received pilot symbol of the data block, wherein N=kn; Generate an error block of k symbols, where each symbol is the difference between: one predetermined pilot symbol among the k predetermined pilot symbols adjusted by the phase angle Δφ, and one received pilot symbol among the corresponding k received pilot symbols; concatenating the error block with a zero block of k zero-valued symbols; Applying Fourier transform to transform the concatenated error block and the zero block into the frequency domain to generate a frequency domain block of 2k symbols; The frequency domain block is replicated n times to generate the error signal E of 2N symbols. pilot of blocks.

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