Communication equipment, communication systems and communication methods

Abstract

[Problem] High-speed serial communication is achieved through a combination of different communication methods. [Solution] The communication device includes a communication unit that transmits a group of serial signals conforming to SPI (Serial Peripheral Interface) sent from the master device synchronously with the clock to the communication counterpart device via a batch of data blocks within a frame period of a predetermined communication protocol, or transmits the serial signal group to the communication counterpart device via multiple data blocks divided into multiple frame periods.

Description

Technical Field

[0001] This disclosure relates to communication equipment, communication systems, and communication methods. Background Technology

[0002] A technique for high-speed serial communication between the master device (using SerDes) and the slave device (using SerDes) is proposed (see PTL 1).

[0003] In serial communication between two SerDes, methods such as FDD (Frequency Division Duplex) or TDD (Time Division Duplex) can be used. When the amount of data sent from one SerDes to another is significantly different from the amount sent from the other SerDes to the first SerDes, the TDD method can be employed to allow the uplink data transmission capacity to differ from the downlink data transmission capacity. The TDD method is a half-duplex communication method that can only communicate in one direction, as uplink and downlink communication cannot occur simultaneously.

[0004] [List of Citations]

[0005] [Patent Literature]

[0006] [PTL 1] Japanese Patent Publication No. 2011-239011 Summary of the Invention

[0007] [Technical Issues]

[0008] One serial communication standard is called SPI (Serial Peripheral Interface). SPI is a full-duplex communication method capable of simultaneous uplink and downlink communication. In some cases, when the two SerDes mentioned above are communicating with other communication devices via SPI, SPI data is sent via each of the two SerDes to the communication device connected to the other SerDes connected to that SerDes. In this situation, if we assume that these SerDes communicate with each other via the TDD method, then SPI data used for full-duplex communication cannot be sent using the TDD method, which is a half-duplex communication method.

[0009] Therefore, this disclosure provides a communication device, communication system, and communication method capable of high-speed serial communication through a combination of different communication methods.

[0010] [Solution to the problem]

[0011] To address the aforementioned problems, this disclosure provides a communication device comprising a communication unit. The communication unit transmits a group of serial signals conforming to SPI (Serial Peripheral Interface), which is transmitted from a master device synchronously with a clock, to a communication counterpart device via a batch of data blocks within a frame period of a predetermined communication protocol, or transmits the serial signal group to the communication counterpart device via multiple data blocks divided into multiple frame periods.

[0012] The communication device may further include a memory that stores a first SPI-compliant serial signal group transmitted from the master device in sync with the clock, and a second SPI-compliant serial signal group transmitted from the slave device in sync with the clock; a packet encoder that converts the first serial signal group stored in the memory into a first packet of the predetermined communication protocol; and a packet decoder that converts the second packet of the predetermined communication protocol received from the communication peer device into a second serial signal group.

[0013] The first group may include frequency information about the clock, polarity information about the clock, and phase information about the clock relative to a data signal conforming to a first serial signal group of SPI.

[0014] The first group may include information indicating that the batch of data blocks is included within the one frame period, or information indicating that the batch of data blocks is included according to the multiple frame periods.

[0015] When the first group includes the plurality of data blocks, the first group may include the total number of the data blocks and information about the segmentation position of the data blocks.

[0016] The first group may include information about the size of the data block.

[0017] The first group may include information indicating whether the data block is valid or invalid.

[0018] The first group may include information indicating a reset of the slave device.

[0019] The second group may include at least one of information indicating the operating status of the slave device and interrupt information from the slave device.

[0020] If the interrupt information is contained in the second packet, and if the second packet itself arrives at the memory from the communication counterpart device, the memory can determine that the slave device has requested to read the slave device's status and send an interrupt signal to the master device.

[0021] The first group may include information about a slave device select signal, which is included in a first serial signal group that conforms to SPI, and is used to select the communication peer device or the slave device.

[0022] The packet encoder can send a first packet to the communication counterpart device or slave device selected by the slave device selection signal as the destination.

[0023] The communication device may further include a shift register that, in sync with the clock, sequentially stores each serial signal contained in the first serial signal group in the memory, and, in sync with the clock, sequentially sends each serial signal contained in the second serial signal group to the master device.

[0024] The communication unit can send a first packet at a first time determined by the predetermined communication protocol, and receive a second packet at a second time determined by the predetermined communication protocol.

[0025] When the slave device select signal sent from the master device changes from the first logic to the second logic, the packet encoder can determine that the transmission of the first serial signal group from the master device has been completed.

[0026] The communication unit can send and receive first and second packets to and from the communication counterpart device in accordance with the TDD (Time Division Duplex) communication protocol.

[0027] This disclosure provides a communication device including a communication unit that synchronously transmits a group of SPI-compliant serial signals from the device to the communication counterpart device via a batch of data blocks within a frame period of a predetermined communication protocol, or via a batch of data blocks divided into multiple data blocks according to multiple frame periods.

[0028] The communication device may further include a packet decoder that converts a first packet of a predetermined communication protocol received from the communication counterpart into a first serial signal group conforming to SPI; a clock generator that generates a clock based on clock frequency information contained in the first serial signal group; a memory that stores the first serial signal group synchronously with the clock and stores a second serial signal group conforming to SPI that is transmitted from the device synchronously with the clock; and a packet encoder that converts the second serial signal group stored in the memory into a second packet of the predetermined communication protocol.

[0029] The second group may include information indicating a batch of data blocks to be transmitted within a frame period of the second serial signal group, or information indicating multiple data blocks to be transmitted in segments of multiple frame periods.

[0030] The second group may include information indicating whether the slave device is in a busy state and cannot receive the first serial signal group, and information indicating whether the first serial signal group received by the slave device contains errors.

[0031] The second group may include interrupt information, which is a request for the master device to read the status of the slave device.

[0032] The communication device may further include a shift register that stores each serial signal contained in the second serial signal group in the memory and sends each serial signal contained in the first serial signal group to the slave device.

[0033] The communication unit can send a second packet at a first time determined by the predetermined communication protocol and receive a first packet at a second time determined by the predetermined communication protocol.

[0034] The communication unit can send and receive first and second packets to and from the communication counterpart device in accordance with the TDD (Time Division Duplex) communication protocol.

[0035] This disclosure provides a communication system comprising a first communication device and a second communication device for transmitting and receiving packets via a predetermined communication protocol. The first communication device includes a first communication unit that transmits a first serial signal group conforming to SPI (Serial Peripheral Interface), transmitted synchronously from a master device, to the second communication device via a batch of data blocks within a frame period of the predetermined communication protocol, or via multiple data blocks divided into multiple frame periods. The second communication device, synchronized with a clock generated based on clock frequency information contained in packets provided from the first communication device, transmits a second serial signal group conforming to SPI, transmitted from the master device, to the first communication device via a batch of data blocks within a frame period of the predetermined communication protocol, or via multiple data blocks divided into multiple frame periods.

[0036] A first communication device may include a first memory storing a first serial signal group transmitted from a master device synchronously with a first clock, and storing a second serial signal group transmitted from a slave device synchronously with the first clock; a first packet encoder converting the first serial signal group stored in the first memory into a first packet of the predetermined communication protocol; a first packet decoder converting the second packet of the predetermined communication protocol received from a second communication device into a second serial signal group; and a first communication unit transmitting the first packet at a timing determined by the predetermined communication protocol, and receiving the second packet at a timing determined by the predetermined communication protocol. The two communication devices may include a second packet decoder that converts a received first packet into a first serial signal group, a clock generator that generates a second clock based on clock frequency information contained in the first serial signal group, a second memory that stores the first serial signal group synchronously with the second clock and stores a second serial signal group that is transmitted from the device synchronously with the second clock, a packet encoder that converts the second serial signal group stored in the second memory into a second packet, and a second communication unit that transmits the second packet at a time determined by the predetermined communication protocol and receives the first packet at a time determined by the predetermined communication protocol.

[0037] This disclosure provides a communication method, the communication method including a communication unit, which transmits a group of SPI-compliant serial signals, which are transmitted synchronously from a master device with a clock, to a communication counterpart device through a batch of data blocks within a frame period of a predetermined communication protocol, or transmits the serial signal group to the communication counterpart device through multiple data blocks divided according to multiple frame periods. Attached Figure Description

[0038] Figure 1 This is a block diagram describing an example configuration of a communication system including a communication device according to the first embodiment.

[0039] Figure 2 This is a block diagram of the parts related to SPI communication between SPI / master and SPI / slave devices.

[0040] Figure 3 Describe the basic signal waveforms of the SPI protocol.

[0041] Figure 4 It is an explanation in Figure 1 A diagram illustrating the TDD method between M_SerDes and S_SerDes.

[0042] Figure 5 This is a diagram illustrating the information contained in the transport packets generated by ECP.

[0043] Figure 6 This is a timing diagram of the communication between the SPI / master device and the SPI / slave device.

[0044] Figure 7A This is a flowchart illustrating the communication process between the SPI / master device and the SPI / slave device.

[0045] Figure 7B Is as Figure 7A The flowchart continues.

[0046] Figure 8 It is a diagram illustrating the sending and receiving of packets via the uplink and downlink.

[0047] Figure 9 This is a timing diagram illustrating the process of transmitting segmented data repeatedly within a single frame time period across multiple frames.

[0048] Figure 10A It is a diagrammatic explanation according to Figure 9 The flowchart shows the processing procedure of the communication system for timed operations.

[0049] Figure 10B Is as Figure 10A The flowchart continues.

[0050] Figure 10C Is as Figure 10B The flowchart continues.

[0051] Figure 11 It is a block diagram of the main parts of a communication system including the communication device according to the third embodiment.

[0052] Figure 12 It includes according to Figure 11 A block diagram of the main parts of the communication system of a modified communication device. Detailed Implementation

[0053] In the following description, embodiments of communication devices, communication systems, and communication methods will be illustrated with reference to the accompanying drawings. The description will primarily focus on the essential components of the communication devices, communication systems, and communication methods; however, the communication devices, communication systems, and communication methods may include any other components or functions not described or illustrated. The following description is not intended to exclude any other components or functions not described or illustrated.

[0054] (First Embodiment)

[0055] Figure 1 This is a block diagram illustrating the schematic configuration of a communication system 2 including communication devices 1a and 1b according to the first embodiment. Figure 1The communication system 2 includes an SPI / master device 11, a master device SerDes (M_SerDes) 31, an SPI / slave device 12, and a slave device SerDes (S_SerDes) 41. M_SerDes 31 corresponds to communication device 1a, while S_SerDes 41 corresponds to communication device 1b.

[0056] SPI / Master Device 11 and M_SerDes 31 perform SPI-compliant serial communication (hereinafter, sometimes referred to as SPI communication). Similarly, SPI / Slave Device 12 and S_SerDes 41 perform SPI-compliant serial communication (SPI communication). M_SerDes 31 and S_SerDes 41 perform high-speed serial communication via the TDD method. Figure 1 In this specification, the signal transmission paths from M_SerDes 31 to S_SerDes 41 and from S_SerDes 41 to M_SerDes 31 are referred to as the uplink and downlink, respectively. In SPI communication, serial communication is performed using a protocol conforming to the SPI standard (hereinafter referred to as the SPI protocol). Furthermore, in this specification, the serial data sent and received via SPI communication can be referred to as SPI data.

[0057] As described below, M_SerDes 31 includes a communication unit (DLL 31-4), which transmits a group of SPI (Serial Peripheral Interface) compliant serial signals, which are transmitted synchronously from the master device (SPI_Master 11) with a clock to the communication peer device (S_SerDes 41) via a batch of data blocks within a frame period of a predetermined communication protocol, or transmits the SPI compliant serial signal group to the communication peer device (S_SerDes41) via multiple data blocks divided according to multiple frame periods. Additionally, S_SerDes 41 includes a communication unit (DLL 41-4), which synchronously transmits a group of SPI-compliant serial signals from the slave device (SPI_Slave 12) to the peer device (M_SerDes 31) via a batch of data blocks within a frame period of a predetermined communication protocol, either by generating a clock based on clock frequency information contained in packets provided by the peer device (M_SerDes 31) or by transmitting the SPI-compliant serial signals to the peer device (M_SerDes 31) via multiple data blocks divided into multiple frame periods.

[0058] Figure 2 This is a block diagram of the parts related to SPI communication between SPI / master device 11 and SPI / slave device 12. It should be noted that, for the sake of simplicity, Figure 2An example of SPI-compliant serial communication is described, in which SPI / master device 11 and SPI / slave device 12 are directly communicated.

[0059] like Figure 2 As shown, the SPI / master device 11 includes a shift register 11-1 and a buffer / memory 11-2. Similarly, the SPI / slave device 12 includes a shift register 12-1 and a buffer / memory 12-2.

[0060] The shift register 12-1 of SPI / slave device 12 operates synchronously with the clock SCK provided by SPI / master device 11. The shift register 11-1 of SPI / master device 11 sequentially outputs serial data synchronously with SCK via the MSB (most significant bit) side. The output serial data is input to the LSB (least significant bit) side of the shift register 12-1 of SPI / slave device 12 via the MOSI pin. The serial data output from the MSB side of the shift register 12-1 of SPI / slave device 12 is input to the LSB side of the shift register 11-1 of SPI / master device 11 via the MISO pin. Data held in the shift register 11-1 of SPI / master device 11 can be stored in buffer / memory 11-2. Furthermore, shift register 11-1 can hold data stored in buffer / memory 11-2. Similarly, data held in the shift register 12-1 of SPI / slave device 12 can be stored in buffer / memory 12-2. In addition, shift register 12-1 can hold the data stored in buffer / memory 12-2.

[0061] Figure 3 Describe the basic signal waveforms of the SPI protocol. In the SPI protocol, when the slave selector signal (CS signal) output from the SPI / master device 11 is idle ( Figure 3 The polarity of SCK (high level in the signal), and when the CS signal is active ( Figure 3 There are four combinations of the edges (rising or falling edges) of the clock (SCK) that latch the low-level data. These four combinations are called SPI modes. The SPI / master device 11 can arbitrarily select one of these four SPI modes. The SPI / master device 11 knows the SPI modes that the SPI / slave device can support, so it needs to select the mode corresponding to the supported modes.

[0062] Figure 3 A through 3D are signal waveform diagrams for the four SPI modes. Figure 3 In SPI mode A = 0, when the CS signal is idle, SCK is low, and data is held when SCK rises. Figure 3In SPI mode = 1 as shown in B, SCK is low when the CS signal is idle, and data is held when SCK falls. Figure 3 In SPI mode 2 as shown in C, SCK is high when the CS signal is idle, and data is held when SCK falls. Figure 3 In SPI mode 3 shown in D, SCK is high when the CS signal is idle, and data is held up when SCK rises.

[0063] The SPI protocol does not define the SCK frequency, and the SCK frequency differs for the respective devices communicating via SPI. The SPI / master device 11 selects the SCK frequency for each device communicating via SPI. Therefore, the SPI / device 11 needs to know in advance the SCK frequencies that each device communicating via SPI can support.

[0064] The following section will describe the communication method using the SPI protocol. Figure 2 In the example, communication using the SPI protocol occurs between the SPI / master device 11 and the SPI / slave device 12. The number of SPI / slave devices 12 connected to the SPI / master device 11 can be one or more. When two or more SPI / slave devices 12 are connected to the SPI / master device 11, the SPI / master device 11 has multiple CS signals corresponding to the respective SPI / slave device 12, and uses the corresponding CS signals to select the slave device with which it wants to communicate, thereby enabling communication with that slave device. The CS signals used by the SPI / master device 11 to select the SPI / slave device 12 to communicate with are included in the SPI control information, as described later. The SPI / master device 11 sends SPI data including the SPI control information to M_SerDes 31.

[0065] In the case of SPI communication, the SPI / master device 11 activates the CS signal connected to the SPI / slave device 12 with which it wants to communicate (in... Figure 3 (A through 3D are low levels). In this specification, in some cases, asserting means putting any signal into an active state, while deasserting means putting any signal into an idle state.

[0066] SPI / Master 11 and SPI / Slave 12 transfer the data to be transmitted from buffers / memories 11-2 and 12-2 to shift registers 11-1 and 12-1, respectively. SPI / Master 11 generates an SCK and provides this SCK not only to shift register 11-1 but also to shift register 12-1 of SPI / Slave 12. Shift registers 11-1 and 12-1 shift the data they are holding by 1 bit by switching the SCK. As a result of switching the SCK according to the number of shift registers 11-1 and 12-1, the data in shift registers 11-1 and 12-1 is replaced. Subsequently, SPI / Master 11 puts the CS signal into an idle state (in... Figure 3 (High level in A-3D). By transferring the current data in shift registers 11-1 and 12-1 to buffers / memories 11-2 and 12-2, SPI / master device 11 and SPI / slave device 12 can obtain data from buffers / memories 11-2 and 12-2. Then, SPI communication ends.

[0067] Although Figure 2 An example of direct SPI communication between SPI / master device 11 and SPI / slave device 12 is described, but Figure 1 The arrangement of M_SerDes 31 and S_SerDes 41 between SPI / master device 11 and M_SerDes 31 is described. Figure 1 In this configuration, SPI / master device 11 and M_SerDes 31 communicate via SPI, M_SerDes 31 and S_SerDes 41 communicate serially with each other via TDD, and SPI / slave device 12 and S_SerDes 41 communicate with each other via SPI.

[0068] Figure 4 This means that in Figure 1 A diagram illustrating the TDD method performed between M_SerDes 31 and S_SerDes 41. Figure 4 In the middle, it is described Figure 1 The simplified internal configuration of the SPI / master device 11 and SPI / slave device 12 is shown below. Additionally, Figure 4 An example is described in which peripheral devices 32 and 42 are connected to M_SerDes 31 and S_SerDes 41, respectively.

[0069] M_SerDes 31 and S_SerDes 41 are connected to each other, for example, via a cable 103 with a length of several meters to more than ten meters. High-speed serial communication is performed between M_SerDes 31 and S_SerDes 41 via cable 103. It should be noted that two or more devices can communicate serially with M_SerDes 31. In this case, each of these devices has a... Figure 4 The configuration is similar to S_SerDes 41 in the example. Additionally, it is possible to set a value similar to... Figure 4 The M_SerDes 31 and S_SerDes 41 in the example are similar to multiple pairs of devices, so that each pair can perform high-speed serial communication. Figure 4 M_SerDes 31 and S_SerDes 41 are suitable for a wide variety of applications, such as vehicle camera modules, for sending and receiving large amounts of data.

[0070] M_SerDes 31 and S_SerDes 41 perform high-speed serial communication via the TDD method. Figure 4 The lower right section describes the timing and frequency band in the TDD method. In the TDD method, as in... Figure 4 As shown on the right, the uplink signal transmission period and downlink signal transmission period are set in time without overlapping within a TDD cycle. Figure 4 The TDD timing diagram illustrates an example where the uplink signal transmission period from M_SerDes 31 to S_SerDes 41 (referred to as the uplink) is excessively shorter than the downlink signal transmission period from S_SerDes 41 to M_SerDes 31 (referred to as the downlink), i.e., an example where the uplink signal ratio is excessively smaller than the downlink signal ratio. For example, when sending the video signal captured by the sensor in S_SerDes 41 to M_SerDes 31, the signal ratio becomes as shown in... Figure 4 The ratio is illustrated in the TDD timing diagram.

[0071] exist Figure 4 The right side describes the frequency bands used for uplink signal transmission and downlink signal transmission in the TDD method. For example... Figure 4As shown, in the TDD method, the uplink and downlink signal transmission bandwidths largely overlap. For example, when sending video signals captured by a sensor in S_SerDes 41 to M_SerDes 31, the downlink signal transmission, due to its larger signal volume, requires a wider bandwidth than the uplink signal transmission. Therefore, the downlink signal transmission is performed using a wider bandwidth that includes the bandwidth used for uplink signal transmission. Since the downlink signal transmission period does not overlap with the uplink signal transmission period in the TDD method, echo cancellation circuitry for separating these signals is not required.

[0072] Performing signal transmission via the TDD method is a prerequisite for M_SerDes 31 and S_SerDes 41 according to this embodiment. However, in some cases, M_SerDes 31 and S_SerDes 41 can also perform signal transmission via the FDD method. Figure 4 The lower left section describes the timing and frequency band in the FDD method. In the FDD method, the frequency band used for signal transmission from M_SerDes31 to S_SerDes41 is different from the frequency band used for signal transmission from S_SerDes41 to M_SerDes31. Therefore, signal transmission from M_SerDes31 to S_SerDes41 and signal transmission from S_SerDes41 to M_SerDes31 can be performed simultaneously, and uplink and downlink signal transmissions can be performed as a whole using one FDD cycle.

[0073] Furthermore, in the FDD method, uplink signal transmission with high semaphore is performed using a wide bandwidth on the high-frequency side, while downlink signal transmission with low semaphore is performed using a narrow bandwidth on the low-frequency side. Figure 4 In the lower left example, to improve frequency efficiency, portions of the frequency band used for uplink signal transmission and the frequency band used for downlink signal transmission overlap. Due to this overlap, an echo cancellation circuit is required. The echo cancellation circuit is configured to separate the uplink and downlink signals with high precision.

[0074] Below is an example in which high-speed serial communication is performed between M_SerDes 31 and S_SerDes 41 using the TDD method. M_SerDes 31 performs SPI-compliant serial communication with SPI / Master 11, while S_SerDes 41 performs SPI-compliant serial communication with SPI / Slave 12.

[0075] Since serial communication between M_SerDes 31 and S_SerDes 41 is conducted via TDD (Transmission-Delivery) instead of SPI, protocol conversion is required between M_SerDes 31 and S_SerDes 41. Furthermore, TDD serial communication is half-duplex, while SPI serial communication is full-duplex. Therefore, in TDD, data cannot be sent and received from either the SPI / master device 11 or the SPI_Slave device at constant timing.

[0076] The following will explain in detail. Figure 1 The composition of communication system 2 in the text. Figure 1 In addition to the SPI / Master device 11, Figure 4 In addition to shift register 11-1 and buffer / memory 11-2, the diagram also includes controller 11-3 and SCK generator 11-4.

[0077] Controller 11-3 provides a slave device select signal (CS signal) to M_SerDes 31 via the M_CSn pin to activate SPI communication. The CS signal is provided according to the number of devices communicating with SPI / master device 11. For example, in... Figure 1 In this specification, different M_CSn pins are assigned to M_SerDes 31, S_SerDes 41, and SPI / slave device 12. The pin that outputs the CS signal from SPI / master device 11 can be represented as M_CSn(x). For example, M_CSn(0) is assigned to M_SerDes 31, while M_CSn(1) is assigned to SPI / slave device 12.

[0078] Controller 11-3 controls the operation of SCK generator 11-4. SCK generator 11-4 outputs SCK when either of the CS signals is active. Shift register 11-1 performs shift operations synchronously with SCK.

[0079] Controller 11-3 detects that the SPI / slave device 12 has output an interrupt signal S_INT based on the interrupt signal M_INT provided from M_SerDes 31. The interrupt signal M_INT is used to trigger controller 11-3 to start the next frame of SPI communication. Alternatively, SPI communication can be similarly initiated when SPI data needs to be sent from controller 11-3 (described later). Figure 6 The time t5 of M_CSn(1) in the middle)

[0080] M_SerDes 31 is connected to the SPI / master device 11. M_SerDes 31 includes an SPI block 31-1 for data communication with the SPI / master device 11 according to the SPI protocol. SPI block 31-1 includes a shift register 31-1-1 and a buffer / memory 31-1-2. When the controller 11-3 of the SPI / master device 11 activates the CS signal for M_SerDes 31 and the SCK generator 41-1-3 outputs SCK, the shift register 31-1-1 outputs SPI data synchronously with the SCK, and the SPI data is provided to the SPI / master device 11 via the MISO pin. Furthermore, synchronously with the SCK, the shift register 31-1-1 retrieves the SPI data output from the SPI / master device 11 via the MOSI pin.

[0081] When the CS signal enters the idle state, the controller 11-3 causes the SCK generator 11-4 to stop outputting SCK. As a result, the state of shift register 31-1-1 immediately preceding the stop of SCK is maintained.

[0082] When the CS signal enters the idle state, SPI block 31-1 in M_SerDes 31 transfers all data in shift register 31-1-1 to buffer / memory 31-1-2. This concludes the data transfer process from SPI / master device 11 to M_SerDes 31 according to the SPI protocol.

[0083] It should be noted that the data transfer from shift register 31-1-1 to buffer / memory 31-1-2 in M_SerDes 31 depends on the amount of data the SPI / master device 11 wants to transfer and the data capacity of shift register 31-1-1. Therefore, if there is a possibility of data overflow in shift register 31-1-1 during the active state of the CS signal, the data in shift register 31-1-1 is transferred to buffer / memory 31-1-2 before overflowing. This prevents data loss.

[0084] In addition, M_SerDes 31 includes a packet encoder (ECP) 31-2, a packet decoder (DCP) 31-3, a DLL 31-4, and a PHY layer block (PHY) 31-5. ECP 31-2 of M_SerDes 31 converts SPI data stored in buffer / memory 31-1-2 into packets conforming to the TDD method (SPI packets). DLL 31-4 generates uplink packets by combining the SPI packets generated by ECP 31-2 with other transport packets besides SPI packets. PHY 31-5 transmits the uplink packets to S_SerDes 41 via the uplink.

[0085] Figure 1 The S_SerDes 41 is connected to the SPI / slave device 12. S_SerDes 41 includes an SPI block 41-1 for sending and receiving data with the SPI / slave device 12 according to the SPI protocol. The SPI block 41-1 includes a controller (CNTR) 41-1-4, an SCK generator 41-1-3, a shift register 41-1-1, and a buffer / memory 41-1-2. The controller 41-1-4 controls the timing and frequency of the SCK output from the SCK generator 41-1-3 based on SPI control information provided from the SPI / slave device 11. The controller 41-1-4 activates the CS signal corresponding to the SPI / slave device 12, and when the SCK generator 41-1-3 outputs SCK, the shift register 41-1-1 outputs SPI data synchronously with the SCK, and the SPI data is provided to the SPI / slave device 12 via the S_MOSI pin. Furthermore, SPI data output from the SPI / slave device 12 via the S_MISO pin is synchronously input to shift register 41-1-1 with SCK. Additionally, S_SerDes 41 includes a packet encoder (ECP) 41-2, a packet decoder (DCP) 41-3, a DLL 41-4, and a PHY layer block (PHY) 41-5. ECP 41-2 of S_SerDes 41 converts the SPI data stored in buffer / memory 41-1-2 into packets conforming to the TDD method (SPI packets). DLL 41-4 generates uplink packets by combining the SPI packets generated by ECP 41-2 with other transport packets besides SPI packets. PHY 41-5 sends the uplink packets to S_SerDes 41 via the uplink.

[0086] Figure 5 This is a diagram illustrating the information contained in the transport packets generated by ECP 31-2 and 41-2. For Figure 5 Each information element in the transmission group is identified by a symbol, an information name, its function in the transmission group for data transmission from SPI / master device 11 to SPI / slave device 12, its function in the transmission group for data transmission from SPI / slave device 12 to SPI / master device 11, and a description of their relationship to each other.

[0087] C-1 is the transmission mode issued as a command by the SPI / master device 11. The SPI / master device 11 uses the transmission mode included in the packets provided from the SPI / slave device 12 to monitor the status. When C-1 is 0, a batch of data blocks is sent within one frame period of TDD. When C-1 is 1, multiple data blocks are sent according to multiple frame periods.

[0088] C-2 is the slave selector signal (CSn signal) issued by the SPI / master device 11 as a command. The SPI / master device 11 uses the CSn signal, which is included in the packet provided by the SPI / slave device 12, to monitor the status. Using the CSn signal, the SPI / master device 11 selects the SPI / slave device 12 with which it wants to communicate. The CSn signal allows selection not only of each SPI / slave device 12, but also of the SerDes (M_SerDes 31 or S_SerDes 41).

[0089] C-3 is the SCK frequency issued by the SPI / master device 11 as a command. The SPI / master device 11 uses the SCK frequency included in the packet provided by the SPI / slave device 12 to monitor the status. C-3 is provided to the SPI / master device 11 to specify the SCK frequency on the SPI / slave device 12 side.

[0090] C-4 is the SPI mode issued as a command by SPI / master 11. SPI / master 11 uses the SPI mode included in the packets provided by SPI / slave 12 to monitor the status. For example, when C-4 is 0, the selected mode is... Figure 3 The pattern shown in diagram A is 0. When C-4 is 1, the selection is... Figure 3 The pattern shown in diagram B is 1. When C-4 is 2, the choice is... Figure 3 The pattern shown in the diagram in C is 2. When C-4 is 3, the choice is in... Figure 3 The pattern shown in diagram D is 3.

[0091] C-5 is the total number of data blocks (DBs) provided as information by the SPI / master device 11. The SPI / master device 11 uses the total number of DBs included in the packets provided by the SPI / slave device 12 to monitor the status. C-5 is 1 when C-1 is 0 (when a segmented DB is sent). The SPI / slave device 12 returns the number of DBs received since the start of SPI communication.

[0092] C-6 is the location of the current data block DB provided by the SPI / master device 11. C-6 is not included in the packets provided from the SPI / slave device 12. A C-6 value of 0 indicates invalid information. C-6 is 0 when C-1 is 0. A C-6 value of 1 indicates the header segment data. A C-6 value of 2 indicates the segment data excluding the header and end segment data. A C-6 value of 3 indicates the end segment data.

[0093] C-7 is the status of the current data block DB provided by SPI / Master 11 and SPI / Slave 12. A C-7 value of 0 indicates dummy data, and a C-7 value of 1 indicates valid data.

[0094] C-8 is the size of the data block DB provided as information by the SPI / master device 11. The SPI / master device 11 uses the data transfer size included in the packets provided from the SPI / slave device 12 to monitor the status. C-8 indicates the data transfer size in bytes. The maximum size is 511 bytes.

[0095] C-9 is an interrupt message for SPI / slave device 12. It is not included in the packets sent by SPI / master device 11, but is included in the interrupt flags sent by SPI / slave device 12. A C-9 value of 0 indicates no interrupt. A C-9 value of 1 indicates an interrupt.

[0096] C-10 represents the operating status on the SPI / slave device 12 side. It is not included in the packets sent by the SPI / master device 11, but is included in the packets provided by the SPI / slave device 12. A C-10 value of 0 indicates a normal state. A C-10 value of 1 indicates a busy state (DCP 31-3 is not empty), and a C-10 value of 2 indicates an error (SPI data is corrupted).

[0097] C-11 is the reset of SPI block 41-1 and is issued as a command by SPI / master device 11. C-11 is not included in the packets provided by SPI / slave device 12. When C-11 is 0, no reset is performed. When C-11 is 1, SPI block 41-1 of S_SerDes 41 is reset.

[0098] D-1 is the SPI data transmitted along with C-1 to C-11 mentioned above. SPI data transmitted by SPI / Master Device 11 is output through the M_MOSI pin. SPI data transmitted by SPI / Slave Device 12 is output through the S_MISO pin.

[0099] E-1 is a CRC sent along with C-1 to C-11 and D-1. E-1 is included in the SPI data to be sent by SPI / master device 11 and the SPI data to be sent by SPI / slave device 12. The CRC is used to detect errors in the control data C-1 to C-11 and the SPI data.

[0100] Figure 6 This is a timing diagram of the communication between SPI / master device 11 and SPI / slave device 12. Figure 7A and Figure 7B These are flowcharts illustrating the communication process between the SPI / master device 11 and the SPI / slave device 12. Figure 8 It is a schematic diagram illustrating the transmission and reception of packets via the uplink and downlink. Figures 6-8 The process of sending and receiving a batch of data blocks within a frame period of TDD is described separately.

[0101] First, the SPI / master device 11 generates SPI control information used by ECP 31-2 and DCP 31-3 of M_SerDes 31, and sends the SPI control information to M_SerDes 31 (steps S1 to S4, times t1 to t4). The SPI control information includes, for example, the SPI transmission mode, SCK frequency information, SPI mode, and the size and number of data blocks (DB) during SPI communication. The SPI / master device 11 initially stores the SPI control information in buffer / memory 11-2.

[0102] In order to communicate with M_SerDes 31 via SPI, the controller 11-3 of the SPI / master device 11 puts M_CSn(0) into an active state (low) (makes it active) (step S1, time t1).

[0103] The controller 11-3 of the SPI / master device 11 controls the SCK generator 11-4 to output the clock M_SCK (step S2, time t2). Synchronized with the clock M_SCK, the SPI control information stored in the buffer / memory 11-2 is sequentially read out and transferred to the shift register 11-1. This SPI control information includes the transmission mode, SCK frequency information, SPI mode, data size, number of data blocks, etc. Synchronized with the clock M_SCK, the shift register 11-1 sequentially outputs the SPI control information (steps S2-S3, times t2-t3). The SPI control information is input to M_SerDes 31 via the M_MOSI pin. Synchronized with M_SCK, the shift register 31-1-1 of M_SerDes 31 retrieves the SPI control information provided by the SPI / master device 11.

[0104] In parallel with retrieving SPI control information from SPI / master 11, shift register 31-1-1 sends the data held in shift register 31-1-1 to SPI / master 11 synchronously with M__SCK via the M_MISO pin. This data is invalid. Figure 6 The times t2 to t3 are indicated by dashed lines. The SPI / master device 11 receives this data and then discards it.

[0105] After the data transfer from SPI / Master 11 is complete, the controller 11-3 of SPI / Master 11 causes the SCK generator 11-4 to stop generating M_SCK and invalidates M_CSn(0) to an idle state (step S4, time t4). When M_SCK stops, the shift register 31-1-1 of M_SerDes 31 transfers the held SPI control information provided by SPI / Master 11 to the buffer / memory 31-1-2.

[0106] The buffer / memory 31-1-2 of M_SerDes 31 transmits the SPI control information provided by the SPI / master device 11 to the ECP 31-2. The ECP 31-2 converts the SPI control information into SPI packets.

[0107] Subsequently, in order to transmit data to the SPI / slave device 12, the SPI / master device 11 sends SPI data to M_SerDes 31. Specifically, the controller 11-3 of the SPI / master device 11 causes M_CSn(1) corresponding to the SPI / slave device 12 to enter the active state from the idle state (make it inactive) (step S5, time t5).

[0108] Furthermore, controller 11-3 causes SCK generator 11-4 to output M_SCK (step S6, time t6). Buffer / memory 11-2 reads the size of the data to be sent to SPI / slave device 12 and inputs the read data into shift register 11-1. Synchronized with M_SCK, shift register 11-1 sequentially outputs data to SPI / slave device 12 via the M_MOSI pin (step S7, time t7).

[0109] The shift register 31-1-1 of M_SerDes 31 is synchronously fetched back into the shift register 31-1-1 from the SPI / master device 11 in sequence with SCK. When the transmission of data of the same size is completed, the controller 11-3 of the SPI / master device 11 causes the SCK generator 11-4 to stop outputting M_SCK (step S8, time t8). Then, the controller 11-3 of the SPI / master device 11 causes M_CSn(1) to enter the idle state (make it invalid) and ends the SPI communication (step S9, time t9).

[0110] When M_SCK stops, M_SerDes 31 transfers the data held in shift register 31-1-1 to buffer / memory 31-1-2. Buffer / memory 31-1-2 transfers the data transferred from shift register 31-1-1 to ECP 31-2. ECP 31-2 generates data including SPI control information received as a result of communication conducted between times t1 and t3, the CS signal (M_CSn(1)) for SPI / slave device 12, and data for SPI / slave device 12. ECP 31-2 generates transmission packets by adding flags indicating packet validity to the generated data.

[0111] ECP 31-2 uses the generated transport packets as Figure 8The SPI packet 51 shown is sent to DLL 31-4. DLL 31-4 generates uplink packet 52 by combining the SPI packet 51 sent from ECP 31-2 with other transmission packets, and outputs uplink packet 52 to PHY layer block 31-5. PHY layer block 31-5 outputs the received uplink packet 52 to cable 103 according to the uplink output timing corresponding to TDD (step S10, time t10).

[0112] S_SerDes 41 communicates with M_SerDes 31 via TDD method and also communicates with SPI / slave device 12 via SPI. The PHY layer block 41-5 of S_SerDes 41 receives uplink packets sent from M_SerDes 31 via cable 103 and outputs the uplink packets to link layer block (DLL) 41-4.

[0113] The link layer block 41-4 of S_SerDes 41 extracts the SPI packet containing SPI data from the uplink packet and outputs the SPI packet to the packet decoder (DCP) 41-3. Based on the CSn information (C-2) contained in the received SPI packet, DCP 41-3 detects that the SPI / slave device 12 is an SPI communication object. Then, in order to start SPI communication with the SPI / slave device 12, the controller 41-1-4 detects that the SPI data has been completely transmitted based on the transmission mode information (C-1) contained in the SPI packet, and obtains the number of SCK cycles required for one SPI communication based on the amount of SPI data (C-5) and the SPI data size (C-8), and then activates the slave device select signal S_CS (makes it active) (step S11, time t11).

[0114] Next, the controller 41-1-4 of S_SerDes 41 obtains the SCK frequency information (C-3) contained in the SPI packet, and uses the obtained frequency to cause the SCK generator 41-1-3 to output S_SCK (step S12, time t12). At this time, the phase relationship between S_CS and SCK follows the SPI mode in the SPI packet (C-4). Thus, S_SerDes 41 can transmit SPI data to the SPI / slave device 12. The data to be transmitted to the SPI / slave device 12 is an SPI packet (D-1) and is stored in the buffer / memory 41-1-2.

[0115] The shift register 41-1-1 of S_SerDes 41 outputs SPI data transferred from buffer / memory 41-1-2 sequentially via the S_MOSI pin according to the SCK provided by the SCK generator 41-1-3 (step S13, time t13). Simultaneously, SPI data to be output from SPI / slave device 12 to the S_MISO pin is stored in shift register 41-1-1 and then transferred to buffer / memory 41-1-2 at appropriate timing.

[0116] The SPI / slave device 12 synchronously retrieves the SPI data from the S_MOSI pin of S_SerDes 41 back into the shift register 12-1, and further sequentially outputs the data held in the shift register 12-1 through the S_MISO pin (step S14, time t14).

[0117] After driving S_SCK to reach the defined SPI data size (C-8), the controller (41-1-4) stops SCK and returns S_CS to the idle state (invalidates it) to end SPI communication (step S15, time t15). In parallel, when SPI / slave device 12 receives SPI data from the S_MOSI pin of S_SerDes 41, it transfers the SPI data sent from the S_MOSI pin to buffer / memory 12-2 at appropriate timing, thus finally completing the data reception from SPI / master device 11.

[0118] Buffer / memory 41-1-2 transmits SPI data received from SPI / slave device 12 to packet encoder (ECP) 41-2 for sending SPI data to SPI / master device 11. ECP 41-2 adds the received SPI data and SPI control information obtained from the SPI packet by ECP 41-2 to SPI packet 53. Additionally, ECP 41-2 will... Figure 5 The information (C-10) and CRC (E-1) indicating the operating status of SPI / slave device 12, as shown in the diagram, are added to the SPI packet.

[0119] Furthermore, when the SPI / slave device 12 outputs an interrupt signal (C-9), ECP 41-2 also adds information about the interrupt signal to SPI packet 53. In this case, SPI data provided by the SPI / slave device 12 is not sent through SPI packet 53. The reason for providing the interrupt signal is that in the SPI protocol, the CS and SCK signals are controlled only by the SPI / master device 11. Therefore, the SPI / slave device 12 cannot actively output any data. Consequently, the SPI / slave device 12 outputs an interrupt signal to wait for commands from the SPI / master device 11.

[0120] Link layer block (DLL) 41-4 generates downlink packet 54 by combining SPI packet 53 received from ECP 41-2 with other transmission packets, and outputs downlink packet 54 to PHY layer block 41-5. PHY layer block 41-5 outputs the received downlink packet 54 to cable 103 according to the downlink output timing (step S16, time t16).

[0121] The PHY layer block 31-5 of M_SerDes 31 receives a downlink packet including SPI packet 53 provided from SPI / slave device 12 and output from S_SerDes 41, and outputs the downlink packet to DLL 31-4. DLL 31-4 extracts SPI packet 53 from the received downlink packet 54 and outputs SPI packet 53 to packet decoder (DCP) 31-3.

[0122] When SPI data O_DB#1 is received from master device 11, DCP31-3 of M_SerDes 31 simultaneously receives a packet including I_DB#1 to be sent to master device 11 and stores the packet in buffer / memory 31-1-2. To indicate that valid SPI data I_DB#1 has been returned from SPI / slave device 12, buffer / memory 31-1-2 activates the interrupt signal M_INT (step S17, time t17). After receiving the interrupt signal M_INT, controller 11-3 of SPI / master device 11 starts SPI communication to read the SPI data provided by SPI / slave device 12 from M_SerDes 31 and activates M_CSn(1) (activates) (step S18, time t18).

[0123] The controller 11-3 of the SPI / master device 11 controls the SCK generator 11-4 to output M_SCK (11-10-2) (step S19, time t19). Synchronized with the SCK, shift register 11-1 retrieves data sequentially from the M_MISO pin according to the data transfer size (c-8) defined in frame #1. Meanwhile, the buffer / memory 31-1-2 of M_SerDes 31 transfers data from the SPI / slave device 12 to shift register 31-1-1 at appropriate timing, and shift register 31-1-1 sequentially outputs data in sync with the SCK generator 11-4 as described above. The output data is retrieved via the M_MIS0 pin (step S20, time t20). Simultaneously, the SPI / master device 11 reads the SPI data to be transmitted to the SPI / slave device 12 from the buffer / memory 11-2, stores the SPI data in the shift register 11-1, and sequentially outputs the SPI data from the shift register 11-1 via the M_MOSI pin (step S21, time t21). After reading the required data, the buffer / memory 31-1-2 restores the interrupt signal M_INT to the idle state (invalidates it) (step S22, time t22).

[0124] As a result of the operations described so far, the SPI data transfer between SPI / master device 11 and SPI / slave device 12 is completed. The above series of operations is repeated the same number of times as the necessary SPI data transfers (step S23, time t23).

[0125] When the last SPI data is read from SPI / slave device 12, SPI / master device 11 enables M_CSn(1) to output dummy data (step S24, time t24). This dummy data is invalid data that does not need to be transmitted to the SPI slave device. Therefore, this dummy data is discarded instead of being transferred from shift register 31-1-1 in M_SerDes 31 to buffer / memory 31-1-2 (step S25, time t25). The last data provided from SPI / slave device 12 is output from shift register 31-1-1 of M_SerDes 31 via the M_MISO pin and retrieved back into shift register 11 of SPI / master device 11 (step S26, time t26).

[0126] In the first embodiment, as described above, within a frame period of the TDD method, a batch of data sent from SPI / master device 11 to M_SerDes 31 via SPI communication can be sent to S_SerDes 41 via the uplink, and a batch of data sent from SPI / slave device 12 to S_SerDes 41 via SPI communication can be sent to M_SerDes 31 via the downlink. Therefore, SPI communication, as full-duplex communication, and TDD communication, as half-duplex communication, are combined, and serial communication between SPI / master device 11 and SPI / slave device 12 can be performed via M_SerDes 31 and S_SerDes 41.

[0127] (Second Embodiment)

[0128] In the second embodiment, the data to be sent and received via SPI communication is divided into multiple frame time periods according to the TDD method.

[0129] The communication system 2 according to the second embodiment has a communication with Figure 1 Similar configuration. However, there are differences in the SPI control information to be sent from SPI / master device 11 to M_SerDes 31.

[0130] Figure 9 It is a timing diagram of the process of repeatedly sending segmented data within each frame time period. Figure 10A , Figure 10B and Figure 10C The diagrams illustrate the process according to the instructions. Figure 9 The flowchart in the diagram illustrates the processing procedure of the timing operation communication system 2.

[0131] Similar to steps S1 to S8 (times t1 to t8) in Figure 7 Figure 10A In steps S31 to S38 (times t31 to t38), the SPI / master device 11 generates SPI control information and sets the SPI control information in ECP 31-2 and DCP 31-3 of M_SerDes 31. This is essentially the same as... Figure 7A and Figure 7B In similar steps S39 and subsequent processing operations, in Figure 9 , Figure 10A , Figure 10B and Figure 10C In SPI, the data to be transmitted in a single SPI frame is divided into multiple segments, with each segment transmitted within a single frame period of TDD. The signal transmitted within a single frame period of TDD is called a TDD burst signal.

[0132] The active state of the slave device select signal M_CSn(1) between SPI / master device 11 and M_SerDes 31 and the active state of the slave device select signal S_CS between S_SerDes 41 and SPI / slave device 12 are maintained until the transmission of all segmented data in the SPI frame is completed.

[0133] SPI / Master 11 enables the CS signal (M_CSn(1)) to begin SPI data transmission (step S35, time t35). SPI / Master 11 enables SCK generator 11-4 to output M_SCK to send a segmented data (data block DB) (step S36, time t36).

[0134] Subsequently, the SPI / master device 11 sequentially outputs SPI data from shift register 11-1 in sync with SCK, and also outputs SPI data through the M_MOSI pin (step S37, time t37). Furthermore, the SPI / master device 11 outputs the CS signal corresponding to the SPI / slave device 12 (the communication target) to M_SerDes 31 (step S38, time t38). Then, the ECP 31-2 of M_SerDes 31 generates a packet including the SPI data and the CS signal (step S39, time t39). The PHY layer block 31-5 combines this packet with other transmission packets to generate an uplink packet. This uplink packet is sent to S_SerDes41 via the uplink.

[0135] SPI / Master 11 continues to keep the CS signal active until all segmented data has been transmitted (step S40, time t40). SPI / Master 11 stops outputting M_SCK from SCK generator 11-4 until the next segmented data is transmitted (step S41, time t41).

[0136] S_SerDes 41 obtains the CS signal and SPI data from the received packet and makes S_CS valid (step S42, time t42). The controller 41-1-4 of S_SerDes 41 causes the SCK generator 41-1-3 to output S_SCK (step S43, time t43). S_SerDes 41 temporarily stores the SPI data from the received packet in buffer / memory 41-1-2, and then transfers the SPI data to shift register 41-1-1. Shift register 41-1-1 outputs data sequentially in sync with S_SCK. The output data is input to SPI / slave device 12 via the S_MOSI pin (step S44, time t44). Furthermore, data output from shift register 12-1 of SPI / slave device 12 in sync with S_SCK is input to S_SerDes 41 via the S_MISO pin (step S45, time t45).

[0137] DLL 41-4 of S_SerDes 41 generates a transmission packet containing data provided from the S_MISO pin. PHY layer block 41-5 sends the transmission packet to the downlink at a timing determined by the TDD method (step S46, time t46).

[0138] DLL 31-4 of M_SerDes 31 sends the SPI packet contained in the transmission packet sent from S_SerDes 41 to DCP 31-3. DCP 31-3 receives the packet containing I_DB#1 sent to master device 11 while receiving SPI data 0_DB#1 from master device 11, and stores the packet in buffer / memory 31-1-2. In order to indicate the return of valid SPI data I_DB#1 from SPI / slave device 12, buffer / memory 31-1-2 activates the interrupt signal M_INT (step S47, time t47).

[0139] When M_INT is detected to be valid, the SPI / master device 11 causes the SCK generator 11-4 to output M_SCK (step S48, time t48). The buffer / memory 11-2 transfers the data to be sent next to the shift register 11-1, and the shift register 11-1 outputs SPI data synchronously with M_SCK through the M_MISO pin (step S49, time t49). In parallel, the data output from M_SerDes 31 through the M_MISO pin is retrieved back into the shift register 11-1 (step S50, time t50).

[0140] After reading all the data provided from M_SerDes 31, the SPI / master device 11 restores M_INT to the idle state (invalidates it) (step S51, time t51).

[0141] S_SerDes 41 maintains the active state of S_CS (makes it valid) until all segmented data has been sent (step S52, time t52). Furthermore, the output of S_SCK from the SCK generator 41-1-3 of S_SerDes 41 is stopped until the next SPI data is sent from M_SerDes 31 (step S53, time t53).

[0142] Then, the processing operations of steps S40 to S53 are repeated (step S54, time t54). When M_SerDes 31 sends the last segmented packet through the uplink (step S55, time t55), S_SerDes 41 outputs S_SCK (step S56, time t56). Then, S_SerDes 41 outputs SPI data through the S_MOSI pin (step S57, time t57), and further receives the last SPI data from SPI / slave device 12 through the S_MISO pin (step S58, time t58).

[0143] After receiving the last SPI data, S_SerDes 41 puts S_CS into an idle state (invalidates it) (step S59, time t59). Additionally, S_SerDes 41 sends a transmission packet containing the last SPI data to M_SerDes 31 via the downlink (step S60, time t60).

[0144] Similar to step S47, M_SerDes 31 activates M_INT (step S61, time t61). Furthermore, M_SerDes 31 causes the SCK generator 11-4 of the SPI / master device 11 to output M_SCK (step S62, time t62). Synchronized with M_SCK, data output from shift register 31-1-1 via the M_MISO pin is retrieved back into shift register 11-1 of the SPI / master device 11 (steps S63-S64, times t63-t64). After retrieving all data, the SPI / master device 11 puts the CS signal into an idle state (step S65, time t65). The data output from shift register 11-1 in step S63 is discarded (step S66, time t66) because it is dummy data.

[0145] Therefore, in the second embodiment, the segmented data obtained by dividing a batch of data sent from the SPI / master device 11 to M_SerDes 31 via SPI communication into multiple segments can be sent to S_SerDes 41 via the uplink during multiple frame periods of the TDD method, and the segmented data obtained by dividing a batch of data sent from the SPI / slave device 12 to S_SerDes 41 via SPI communication can be sent to M_SerDes 31 via the downlink during multiple frame periods of the TDD method.

[0146] (Third Embodiment)

[0147] In the third embodiment, the SPI / master device 11 communicates serially with a plurality of SPI / slave devices 12.

[0148] Figure 11This is a block diagram of the main parts of a communication system 2 that includes the communication device according to the third embodiment. Figure 11 The S_SerDes 41 and multiple SPI / slave devices 12 are described. The internal configuration of each SPI / slave device 12 and M_SerDes 31 is similar to... Figure 1 The similarity in, therefore in Figure 11 The middle part is omitted. Additionally, Figure 11 Zhongyu Figure 1 The same components are indicated by the same reference numerals.

[0149] The SPI / master device 11 specifies the CSn signal of the SPI / slave device 12 to which it will communicate by using the SPI control information sent to M_SerDes 31. The controller 41-1-4 of S_SerDes 41 activates the CSn signal specified by the SPI / master device 11. Figure 11 An example is described where two of the SPI / slave devices, 12_1 and 12_2, are connected to S_SerDes 41.

[0150] When data communication with SPI / slave device 12_1 is desired, SPI / master device 11 sets the CSn signal in the SPI control signals to CS1. Consequently, the S_CS1 pin of controller 41-1-4 of S_SerDes 41, used to output the CS1 signal, becomes active. The CS1 signal sent from the S_CS1 pin is input to SPI / slave device 12_1. Thus, SPI / slave device 12_1 receives SPI data synchronously with S_SCK provided by S_SerDes 41, and sends SPI data synchronously with S_SCK to S_SerDes 41.

[0151] Furthermore, in the event of desired data communication with the SPI / slave device 12_2, the SPI / master device 11 sets the CSn signal in the SPI control signals to CS2. Consequently, the S_CS2 pin of the controller 41-1-4 of S_SerDes 41, used to output the CS2 signal, becomes active. The CS2 signal sent from the S_CS2 pin is input to the SPI / slave device 12_2. Thus, the SPI / slave device 12_2 receives SPI data synchronously with the S_SCK provided by S_SerDes 41, and synchronously sends SPI data to S_SerDes 41 with the S_SCK.

[0152] Figure 11 Communication system 2 describes an example in which the SPI / master device 11 specifies the SPI / slave device 12 to communicate with by using the CSn signal included in the SPI control signals. However, as Figure 12 As shown, multiple SPI / slave devices 12 can be connected in a daisy chain.

[0153] Figure 12 It includes according to Figure 11 A block diagram of the main components of a communication system 2, a modified example of a communication device. Figure 12 The document describes two SPI / slave devices 12 capable of simultaneously communicating serially with the SPI / master device 11. However, three or more SPI / slave devices 12 can be configured to simultaneously communicate serially with the SPI / master device 11.

[0154] Figure 12 The corresponding shift registers 12-1 of the two SPI / slave devices 12_1 and 12_2 are daisy-chained together. Data output from the MSB of shift register 12-1 of SPI / slave device 12_2 synchronously with SCK is input to the LSB of shift register 12-1 of SPI / slave device 12_1, and further, the data output from the MSB is sent to S_SerDes 41 via SPI communication.

[0155] Figure 12 The communication equipment in the middle needs to be repeated Figure 6 Steps S24 to S26 are repeated the same number of times as the number of SPI / slave devices 12.

[0156] Therefore, in the third embodiment, the SPI / master device 11 designates the SPI / slave device 12 by using the corresponding CSn signal included in the SPI control information, thereby enabling bidirectional serial communication with multiple SPI / slave devices 12. Furthermore, if the multiple SPI / slave devices 12 are daisy-chained, the SPI / master device 11 can simultaneously perform serial communication with multiple SPI / slave devices 12.

[0157] It should be noted that this technology can have the following configuration.

[0158] (1) A communication device, comprising:

[0159] The communication unit transmits a group of serial signals conforming to SPI (Serial Peripheral Interface), which is transmitted from the master device in sync with the clock, to the communication counterpart device via a batch of data blocks within a frame period of a predetermined communication protocol, or transmits the group of serial signals to the communication counterpart device via multiple data blocks divided into multiple frame periods.

[0160] (2) The communication device according to (1) further includes:

[0161] The memory stores a first SPI-compliant serial signal group transmitted from the master device in sync with the clock, and stores a second SPI-compliant serial signal group transmitted from the slave device in sync with the clock;

[0162] A packet encoder that converts a first group of serial signals stored in the memory into a first packet of the predetermined communication protocol; and

[0163] A packet decoder that converts a second packet of the predetermined communication protocol received from the communication counterpart device into a second serial signal group.

[0164] (3) The communication device according to (2), wherein

[0165] The first group includes frequency information about the clock, polarity information about the clock, and phase information about the clock relative to the data signal of the first serial signal group conforming to SPI.

[0166] (4) The communication device according to (2) or (3), wherein

[0167] The first group includes information indicating that the batch of data blocks is included within the one frame period, or information indicating that the batch of data blocks is included according to the multiple frame periods.

[0168] (5) The communication device according to (4), wherein

[0169] In the case where the first group includes the plurality of data blocks, the first group includes the total number of the data blocks and information about the segmentation position of the data blocks.

[0170] (6) The communication device according to (4) or (5), wherein

[0171] The first group includes information about the size of the data block.

[0172] (7) The communication device according to any one of (2) to (6), wherein

[0173] The first group includes information indicating whether the data block is valid or invalid.

[0174] (8) The communication device according to any one of (2) to (7), wherein

[0175] The first group includes information indicating the reset of the slave device.

[0176] (9) The communication device according to any one of (2) to (8), wherein

[0177] The second group includes at least one of information indicating the operating status of the slave device and interrupt information from the slave device.

[0178] (10) The communication device according to (9), wherein

[0179] If the interrupt information is contained in the second packet, and if the second packet itself arrives at the memory from the communication counterpart device, the memory determines that the slave device has requested to read the slave device's state and sends an interrupt signal to the master device.

[0180] (11) The communication device according to any one of (2) to (10), wherein

[0181] The first group includes information about a slave device selection signal, which is contained in a first serial signal group that conforms to SPI, and is used to select either the communication peer device or the slave device.

[0182] (12) The communication device according to (11), wherein

[0183] The packet encoder sends the first packet to the communication peer device or slave device selected by the slave device selection signal as the destination.

[0184] (13) The communication device according to any one of (2) to (12) further includes:

[0185] A shift register, synchronized with the clock, sequentially stores each serial signal contained in a first serial signal group in the memory, and sequentially sends each serial signal contained in a second serial signal group to the master device, synchronized with the clock.

[0186] (14) The communication device according to any one of (2) to (13), wherein

[0187] The communication unit sends a first packet at a first timing determined by the predetermined communication protocol, and receives a second packet at a second timing determined by the predetermined communication protocol.

[0188] (15) The communication device according to any one of (2) to (14), wherein

[0189] When the slave device select signal sent from the master device changes from the first logic to the second logic, the packet encoder determines that the transmission of the first serial signal group from the master device has been completed.

[0190] (16) The communication device according to any one of (2) to (15), wherein

[0191] The communication unit sends and receives first and second packets to and from the communication counterpart device in accordance with the TDD (Time Division Duplex) communication protocol.

[0192] (17) A communication device, comprising:

[0193] The communication unit, synchronized with a clock generated based on clock frequency information contained in packets provided from the communication counterpart device, transmits a SPI-compliant serial signal group from the device to the communication counterpart device in a batch of data blocks within a frame period of a predetermined communication protocol, or transmits the serial signal group to the communication counterpart device in multiple data blocks divided into multiple frame periods.

[0194] (18) The communication device according to (17) further includes:

[0195] A packet decoder that converts a first packet of a predetermined communication protocol received from the communication counterpart into a first serial signal group conforming to SPI;

[0196] A clock generator that generates the clock based on clock frequency information contained in a first serial signal group;

[0197] A memory that stores a first serial signal group in sync with the clock, and stores a second serial signal group compliant with SPI that is transmitted from the device in sync with the clock; and

[0198] A packet encoder that converts a second group of serial signals stored in the memory into a second packet of the predetermined communication protocol.

[0199] (19) The communication device according to (18), wherein

[0200] The second group includes information indicating a batch of data blocks to be transmitted within a frame period of the second serial signal group, or information indicating multiple data blocks to be transmitted in segments of multiple frame periods.

[0201] (20) The communication device according to (18) or (19), wherein

[0202] The second group includes information indicating whether the slave device is in a busy state and cannot receive the first serial signal group, and information indicating whether the first serial signal group received by the slave device contains errors.

[0203] (21) The communication device according to any one of (18) to (20), wherein

[0204] The second group includes interrupt information, which is a request for the master device to read the status of the slave device.

[0205] (22) The communication device according to any one of (18) to (21) further includes:

[0206] A shift register that stores each serial signal contained in a second serial signal group in the memory and sends each serial signal contained in a first serial signal group to the slave device.

[0207] (23) The communication device according to any one of (18) to (22), wherein

[0208] The communication unit sends the second packet at a first timing determined by the predetermined communication protocol, and receives the first packet at a second timing determined by the predetermined communication protocol.

[0209] (24) The communication device according to any one of (18) to (23), wherein

[0210] The communication unit sends and receives first and second packets to and from the communication counterpart device in accordance with the TDD (Time Division Duplex) communication protocol.

[0211] (25) A communication system, comprising:

[0212] A first communication device and a second communication device that send and receive packets through a predetermined communication protocol, wherein

[0213] The first communication device includes a first communication unit. The first communication unit transmits a first serial signal group conforming to SPI (Serial Peripheral Interface), which is transmitted synchronously from a master device and is based on a clock, to a second communication device via a batch of data blocks within a frame period of a predetermined communication protocol. Alternatively, the first communication unit transmits the serial signal group to the second communication device via multiple data blocks divided into multiple frame periods.

[0214] The second communication device, synchronized with a clock generated based on clock frequency information contained in packets provided from the first communication device, transmits a second SPI-compliant serial signal group from the device to the first communication device in a batch of data blocks within a frame period of a predetermined communication protocol, or transmits the serial signal group to the first communication device in multiple data blocks divided according to multiple frame periods.

[0215] (26) The communication system according to (25), wherein

[0216] The first communication device includes

[0217] A first memory stores a first serial signal group transmitted from the master device in synchronization with a first clock, and stores a second serial signal group transmitted from the slave device in synchronization with the first clock.

[0218] The first packet encoder converts a first group of serial signals stored in a first memory into a first packet of the predetermined communication protocol.

[0219] A first packet decoder converts a second packet of the predetermined communication protocol received from a second communication device into a second serial signal group, and

[0220] A first communication unit transmits a first packet at a time determined by the predetermined communication protocol, and receives a second packet at a time determined by the predetermined communication protocol.

[0221] The second communication device includes

[0222] The second packet decoder converts the received first packet into a first serial signal group.

[0223] A clock generator that generates a second clock based on clock frequency information contained in a first serial signal group.

[0224] A second memory, synchronized with a second clock, stores the first serial signal group and also stores the second serial signal group transmitted from the device, synchronized with the second clock.

[0225] A block encoder that converts a second serial signal group stored in a second memory into a second block, and

[0226] The second communication unit sends a second packet at a time determined by the predetermined communication protocol and receives a first packet at a time determined by the predetermined communication protocol.

[0227] A communication method, comprising:

[0228] The communication unit transmits a group of SPI-compliant serial signals, which is transmitted from the master device in sync with the clock, to the communication counterpart device via a batch of data blocks within a frame period of a predetermined communication protocol, or transmits the serial signal group to the communication counterpart device via multiple data blocks divided into multiple frame periods.

[0229] The aspects of this disclosure are not limited to the embodiments described above, but also include various modifications that can be conceived by those skilled in the art. The effects of this disclosure are also not limited to the content described above. That is, various additions, changes, and partial deletions can be made within the conceptual ideas and purposes of this disclosure derived from the definitions in the claims and their equivalents.

[0230] [List of reference numerals]

[0231] 1a: Communication equipment

[0232] 1b: Communication equipment

[0233] 2: Communication System

[0234] 11: SPI / Master Device

[0235] 11-1: Sequential Shift Register

[0236] 11-1: Shift Register

[0237] 11-2: Buffer / Memory

[0238] 11-3: Controller

[0239] 11-4: SCK Generator

[0240] 12: SPI / Slave Device

[0241] 12-1: Shift Register

[0242] 12-2: Buffer / Memory

[0243] 31:M_SerDes

[0244] 31-1: SPI Block

[0245] 31-1-1: Shift Register

[0246] 31-1-2: Buffer / Memory

[0247] 31-3: Block Decoder (DCP)

[0248] 31-5: PHY layer block

[0249] 32: Peripheral equipment

[0250] 41:S_SerDes

[0251] 41-1: SPI Block

[0252] 41-1-1: Shift Register

[0253] 41-1-2: Buffer / Memory

[0254] 41-1-3: SCK Generator

[0255] 41-1-4: Controller

[0256] 41-2: Packet Encoder (ECP)

[0257] 41-3: Block Decoder (DCP)

[0258] 41-4: Link Layer Block (DLL)

[0259] 41-5: PHY layer block

[0260] 42: Peripheral equipment

[0261] 51:SPI Grouping

[0262] 52: Uplink Packet

[0263] 53:SPI Grouping

[0264] 54: Downlink Packets

[0265] 103: Cable

Claims

1. A communication device, operating as a SerDes, comprising: The communication unit transmits a group of serial signals conforming to the Serial Peripheral Interface (SPI) sent from the master device in sync with the clock to the communication counterpart device via a batch of data blocks within a frame period of a predetermined communication protocol, or transmits the serial signal group to the communication counterpart device via multiple data blocks divided into multiple frame periods. The memory stores a first SPI-compliant serial signal group transmitted from the master device in sync with the clock, and stores a second SPI-compliant serial signal group transmitted from the slave device in sync with the clock; A packet encoder that converts a first group of serial signals stored in the memory into a first packet of the predetermined communication protocol; A packet decoder that converts a second packet of the predetermined communication protocol received from the communication counterpart device into a second serial signal group; as well as A shift register, synchronized with the clock, sequentially stores each serial signal contained in a first serial signal group in the memory, and sequentially sends each serial signal contained in a second serial signal group to the master device, synchronized with the clock.

2. The communication device according to claim 1, wherein The first group includes frequency information about the clock, polarity information about the clock, and phase information about the clock relative to the data signal of the first serial signal group conforming to SPI.

3. The communication device according to claim 1, wherein The first group includes information indicating that the batch of data blocks is included within the one frame period, or information indicating that the batch of data blocks is included according to the multiple frame periods.

4. The communication device according to claim 3, wherein In the case where the first group includes the plurality of data blocks, the first group includes the total number of the data blocks and information about the segmentation position of the data blocks.

5. The communication device according to claim 3, wherein The first group includes information about the size of the data block.

6. The communication device according to claim 1, wherein The first group includes information indicating whether the data block is valid or invalid.

7. The communication device according to claim 1, wherein The first group includes information indicating the reset of the slave device.

8. The communication device according to claim 1, wherein The second group includes at least one of information indicating the operating status of the slave device and interrupt information from the slave device.

9. The communication device according to claim 8, wherein If the interrupt information is contained in the second packet, and if the second packet itself arrives at the memory from the communication counterpart device, the memory determines that the slave device has requested to read the slave device's state and sends an interrupt signal to the master device.

10. The communication device according to claim 1, wherein The first group includes information about a slave device select signal, which is contained in a first serial signal group compliant with SPI, and the communication peer device or the slave device is selected based on the slave device select signal.

11. The communication device according to claim 10, wherein The packet encoder sends the first packet to the communication counterpart device or the slave device selected by the slave device selection signal as the destination.

12. The communication device according to claim 1, wherein The communication unit sends a first packet at a first timing determined by the predetermined communication protocol, and receives a second packet at a second timing determined by the predetermined communication protocol.

13. The communication device according to claim 1, wherein When the slave device select signal sent from the master device changes from the first logic to the second logic, the packet encoder determines that the transmission of the first serial signal group from the master device has been completed.

14. The communication device according to claim 1, wherein The communication unit sends a first packet to the communication counterpart device and receives a second packet from the communication counterpart device according to the Time Division Duplex (TDD) communication protocol.

15. A communication device, operating as a SerDes, comprising: The communication unit, synchronized with a clock generated based on clock frequency information contained in packets provided from the communication counterpart device, transmits a SPI-compliant serial signal group from the device to the communication counterpart device in a batch of data blocks within a frame period of a predetermined communication protocol, or transmits the serial signal group to the communication counterpart device in multiple data blocks divided into multiple frame periods. A packet decoder that converts a first packet of the predetermined communication protocol received from the communication counterpart device into a first serial signal group conforming to SPI; A clock generator that generates the clock based on clock frequency information contained in the first serial signal group; The memory stores the first serial signal group in sync with the clock, and stores the second serial signal group that complies with the SPI and is transmitted from the device in sync with the clock; A packet encoder that converts a second group of serial signals stored in the memory into a second packet of the predetermined communication protocol; as well as A shift register that stores each serial signal contained in the second serial signal group in the memory and sends each serial signal contained in the first serial signal group to the slave device.

16. The communication device according to claim 15, wherein The second group includes information indicating a batch of data blocks to be transmitted within a frame period of the second serial signal group, or information indicating multiple data blocks to be transmitted in segments of multiple frame periods.

17. The communication device according to claim 15, wherein The second group includes information indicating whether the slave device is in a busy state and cannot receive the first serial signal group, and information indicating whether the first serial signal group received by the slave device contains errors.

18. The communication device according to claim 15, wherein The second group includes interrupt information, which is a request for the master device to read the status of the slave device.

19. The communication device according to claim 15, wherein The communication unit sends the second packet at a first timing determined by the predetermined communication protocol, and receives the first packet at a second timing determined by the predetermined communication protocol.

20. The communication device according to claim 15, wherein The communication unit sends a second packet to the communication counterpart device and receives a first packet from the communication counterpart device in accordance with the Time Division Duplex (TDD) communication protocol.

21. A communication system, comprising: A first communication device and a second communication device transmit and receive packets via a predetermined communication protocol. Both the first and second communication devices operate as SerDes. The first communication device includes: The first communication unit transmits a first serial signal group conforming to the Serial Peripheral Interface (SPI) sent from the master device synchronously with the first clock to the second communication device via a batch of data blocks within a frame period of a predetermined communication protocol, or transmits the serial signal group to the second communication device via multiple data blocks divided into multiple frame periods. A first memory stores a first serial signal group transmitted from the master device in synchronization with a first clock, and stores a second serial signal group transmitted from the slave device in synchronization with the first clock. The first packet encoder converts a first serial signal group stored in a first memory into a first packet of the predetermined communication protocol. A first packet decoder converts a second packet of the predetermined communication protocol received from a second communication device into the second serial signal group; and A first shift register, synchronized with the first clock, sequentially stores each serial signal contained in the first serial signal group in the first memory, and sequentially sends each serial signal contained in the second serial signal group to the master device, synchronized with the first clock. The second communication device includes: The second communication unit, synchronized with a second clock generated based on clock frequency information contained in packets provided from the first communication device, transmits a second serial signal group conforming to SPI from the device to the first communication device in a batch of data blocks within a frame period of a predetermined communication protocol, or transmits the serial signal group to the first communication device in multiple data blocks divided according to multiple frame periods. The second packet decoder converts the received first packet into a first serial signal group; A clock generator generates the second clock based on the clock frequency information contained in the first serial signal group; The second memory stores the first serial signal group in synchronization with the second clock, and stores the second serial signal group transmitted from the device in synchronization with the second clock; The second group encoder converts the second serial signal group stored in the second memory into a second group; and The second shift register stores each serial signal contained in the second serial signal group in the second memory, and sends each serial signal contained in the first serial signal group to the slave device.

22. The communication system according to claim 21, wherein The first communication unit transmits a first packet at a time determined by the predetermined communication protocol, and receives a second packet at a time determined by the predetermined communication protocol. The second communication unit sends a second packet at a time determined by the predetermined communication protocol, and receives a first packet at a time determined by the predetermined communication protocol.

23. A communication method performed by a communication device operating as a SerDes, the communication method comprising: The communication unit transmits a group of SPI-compliant serial signals, which are transmitted from the master device in sync with the clock, to the communication counterpart device in a batch of data blocks within a frame period of a predetermined communication protocol, or transmits the serial signal group to the communication counterpart device in multiple data blocks divided into multiple frame periods. The memory stores a first set of SPI-compliant serial signals transmitted from the master device in sync with the clock, and stores a second set of SPI-compliant serial signals transmitted from the slave device in sync with the clock. The packet encoder converts the first serial signal group stored in the memory into the first packet of the predetermined communication protocol; The packet decoder converts the second packet of the predetermined communication protocol received from the communication counterpart device into the second serial signal group; as well as Each serial signal contained in the first serial signal group is sequentially stored in the memory by a shift register in sync with the clock, and each serial signal contained in the second serial signal group is sequentially sent to the master device in sync with the clock.

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