Analog Front End Chip Circuit and Battery Management System

Abstract

The present invention provides an analog front-end chip circuit and a battery management system, including a BAT pin, a PACK pin, and a function selection module, a configurable voltage acquisition module, a voltage comparison module, and a detection result output module that are sequentially connected in series; the configurable voltage acquisition module is connected to the BAT pin and the PACK pin; the BAT pin is connected to an external battery; the PACK pin is connected to an external load or an external charger. In this way, by integrating the charger detection circuit and the load detection circuit into one PIN pin, the number of high-voltage devices in the analog front-end chip is reduced, and thus the area of the analog front-end chip is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of battery management, and more particularly to an analog front-end chip circuit and a battery management system. Background Art

[0002] A BMS system (Battery Management System) is a system for monitoring and managing batteries. By collecting and calculating parameters such as voltage, current, temperature, and SOC, it controls the charging and discharging process of the battery, realizes the protection of the battery, and improves the comprehensive performance of the battery through an electronic and software system.

[0003] In a BMS system with high-side switch control, a dedicated analog front-end chip (AFE) is usually used to collect information such as the voltage, current, and temperature of the battery pack. At the same time, in order to obtain information about the insertion and removal of the battery charger (Charger) and the insertion and removal of the load (Load), the AFE usually needs to internally integrate a dedicated charger detection circuit (Charger Detection Circuit) and a load detection circuit (Load Detection Circuit).

[0004] In existing common charger detection and load detection schemes, an independent chip PIN foot CHARGER is connected to the charger detection circuit, and an independent PIN foot LOAD is connected to the load detection circuit. However, the PIN foot LOAD usually has no other functional role except for load detection. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide an analog front-end chip circuit and a battery management system. By integrating the charger detection circuit and the load detection circuit into one PIN foot, the number of high-voltage devices in the analog front-end chip is reduced, and thus the area of the analog front-end chip is reduced.

[0006] In a first aspect, an embodiment of the present invention provides an analog front-end chip circuit, which includes a BAT pin, a PACK pin, and a function selection module, a configurable voltage acquisition module, a voltage comparison module, and a detection result output module that are sequentially connected in series; the configurable voltage acquisition module is connected to the BAT pin and the PACK pin; the BAT pin is connected to an external battery; the PACK pin is connected to an external load or an external charger; the function selection module is configured to obtain a detection enable signal and send the detection enable signal to the configurable voltage acquisition module; the detection enable signal includes a charger detection enable signal and a load detection enable signal; the configurable voltage acquisition module is configured to output a first voltage to the voltage comparison module when the charger detection enable signal is valid and / or the load detection enable signal is valid; wherein, when the charger detection enable signal is valid, the first voltage is the charger detection voltage; when the load detection enable signal is valid, the first voltage is the load detection voltage; the voltage comparison module is configured to compare the first voltage with a preset reference voltage and output the comparison result to the detection result output module; the detection result output module is configured to output a charger detection result or a load detection result according to the comparison result.

[0007] Further, the function selection module includes a charger detection enable signal input pin, a load detection enable signal input pin, and a first logic gate circuit; the charger detection enable signal input pin is connected to the first logic gate circuit and transmits the charger detection enable signal to the first logic gate circuit; the load detection enable signal input pin is connected to the configurable voltage acquisition module and transmits the load detection enable signal to the configurable voltage acquisition module, and is also connected to the first logic gate circuit and transmits the load detection enable signal to the first logic gate circuit; the first logic gate circuit is configured to generate a control signal based on the received charger detection enable signal and load detection enable signal and output a high level to the configurable voltage acquisition module.

[0008] Further, the configurable voltage acquisition module includes a second PMOS transistor and a voltage dividing resistor array; the gate of the second PMOS transistor is connected to the BAT pin, the source is connected to the PACK pin, and the drain is connected to the voltage dividing resistor array; the voltage dividing resistor array is configured to receive the drain current of the second PMOS transistor when the second PMOS transistor is turned on, generate a charger detection voltage according to the drain current, and output it to the voltage comparison module.

[0009] Further, the configurable voltage acquisition module further includes a first PMOS transistor, a first diode, a fourth resistor, a fifth resistor, and a first resistor, a second resistor, a first NMOS transistor, and a third resistor connected in sequence; the gate of the first NMOS transistor is connected to the function selection module; the drain of the first NMOS transistor is connected to the second end of the second resistor, and the source is connected to the first end of the third resistor; the second end of the third resistor is grounded; the first end of the first resistor and the source of the first PMOS transistor are respectively connected to the BAT pin; the first end of the fourth resistor is connected to the source of the first PMOS transistor; the second end of the fourth resistor is connected to the gate of the second PMOS transistor; the gate of the first PMOS transistor is connected to the second end of the first resistor; the drain of the first PMOS transistor is connected to the first end of the first diode; the second end of the first diode is connected to the first end of the fifth resistor; the fifth resistor, the voltage dividing resistor array, and the drain of the second PMOS transistor intersect at a first common point; the first NMOS transistor is used to turn on when the load detection enable signal is valid, so as to turn on the first PMOS transistor; the voltage dividing resistor array is used to receive the drain current of the first PMOS transistor when the first PMOS transistor is conducting, generate a load detection voltage according to the drain current, and output it to the voltage comparison module.

[0010] Further, the voltage dividing resistor array includes a sixth resistor, a second NMOS transistor, a seventh resistor, a first comparison resistor, and a second comparison resistor connected in sequence; the source of the second NMOS transistor is connected to the first end of the seventh resistor; the gate of the second NMOS transistor is connected to the function selection module; the drain of the second NMOS transistor is connected to the second end of the sixth resistor; the first end of the sixth resistor is connected to the first common point; the second end of the seventh resistor, the first end of the first comparison resistor, and the voltage comparison module intersect at a first node; the second end of the first comparison resistor, the first end of the second comparison resistor, and the voltage comparison module intersect at a second node; the second NMOS transistor is used to turn on when the charger detection enable signal is valid to obtain the drain current of the second PMOS transistor; and turn on when the load detection enable signal is valid to obtain the drain current of the first PMOS transistor; the second comparison resistor is used to generate a charger detection voltage according to the drain current of the second PMOS transistor and send the charger detection voltage to the voltage comparison module through the second node; the first comparison resistor, the sixth resistor, the seventh resistor, and the second comparison resistor are used to generate a load detection voltage according to the drain current of the first PMOS transistor and send the load detection voltage to the voltage comparison module through the first node.

[0011] Further, the voltage comparison module includes a third NMOS transistor, a fourth NMOS transistor, and a comparator; the drain of the third NMOS transistor is connected to the first node; the gate of the third NMOS transistor is connected to the function selection module; the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor; the source of the fourth NMOS transistor is connected to the second node; the gate of the fourth NMOS transistor is connected to the function selection module; the first input terminal of the comparator is connected between the source of the third NMOS transistor and the drain of the fourth NMOS transistor; the second input terminal of the comparator is connected to the reference voltage input terminal; the third NMOS transistor is used to conduct when the load detection enable signal is valid, obtain the load detection voltage and output it to the comparator; the fourth NMOS transistor is used to conduct when the charger detection enable signal is valid, obtain the charger detection voltage and output it to the comparator.

[0012] Further, the voltage division resistor array includes a sixth resistor, a second NMOS transistor, a first comparison resistor, and a second comparison resistor connected in sequence; the voltage comparison module includes a comparator; the source of the second NMOS transistor is connected to the first end of the first comparison resistor; the gate of the second NMOS transistor is connected to the function selection module; the drain of the second NMOS transistor is connected to the second end of the sixth resistor; the first end of the sixth resistor is connected to the first common point; the second end of the second comparison resistor is grounded; the second end of the first comparison resistor, the first end of the second comparison resistor, and the first input terminal of the comparator intersect at the third node; the second input terminal of the comparator is connected to the reference voltage input terminal; the second NMOS transistor is used to turn on when the charger detection enable signal is valid to obtain the drain current of the second PMOS transistor; and turn on when the load detection enable signal is valid to obtain the drain current of the first PMOS transistor; the second comparison resistor is used to generate the charger detection voltage according to the drain current of the second PMOS transistor and send the charger detection voltage to the comparator through the third node; the first comparison resistor, the sixth resistor, and the second comparison resistor are used to generate the load detection voltage according to the drain current of the first PMOS transistor and send the load detection voltage to the comparator through the third node.

[0013] Further, the detection result output module includes a second logic gate circuit, a third logic gate circuit, a charger detection signal output pin, and a load detection signal output pin; the first input terminal of the second logic gate circuit is connected to the load detection enable signal input pin; the first input terminal of the third logic gate circuit is connected to the charger detection enable signal input pin; the second input terminals of the second logic gate circuit and the third logic gate circuit are respectively connected to the voltage comparison module; the output terminal of the second logic gate circuit is connected to the load detection signal output pin; the output terminal of the third logic gate circuit is connected to the charger detection signal output pin.

[0014] Further, the configurable voltage acquisition module further includes a tenth resistor and a third diode; a first end of the tenth resistor is connected to the PACK pin, and a second end of the tenth resistor is connected to the first common point; a first end of the third diode is connected to a drain of the second PMOS transistor; the second end of the tenth resistor is connected to the first common point.

[0015] In a second aspect, an embodiment of the present invention provides a battery management system, including the analog front-end chip circuit of any one of the above, and further including a connected battery pack and a switch group; wherein, the battery pack is connected to the analog front-end chip circuit through the BAT pin; the analog front-end chip circuit is configured to obtain charging detection information and load detection information of the battery management system.

[0016] An embodiment of the present invention provides an analog front-end chip circuit and a battery management system, including a BAT pin, a PACK pin, and a function selection module, a configurable voltage acquisition module, a voltage comparison module, and a detection result output module that are sequentially connected in series; the configurable voltage acquisition module is connected to the BAT pin and the PACK pin; the BAT pin is connected to an external battery; the PACK pin is connected to an external load or an external charger; the function selection module is configured to obtain a detection enable signal and send the detection enable signal to the configurable voltage acquisition module; the detection enable signal includes a charger detection enable signal and a load detection enable signal; the configurable voltage acquisition module is configured to output a first voltage to the voltage comparison module when the charger detection enable signal is valid and / or the load detection enable signal is valid; wherein, when the charger detection enable signal is valid, the first voltage is the charger detection voltage; when the load detection enable signal is valid, the first voltage is the load detection voltage; the voltage comparison module is configured to compare the first voltage with a preset reference voltage and output a comparison result to the detection result output module; the detection result output module is configured to output a charger detection result or a load detection result according to the comparison result. In this way, by integrating the charger detection circuit and the load detection circuit into one PIN pin, the charger detection circuit and the load detection circuit are integrated. No additional low-voltage current source is required, and only one voltage comparison module needs to be reused to complete two functions of charger detection and load detection, thereby reducing the number of high-voltage devices in the analog front-end chip and further reducing the area of the analog front-end chip.

[0017] Other features and advantages of the present invention will be described in the following specification, and part of them will become obvious from the specification, or will be understood by implementing the present invention. The objectives and other advantages of the present invention are achieved and obtained by the structures specifically pointed out in the specification, the claims, and the drawings.

[0018] To make the above objectives, features, and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given in conjunction with the accompanying drawings and described in detail as follows. Description of the Drawings

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 Schematic diagram of the analog front-end chip circuit provided in the first embodiment of the present invention;

[0021] Figure 2 Schematic diagram of the voltage-dividing resistor array 5 and the voltage comparison module 3 provided in the first embodiment of the present invention;

[0022] Figure 3 Schematic diagram of the current path of the external charger of the analog front-end chip circuit provided in the first embodiment of the present invention;

[0023] Figure 4 Schematic diagram of the current path of the external load of the analog front-end chip circuit provided in the first embodiment of the present invention;

[0024] Figure 5 Schematic diagram of the simplified analog front-end chip circuit of the voltage-dividing resistor array provided in the second embodiment of the present invention;

[0025] Figure 6 Schematic diagram of another analog front-end chip circuit provided in the third embodiment of the present invention;

[0026] Figure 7 Schematic diagram of the TV management system provided in the fourth embodiment of the present invention.

[0027] Icon: 1 - Function selection module; 2 - Configurable voltage acquisition module; 3 - Voltage comparison module; 4 - Detection result output module; 5 - Voltage-dividing resistor array. Specific embodiments

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions of the present invention with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0029] For ease of understanding of this embodiment, the following will provide a detailed introduction to the embodiments of the present invention.

[0030] Embodiment 1:

[0031] Figure 1 Schematic diagram of the analog front-end chip circuit provided in the first embodiment of the present invention.

[0032] Refer to Figure 1 , the analog front-end chip (AFE, Analog Front End) includes: a BAT pin, a PACK pin, and a function selection module 1, a configurable voltage acquisition module 2, a voltage comparison module 3, and a detection result output module 4 that are sequentially connected; the configurable voltage acquisition module 2 is connected to the BAT pin and the PACK pin; the BAT pin is connected to an external battery; the PACK pin is connected to an external load or an external charger.

[0033] Here, the function selection module 1 and the detection result output module 4 may or may not be connected; if the voltage comparison module 3 and the detection result output module 4 are connected, the detection result output module 4 can, according to the detection enable signal output by the voltage comparison module 3, after making a logical judgment based on the detection enable signal, determine to output a charger detection result or a load detection result; if the voltage comparison module 3 and the detection result output module 4 are not connected, the analog front-end chip circuit determines the charger detection result or the load detection result output by the detection result output module 4 according to the enable signals input by the BAT pin and the PACK pin.

[0034] The function selection module 1 is used to obtain a detection enable signal and send the detection enable signal to the configurable voltage acquisition module 2; the detection enable signal includes a charger detection enable signal and a load detection enable signal.

[0035] In one embodiment, the charger detection enable signal and the load detection enable signal are intermittently emitted and cannot be emitted simultaneously.

[0036] In one embodiment, refer to Figure 1 , the function selection module 1 includes a charger detection enable signal EN_CHG input pin P1, a load detection enable signal EN_LD input pin P2, and a first logic gate circuit.

[0037] Here, the function selection module 1 further includes a fifth inverter INV5 and a sixth inverter INV6, and the first logic gate circuit includes an OR gate OR1.

[0038] The input pin P1 of the charger detection enable signal EN_CHG is respectively connected to the input terminal of the fifth inverter INV5, the detection result output module 4, and the first input terminal of the OR gate OR1; the input pin P2 of the load detection enable signal EN_LD is respectively connected to the second input terminal of the OR gate OR1 and the detection result output module 4; the output terminal of the fifth inverter INV5 is connected to the input terminal of the sixth inverter INV6; the output terminals of the sixth inverter INV6 and the OR gate OR1 are respectively connected to the configurable voltage acquisition module 2. The input pin P1 of the charger detection enable signal EN_CHG is connected to the first logic gate circuit and transmits the charger detection enable signal to the first logic gate circuit. In an embodiment, the input pin P1 of the charger detection enable signal EN_CHG and the configurable voltage acquisition module 2 can be directly connected or indirectly connected via other components.

[0039] Here, when performing charger detection, the charger detection enable signal EN_CHG output from the input pin P1 of the charger detection enable signal EN_CHG is a logic high level, that is, the charger detection enable signal EN_CHG = 1; when performing load detection, the charger detection enable signal EN_CHG output from the input pin EN_CHG of the charger detection enable signal is a logic low level, that is, the charger detection enable signal EN_CHG = 0.

[0040] The input pin EN_LD of the load detection enable signal is used to obtain the load detection enable signal EN_LD and send the load detection enable signal EN_LD to the OR gate OR1 and the detection result output module 4.

[0041] The input pin P2 of the load detection enable signal EN_LD is connected to the configurable voltage acquisition module 2 and transmits the load detection enable signal to the configurable voltage acquisition module 2, and is also connected to the first logic gate circuit and transmits the load detection enable signal to the first logic gate circuit.

[0042] In an embodiment, the input pin P2 of the load detection enable signal EN_LD and the configurable voltage acquisition module 2 can be directly connected or indirectly connected via other components.

[0043] Here, when the function selection module 1 and the detection result output module 4 are connected to perform charger detection, the charger detection enable signal EN_CHG output from the input pin P1 of the charger detection enable signal EN_CHG is a logic high level, that is, the charger detection enable signal EN_CHG = 1; when the function selection module 1 and the detection result output module 4 are connected to perform load detection, the charger detection enable signal EN_CHG output from the input pin EN_CHG of the charger detection enable signal is a logic low level, that is, the charger detection enable signal EN_CHG = 0.

[0044] The load detection enable signal EN_LD is input to pin P2, which is used to obtain the load detection enable signal EN_LD and send the load detection enable signal EN_LD to the OR gate OR1 and the detection result output module 4.

[0045] When the function selection module 1 is connected to the detection result output module 4 for charger detection, the load detection enable signal EN_LD output from the load detection enable signal input pin is at a logic low level, that is, the load detection enable signal EN_LD = 0; when the function selection module 1 is connected to the detection result output module 4 for load detection, the load detection enable signal EN_LD output from the load detection enable signal input pin is at a logic high level, that is, the load detection enable signal EN_LD = 1.

[0046] The fifth inverter INV5 and the sixth inverter INV6 are used to shape the load detection enable signal EN_LD and output the shaped standard load detection enable signal EN_LD to the configurable voltage acquisition module.

[0047] The first logic gate circuit is used to generate a control signal based on the received charger detection enable signal and load detection enable signal and output a high-level control signal to the configurable voltage acquisition module 2.

[0048] Here, the OR gate OR1 is a logic gate that implements logical OR in digital logic. When both the first input terminal and the second input terminal input low levels, a low level is output; when at least one of the first input terminal and the second input terminal is at a high level, a high level is output.

[0049] The configurable voltage acquisition module 2 is used to output a first voltage to the voltage comparison module 3 when the charger detection enable signal is valid and / or the load detection enable signal is valid; wherein, when the charger detection enable signal is valid, the first voltage is the charger detection voltage; when the load detection enable signal is valid, the first voltage is the load detection voltage.

[0050] Here, the analog front-end chip AFE multiplexes the configurable voltage acquisition module 2 to perform charger detection and load detection. When the charger detection enable signal is valid, it obtains the insertion and removal of the external charger; when the load detection enable signal is valid, it obtains the insertion and removal information of the external load.

[0051] In one embodiment, the charger detection and load detection are performed in time segments to achieve the multiplexing of the configurable voltage acquisition module 2. When the system generates the detection enable signal, it controls the charger detection enable signal EN_CHG and the load detection enable signal EN_LD to be valid only one at the same time.

[0052] In one embodiment, refer toFigure 1 and Figure 2 The configurable voltage acquisition module 2 includes a ninth resistor R9, a second PMOS transistor PM2, a first diode D1, a second diode D2, and a voltage dividing resistor array 5.

[0053] The gate of the second PMOS transistor PM2 and the first end of the first diode D1 are respectively connected to the BAT pin; the first end of the ninth resistor R9 is connected to the PACK pin, and the second end of the ninth resistor R9 is connected to the source of the second PMOS transistor PM2; the drain of the second PMOS transistor PM2 is respectively connected to the second end of the first diode D1 and the voltage dividing resistor array 5; both ends of the second diode D2 are respectively connected to the source and the gate of the second PMOS transistor PM2; the voltage dividing resistor array 5 is connected to the output end of the OR gate OR1.

[0054] The voltage dividing resistor array 5 is configured to receive the drain current of the second PMOS transistor when the second PMOS transistor is turned on, generate a charger detection voltage according to the drain current, and output it to the voltage comparison module.

[0055] In one embodiment, when the no-load voltage of the charger is greater than the battery voltage, the second PMOS transistor PM2 is turned on.

[0056] The first diode D1 is configured to prevent the drain current of the second PMOS transistor PM2 from flowing back to the external battery through the BAT pin when the second PMOS transistor PM2 conducts a detection enable signal.

[0057] Here, in a system (BMS, Battery Management System) for monitoring and managing the battery, the external charger cannot charge the battery through the analog front-end chip, but charges the battery through the charging circuit in the BMS system.

[0058] The second diode D2 is configured to stabilize the gate voltage and the source voltage of the second PMOS transistor PM2 under high voltage.

[0059] Here, the second diode is a Zener diode, because the second PMOS transistor PM2 is not resistant to high voltage, and is used for voltage withstand protection of the second PMOS transistor PM2. If the second diode D2 is not in a high-voltage environment in the analog front-end chip AFE, it can be omitted.

[0060] In one embodiment, referring to Figure 1 The configurable voltage acquisition module 2 further includes a first PMOS transistor PM1, a fourth resistor R4, a fifth resistor R5, and a first resistor R1, a second resistor R2, a first NMOS transistor NM1, and a third resistor R3 connected in sequence.

[0061] The gate of the first NMOS transistor is connected to the function selection module; the drain of the first NMOS transistor is connected to the second terminal of the second resistor, and the source is connected to the first terminal of the third resistor.

[0062] The second terminal of the third resistor is grounded; the first terminal of the first resistor R1 and the source of the first PMOS transistor PM1 are respectively connected to the BAT pin; the first terminal of the fourth resistor R4 is connected to the source of the first PMOS transistor PM1; the second terminal of the fourth resistor R4 is connected to the gate of the second PMOS transistor PM2.

[0063] The gate of the first PMOS transistor PM1 is connected to the second terminal of the first resistor R1; the drain of the first PMOS transistor PM1 is connected to the first terminal of the first diode D1; the second terminal of the first diode D1 is connected to the first terminal of the fifth resistor R5; the fifth resistor R5, the voltage dividing resistor array 5 and the drain of the second PMOS transistor PM2 intersect at the first common point M.

[0064] In one embodiment, the resistance value of the fourth resistor R4 is greater than that of the fifth resistor R5.

[0065] The first NMOS transistor NM1 is used to turn on when the load detection enable signal EN_LD is valid, that is, when the detection enable signal EN_LD = 1, so as to turn on the first PMOS transistor PM1 to establish an internal path of the detection circuit between the external battery and the external load, that is, as Figure 4 shown, the current path 1 formed by the BAT pin, the first PMOS transistor PM1, the first diode D1, the fifth resistor R5, the second PMOS transistor PM2 and the ninth resistor R9.

[0066] The voltage dividing resistor array 5 is further used to receive the drain current of the first PMOS transistor PM1 when the first PMOS transistor is conducting, generate a load detection voltage according to the drain current, and output it to the voltage comparison module 3. When the load detection enable signal EN_LD is valid, that is, when the detection enable signal EN_LD = 1, the first common point voltage V M is obtained through the current path 1, and a load detection voltage is generated according to the first common point voltage V M and output to the voltage comparison module;

[0067] The fourth resistor R4 is used to reduce Figure 4 the current on the current path 3 shown, that is, the current path 3 formed by the BAT pin, the second diode and the ninth resistor.

[0068] Here, in the BMS system, the external battery cannot supply power to the external load through the analog front-end chip, but supplies power to the external load through the power supply circuit in the BMS system.

[0069] The voltage comparison module 3 is used to compare the first voltage with the preset reference voltage VREF Compare. When the first voltage is greater than the reference voltage V REF , output a high level to the detection result output module 4; otherwise, output a low level to the detection result output module 4.

[0070] Here, the preset reference voltage V REF is the reference voltage V inside the chip REF , which is set according to the actual situation.

[0071] In one embodiment, the voltage comparison module 3 is multiplexed by the charger detection function and the load detection function.

[0072] The detection result output module 4 is used to output the final detection result according to the voltage comparison result of the voltage comparison module 3 and the detection enable signal provided by the function selection module 1.

[0073] In one embodiment, when the detection result output module 4 receives a high level of the voltage comparison result and the charger detection EN_CHG = 1, it outputs the charger detection signal CHARGER_DET as a high level CHARGER_DET = 1, which means the charger is inserted; when it receives a high level of the voltage comparison result and the load detection enable signal EN_LD = 1, it outputs the load detection signal LOAD_DET as a high level LOAD_DET = 1, which means the load is removed.

[0074] Figure 2 This is a schematic diagram of the voltage dividing resistor array 5 and the voltage comparison module 3 provided in the first embodiment of the present invention.

[0075] Figure 3 This is a schematic diagram of the external charger current path of the analog front-end chip circuit provided in the first embodiment of the present invention. In one embodiment, referring to Figure 2 , the voltage dividing resistor array 5 includes a sixth resistor R6, a second NMOS transistor NM2, a seventh resistor R7, a first comparison resistor R8a, and a second comparison resistor R8b connected in sequence.

[0076] The source of the second NMOS transistor NM2 is connected to the first end of the seventh resistor R7; the gate of the second NMOS transistor NM2 is connected to the function selection module 1; the drain of the second NMOS transistor NM2 is connected to the second end of the sixth resistor R6; the first end of the sixth resistor R6 is connected to the first common point M; the second end of the second comparison resistor R8b is grounded; both ends of the first comparison resistor R8a are connected to the voltage comparison module 3.

[0077] The source of the second NMOS transistor NM2 is connected to the first end of the seventh resistor R7; the gate of the second NMOS transistor NM2 is connected to the output terminal of the OR gate OR1; the drain of the second NMOS transistor NM2 is connected to the second end of the sixth resistor R6; the first end of the sixth resistor R6 is connected to the first common point M; the second end of the second comparison resistor R8b is grounded; the second end of the seventh resistor R7, the first end of the first comparison resistor R8a, and the voltage comparison module 3 intersect at the first node VLD; the second end of the first comparison resistor R8a, the first end of the second comparison resistor R8b, and the voltage comparison module 3 intersect at the second node VCHG.

[0078] The second comparison resistor R8b is configured to generate a charger detection voltage according to Figure 3 the current path shown, and send the charger detection voltage to the voltage comparison module 3 through the second node VCHG.

[0079] The first comparison resistor R8a, the sixth resistor R6, the seventh resistor R7, and the second comparison resistor R8b are configured to generate a load detection voltage according to the voltage of the first common point M, and send the load detection voltage to the voltage comparison module 3 through the first node VLD.

[0080] In one embodiment, referring to Figure 2 , the voltage comparison module 3 includes a third NMOS transistor NM3, a fourth NMOS transistor NM4, a comparator COMP1, and a Schmitt trigger SMT1, a first inverter INV1, and a second inverter INV2 connected in sequence.

[0081] The drain of the third NMOS transistor NM3 is connected to the first node VLD; the gate of the third NMOS transistor NM3 is connected to the load detection enable signal input pin; the source of the third NMOS transistor NM3 is connected to the drain of the fourth NMOS transistor NM4.

[0082] The source of the fourth NMOS transistor NM4 is connected to the second node VCHG; the gate of the fourth NMOS transistor NM4 is connected to the charger detection enable signal input pin.

[0083] The positive input terminal of the comparator COMP1 is connected to the source of the third NMOS transistor NM3 and the drain of the fourth NMOS transistor NM4; the negative input terminal of the comparator COMP1 is connected to the reference voltage input terminal; the output terminal of the comparator COMP1 is connected to the input terminal of the Schmitt trigger SMT1.

[0084] Here, the comparator COMP1 is connected to the voltage dividing resistor array through two taps. The number of taps can be adjusted according to the set threshold.

[0085] The third NMOS transistor NM3 is used to conduct when the load detection enable signal is valid, i.e., EN_LD = 1, and introduce the load detection voltage to the input terminal of the comparator COMP1.

[0086] The fourth NMOS transistor NM4 is used to conduct when the charger detection enable signal is valid, i.e., EN_CHG = 1, and introduce the charger detection voltage to the input terminal of the comparator COMP1.

[0087] The comparator COMP1 is used to compare the first voltage with the reference voltage. When the first voltage is greater than the reference voltage, it outputs a high level to the Schmitt trigger SMT1; otherwise, it outputs a low level to the Schmitt trigger SMT1.

[0088] The Schmitt trigger SMT1 is used to improve the anti-interference ability of the output level and output the output level after anti-interference processing to the first inverter INV1.

[0089] Here, the Schmitt trigger SMT1 can be combined with the comparator.

[0090] The first inverter INV1 and the second inverter INV2 are used to shape the output level into a standard level and then output it to the detection result output module 4.

[0091] Here, the first inverter INV1 and the second inverter INV2 can be omitted.

[0092] In one embodiment, referring to Figure 3 , when the analog front-end chip circuit performs the charger detection function, the charger detection enable signal EN_CHG is set to a logic high level, and the load detection enable signal EN_LD is set to a logic low level, and the second NMOS transistor NM2 is turned on. When the charger is connected to the circuit, the no-load voltage V2 of the charger is greater than the battery voltage V1, and at this time PM2 is turned on. Let the threshold voltage of the second PMOS transistor PM2 be Vthp. Among them, Vthp = 0.7V, and the voltage difference between the no-load voltage V2 of the charger and the battery voltage V1 can be set to 1 - 2V.

[0093] The current of the ninth resistor, that is, the current in the entire current path, is shown in the following formula (1):

[0094]

[0095] Among them, I is the current in the entire current path, V2 is the charger voltage at the PACK pin, V1 is the battery voltage at the BAT pin, R9 is the resistance value of the ninth resistor, and V thp is the threshold voltage of the second PMOS transistor PM2.

[0096] The voltage at the second node of the voltage dividing resistor array 5 is shown in the following formula (2):

[0097]

[0098] Among them, V CHG is the second node voltage, and R 8b is the resistance value of the second comparison resistor.

[0099] In the voltage comparison module 3, when the second node voltage V CHG ≥V REF , in the detection result output module 4, the charger detection signal CHARGER_DET changes from low level to high level. Therefore, when the analog front-end chip performs charger detection, the threshold voltage it can detect is as shown in formula (3):

[0100]

[0101] Among them, VTH CHG is the threshold voltage for the analog front-end chip to perform charger detection.

[0102] Figure 4 This is a schematic diagram of the external load current path of the analog front-end chip circuit provided in the first embodiment of the present invention.

[0103] In one embodiment, referring to Figure 4 , when the analog front-end chip circuit executes the load detection function, the charger detection enable signal EN_CHG is set to logic low level, the load detection enable signal EN_LD is set to logic high level, the second NMOS transistor NM2 is turned on, and the first NMOS transistor NM1 is also turned on. Theoretically, there are 3 current paths from V1 to ground, which are respectively Figure 4 the current path 1, current path 2, and current path 3 in. It should be noted that the circuit path 1 includes the body diode of the second PMOS transistor PM2. By setting the fourth resistor R4 to be much larger than the fifth resistor R5 and the sixth resistor R6 in parameter setting, the current path 3 can be ignored.

[0104] Assume that the resistance value of the external load resistor is R load , the voltage drop generated by the first diode D1 is V d , among which, the voltage drop V d =0.7V, and the voltage V M of the first common point M is as shown in formula (4):

[0105]

[0106] Among them, V M is the voltage of the first common point M, V1 is the battery voltage externally connected to the BAT pin, V d is the voltage drop of the first diode, R5 is the resistance value of the fifth resistor, R6 is the resistance value of the sixth resistor, R7 is the resistance value of the seventh resistor, R8a is the resistance value of the first comparison resistor, R 8b is the resistance value of the second comparison resistor, R load is the resistance value of the external load resistor, R9 is the resistance value of the ninth resistor, R nm is the resistance value of the second NMOS transistor NM2.

[0107] The required load detection threshold can be set by flexibly configuring the circuit parameters. Assuming that the threshold for load detection needs to be set to R th , the following conditions are set as shown in formula (5):

[0108] R9 = R th , R5 = 2×R th , R7 + R 8a +R 8b = K×R th , R6 = K×M×R th (5)

[0109] When K×M ≥ 10, when the load is close to R th nearby, the voltage dividing resistor array is equivalent to a voltmeter, and the influence of current path 2 can be ignored. At this time, the voltage V M at the first common point M is as shown in formula (6):

[0110]

[0111] Thus, the voltage at the first node can be obtained as shown in formula (7):

[0112]

[0113] Set R 8a +R 8b > 10×R nm , then the influence of R nm can be ignored within a certain accuracy range, and thus formula (8) is obtained:

[0114]

[0115] Therefore, when it is set that V LD = V REF , the load detection threshold can be set to R th .

[0116] An embodiment of the present invention provides an analog front-end chip circuit, which includes a BAT pin, a PACK pin, and a function selection module, a configurable voltage acquisition module, a voltage comparison module, and a detection result output module that are sequentially connected in sequence; the configurable voltage acquisition module is connected to the BAT pin and the PACK pin; the BAT pin is connected to an external battery; the PACK pin is connected to an external load or an external charger; the function selection module is configured to obtain a detection enable signal and send the detection enable signal to the configurable voltage acquisition module; the detection enable signal includes a charger detection enable signal and a load detection enable signal; the configurable voltage acquisition module is configured to output a first voltage to the voltage comparison module when the charger detection enable signal is valid and / or the load detection enable signal is valid; wherein, when the charger detection enable signal is valid, the first voltage is the charger detection voltage; when the load detection enable signal is valid, the first voltage is the load detection voltage; the voltage comparison module is configured to compare the first voltage with a preset reference voltage and output the comparison result to the detection result output module; the detection result output module is configured to output a charger detection result or a load detection result according to the comparison result. In this way, by integrating the charger detection circuit and the load detection circuit into one PIN, the number of high-voltage devices in the analog front-end chip is reduced, and thus the area of the analog front-end chip is reduced.

[0117] Embodiment 2:

[0118] Figure 5 It is a schematic diagram of a voltage-dividing resistor array simplified analog front-end chip circuit provided by Embodiment 2 of the present invention.

[0119] Refer to Figure 5 , an analog front-end chip (AFE, Analog Front End) includes: a BAT pin, a PACK pin, and a function selection module 1, a configurable voltage acquisition module 2, a voltage comparison module 3, and a detection result output module 4 that are sequentially connected in sequence; the function selection module 1 is also connected to the detection result output module 4; the BAT pin and the PACK pin are arranged on the configurable voltage acquisition module 2; the BAT pin is connected to an external battery; the PACK pin is connected to an external load or an external charger.

[0120] In one embodiment, refer to Figure 5 , the voltage-dividing resistor array 5 includes a sixth resistor R6, a second NMOS transistor NM2, a first comparison resistor R8a, and a second comparison resistor R8b that are sequentially connected.

[0121] The source of the second NMOS transistor NM2 is connected to the first comparison resistor R8a; the gate of the second NMOS transistor NM2 is connected to the output terminal of the OR gate OR1; the drain of the second NMOS transistor NM2 is connected to the second end of the sixth resistor R6.

[0122] The first end of the sixth resistor R6 is connected to the first common point M; the second end of the second comparison resistor R8b is grounded; the second end of the first comparison resistor R8a, the first end of the second comparison resistor R8b, and the voltage comparison module 3 intersect at a third node.

[0123] The second NMOS transistor NM2 is used to turn on when the charger detection enable signal is valid to obtain the ninth resistor current; and turn on when the load detection enable signal is valid to obtain the voltage of the first common point M.

[0124] The second comparison resistor R8b is used to generate a charger voltage based on the ninth resistor current and send the charger voltage to the voltage comparison module 3 through the third node.

[0125] The first comparison resistor R8a, the sixth resistor R6, and the second comparison resistor R8b are used to generate a load voltage based on the voltage of the first common point M and send the load voltage to the voltage comparison module 3 through the third node.

[0126] Here, through reasonable circuit parameter configuration, the tap of the voltage division resistor array 5 can be adjusted to one by adjusting the threshold.

[0127] In one embodiment, referring to Figure 5 , the voltage comparison module 3 includes a comparator COMP1 and a Schmidt trigger SMT1, a first inverter INV1, and a second inverter INV2 connected in sequence.

[0128] The positive input terminal of the comparator COMP1 is connected to the third node; the negative input terminal of the comparator COMP1 is connected to the reference voltage input terminal; the output terminal of the comparator COMP1 is connected to the input terminal of the Schmidt trigger SMT1.

[0129] An embodiment of the present invention provides an analog front-end chip circuit, which includes a BAT pin, a PACK pin, and a function selection module, a configurable voltage acquisition module, a voltage comparison module, and a detection result output module that are sequentially connected in series; the configurable voltage acquisition module is connected to the BAT pin and the PACK pin; the BAT pin is connected to an external battery; the PACK pin is connected to an external load or an external charger; the function selection module is configured to obtain a detection enable signal and send the detection enable signal to the configurable voltage acquisition module; the detection enable signal includes a charger detection enable signal and a load detection enable signal; the configurable voltage acquisition module is configured to output a first voltage to the voltage comparison module when the charger detection enable signal is valid and / or the load detection enable signal is valid; wherein, when the charger detection enable signal is valid, the first voltage is the charger detection voltage; when the load detection enable signal is valid, the first voltage is the load detection voltage; the voltage comparison module is configured to compare the first voltage with a preset reference voltage and output the comparison result to the detection result output module; the detection result output module is configured to output a charger detection result or a load detection result according to the comparison result. In this way, by adjusting the threshold value, the number of resistors and taps in the voltage division resistor array is reduced, thereby reducing the number of high-voltage devices in the analog front-end chip, and further reducing the area of the analog front-end chip.

[0130] Embodiment 3:

[0131] Figure 6 Another schematic diagram of the analog front-end chip circuit provided by Embodiment 3 of the present invention.

[0132] Refer to Figure 6 , the analog front-end chip (AFE, Analog Front End) includes: a BAT pin, a PACK pin, and a function selection module 1, a configurable voltage acquisition module 2, a voltage comparison module 3, and a detection result output module 4 that are sequentially connected in series; the function selection module 1 is also connected to the detection result output module 4; the BAT pin and the PACK pin are arranged on the configurable voltage acquisition module 2; the BAT pin is connected to an external battery; the PACK pin is connected to an external load or an external charger.

[0133] In one embodiment, in order to reduce the influence of the BJT device in the second PMOS transistor PM2 during load detection, the configurable voltage acquisition module further includes a tenth resistor R10 and a third diode D3.

[0134] The first end of the tenth resistor R10 is connected to the PACK pin, and the second end of the tenth resistor R10 is connected to the first common point M.

[0135] The first end of the third diode D3 is connected to the drain of the second PMOS transistor; the second end of the tenth resistor R10 is connected to the first common point M1.

[0136] In one embodiment, the voltage comparison module 3 includes a first comparator COMP1, a first Schmitt trigger SMT1, a first inverter INV1, and a second inverter INV2 connected in sequence, and a second comparator COMP2, a second Schmitt trigger SMT2, a third inverter INV3, and a fourth inverter INV4 connected in sequence.

[0137] The first input terminal of the first comparator COMP1 is connected to the first intersection point; the second input terminal of the first comparator COMP1 is connected to the reference voltage input terminal; the output terminal of the first comparator COMP1 is connected to the input terminal of the first Schmitt trigger SMT1; the output terminal of the second inverter INV2 is connected to the load detection signal output pin.

[0138] The first input terminal of the second comparator COMP2 is connected to the second intersection point; the second input terminal of the second comparator COMP2 is connected to the reference voltage input terminal; the output terminal of the second comparator COMP2 is connected to the input terminal of the second Schmitt trigger SMT2; the output terminal of the fourth inverter INV4 is connected to the charger detection signal output pin. An embodiment of the present invention provides an analog front-end chip circuit, including a BAT pin, a PACK pin, and a function selection module, a configurable voltage acquisition module, a voltage comparison module, and a detection result output module connected in sequence; the configurable voltage acquisition module is connected to the BAT pin and the PACK pin; the BAT pin is connected to an external battery; the PACK pin is connected to an external load or an external charger; the function selection module is configured to obtain a detection enable signal and send the detection enable signal to the configurable voltage acquisition module; the detection enable signal includes a charger detection enable signal and a load detection enable signal; the configurable voltage acquisition module is configured to output a first voltage to the voltage comparison module when the charger detection enable signal is valid and / or the load detection enable signal is valid; wherein, when the charger detection enable signal is valid, the first voltage is the charger detection voltage; when the load detection enable signal is valid, the first voltage is the load detection voltage; the voltage comparison module is configured to compare the first voltage with a preset reference voltage and output the comparison result to the detection result output module; the detection result output module is configured to output a charger detection result or a load detection result according to the comparison result. In this way, by separately providing two comparators in the voltage comparison module, the voltage comparison is made more accurate.

[0139] Embodiment 4:

[0140] Figure 7 It is a schematic diagram of the TV management system provided by Embodiment 4 of the present invention.

[0141] Refer to Figure 7, a battery management system, including the analog front-end chip circuit of any one of the above, further includes a connected battery pack and a switch group; wherein, the battery pack is connected to the analog front-end chip circuit through the BAT pin; the analog front-end chip circuit is used to obtain the charging detection information and load detection information of the battery management system.

[0142] An embodiment of the present invention provides a battery management system, which combines the charger detection circuit and the load detection circuit into one PIN foot, thereby reducing the number of high-voltage devices in the analog front-end chip, and further reducing the area of the analog front-end chip.

[0143] The computer program product provided by the embodiment of the present invention includes a computer-readable storage medium storing program code, and the instructions included in the program code can be used to execute the method described in the foregoing method embodiment. For specific implementation, reference can be made to the method embodiment, which will not be elaborated here.

[0144] Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the above-described systems and devices can refer to the corresponding processes in the foregoing method embodiments, which will not be elaborated here.

[0145] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0146] If the above function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program code.

[0147] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0148] Finally, it should be noted that the above-described embodiments are only specific embodiments of the present invention, used to illustrate the technical solutions of the present invention, rather than limiting it. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that any person skilled in the art within the technical scope disclosed by the present invention can still modify the technical solutions described in the foregoing embodiments or can easily conceive of changes, or make equivalent replacements for some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. An analog front-end chip circuit, characterized in that It includes a BAT pin, a PACK pin, and a function selection module, a configurable voltage acquisition module, a voltage comparison module, and a detection result output module connected in sequence; the configurable voltage acquisition module is connected to the BAT pin and the PACK pin; the BAT pin is connected to an external battery; the PACK pin is connected to an external load or an external charger; The function selection module is used to obtain a detection enable signal and send the detection enable signal to the configurable voltage acquisition module; the detection enable signal includes a charger detection enable signal and a load detection enable signal; The configurable voltage acquisition module is used to output a first voltage to the voltage comparison module when the charger detection enable signal is valid and / or the load detection enable signal is valid; wherein, when the charger detection enable signal is valid, the first voltage is the charger detection voltage; when the load detection enable signal is valid, the first voltage is the load detection voltage; The voltage comparison module is used to compare the first voltage with a preset reference voltage and output the comparison result to the detection result output module; The detection result output module is used to output a charger detection result or a load detection result according to the comparison result.

2. The analog front-end chip circuit according to claim 1, wherein The function selection module includes a charger detection enable signal input pin, a load detection enable signal input pin, and a first logic gate circuit; The charger detection enable signal input pin is connected to the first logic gate circuit and transmits the charger detection enable signal to the first logic gate circuit; The load detection enable signal input pin is connected to the configurable voltage acquisition module and transmits the load detection enable signal to the configurable voltage acquisition module, and is also connected to the first logic gate circuit and transmits the load detection enable signal to the first logic gate circuit; The first logic gate circuit is used to generate a control signal based on the received charger detection enable signal and load detection enable signal and output a high level to the configurable voltage acquisition module.

3. The analog front-end chip circuit according to claim 1, wherein The configurable voltage acquisition module includes a second PMOS transistor and a voltage dividing resistor array; The gate of the second PMOS transistor is connected to the BAT pin, the source is connected to the PACK pin, and the drain is connected to the voltage dividing resistor array; The voltage dividing resistor array is used to receive the drain current of the second PMOS transistor when the second PMOS transistor is turned on, generate the charger detection voltage according to the drain current, and output it to the voltage comparison module.

4. The analog front-end chip circuit according to claim 3, wherein The configurable voltage acquisition module further includes a first PMOS transistor, a first diode, a fourth resistor, a fifth resistor, and a first resistor, a second resistor, a first NMOS transistor, and a third resistor connected in sequence; The gate of the first NMOS transistor is connected to the function selection module; the drain of the first NMOS transistor is connected to the second end of the second resistor, and the source is connected to the first end of the third resistor; The second terminal of the third resistor is grounded; the first terminal of the first resistor and the source of the first PMOS transistor are respectively connected to the BAT pin; the first terminal of the fourth resistor is connected to the source of the first PMOS transistor; the second terminal of the fourth resistor is connected to the gate of the second PMOS transistor; The gate of the first PMOS transistor is connected to the second terminal of the first resistor; the drain of the first PMOS transistor is connected to the first terminal of the first diode; the second terminal of the first diode is connected to the first terminal of the fifth resistor; the fifth resistor, the voltage dividing resistor array and the drain of the second PMOS transistor intersect at a first common point; The first NMOS transistor is used to turn on when the load detection enable signal is valid, so as to turn on the first PMOS transistor; The voltage dividing resistor array is used to receive the drain current of the first PMOS transistor when the first PMOS transistor is conducting, generate a load detection voltage according to the drain current, and output it to the voltage comparison module.

5. The analog front-end chip circuit according to claim 4, wherein The voltage dividing resistor array includes a sixth resistor, a second NMOS transistor, a seventh resistor, a first comparison resistor and a second comparison resistor connected in sequence; The source of the second NMOS transistor is connected to the first terminal of the seventh resistor; the gate of the second NMOS transistor is connected to the function selection module; the drain of the second NMOS transistor is connected to the second terminal of the sixth resistor; the first terminal of the sixth resistor is connected to the first common point; the second terminal of the seventh resistor, the first terminal of the first comparison resistor and the voltage comparison module intersect at a first node; the second terminal of the first comparison resistor, the first terminal of the second comparison resistor and the voltage comparison module intersect at a second node; The second NMOS transistor is used to turn on when the charger detection enable signal is valid to obtain the drain current of the second PMOS transistor; and turn on when the load detection enable signal is valid to obtain the drain current of the first PMOS transistor; The second comparison resistor is used to generate the charger detection voltage according to the drain current of the second PMOS transistor, and send the charger detection voltage to the voltage comparison module through the second node; The first comparison resistor, the sixth resistor, the seventh resistor and the second comparison resistor are used to generate the load detection voltage according to the drain current of the first PMOS transistor, and send the load detection voltage to the voltage comparison module through the first node.

6. The analog front-end chip circuit according to claim 5, characterized in that, The voltage comparison module includes a third NMOS transistor, a fourth NMOS transistor and a comparator; The drain of the third NMOS transistor is connected to the first node; the gate of the third NMOS transistor is connected to the function selection module; the source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor; The source of the fourth NMOS transistor is connected to the second node; the gate of the fourth NMOS transistor is connected to the function selection module; The first input terminal of the comparator is connected between the source of the third NMOS transistor and the drain of the fourth NMOS transistor; the second input terminal of the comparator is connected to the reference voltage input terminal; The third NMOS transistor is used to conduct when the load detection enable signal is valid, obtain the load detection voltage and output it to the comparator; The fourth NMOS transistor is used to conduct when the charger detection enable signal is valid, obtain the charger detection voltage and output it to the comparator.

7. The analog front-end chip circuit according to claim 4, wherein The voltage dividing resistor array includes a sixth resistor, a second NMOS transistor, a first comparison resistor, and a second comparison resistor connected in sequence; the voltage comparison module includes a comparator; the source of the second NMOS transistor is connected to the first end of the first comparison resistor; the gate of the second NMOS transistor is connected to the function selection module; the drain of the second NMOS transistor is connected to the second end of the sixth resistor; The first end of the sixth resistor is connected to the first common point; the second end of the second comparison resistor is grounded; the second end of the first comparison resistor, the first end of the second comparison resistor, and the first input terminal of the comparator intersect at a third node; The second input terminal of the comparator is connected to the reference voltage input terminal; The second NMOS transistor is used to turn on when the charger detection enable signal is valid to obtain the drain current of the second PMOS transistor; and turn on when the load detection enable signal is valid to obtain the drain current of the first PMOS transistor; The second comparison resistor is used to generate a charger detection voltage according to the drain current of the second PMOS transistor and send the charger detection voltage to the comparator through the third node; The first comparison resistor, the sixth resistor, and the second comparison resistor are used to generate the load detection voltage according to the drain current of the first PMOS transistor and send the load detection voltage to the comparator through the third node.

8. The analog front-end chip circuit according to claim 2, characterized in that The detection result output module includes a second logic gate circuit, a third logic gate circuit, a charger detection signal output pin, and a load detection signal output pin; The first input terminal of the second logic gate circuit is connected to the load detection enable signal input pin; the first input terminal of the third logic gate circuit is connected to the charger detection enable signal input pin; the second input terminals of the second logic gate circuit and the third logic gate circuit are respectively connected to the voltage comparison module; the output terminal of the second logic gate circuit is connected to the load detection signal output pin; the output terminal of the third logic gate circuit is connected to the charger detection signal output pin.

9. The analog front-end chip circuit according to claim 4, wherein The configurable voltage acquisition module further includes a tenth resistor and a third diode; The first end of the tenth resistor is connected to the PACK pin, and the second end of the tenth resistor is connected to the first common point; The first end of the third diode is connected to the drain of the second PMOS transistor; the second end of the tenth resistor is connected to the first common point.

10. A battery management system includes the analog front-end chip circuit described in any one of claims 1-9, and further includes a battery pack and a switch group connected thereto; wherein, The battery pack is connected to the analog front-end chip circuit through the BAT pin; the analog front-end chip circuit is used to obtain the charging detection information and load detection information of the battery management system.

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