Control device, display device, and control method

Abstract

Provided are a control device, a display device, and a control method that can both prevent flickering and suppress delays during image switching. The control device (20) is a control device for a display panel (10) when the correct frame period is not known in advance. The frame period is a period during which the same image is continuously displayed, and the frame period varies or temporarily stabilizes within a certain range for each frame. When a frame having a length exceeding a predetermined number of lines is input, the control device (20) controls the display panel (10) in such a manner that an image is displayed by a frame period corresponding to the predetermined number of lines and an additional period added after the frame period. The additional period includes one or more individual additional periods each including a light-emitting period and an extinction period, and each of the one or more individual additional periods is a period corresponding to the predetermined number of lines.

Description

Technical Field

[0001] The present disclosure relates to a control device, a display device, and a control method, and in particular to a control device, a display device, and a control method for controlling the display brightness of a display. Background Art

[0002] Techniques for suppressing visually detectable flicker in display devices have been previously discussed. For example, a technique has been discussed in which the number of subframes constituting a single frame period is varied according to a duty cycle set in accordance with brightness information, so that the duty cycle within a subframe is the same as the duty cycle of a single frame period. This allows for suppressing flicker on the display screen even when the light emission period is changed due to brightness adjustment or other means.

[0003] Furthermore, in recent years, image rendering on displays of personal computers, mobile devices, and the like has increasingly been performed by image processing devices called GPUs (Graphics Processing Units). Furthermore, the display speed of a display is determined by the performance of the GPU. In other words, the frame rate (frame duration) has recently fluctuated depending on the content processed by the GPU.

[0004] Therefore, patent documents 1 and 2 disclose control devices that can suppress flicker even when the frame period varies. For example, patent document 1 discloses a technology that controls the length of the extinction period when an extended period is provided, based on the ratio of the number of vertical lines representing the frame period of the current frame to a predetermined minimum number of vertical lines, so that the ratio of the length of the luminous period to the length of the extinction period in the frame period when displaying an image of the vertical number of lines of the current frame becomes constant. In addition, for example, patent document 2 discloses a technology that controls the length of the extinction period when an extended period is provided, in which the frame period is composed of an image period and an extended period, the display panel is illuminated during the image period, and the display panel is controlled in such a manner that the display panel is illuminated and extinguished at a predetermined duty cycle during the extended period.

[0005] (Prior art literature)

[0006] (Patent Document)

[0007] Patent Document 1: Japanese Patent Application Publication No. 2019-015794

[0008] Patent Document 2: Japanese Patent Application Publication No. 2018-205457

[0009] However, in the techniques of Patent Documents 1 and 2, images are switched in sub-frame units (line units), so depending on the timing of obtaining a video signal, a delay may occur until an image corresponding to the video signal is displayed. Summary of the Invention

[0010] Therefore, the present disclosure provides a control device, a display device, and a control method that can suppress both the flicker phenomenon and the delay when switching images.

[0011] One scheme of the present disclosure involves a control device for a display panel in a case where the correct frame period is not known in advance, wherein the frame period is a period during which the same image is continuously displayed, and the frame period varies within a certain range or is temporarily stabilized for each frame. When a frame having a length exceeding a predetermined number of rows is input, the control device controls the display panel in a manner of displaying an image by a frame period corresponding to the predetermined number of rows and an additional period added after the frame period, wherein the additional period includes one or more individual additional periods, and each of the one or more individual additional periods includes a light-emitting period and an extinction period, and each of the one or more individual additional periods is a period corresponding to the predetermined number of rows.

[0012] A display device according to one embodiment of the present disclosure comprises: the control device described above; and the display panel having a gate drive circuit and a source drive circuit, wherein the gate drive circuit receives a control signal from the control device, and the source drive circuit receives an image signal from the control device.

[0013] A control method involved in one scheme of the present disclosure is a control method for a display panel when the correct frame period is not known in advance, the frame period is a period during which the same image is continuously displayed, the frame period varies within a certain range or is temporarily stabilized for each frame, and when a frame having a length exceeding a predetermined number of rows is input, the display panel is controlled in a manner of displaying an image during a frame period corresponding to the predetermined number of rows and an additional period added after the frame period, the additional period including one or more individual additional periods, each of the one or more individual additional periods including a light-emitting period and an extinction period, and each of the one or more individual additional periods is a period corresponding to the predetermined number of rows.

[0014] According to one aspect of the present disclosure, a control device or the like can be realized that can suppress both flickering and delay in image switching. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram showing a configuration example of a display device in an embodiment.

[0016] Figure 2 This is a circuit diagram schematically showing the configuration of a pixel circuit in an embodiment.

[0017] Figure 3 1 is a diagram showing a configuration of a gate drive circuit in an embodiment.

[0018] Figure 4 FIG. 1 is a diagram showing an example of a gate control signal output from a gate drive circuit under control of a control device in a comparative example.

[0019] Figure 5 1 is a diagram showing an example of a gate control signal output from a gate drive circuit under control of a control device in an embodiment.

[0020] Figure 6 1 is a diagram showing an example of a control signal input to a gate drive circuit in an embodiment.

[0021] Figure 7 This is a diagram showing a control signal input to the AND circuit corresponding to the first row of the gate driving circuit in an embodiment, and a gate control signal for the first row in an additional period output from the AND circuit corresponding to the first row based on the control signal.

[0022] Figure 8 1 is a diagram showing gate control signals for each row in the embodiment.

[0023] Figure 9 This is a flowchart showing the operation of the control device in the embodiment.

[0024] Figure 10 This is a diagram showing an example of a gate control signal output from a gate drive circuit under control of a control device in Modification 1 of the embodiment.

[0025] Figure 11 1 and 2 are diagrams illustrating gate control signals output from a gate driving circuit under control of a control device and the operation of a display panel in Modification 1 of the embodiment.

[0026] Figure 12 It is a diagram for explaining a writing operation performed by the control device in the first modification of the embodiment.

[0027] Figure 13 This is a diagram showing the configuration of a gate drive circuit in a second modification of the embodiment.

[0028] Figure 14 This is a diagram showing gate control signals for each row in Modification 2 of the embodiment.

[0029] Explanation of symbols

[0030] 1 Display device

[0031] 10 Display Panel

[0032] 12 Display unit

[0033] 14, 14a Gate drive circuit

[0034] 16 Source driver circuit

[0035] 20 Control device

[0036] 30 pixel circuit

[0037] 32 light-emitting elements

[0038] 33 driver transistor

[0039] 34, 36, 37 Switching transistors

[0040] 35 Select transistor

[0041] 38 pixel capacitors

[0042] 39 EL capacitor

[0043] 40 scan lines

[0044] 42 signal lines

[0045] 100 1st register unit

[0046] 110, 120, 130, 210, 220, 230 shift registers

[0047] 200 Second register unit

[0048] 211, 221, 231 AND circuits

[0049] 300 Output

[0050] 310, 320, 330 OR circuits DETAILED DESCRIPTION

[0051] The following describes the embodiments with reference to the drawings.

[0052] In addition, the embodiments described below are all examples showing the generality or specificity of the present disclosure. The numerical values, shapes, constituent elements, configuration positions of constituent elements, connection forms, steps, order of steps, etc. shown in the following embodiments are all examples, and their main purpose is not to limit the present disclosure. For example, terms such as consistent and identical that indicate the relationship between elements, as well as numerical values and numerical ranges, not only represent expressions in a strict sense, but also represent expressions with actually equivalent ranges, such as expressions including differences of about a few percent (for example, about 5%). Furthermore, among the constituent elements of the following embodiments, the constituent elements that are not recorded in the independent technical solutions are described as arbitrary constituent elements.

[0053] In addition, each figure is a schematic diagram and is not a strict illustration. Therefore, for example, the scale etc. in each figure are not consistent. In addition, in each figure, the same symbols are given to substantially the same structure, and repeated descriptions are omitted or simplified.

[0054] (Implementation Method)

[0055] Regarding the control device and the like according to this embodiment, reference is made to Figures 1 to 9 In this embodiment, an example in which an organic electroluminescence (EL) element is used as a display device will be described.

[0056] [1. Structure of Display Device]

[0057] First, regarding the structure of a display device having a control device according to one embodiment of the present disclosure, refer to Figure 1 To explain. Figure 1 It is a schematic diagram showing a configuration example of the display device 1 in this embodiment.

[0058] like Figure 1 As shown, the display device 1 is composed of a display panel 10 and a control device 20. The display device 1 is driven, for example, by a row-by-row driving method of an organic electroluminescent panel.

[0059] [1-1. Structure of Display Panel]

[0060] The display panel 10 includes a display unit 12 having a plurality of pixel circuits 30, and further includes a gate driver circuit 14 and a source driver circuit 16 as peripheral circuits of the display unit 12. The display unit 12, the gate driver circuit 14, the source driver circuit 16, the scanning lines 40, and the signal lines 42 are mounted on a panel substrate (not shown) formed of, for example, glass or a resin such as acrylic.

[0061] The display unit 12 displays an image based on an image signal (image signal R, G, B) input from the outside to the display device 1. Figure 1 As shown, the display unit 12 includes a plurality of pixel circuits 30 arranged in a matrix, and is provided with row-shaped scanning lines 40 and column-shaped signal lines 42. In the display unit 12, initialization, writing, and light-emitting operations are sequentially performed in the order of the rows of the plurality of pixel circuits 30.

[0062] The display panel 10 includes a plurality of pixel circuits 30 arranged in a matrix. More specifically, each of the plurality of pixel circuits 30 is arranged at a location where a scanning line 40 intersects a signal line 42. Details will be described later.

[0063] The scanning line 40 is wired for each row of the plurality of pixel circuits 30 . One end of the scanning line 40 is connected to the pixel circuit 30 , and the other end of the scanning line 40 is connected to the gate driving circuit 14 .

[0064] The signal line 42 is wired for each column of the plurality of pixel circuits 30 . One end of the signal line 42 is connected to the pixel circuit 30 , and the other end of the signal line 42 is connected to the source driver circuit 16 .

[0065] The gate drive circuit 14, also known as a scan line drive circuit, is composed of, for example, a shift register (see later). Figure 3 ) and the like. The gate drive circuit 14 is connected to the scan line 40 and outputs a gate control signal to the scan line 40, thereby controlling the on / off state of each transistor included in the pixel circuit 30. In this embodiment, the gate drive circuit 14 outputs, as gate control signals for controlling the on / off state of each transistor included in the pixel circuit 30, for example, a control signal WS, a control signal REF, a control signal INI, and an extinction signal EN, to the gate (gate electrode) of each transistor included in the pixel circuit 30. The control signal WS, the control signal REF, the control signal INI, and the extinction signal EN are examples of control signals.

[0066] The source driver circuit 16 is also called a signal line driver circuit. The source driver circuit 16 is connected to the signal line 42, and outputs the image signal provided by the control device 20 in frame units to the signal line 42, thereby providing the image signal to each pixel circuit 30. The source driver circuit 16 writes brightness information based on the image signal to each pixel circuit 30 in the form of a current value or a voltage value through the signal line 42. In addition, the image signal input to the source driver circuit 16 is, for example, digital serial data of each color of the three primary colors of RGB (image signals R, G, B). The image signals R, G, B input to the source driver circuit 16 are converted into parallel data of row units (an example of output image signals) inside the source driver circuit 16. Furthermore, the parallel data of row units are converted into analog data of row units inside the source driver circuit 16 and output to the signal line 42 as image signals.

[0067] [1-2. Structure of Pixel Circuit]

[0068] The plurality of pixel circuits 30 are arranged, for example, in N rows and M columns. N and M vary depending on the size and resolution of the display screen. For example, at a resolution known as HD (High Definition), when pixel circuits 30 corresponding to the three primary colors of RGB are adjacent within a row, N is at least 1080 rows and M is at least 1920 × 3 columns. In this embodiment, each pixel circuit 30 includes an organic EL element as a light-emitting element.

[0069] For further information on the structure of the pixel circuit 30, refer to Figure 2 To explain. Figure 2 3 is a circuit diagram schematically showing the configuration of the pixel circuit 30 in this embodiment.

[0070] like Figure 2 As shown, the pixel circuit 30 includes a light emitting element 32, a driving transistor 33, switching transistors 34, 36, and 37, a selection transistor 35, and a pixel capacitor 38. Figure 2 In FIG. 3 , the pixel capacitor 38 is also labeled as Cs.

[0071] In the light-emitting element 32, the cathode is connected to the power supply Vcath (negative power supply line), and the anode is connected to the source of the driving transistor 33. A current corresponding to the signal voltage of the image signal provided by the driving transistor 33 flows to the light-emitting element 32, thereby emitting light with a brightness corresponding to the signal voltage. The light-emitting element 32 is, for example, an organic EL element such as OLED (Organic Light Emitting Diode). For example, the pixel circuit 30 (pixel) constituting the display panel 10 for displaying an image is composed of a light-emitting element 32 that emits light by current driving, including an organic EL element. In addition, the light-emitting element 32 is not limited to an organic EL element, but may also be an inorganic electroluminescent element or a self-luminous element such as QLED (Quantum-dot Light Emitting Diode), and may not be a self-luminous element as long as it is an element controlled by current driving.

[0072] In the driving transistor 33, the gate is connected to one electrode of the pixel capacitor 38, the drain is connected to the source of the switching transistor 34, and the source is connected to the anode of the light emitting element 32. Figure 2 The source is also connected to the other electrode of the pixel capacitor 38. The driving transistor 33 converts the signal voltage applied between the gate and source into a current corresponding to the signal voltage (also referred to as the drain-source current). Furthermore, by being turned on, the driving transistor 33 supplies the drain-source current to the light-emitting element 32, causing the light-emitting element 32 to emit light. The driving transistor 33 is, for example, an n-type thin-film transistor (n-type TFT).

[0073] The switching transistor 34 has a gate connected to the scanning line 40, one of its source and drain connected to the power supply Vcc, and the other connected to the drain of the driving transistor 33. The switching transistor 34 is turned on or off in response to the extinction signal EN supplied from the scanning line 40. When the switching transistor 34 is turned on, it connects the driving transistor 33 to the power supply Vcc, allowing current between the drain and source of the driving transistor 33 to be supplied to the light-emitting element 32. The switching transistor 34 is, for example, a p-type thin-film transistor (p-type TFT).

[0074] The select transistor 35 has a gate connected to the scan line 40, one of its source and drain connected to the signal line 42, and the other of its source and drain connected to one electrode of the pixel capacitor 38. The select transistor 35 is turned on or off in accordance with a control signal WS supplied from the scan line 40. When the select transistor 35 is turned on, it applies the signal voltage of the video signal supplied from the signal line 42 to the electrode of the pixel capacitor 38, thereby accumulating charge corresponding to the signal voltage in the pixel capacitor 38. The select transistor 35 is, for example, an n-type thin film transistor (n-type TFT).

[0075] In the switching transistor 36, the gate is connected to the scanning line 40, one of the source and drain is connected to the power supply Vref, and the other of the source and drain is connected to one electrode of the pixel capacitor 38. The switching transistor 36 is turned on or off according to the control signal REF supplied from the scanning line 40. When the switching transistor 36 is turned on, the electrode of the pixel capacitor 38 is set to the voltage of the power supply Vref (reference voltage). The switching transistor 36 is formed, for example, of an n-type thin film transistor (n-type TFT).

[0076] The switching transistor 37 has a gate connected to the scan line 40, one of its source and drain connected to the source of the switching transistor 34 and the drain of the driving transistor 33, and the other of its source and drain connected to the power supply Vini. The switching transistor 37 is switched on or off in response to a control signal INI supplied from the scan line 40. When the driving transistor 33 and the switching transistor 34 are both on and the power supply Vcc is disconnected, the switching transistor 37 is switched on, thereby setting the anode of the light-emitting element 32 to the voltage of the power supply Vini (reference voltage). The switching transistor 37 is, for example, an n-type thin-film transistor (n-type TFT).

[0077] The pixel capacitor 38 is a capacitor having one electrode connected to the gate of the drive transistor 33, the source of the select transistor 35, and the source of the switching transistor 36, and the other electrode connected to the source of the drive transistor 33. The pixel capacitor 38 stores charge corresponding to the signal voltage supplied from the signal line 42. For example, after the select transistor 35 and the switching transistor 36 are turned off, the pixel capacitor 38 stably maintains the voltage between the gate and source electrodes of the drive transistor 33. Thus, when the select transistor 35 and the switching transistor 36 are turned off, the pixel capacitor 38 applies a voltage between the gate and source of the drive transistor 33 in accordance with the signal potential of the stored charge.

[0078] The EL capacitor 39 is a parasitic capacitor inside the EL element. When this capacitor is charged and the voltage between the electrodes rises, current flows to the EL element side, and the EL element starts to emit light.

[0079] The conductivity type of each of the drive transistor 33, the select transistor 35, the switch transistor 36, and the switch transistor 37 is not limited to the conductivity type described above; n-type and p-type TFTs may be mixed as appropriate. Furthermore, the conductivity type of the switch transistor 34 is not limited to the conductivity type described above; an n-type TFT may also be used. Furthermore, each transistor is not limited to a polysilicon TFT; an amorphous silicon TFT or the like may also be used.

[0080] [1-3. Structure of Control Device]

[0081] The control device 20 is formed on a circuit board (not shown) external to the display panel 10, for example, an external system circuit board. The control device 20 functions as, for example, a TCON (Timing Controller) to control the overall operation of the display device 1. Specifically, the control device 20 generates gate control signals based on externally supplied vertical synchronization signals VS, horizontal synchronization signals HS, and image duration signals DE, and outputs these signals to the gate driver circuit 14. Furthermore, the control device 20 provides digital serial data of the image signals R, G, and B to the source driver circuit 16.

[0082] The control device 20 involved in this embodiment is a control device for the display panel 10 when the correct frame period is not known in advance. The frame period is the period during which the same image is continuously displayed, and the frame period fluctuates or temporarily stabilizes within a certain range for each frame. Furthermore, when a frame length exceeding a predetermined number of lines (e.g., a minimum number of lines) is input, the control device 20 controls the display panel 10 so that the image is displayed using a minimum frame period corresponding to the minimum number of lines and an additional period added after the minimum frame period. Furthermore, the additional period includes one or more individual additional periods, each of which includes a light-emitting period and an extinction period, and each of the one or more individual additional periods corresponds to a predetermined number of lines. For example, the period corresponds to one horizontal period for each of the predetermined number of lines. In this embodiment, the predetermined number of lines is one line. In other words, the period corresponding to the predetermined number of lines is a period corresponding to one line (one line period). One line period is, for example, a period corresponding to one horizontal period. Furthermore, the minimum number of lines refers to the number of vertical lines representing the minimum frame period.

[0083] Thus, the control device 20 according to this embodiment controls the display panel 10 so that, when the number of lines of an input frame exceeds the minimum number of lines, an additional period including a light-emitting period and a non-light-emitting period is provided for each line period of the frame whose length exceeds the minimum number of lines. In other words, the control device 20 controls the display panel 10 so that, when the number of lines of an input frame exceeds the minimum number of lines, the frame length is extended in units of one line.

[0084] Not knowing the correct frame period in advance means that the frame period is changed according to the input video signal, for example. Also, one line period is an example of a line period corresponding to one line (an example of a predetermined number of lines) in which the same signal voltage is written.

[0085] The minimum number of lines is a value common to all frames, and is, for example, based on the frame rate of the video signal. For example, the minimum number of lines is the number of lines required to render one frame, provided externally. For example, the minimum number of lines is based on the number of display lines on the display unit 12 and the number of lines during the blanking period.

[0086] Although not shown, the control device 20 is configured to include a synchronization control unit, which receives a vertical synchronization signal VS, a horizontal synchronization signal HS, and an image period signal DE from the outside and controls the timing at which the image signals R, G, and B are displayed on the display unit 12, and a duty control unit, which generates a gate control signal for controlling the gate drive circuit 14 so that the image signals R, G, and B are displayed on the display unit 12 at a desired timing. Furthermore, the control device 20 includes a frame memory, which serves as a buffer for temporarily storing the image signals R, G, and B input from a signal source external to the display panel 10.

[0087] The duty control unit detects the reception of the vertical synchronization signal VS or the video period signal DE and generates a control signal for executing the minimum frame period and the additional period.

[0088] The duty control unit generates and outputs a control signal so that light is emitted and light is extinguished according to the length of the light emission period and the length of the light extinction period in the minimum frame period of the current frame that are predetermined.

[0089] In addition, the duty control unit generates and outputs a control signal to the gate drive circuit 14 in such a manner that the on-duty in each of one or more individual additional periods of the current frame matches the on-duty in the minimum frame period of the current frame.

[0090] Regarding the structure of the gate drive circuit 14 in this embodiment, refer to Figure 3 To explain. Figure 3 1 is a diagram showing the structure of the gate drive circuit 14 in this embodiment. Figure 3 , a circuit for generating a gate control signal ( Figure 2 The structure of the extinction signal EN) is shown. In addition, Figure 3 , the structures of the first to third rows among the plurality of rows are shown.

[0091] like Figure 3 As shown, the gate drive circuit 14 includes a first register section 100, a second register section 200, and an output section 300. The first register section 100 and the second register section 200 are provided to output gate control signals to the scanning line 40 connected to the switching transistor 34. The first register section 100 and the second register section 200 output signals to the output section 300 at different timings, for example.

[0092] The first register unit 100 outputs a signal for generating a gate control signal for controlling the on / off state of the switching transistor 34 during the minimum frame period of the minimum frame period and the additional period. The first register unit 100 is composed of a plurality of shift registers (shift register circuits) connected in series. The plurality of shift registers are connected to the switching transistor 34 via scan lines 40 and output unit 300, respectively. The plurality of shift registers include shift registers 110, 120, and 130. Hereinafter, the plurality of shift registers included in the first register unit 100 will also be referred to as the plurality of shift registers 110, etc. The circuit structures of the plurality of shift registers 110, etc., for example, are the same.

[0093] When the input signal for the first row is input to the shift register 110, it outputs the input signal for the first row to the OR circuit 310 of the output unit 300 and the shift register 120 according to the clock signal. The output signal from the shift register 110 to the OR circuit 310 of the output unit 300 is used to generate the gate control signal for the first row during the minimum frame period. Furthermore, the output signal output to the shift register 120 is used as the input signal for the shift register 120. The input signal for the first row is, for example, a signal for initializing write to the first row.

[0094] When the output signal from the shift register 110 is input to the shift register 120, the shift register 120 outputs the output signal to the OR circuit 320 of the output unit 300 and the shift register 130 according to the clock signal. Furthermore, when the output signal from the shift register 120 is input to the shift register 130, the shift register 130 outputs the output signal to the OR circuit 330 of the output unit 300 according to the clock signal.

[0095] The second register unit 200 outputs a signal for generating a gate control signal for controlling the on / off state of the switching transistor 34 during the supplementary period, which is one of the minimum frame period and the supplementary period. The second register unit 200 is configured to include multiple shift registers (shift register circuits) and multiple AND circuits. The multiple shift registers are connected in series and are connected to the switching transistor 34 via the scan line 40, the AND circuit, and the output unit 300.

[0096] The plurality of shift registers include shift registers 210, 220, and 230. Hereinafter, the plurality of shift registers included in the second register unit 200 will also be referred to as the plurality of shift registers 210, etc. The circuit configurations of the plurality of shift registers 210, etc., for example, are the same. Furthermore, the plurality of AND circuits include AND circuits 211, 221, and 231. Hereinafter, the plurality of AND circuits included in the second register unit 200 will also be referred to as the plurality of AND circuits 211, etc. The circuit configurations of the plurality of AND circuits 211, etc., for example, are the same.

[0097] Furthermore, a whole row common signal common to all rows is input to the plurality of AND circuits 211 and the like.

[0098] When the input signal of the first row is input, the shift register 210 outputs the input signal of the first row to the AND circuit 211 and the shift register 220 according to the clock signal. Here, the output signal from the shift register 210 to the AND circuit 211 is described as the 1H shift signal of the first row (refer to Figures 6 to 8 ) In addition, the signal output from the shift register 210 to the shift register 220 is also the same signal as the 1H shift signal of the first row, for example.

[0099] The AND circuit 211 receives the 1H shift signal of the first row from the shift register 210 and the all-row common signal, and when either signal is High, outputs a High signal to the OR circuit 310. Otherwise, it outputs a Low signal to the OR circuit 310. The output signal from the AND circuit 211 to the OR circuit 310 is used to generate the gate control signal for the first row in the additional period.

[0100] Similarly, the AND circuit 221 receives the 1H shift signal (refer to Figure 6 、 Figure 7 ) and the common signal for all rows, when each signal is High, the High signal is output to the OR circuit 320, and otherwise, the Low signal is output to the OR circuit 320. In addition, the AND circuit 231 receives the 1H shift signal (reference signal) from the third row of the shift register 230. Figure 6 、 Figure 7 ) and the common signal for all rows. When each signal is High, the High signal is output to the OR circuit 330. Otherwise, the Low signal is output to the OR circuit 330.

[0101] In addition, the input signal of the first row is input from the control device 20, for example.

[0102] The output unit 300 outputs a gate control signal for each row based on an output signal output from at least one of the first register unit 100 and the second register unit 200 .

[0103] The OR circuit 310 is connected to the scanning line 40 connected to the switching transistor 34 in the first row, and outputs a gate control signal to the scanning line 40. For example, when the OR circuit 310 receives at least one of a high-level signal from the shift register 110 and a high-level signal from the AND circuit 211, the OR circuit 310 outputs a high gate control signal to the first row, in other words, outputs a gate control signal for turning off the switching transistor 34 in the first row. Otherwise, the OR circuit 310 outputs a low gate control signal to the first row, in other words, outputs a gate control signal for turning on the switching transistor 34 in the first row.

[0104] The OR circuit 320 is connected to the scanning line 40 connected to the switching transistor 34 in the second row, and outputs a gate control signal to the scanning line 40. For example, when the OR circuit 320 receives at least one of a high-level signal from the shift register 120 and a high-level signal from the AND circuit 221, the OR circuit 320 outputs a high gate control signal to the second row, in other words, outputs a gate control signal for turning off the switching transistor 34 in the second row. Otherwise, the OR circuit 320 outputs a low gate control signal to the second row, in other words, outputs a gate control signal for turning on the switching transistor 34 in the second row.

[0105] The OR circuit 330 is connected to the scan line 40 connected to the switching transistor 34 in the third row, and outputs a gate control signal to the scan line 40. For example, when the OR circuit 330 receives at least one of a high-level signal from the shift register 130 and a high-level signal from the AND circuit 231, the OR circuit 330 outputs a high gate control signal to the third row, in other words, outputs a gate control signal for turning off the switching transistor 34 in the third row. Otherwise, the OR circuit 330 outputs a low gate control signal to the third row, in other words, outputs a gate control signal for turning on the switching transistor 34 in the third row.

[0106] Here, a gate control signal generated by the control of the control device 20 (a signal output by the aforementioned gate drive circuit 14 ) will be described in comparison with a gate control signal generated by the control of the control device in a comparative example. Figure 4 1 is a diagram showing an example of a gate control signal output from the gate drive circuit 14 under the control of the control device in the comparative example.

[0107] exist Figure 4 and the following Figure 5 Shows the input to Figure 2The waveform of the gate control signal of the switching transistor 34 is shown. Figure 4 as well as Figure 5 The horizontal axis represents time, and the vertical axis represents voltage. Figure 4 as well as Figure 5 The period in which the voltage is Low is a period in which the switching transistor 34 is on, which corresponds to a light-emitting period.

[0108] The minimum frame period is, for example, set to a period corresponding to the maximum refresh rate (e.g., 144 Hz). When the maximum refresh rate is 144 Hz, the minimum frame period is approximately 6.94 msec. The maximum refresh rate is set, for example, based on the minimum number of rows and is the highest refresh rate of the control device 20. The maximum refresh rate is pre-stored in the storage unit of the control device 20.

[0109] like Figure 4 As shown, in the control device according to the comparative example, an additional period is provided after the minimum frame period, and the additional period is a constant multiple ( Figure 4 In the example, the subframe rate (720Hz) is 5 times) to repeat the light-emitting period and the extinction period. The minimum frame period is time t1 to t3, the time between t1 and t2 is the non-light-emitting period, and the time between t2 and t3 is the light-emitting period. In addition, the period after time t3 is the additional period. Figure 4 In the example, non-luminous periods and luminous periods are repeated at a subframe rate of 720 Hz. Time t3 to t4 and time t5 to t6 are non-luminous periods, while time t4 to t5 and time t6 to t7 are luminous periods. Furthermore, time t3 to t5 is the first subframe period in the additional period, and time t5 to t7 is the second subframe period in the additional period.

[0110] Here, the control device according to the comparative example, when the image signal for the next frame is obtained immediately after time t3 (immediately after the start of the first sub-frame period in the supplementary period), does not start the next sub-frame period (the second sub-frame period in the supplementary period), but instead starts the minimum frame period in the image signal for the next frame. This means that in the control device according to the comparative example, a delay of up to a sub-frame period in the supplementary period may occur from the start of the frame period corresponding to the image signal after the image signal is obtained. In other words, the start of the frame period when switching to the next frame image may be delayed.

[0111] On the other hand, the control device 20 according to the present embodiment can suppress a delay in the start of a frame period when switching to an image of the next frame. Figure 5 1 is a diagram showing an example of a gate control signal output from the gate drive circuit 14 under the control of the control device 2 in this embodiment. Figure 5 The gate control signals shown are from Figure 3 The output unit 300 outputs the signal shown. Figure 5 The gate control signal represented by the time t11 to t13 is Figure 4 The gate control signals during times t1 to t3 are the same, so their description is omitted. A frame period is composed of a minimum frame period and an additional period. The waveform of the dotted line region R during the additional period is shown in an enlarged form.

[0112] like Figure 5 As shown, the control device 20 controls the display panel 10 by repeating the non-light-emitting period and the light-emitting period in the additional period after time t13 with a shorter cycle than the control device involved in the comparative example. It can be said that the control device 20 controls the display panel 10 by providing the additional period including the light-emitting period and the non-light-emitting period in the horizontal period. Figure 5 In the example, the non-luminous period and the luminous period are repeated for each row period (each 1H in the figure). Time t21~t22 and time t23~t24 are non-luminous periods. Time t21~t22 and time t23~t24 are, for example, periods of the same length. In addition, time t22~t23 and time t24~t25 are luminous periods. Time t22~t23 and time t24~t25 are periods of the same length. In addition, the period from t21 to t23 is the mth (m is an integer greater than 1) row period in the additional period (an example of an individual additional period), and the period from t23 to t25 is the m+1th row period in the additional period (an example of an individual additional period).

[0113] The gate control signal from time t11 to time t13 is generated based on the output signal from the first register unit 100 , and the gate control signal after time t13 is generated based on the output signal from the second register unit 200 .

[0114] Furthermore, when the minimum frame period is 6.94 msec and the number of lines is 2314, one line period is, for example, 3 μsec, but is not limited thereto.

[0115] Here, if the control device 20 obtains the image signal for the next frame immediately after time t21 (immediately after the start of the m-th line period), the minimum frame period of the image signal for the next frame can be started from the next line period (the m+1-th line period). For example, when the duty control unit detects a signal indicating the start of a frame period, it outputs a control signal to the gate drive circuit 14 to execute the initialization operation and writing operation for the next frame during the extinction period after the line period being executed at the time of detection ends. In other words, the duty control unit can start the minimum frame period of the next frame after the line period being executed at the time of detection ends.

[0116] Thus, in control device 20, a delay of a maximum of one line period occurs from the moment an image signal is acquired until the start of the frame period corresponding to that image signal. Consequently, control device 20 according to this embodiment can suppress delays during image switching more effectively than control devices according to comparative examples. Furthermore, control device 20 eliminates the need for a memory buffer to store image signals in subframe units, reducing storage capacity and achieving a more cost-effective and heat-efficient control device compared to comparative examples.

[0117] Furthermore, when the duty control unit does not detect a signal indicating the start of a frame period, it outputs a control signal to the gate drive circuit 14 to generate a gate control signal for repeatedly executing one line period consisting of a light-emitting period and an extinction period at a constant interval.

[0118] Furthermore, the duty control unit controls the length of the extinction period of each of the one or more individual additional periods so that the ratio of the length of the light-emitting period (e.g., the length of time t22 to t23 and time t24 to t25) to the length of the extinction period (e.g., the length of time t21 to t22 and time t23 to t24) in each of the one or more individual additional periods of the current frame is consistent with the ratio of the length of the light-emitting period (e.g., the length of time t12 to t13) to the length of the extinction period (e.g., the length of time t11 to t12) in the minimum frame period of the current frame. In other words, the duty control unit generates a control signal corresponding to the length of the extinction period and outputs it to the gate drive circuit 14.

[0119] In addition, the length of the light-emitting period and the length of the extinction period are consistent in each of the one or more individual additional periods. Thus, the additional period is a period in which the light-emitting period and the extinction period are repeated at a certain interval, and can also be said to be a blanking period until the next frame is input.

[0120] Furthermore, the control device 20 can simultaneously control the switching between the light-emitting period and the non-light-emitting period for each of one or more individual additional periods, for example, across the entire display screen of the display panel 10. The control device 20 generates a control signal so that each row of the display panel 10 simultaneously switches from a light-emitting period to a non-light-emitting period, and outputs the control signal to the gate drive circuit 14. Furthermore, a configuration in which each row simultaneously switches from a light-emitting period to a non-light-emitting period during the additional period, in other words, each switching transistor 34 of each row simultaneously switches from on to off during the additional period, is described in (Variation 2 of the Embodiment).

[0121] In addition, during the time period t11 to t12, initialization operations and write operations of the pixel circuit 30 can be performed. The initialization of the pixel circuit 30 means that before the charge corresponding to the signal voltage is accumulated (written) in the pixel capacitor 38, a reverse bias is applied to the light-emitting element 32 and the EL capacitor 39, and the inter-electrode voltage of the pixel capacitor 38 is corrected (reset) according to the characteristic deviation of the driving transistor 33. In addition, the initialization period of the pixel circuit 30 refers to the period during which a reverse bias is applied to the light-emitting element 32 and the EL capacitor 39, and the inter-electrode voltage of the pixel capacitor 38 is corrected (reset) according to the characteristic deviation of the driving transistor 33. In addition, in the present embodiment, during the initialization period of the pixel circuit 30, the light-emitting element 32 is extinguished. In other words, the initialization period of the pixel circuit 30 is included in the extinction period (also called the non-luminous period).

[0122] In addition, the initialization operation and the writing operation cannot be performed in the additional period. Therefore, the luminance of the display panel 10 in the minimum frame period and the luminance of the display panel 10 in the additional period can be made close.

[0123] Next, regarding the control signal input from the control device 20 to the gate drive circuit 14 and the gate control signal output from the gate drive circuit 14 to the display unit 12 during the additional period, refer to Figures 6 to 8 Provide explanation. Figure 6 : is a diagram showing an example of a control signal input to the gate drive circuit 14 in this embodiment. Figure 6 1H shift signals input to the first to third rows among a plurality of rows (display rows) are shown. Figure 6 The 1H shift signal shown is a signal for generating a gate control signal input to the gate of the switching transistor 34 , and specifically, is a signal output from the shift register of the second register unit 200 to the AND circuit during the additional period.

[0124] Figure 7The diagram shows a control signal input to the AND circuit 211 corresponding to the first row of the gate driving circuit 14 in this embodiment, and a gate control signal for the first row in an additional period output from the AND circuit 211 corresponding to the first row based on the control signal. Figure 7 The gate control signal for the first row during the additional period shown indicates the gate control signal input during the additional period to the gate of each of the plurality of switching transistors 34 arranged in row 1. The first row, the second row, and the third row are display rows arranged in this order in the display unit 12.

[0125] like Figure 6 As shown, 1H shift signals having waveforms shifted by one horizontal period (1H) are sequentially input to AND circuits 211 corresponding to the first row through 231 corresponding to the third row. Specifically, a 1H shift signal that switches from Low to High at time t34 is input to AND circuit 211 corresponding to the first row, a 1H shift signal that switches from Low to High at time t36 is input to AND circuit 221 corresponding to the second row, and a 1H shift signal that switches from Low to High at time t37 is input to AND circuit 231 corresponding to the third row. For example, the High and Low periods in the 1H shift signal are the same for each of the multiple rows, including rows 1 through 3.

[0126] like Figure 7 As shown, the AND circuit 211 corresponding to the first row receives the 1H shift signal of the first row and the common signal for all rows. The 1H shift signal of the first row is the shift signal input to the AND circuit 211 corresponding to the first row and is a common signal for all rows. Figure 6 The same signal as the 1H shift signal of row 1 is shown.

[0127] The gate drive circuit 14 is configured, for example, to include a plurality of OR circuits 310 and the like in the output portion 300. Furthermore, the gate drive circuit 14 is configured, for example, to output a gate control signal that is low during a period in which the 1H shift signal of the first row and the common signal for all rows are respectively low, and that is high during a period in which the 1H shift signal of the first row and any one of the common signals for all rows are high. Thus, the gate control signal for the first row is a signal that makes the periods p1, p2, p3, and p4 (hereinafter also referred to as period p1, etc.) high (non-luminous period). By adjusting the time length of the period p1, etc., it is possible to adjust Figure 5 The lengths of the non-light-emitting period and the light-emitting period in the additional period are shown. In addition, the periods p1, p2, p3, and p4 are periods of the same length.

[0128] In addition, for the gate control signal of each row, refer to Figure 8 Provide explanation. Figure 8 1 is a diagram showing gate control signals for each row in this embodiment. Figure 8 The gate control signal shown is a signal output from the output unit 300 of the gate drive circuit 14 and input to the switching transistor 34 .

[0129] The gate control signal for the minimum frame period is generated based on the output signal from the first register unit 100. Gate control signals with waveforms shifted by one horizontal period (1H) are sequentially output to the OR circuits 310 corresponding to the first row through the OR circuits 330 corresponding to the third row. Specifically, the gate control signal for the first row, which switches from Low to High at time t31, is output to the gate of the switching transistor 34 in the first row. The gate control signal for the second row, which switches from Low to High at time t32, is output to the gate of the switching transistor 34 in the second row. The gate control signal for the third row, which switches from Low to High at time t33, is output to the gate of the switching transistor 34 in the third row.

[0130] In addition, the gate control signal in the minimum frame period of the next frame may be the same as the gate control signal in the minimum frame period. Time t38 in the minimum frame period of the next frame corresponds to time t31 in the minimum frame period.

[0131] The gate control signal for the additional period is generated based on the output signal from the second register unit 200. Gate control signals with waveforms shifted by one horizontal period (1H) are sequentially output from the OR circuits 310 corresponding to the first row through the OR circuits 330 corresponding to the third row. Specifically, the gate control signal for the first row, which switches from Low to High at time t35, is output to the gate of the switching transistor 34 in the first row. Furthermore, the gate control signal for the second row, which switches from Low to High after one horizontal period at time t35, is output to the gate of the switching transistor 34 in the second row. Furthermore, the gate control signal for the third row, which switches from Low to High after one horizontal period, is output to the gate of the switching transistor 34 in the third row. The additional period for each row begins sequentially every one horizontal period.

[0132] During period p2, the gate control signals for rows 1 and 2 are simultaneously high, and during periods p3 and p4, the gate control signals for rows 1 through 3 are simultaneously high. In other words, during periods p3 and p4, the switching transistors 34 of each row are simultaneously switched on and off.

[0133] in addition, Figure 8 The period p1 to p4 shown is Figure 7 The periods p1 to p4 shown correspond to each other.

[0134] [2. Operation of the control device]

[0135] Next, regarding the operation of the control device 20 configured as above, refer to Figure 9 Provide explanation. Figure 9 : is a flowchart showing the operation of the control device 20 in this embodiment. Figure 9 Steps S11 to S15 shown are processes for one frame, and the processes of steps S11 to S15 are repeatedly executed for each frame.

[0136] like Figure 9 As shown, first, the control device 20 obtains a video signal from an external signal source (S11). The control device 20 stores the video signal in a storage unit, for example.

[0137] Next, the control device 20 performs light emission during the minimum frame period (S12). The minimum frame period is Figure 5 The control device 20 performs the initialization and writing operations during the non-light-emitting period (time t11 to t12), and then, at time t12, turns the gate control signal input to the gate of the switching transistor 34 low to start the light-emitting period.

[0138] Next, the control device 20 determines whether the image signal of the next frame has been obtained (S13). If the image signal of the next frame has been obtained ("Yes" in S13), the control device 20 ends the processing in the current frame. If the image signal of the next frame has not been obtained ("No" in S13), the control device 20 proceeds to step S14.

[0139] Next, the control device 20 extends the blanking period (additional period) in units of one line (S14). Figure 5 The control device 20 controls the gate control signal input to the gate of the switching transistor 34 so that a light-emitting period and a non-light-emitting period are provided for each row period, without having to re-perform the initialization operation and the writing operation. In other words, the charge corresponding to the signal voltage of the image signal obtained in step S11 is accumulated in the pixel capacitor 38.

[0140] Next, the control device 20 determines whether the video signal of the next frame has been obtained (S15). Step S15 is continued during the blanking period, for example.

[0141] If the image signal for the next frame is obtained during the blanking period ("YES" in S15), the control device 20 terminates processing in the current frame. If the image signal for the next frame is not obtained during the blanking period ("NO" in S15), the process proceeds to step S14. For example, the blanking period is extended by one line until the image signal for the next frame is obtained. In other words, the blanking period (additional period) is continued until the next frame is input.

[0142] [3. Effects, etc.]

[0143] As described above, the control device 20 according to this embodiment is a control device 20 for the display panel 10 in a case where the correct frame period is not known in advance. The frame period is a period during which the same image is continuously displayed, and the frame period fluctuates or temporarily stabilizes within a certain range for each frame. When a frame length exceeding a predetermined number of lines is input, the control device 20 controls the display panel 10 so that the image is displayed using a frame period corresponding to the predetermined number of lines and an additional period added after the frame period. The additional period includes one or more individual additional periods, each of which includes a light emission period and an extinction period, and each of the one or more individual additional periods corresponds to the predetermined number of lines.

[0144] Thus, the control device 20 can maintain the same light-emission duty cycle even when the number of lines varies from frame to frame, thus suppressing visual flicker. Furthermore, the control device 20 sets the additional period so that the line period, which includes both light-emitting and non-light-emitting periods, repeats. Therefore, when the next frame is input, switching can be performed on a line-by-line basis. Thus, the control device 20 can suppress flicker and delays in image switching.

[0145] Furthermore, the predetermined number of lines is one line, and the period corresponding to the predetermined number of lines is a period corresponding to one line.

[0146] Therefore, the control device 20 can reduce the delay in switching images to less than one line period, and thus can further suppress the delay in switching images.

[0147] In addition, the control device 20 controls the length of the extinction period of each of the more than one individual additional periods in a manner that is consistent with the ratio of the length of the luminous period to the length of the extinction period in each of the more than one individual additional periods of the current frame and the ratio of the length of the luminous period to the length of the extinction period in the frame period of the current frame.

[0148] Therefore, the control device 20 can suppress visual flicker by keeping the ratio of the light emission period to the light extinction period constant between the additional period and the predetermined frame period. Therefore, the control device 20 can further suppress the flicker phenomenon.

[0149] Furthermore, the control device 20 continues the additional period until the next frame is input.

[0150] Therefore, the control device 20 can display images without interruption even when the frame period varies within a certain range for each frame.

[0151] Furthermore, when the next frame is inputted within the current individual additional period among the additional periods, the control device 20 performs control so that the frame period corresponding to the next frame starts after the current individual additional period ends.

[0152] Therefore, the control device 20 can reduce the delay when switching images to less than one line period, and thus can more reliably suppress the delay when switching images.

[0153] The pixels constituting the display panel 10 are composed of light-emitting elements including organic EL elements that are driven by current to emit light.

[0154] Therefore, the control device 20 prevents visually recognized flickering in the display panel 10 using OLEDs, even if the frame period fluctuates significantly due to factors such as the GPU's processing power, and can suppress delays in image switching. In other words, the control device 20 can suppress flickering and image delays in the display panel 10 using OLEDs, even if the frame period fluctuates.

[0155] In addition, as described above, the display device 1 involved in this embodiment comprises: the control device 20 described above; and a display panel 10, which has a gate drive circuit 14 and a source drive circuit 16, wherein the gate drive circuit 14 is input with a control signal from the control device 20, and the source drive circuit 16 is input with an output image signal from the control device 20.

[0156] Therefore, it is possible to realize the display device 1 that can suppress flickering and image delay.

[0157] Furthermore, as described above, the control method according to this embodiment is a method for controlling the display panel 10 when the correct frame period is not known in advance. The frame period is a period during which the same image is continuously displayed, and the frame period varies or temporarily stabilizes within a certain range for each frame. In this control method, when a frame having a length exceeding a predetermined number of lines is input, the display panel 10 is controlled so that an image is displayed during a frame period corresponding to the predetermined number of lines and an additional period added after the frame period. Furthermore, the additional period includes one or more individual additional periods, each of which includes a light-emitting period and an extinction period, and each of the one or more individual additional periods is a period corresponding to the predetermined number of lines.

[0158] Therefore, the same effects as those of the above-mentioned control device 20 can be achieved.

[0159] (Variation 1 of the embodiment)

[0160] In the above embodiment, the control device performs control in the additional period, and sets the luminous period and the non-luminous period for each row period. However, the luminous period and the non-luminous period do not need to be limited to being set for each row period, and the luminous period and the non-luminous period can be set for every n (n is an integer greater than 2) row periods. Figures 10 to 12 Provide explanation. Figure 10 1 is a diagram showing an example of a gate control signal output from the gate drive circuit 14 under the control of the control device in this modification. Figure 10 It will be with Figure 5 The dashed area R shown is an enlarged view of the gate control signal according to the present modification (the gate control signal output to the gate of the switching transistor 34 during the additional period).

[0161] like Figure 10 As shown, the control device according to this variation controls the display so that during the additional period, the light-emitting period and the non-light-emitting period are repeated every n-row period (nH). Time t41-t42 and time t43-t44 are non-light-emitting periods. The n-row period is a period corresponding to two or more rows. The n-row period is an example of a period corresponding to a specified number of rows. For example, if the specified number of rows is doubled, the n-row period is also doubled.

[0162] Time t41-t42 and time t43-t44 are, for example, periods of the same length. Furthermore, time t42-t43 and time t44-t45 are light-emission periods. Time t42-t43 and time t44-t45 are periods of the same length. Furthermore, the period t41-t43 is the mth (m is an integer greater than or equal to 1)th n-line period in the additional period, and the period t43-t45 is the m+1th n-line period in the additional period. n lines is an example of the specified number of lines.

[0163] Next, for the control in the case of n=2 (prescribed number of rows=2), refer to Figure 11 as well as Figure 12 Provide explanation. Figure 11 1 is a diagram showing the gate control signal output from the gate drive circuit 14 and the operation of the display panel 10 under the control of the control device in this modification. In addition, n is not limited to 2, and can be set to 3 or more, or a power of 2. The value of n can be set in advance and stored in the storage unit of the control device. In addition, Figure 11 The gate control signal shown is a signal output from the gate drive circuit 14 to the gate of the switching transistor 34 .

[0164] like Figure 11 As shown, the control device controls the additional period after the minimum frame period (the period after time t51) so that the non-luminous period (extinction) and the luminous period (luminescence) are repeated every two line periods (2H). The periods from time t51 to t52, from time t52 to t53, and from time t53 to t54 are all equal periods (2H). Furthermore, the ratio of the luminous period to the non-luminous period is the same for each of the two line periods.

[0165] During each of the two line periods, extinction occurs from the time the gate control signal input to the gate of the switching transistor 34 goes High (e.g., time t51, t52, and t53) until the gate control signal goes Low. When n = 2, one duty cycle (non-lighting period and light-emitting period) ends during each two-line drawing period (every 2 hours).

[0166] Next, regarding the writing operation to the pixel circuit 30 in the case where the non-light emitting period and the light emitting period are repeated every two row periods as described above, refer to Figure 12 Provide explanation. Figure 12 It is a diagram for explaining the writing operation performed by the control device in this modification. Figure 12 The straight lines indicated by High and Low indicate gate control signals input from the gate drive circuit 14 to the selection transistor 35 .

[0167] like Figure 12 As shown, the control device performs a write operation for every two rows. In other words, in two rows, the same amount of charge is accumulated in the pixel capacitors 38 of the pixel circuits 30 connected to the same signal line 42. For example, the control device can output a control signal for writing a signal voltage to two rows (an example of more than two rows) to the display panel 10 at the same time. In other words, in two rows, the same amount of charge is accumulated in the pixel capacitors 38 of the pixel circuits 30 connected to the same signal line 42 at the same time.

[0168] For example, the first and second rows arranged in sequence are written simultaneously, the third and fourth rows arranged in sequence are written simultaneously after the first and second rows are written, and the fifth and sixth rows arranged in sequence are written simultaneously after the third and fourth rows are written. For example, between time t61 and t62, the first and second rows are written simultaneously, between time t63 and t64, the third and fourth rows are written simultaneously, and between time t65 and t66, the fifth and sixth rows are written simultaneously.

[0169] The gate drive circuit of such a display panel 10 is configured to output the same gate control signal to each of the select transistors 35 in two consecutive rows (e.g., the first and second rows, the third and fourth rows, the fifth and sixth rows, etc.). For example, the select transistors 35 in the first and second rows are turned on and off simultaneously, the select transistors 35 in the third and fourth rows are turned on and off simultaneously, and the select transistors 35 in the fifth and sixth rows are turned on and off simultaneously.

[0170] Thus, the two rows as an example of the predetermined number of rows may be rows into which the same signal voltage is written. In addition, the predetermined number of rows is not limited to rows into which the same signal voltage is written.

[0171] As described above, the period corresponding to the predetermined number of rows in the control device according to this modification is a period corresponding to two or more rows.

[0172] Therefore, the control device can reduce the frequency of turning on and off the switching transistor 34 compared to the case where the predetermined number of rows is 1, thereby reducing switching power. In other words, the control device according to this modification can realize a display device with improved energy saving performance.

[0173] Furthermore, the control device outputs a control signal for simultaneously writing signal voltages to two or more rows to the display panel 10 .

[0174] Therefore, by simply outputting a control signal for simultaneously writing a signal voltage to two or more rows, a display device with improved energy saving performance can be realized.

[0175] (Variation 2 of the embodiment)

[0176] The above description describes the structure of the gate drive circuit 14 in the above embodiment and modification 1. However, the structure of the gate drive circuit 14 is not limited to the structure of the above embodiment and modification 1. For other examples of the gate drive circuit 14, refer to Figure 13 as well as Figure 14 Note that, except for the structure of the gate drive circuit in the display device, since it can be the same as the above-mentioned embodiment, the description thereof will be omitted. Figure 13 1 is a diagram showing the configuration of a gate drive circuit 14 a in this modification.

[0177] like Figure 13 As shown, the gate driving circuit 14 a includes a first register section 100 and an output section 300 .

[0178] First register unit 100 and embodiment Figure 3 The first register unit 100 is similar and its description is omitted. The first register unit 100 outputs an output signal for generating a gate control signal for controlling the on / off state of the switching transistor 34 during the minimum frame period of the minimum frame period and the additional period.

[0179] The output unit 300 outputs a gate control signal for each row based on at least one of the output signal from the first register unit 100 and the signal common to all rows. Figure 3 The output section 300 shown is different in that a signal common to all rows is directly input.

[0180] OR circuit 310 is connected to scan line 40 connected to switching transistor 34 in row 1, and outputs a gate control signal to scan line 40. When receiving at least one of a high-level signal from shift register 110 and a high-level signal common to all rows, OR circuit 310 outputs a high-level gate control signal to row 1, in other words, outputs a gate control signal for turning off switching transistor 34. When receiving at least one of a high-level signal from shift register 110 and a high-level signal common to all rows, OR circuit 310 outputs a low-level gate control signal to row 1, in other words, outputs a gate control signal for turning on switching transistor 34.

[0181] During the minimum frame period, the OR circuit 310 outputs a gate control signal of the first row, which is High or Low, according to the output signal from the shift register 110. At this time, a common signal for all rows, for example, Low, is input.

[0182] During the additional period, OR circuit 310 outputs a High or Low gate control signal for row 1 based on a signal common to all rows from control device 20. Therefore, all OR circuits included in output unit 300, including OR circuit 310, output the same gate control signal. For example, during the additional period, the gate control signal for row 1, row 2, and row 3 can be the same signal.

[0183] Figure 14 is a diagram showing gate control signals for each row in this modification. Figure 14 In order to compare, the Figure 8 The corresponding time.

[0184] like Figure 14 As shown, the gate control signal for the minimum frame period is generated based on the switching between High and Low of the output signal from the first register unit 100. OR circuits 310 corresponding to the first row through 330 corresponding to the third row sequentially output gate control signals having waveforms shifted by one horizontal period (1H).

[0185] The gate control signal of the additional period is a signal generated by switching the High and Low common signals for all rows. From the OR circuit 310 corresponding to the 1st row to the OR circuit 330 corresponding to the 3rd row, the output of the gate control signal in the additional period starts at the same time at time t35. Specifically, the gate control signals of the 1st row to the 3rd row, which are switched from Low to High at time t35, are output to the gates of all the switching transistors 34 of the 1st row to the 3rd row. In this way, in this modification, the additional period of each row starts at the same time. In other words, in this modification, in the additional period including one or more individual additional periods, the switching between the luminous period and the non-luminous period is controlled for the entire display screen of the display panel 10 at the same time.

[0186] In addition, in this variant, the display panel 10 can be a liquid crystal panel (liquid crystal display, i.e., LCD: Liquid Crystal Display)). In other words, the pixels constituting the display panel 10 can be composed of liquid crystal elements. In this case, the display device 1 can further have a backlight source for performing backlight scanning. In addition, the control device 20 can switch the luminous and non-luminous periods of the backlight source provided as the light source of the liquid crystal display simultaneously across the entire screen. For example, individual additional periods can also be achieved by utilizing the backlight source of the liquid crystal display to control the luminous and non-luminous periods of the backlight source simultaneously across the entire screen. For example, the luminous period can be the period when the backlight source is on during backlight scanning, and the extinction period can be the period when the backlight source is off.

[0187] Backlight scanning here refers to a technique that sequentially turns off the backlight sources near the rows containing the pixels to be rewritten. Furthermore, the LCD backlight is typically not synchronized with the image. However, in this variation, backlight scanning is performed in synchronization with the image, with the light-on period being the period when the backlight source is on, and the light-off period being the period when the backlight source is off.

[0188] As described above, the control device 20 according to this modification simultaneously controls the switching between the light emission period and the light extinction period for each of one or more individual additional periods over the entire display screen of the display panel 10 .

[0189] Therefore, the control device 20 can simplify the gate drive circuit 14 , and thus can reduce the circuit area of the gate drive circuit 14 .

[0190] In addition, the display panel 10 is a liquid crystal display (LCD: Liquid Crystal Display).

[0191] Therefore, the control device 20 can reduce the circuit area of the gate drive circuit 14 in the liquid crystal display.

[0192] The display panel 10 is a liquid crystal display, and the light emission period in the additional period is a period in which the backlight is turned on during backlight scanning, while the light extinction period in the additional period is a period in which the backlight is turned off.

[0193] Therefore, even if the frame period of backlight scanning fluctuates significantly, the control device 20 will not visually detect flicker on the display panel 10 using liquid crystals. In other words, even if the frame period of backlight scanning fluctuates, flicker on the display panel 10 using liquid crystals can be suppressed. Furthermore, during the additional period, the backlight emission mode can be switched in periods corresponding to n rows. This allows the control device 20 to suppress delays in image switching compared to switching the backlight emission mode in sub-frame units.

[0194] (Other embodiments)

[0195] The control devices and the like involved in one or more of the above schemes have been described based on various embodiments, but the present disclosure is not limited to these embodiments. Within the scope of the present disclosure, various modifications that can be imagined by those skilled in the art are implemented in the present embodiment, and forms formed by combining components in different embodiments are also included in the scope of the present disclosure.

[0196] For example, in the above embodiments, the pixels of the display panel that displays an image are described as organic EL elements, but they may also be liquid crystal elements. In this case, the light-emitting period may be the period when the backlight source is on during backlight scanning, and the extinction period may be the period when the backlight source is off.

[0197] Therefore, even if the backlight scanning frame period fluctuates significantly, flicker is not visually observed on a display panel using liquid crystals. In other words, even if the backlight scanning frame period fluctuates, flicker on a display panel using liquid crystals can be suppressed. Furthermore, during the additional period, the backlight emission mode can be switched in periods of n rows, thus reducing delays in image switching compared to switching the backlight emission mode in sub-frame units.

[0198] Furthermore, in the above-described embodiments and other embodiments, the control device controls the display panel such that, when the next frame is input into the current individual supplementary period within the supplementary period, the minimum frame period corresponding to the next frame begins after the current individual supplementary period ends. However, the present invention is not limited thereto. The control device may control the display panel such that, after the next frame is input and a predetermined individual supplementary period has elapsed, the minimum frame period corresponding to the next frame begins.

[0199] In the above-described embodiments, each component may be implemented by dedicated hardware or by executing a software program suitable for each component. Each component may be implemented by a program execution unit such as a CPU (Central Processing Unit) or a processor reading and executing a software program stored on a recording medium such as a hard disk or semiconductor memory.

[0200] In addition, the order in which each step in the flowchart is executed is an example shown for the purpose of specifically illustrating the present disclosure, and may be an order other than the order described. In addition, part of the steps may be executed simultaneously (in parallel) with other steps, or part of the steps may not be executed.

[0201] The division of functional blocks in the block diagram is merely an example. Multiple functional blocks can be implemented as a single functional block, or a single functional block can be divided into multiple blocks, or a portion of the functionality can be transferred to another functional block. Furthermore, the functions of multiple functional blocks having similar functions can be processed in parallel or in a time-sharing manner by a single hardware or software.

[0202] Furthermore, the control device according to the above-described embodiment and the like may be implemented as a single device (eg, a single IC chip) or may be implemented by a plurality of devices (eg, a plurality of IC chips).

[0203] In addition, each component of the control device described in the above embodiments can be implemented as software, typically as an integrated circuit, i.e., LSI. These can be monolithic separately, or they can be monolithic in a manner that includes part or all of them. It is called LSI here, but depending on the degree of integration, it is also called IC, system LSI, super LSI, and extra-large LSI. In addition, integrated circuitization is not limited to LSI, and can be implemented using a dedicated circuit or a general-purpose processor. It is also possible to use an FPGA (Field Programmable Gate Array) that can be programmed after the LSI is manufactured, or a reconfigurable processor that can reconfigure the connections and settings of the circuit units inside the LSI. Furthermore, with the advancement of semiconductor technology or other derived technologies, when an integrated circuit technology that can replace LSI emerges, it is of course possible to use this technology to integrate the components.

[0204] A system LSI is a highly multifunctional LSI that integrates multiple processing units on a single chip. Specifically, it is a computer system consisting of a microprocessor, ROM (Read Only Memory), and RAM (Random Access Memory). The ROM stores computer programs. The microprocessor operates according to the computer program, allowing the system LSI to achieve its functions.

[0205] In addition, one embodiment of the present disclosure may be to enable a computer to execute Figures 5 to 9 、 Figure 11 as well as Figure 12 A computer program of the characteristic steps included in any one of the control methods shown.

[0206] Furthermore, for example, the program may be a program for causing a computer to execute. Furthermore, one aspect of the present disclosure may also include a computer-readable, non-transitory recording medium that records such a program. For example, such a program may be recorded on a recording medium and distributed or circulated. For example, the distributed program may be installed on a device having another processor, and the processor may execute the program, thereby causing the device to perform the aforementioned processes.

[0207] Furthermore, these general or specific solutions may be implemented by a system, method, integrated circuit, computer program, or non-transitory recording medium such as a computer-readable CD-ROM, or by any combination of systems, methods, integrated circuits, computer programs, and recording media. The program may be pre-stored on a recording medium or provided to the recording medium via a wide area network, such as the Internet.

[0208] The present disclosure is particularly useful in technical fields such as television systems, game consoles, and personal computer displays that require high-speed and high-resolution display.

Claims

1. A control device for a display panel when a correct frame period is not known in advance, wherein the frame period is a period during which the same image is continuously displayed, and the frame period fluctuates within a certain range or is temporarily stable for each frame. The control device controls the display panel to display an image during a frame period corresponding to the predetermined number of lines and an additional period added after the frame period when a frame having a length exceeding a predetermined number of lines is input. The additional period includes one or more individual additional periods, each of which includes a light emission period and an extinction period. Each of the one or more individual additional periods is a period corresponding to a predetermined number of rows. The control device controls the length of the extinction period of each of the one or more individual additional periods in a manner that is consistent with the ratio of the length of the luminous period to the length of the extinction period in each of the one or more individual additional periods in the current frame and the ratio of the length of the luminous period to the length of the extinction period in the frame period of the current frame.

2. The control device according to claim 1, The specified number of lines is 1 line, The period corresponding to the predetermined number of lines is a period corresponding to one line.

3. The control device according to claim 1, The period corresponding to the predetermined number of rows is a period corresponding to two or more rows.

4. The control device according to claim 3, The control device outputs a control signal for simultaneously writing signal voltages to the two or more rows to the display panel.

5. The control device according to any one of claims 1 to 4, The control device controls the switching between the light-emitting period and the light-extinguishing period of each of the one or more individual additional periods simultaneously on the entire display screen of the display panel.

6. The control device according to any one of claims 1 to 4, The control device continues the additional period until the next frame is input.

7. The control device according to claim 6, When the next frame is inputted during a current individual additional period among the additional periods, the control device controls the display panel so that the frame period corresponding to the next frame starts after the current individual additional period ends.

8. The control device according to claim 5, The display panel is a liquid crystal display.

9. The control device according to any one of claims 1 to 4, The display panel is a liquid crystal display, The light-emitting period is the period during which the backlight source is turned on during backlight scanning. The extinction period is a period during which the backlight source is turned off.

10. The control device according to any one of claims 1 to 4, The pixels constituting the display panel are composed of light-emitting elements including organic EL elements that are driven by current to emit light.

11. A display device comprising: The control device according to any one of claims 1 to 10; and The display panel includes a gate driving circuit and a source driving circuit. The gate driving circuit receives a control signal from the control device, and the source driving circuit receives an image signal from the control device.

12. A control method for a display panel when a correct frame period is not known in advance, wherein the frame period is a period during which the same image is continuously displayed, and the frame period fluctuates within a certain range or is temporarily stable for each frame. When a frame having a length exceeding a predetermined number of lines is input, the display panel is controlled so as to display an image during a frame period corresponding to the predetermined number of lines and an additional period added after the frame period. The additional period includes one or more individual additional periods, each of which includes a light emission period and an extinction period. Each of the one or more individual additional periods is a period corresponding to a predetermined number of rows. The length of the extinction period of each of the one or more individual additional periods is controlled in a manner that the ratio of the length of the luminescence period to the length of the extinction period of each of the one or more individual additional periods of the current frame is consistent with the ratio of the length of the luminescence period to the length of the extinction period in the frame period of the current frame.

Images