A filter system based on FPGA
By combining analog switches, high-speed ADCs, and FPGA modules, the problems of extended data update cycles and increased costs in multi-channel signal filtering are solved, achieving fast filtering and resource saving.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUPCON TECH CO LTD
- Filing Date
- 2023-01-16
- Publication Date
- 2026-07-03
AI Technical Summary
In existing technologies, when using a single Delta-Sigma ADC for multi-channel signal filtering, the data update cycle is prolonged or the number of ADCs needs to be increased, leading to increased cost and PCB layout area.
By combining analog switches, high-speed ADC modules, and FPGA modules, AI signals are acquired through analog switches, polled and sampled by the high-speed ADC module, and filtered by the FPGA module, achieving fast data filtering across multiple channels.
It achieves fast filtering of multi-channel signals, simplifies hardware circuit design, saves FPGA logic resources and PCB layout area, and reduces hardware costs.
Smart Images
Figure CN115966228B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of data filtering, and in particular to an FPGA-based filtering system. Background Technology
[0002] Currently, most AI module sampling circuits use Delta-Sigma ADCs, which utilize built-in filtering algorithms for filtering. In multi-channel sampling, using only a single Delta-Sigma ADC to filter multiple input signals proportionally increases the data update cycle. Using multiple Delta-Sigma ADCs results in high costs and a large PCB (Printed Circuit Board) footprint.
[0003] Therefore, how to use a single ADC to achieve fast data filtering across multiple channels is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0004] To address the aforementioned issues, this application provides an FPGA-based filtering system that uses a single ADC to achieve fast data filtering across multiple channels.
[0005] To address the above problems, the technical solutions provided in this application are as follows:
[0006] An FPGA-based filtering system, the system comprising: an analog switch, a high-speed ADC module, and an FPGA module;
[0007] The analog switch is connected to the high-speed ADC module; the high-speed ADC module is connected to both the analog switch and the FPGA module.
[0008] The analog switch is used to acquire AI signals from the AI channel to obtain AI data as a first data signal, wherein the AI channel is a channel for transmitting the AI signals; the first data signal consists of one or more of the AI data.
[0009] The high-speed ADC module is used to poll and sample the first data signal to obtain the second data signal;
[0010] The FPGA module is used to filter the second data signal to obtain a filtered data signal.
[0011] In one possible implementation, the FPGA module includes: N RAM storage areas, a RAM selection module, and a digital filtering module;
[0012] The RAM storage area is connected to the RAM selection module; the RAM selection module is connected to both the RAM storage area and the digital filtering module.
[0013] The RAM storage area is used to cache the second data signal by rolling over the data.
[0014] The RAM selection module is used to read the second data signal cached in the N RAM storage areas as the third data signal by polling, and send the third data signal to the digital filtering module.
[0015] The digital filtering module is used to filter the third data signal to obtain the filtered data signal.
[0016] In one possible implementation, the digital filtering module is specifically used for:
[0017] The second data signal is then weighted and averaged.
[0018] In one possible implementation, the RAM storage area is specifically used for:
[0019] The second data signal is stored in each RAM address of the RAM storage area by a rolling method.
[0020] In one possible implementation, the RAM selection module is specifically used for:
[0021] Obtain the real-time write address of the RAM address in the RAM storage area and record it as x;
[0022] The second data signal cached in the RAM storage area is read starting from address x+1 and used as the third data signal.
[0023] In one possible implementation, the RAM selection module is further configured to:
[0024] In response to the second data signal stored in the nth RAM storage area being filtered to obtain a filtered data signal, the second data signal cached in the (n+1)th RAM storage area is read as a third data signal, and the third data signal is sent to the digital filtering module.
[0025] In one possible implementation, the FPGA module further includes: a communication module;
[0026] The communication module is connected to the digital filtering module;
[0027] The communication module is used to send the filtered data signal obtained by the digital filtering module to the control system.
[0028] In one possible implementation, the sampling frequency of the high-speed ADC module is f = 50 Hz * q * s; where q is the number of AI data points and s is the number of AI channels.
[0029] Compared with the prior art, this application has the following beneficial effects:
[0030] This application provides an FPGA-based filtering system, comprising: an analog switch, a high-speed ADC module, and an FPGA module. The analog switch is connected to the high-speed ADC module, and the high-speed ADC module is connected to both the analog switch and the FPGA module. The analog switch is used to acquire AI signals from an AI channel to obtain AI data as a first data signal, wherein the AI channel is a channel for transmitting AI signals. The first data signal consists of one or more of the AI data. The high-speed ADC module is used to poll and sample the first data signal to obtain a second data signal. The FPGA module is used to filter the second data signal to obtain a filtered data signal. This application implements data filtering based on an FPGA module, thereby supporting simultaneous filtering of multiple AI input channels, accelerating the data update cycle, simplifying hardware circuit design, greatly saving FPGA logic resources and PCB layout area, and reducing hardware costs. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a schematic diagram of an FPGA filtering system structure provided in an embodiment of this application;
[0033] Figure 2 This application provides a schematic diagram of an FPGA module structure.
[0034] Figure 3 This is a schematic diagram of another FPGA module structure provided in an embodiment of this application;
[0035] Figure 4 This is a schematic diagram of a RAM data cache provided in an embodiment of this application. Detailed Implementation
[0036] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0037] To facilitate understanding of the technical solutions provided in the embodiments of this application, the background technology involved in the embodiments of this application will be described below.
[0038] Currently, in DCS (Distributed Control System) applications, numerous multi-channel AI modules are configured to acquire analog signals such as current and voltage from industrial sites. Due to the characteristics of industrial environments, analog signals are often susceptible to power frequency interference, necessitating filtering of the acquired signals to achieve power frequency immunity. Furthermore, an increasing number of applications require the simultaneous acquisition of current and voltage signals from different channels for real-time processing. This demands that different input channels be able to quickly sample, filter, and update data, posing a challenge to the filtering design of AI modules.
[0039] Currently, most AI module sampling circuits use Delta-Sigma ADCs, which utilize built-in filtering algorithms for filtering. In multi-channel sampling, using only a single Delta-Sigma ADC to filter multiple input signals proportionally increases the data update cycle. Using multiple Delta-Sigma ADCs results in high costs and a large PCB (Printed Circuit Board) footprint.
[0040] To address this issue, this application provides an FPGA-based filtering system, comprising: an analog switch, a high-speed ADC module, and an FPGA module. The analog switch is connected to the high-speed ADC module, which in turn is connected to both the analog switch and the FPGA module. The analog switch acquires AI signals from an AI channel to obtain AI data as a first data signal, where the AI channel is the channel for transmitting AI signals. The first data signal consists of one or more of the AI data. The high-speed ADC module then polls and samples the first data signal acquired by the analog switch to obtain a second data signal. Finally, the FPGA module filters the second data signal to obtain a filtered data signal. This application implements data filtering based on an FPGA module, supporting simultaneous filtering of multiple AI input channels, accelerating the data update cycle, simplifying hardware circuit design, significantly saving FPGA logic resources and PCB layout area, and reducing hardware costs.
[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0042] See Figure 1 , Figure 1 This is a schematic diagram of an FPGA filtering system structure provided in an embodiment of this application. Figure 1 The structure shown includes an analog switch 110, a high-speed ADC module 120, and an FPGA module 130. The analog switch is connected to the high-speed ADC module. The high-speed ADC module is connected to both the analog switch and the FPGA module.
[0043] The analog switch is used to collect AI signals from the AI channel to obtain AI data as a first data signal, wherein the AI channel is a channel for transmitting the AI signals; the first data signal consists of one or more of the AI data.
[0044] The high-speed ADC module is used to poll and sample the first data signal to obtain the second data signal.
[0045] The FPGA module is used to filter the second data signal to obtain a filtered data signal.
[0046] In one possible implementation, the high-speed ADC module can be, but is not limited to, a high-speed SAR ADC. SAR ADCs are also often referred to as binary search ADCs, primarily used in medium-to-high resolution and medium-to-high conversion rate applications. Their working principle is based on a binary algorithm search method. By sampling the input signal, the obtained sampled values are sequentially compared with the reference voltage value generated by the D / A network, finally obtaining a logic output from the most significant bit to the least significant bit.
[0047] In one possible implementation, the AI signal refers to an analog input data signal.
[0048] In one possible implementation, the sampling frequency of the high-speed ADC module is f = 50 Hz * q * s.
[0049] Where q is the amount of AI data; and s is the number of AI channels.
[0050] Figure 2 This application provides a schematic diagram of an FPGA module structure, as shown in the embodiment of the present application. Figure 2 As shown, the FPGA module 130 includes: N RAM storage areas 131, a RAM selection module 132, and a digital filtering module 133.
[0051] RAM storage area 131 is connected to RAM selection module 132. RAM selection module 132 is connected to both RAM storage area 131 and digital filtering module 133. The RAM storage area is used to buffer the second data signal via a rolling cache method.
[0052] The RAM selection module 132 is used to read the second data signal cached in the N RAM storage areas 131 as the third data signal by polling, and send the third data signal to the digital filtering module 133.
[0053] The digital filtering module 133 is used to filter the third data signal to obtain the filtered data signal.
[0054] In one possible implementation, RAM stands for Random Access Memory, a volatile memory. RAM allows data to be written to or read from any specified address at any time, and its stored data can also be modified (i.e., new data is written), a feature not available in ROM. This is the biggest difference between RAM and ROM in FPGAs. ROM is read-only memory, while RAM is writable and readable memory. RAM can be single-ended or double-ended. Double-ended RAM is further divided into ordinary double-ended and simple double-ended. Ordinary single-ended: uses a shared address line for reading and writing, but cannot be read or written simultaneously. Simple double-ended: has one read address port and one write address port. True double-ended: has two read and write ports, both of which can be used for reading and writing.
[0055] In one possible implementation, the digital filtering module is an algorithm or device composed of digital multipliers, adders, and delay units. The function of a digital filter is to process the digital code of an input discrete signal to change the signal spectrum.
[0056] In one possible implementation, the digital filtering module 133 is specifically used for:
[0057] The second data signal is then weighted and averaged.
[0058] In one possible implementation, the RAM storage area 131 is specifically used for:
[0059] The second data signal is stored in each RAM address of the RAM storage area 131 by means of rolling.
[0060] In one possible implementation, digital filtering modules often consume significant FPGA logic resources. To conserve FPGA logic resources and reduce FPGA cost, a single digital filtering module is considered. Therefore, the AI sampling data from different channels needs to be stored in their respective RAM areas first, with each RAM having a storage length n of at least q+1. For example... Figure 4 As shown, when AI sampled data is written to address n, the next data will be written to address 0, and the data will be cached using a rolling method.
[0061] In one possible implementation, the RAM selection module 132 is specifically used for:
[0062] Obtain the real-time write address of the RAM address in the RAM storage area 131, and record it as x;
[0063] The second data signal cached in the RAM storage area 131 is read starting from address x+1 and used as the third data signal.
[0064] In one possible implementation, the RAM selection module 132 is further configured to:
[0065] In response to the second data signal stored in the nth RAM storage area 131 being filtered to obtain a filtered data signal, the second data signal cached in the (n+1)th RAM storage area 131 is read as a third data signal, and the third data signal is sent to the digital filtering module 133.
[0066] Figure 3 This is a schematic diagram of another FPGA module structure provided in an embodiment of this application, such as... Figure 3 As shown, the FPGA module 130 also includes a communication module 134.
[0067] The communication module 134 is connected to the digital filtering module 133;
[0068] The communication module 134 is used to send the filtered data signal obtained by the digital filtering module 133 to the control system.
[0069] This application provides an FPGA filtering system, including an analog switch 110, a high-speed ADC module 120, and an FPGA module 130. The analog switch 110 is connected to the high-speed ADC module 120, and the high-speed ADC module 120 is connected to both the analog switch 110 and the FPGA module 130. The analog switch 110 acquires AI signals from an AI channel to obtain AI data as a first data signal, where the AI channel is the channel for transmitting AI signals. The first data signal consists of one or more of the AI data. The high-speed ADC module 120 then polls and samples the first data signal acquired by the analog switch 110 to obtain a second data signal. Finally, the FPGA module 130 filters the second data signal to obtain a filtered data signal. This application implements data filtering based on an FPGA module, which can support simultaneous filtering of multiple AI input channels, accelerates the data update cycle, simplifies hardware circuit design, greatly saves FPGA logic resources and PCB layout area, and reduces hardware costs.
[0070] The above provides a detailed description of an FPGA filtering system provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.
[0071] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.
[0072] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0073] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0074] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A filtering system based on FPGA, characterized in that, The system includes: an analog switch, a high-speed ADC module, and an FPGA module; The analog switch is connected to the high-speed ADC module; the high-speed ADC module is connected to both the analog switch and the FPGA module. The analog switch is used to acquire AI signals from the AI channel to obtain AI data as a first data signal, wherein the AI channel is a channel for transmitting the AI signals; the first data signal consists of one or more of the AI data. The high-speed ADC module is used to poll and sample the first data signal to obtain the second data signal; The FPGA module is used to filter the second data signal to obtain a filtered data signal. The FPGA module includes: N RAM storage areas, a RAM selection module, and a digital filtering module; The RAM storage area is connected to the RAM selection module; the RAM selection module is connected to both the RAM storage area and the digital filtering module. The RAM storage area is used to cache the second data signal by rolling over the data. The RAM selection module is used to read the second data signal cached in the N RAM storage areas as the third data signal by polling, and send the third data signal to the digital filtering module. The digital filtering module is used to filter the third data signal to obtain the filtered data signal.
2. The system according to claim 1, characterized in that, The digital filtering module is specifically used for: The second data signal is then weighted and averaged.
3. The system according to claim 1, characterized in that, The RAM storage area is specifically used for: The second data signal is stored in each RAM address of the RAM storage area by a rolling method.
4. The system according to claim 3, characterized in that, The RAM selection module is specifically used for: Obtain the real-time write address of the RAM address in the RAM storage area and record it as x; The second data signal cached in the RAM storage area is read starting from address x+1 and used as the third data signal.
5. The system according to claim 1, characterized in that, The RAM selection module is also used for: In response to the second data signal stored in the nth RAM storage area being filtered to obtain a filtered data signal, the second data signal cached in the (n+1)th RAM storage area is read as a third data signal, and the third data signal is sent to the digital filtering module.
6. The system according to claim 1, characterized in that, The FPGA module further includes: a communication module; The communication module is connected to the digital filtering module; The communication module is used to send the filtered data signal obtained by the digital filtering module to the control system.
7. The system according to claim 1, characterized in that, The sampling frequency of the high-speed ADC module is f=50Hz. q s; Where q is the amount of AI data; and s is the number of AI channels.